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| april 2011 doc id 15403 rev 3 1/1317 RM0033 reference manual stm32f205xx, stm32f207xx, stm32f215xx and stm32f217xx advanced arm-based 32-bit mcus introduction this reference manual targets application deve lopers. it provides complete information on how to use the stm32f205xx, stm32f207xx, stm32f215xx and stm32f217xx microcontroller memory and peripherals. the stm32f205xx, stm32f207xx, stm32f215xx and stm32f217xx will be referr ed to as stm32f20x and stm32f21x throughout the document, unless otherwise specified. the stm32f20x and stm32f21x constitute a family of microcontrollers with different memory sizes, packages and peripherals. for ordering information, mechanical and electrical device characteristics please refer to the stm32f20x and stm32f21x datasheets. for information on programming, erasing and protection of the internal flash memory please refer to the stm32f20x and stm32f21x flash programming manual. for information on the arm cortex?-m3 core, please refer to the cortex?-m3 technical reference manual . related documents available from www.arm.com: cortex?-m3 technical reference manual, available from: http://infocenter.arm.com/help /topic/com.arm.doc.d di0337g/ddi0337g_cor tex_m3_r2p0_trm.pdf available from your stmicr oelectronics sales office: stm32f20x and stm32f21x datasheets stm32f20x and stm32f21x flash programming manual cortex-m3 programming manual (pm0056) www.st.com http://
contents RM0033 2/1317 doc id 15403 rev 3 contents 1 documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 1.1 list of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 1.2 peripheral availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2 memory and bus architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.1 system architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.1.1 s0: i-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.1.2 s1: d-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.1.3 s2: s-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.1.4 s3, s4: dma memory bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.1.5 s5: dma peripheral bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.1.6 s6: ethernet dma bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.1.7 s7: usb otg hs dma bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.1.8 busmatrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.1.9 ahb/apb bridges (apb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.2 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.3 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.3.1 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.3.2 bit banding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.3.3 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.3.4 flash memory read interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.3.5 adaptive real-time memory accelerator (art accelerator?) . . . . . . . . 57 2.4 boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3 crc calculation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.1 crc introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.2 crc main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.3 crc functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.4 crc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.4.1 data register (crc_dr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.4.2 independent data register (crc_idr) . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.4.3 control register (crc_cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.4.4 crc register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 RM0033 contents doc id 15403 rev 3 3/1317 4 power control (pwr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.1 power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.1.1 independent a/d converter supply and reference voltage . . . . . . . . . . . 64 4.1.2 battery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.1.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4.2 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.2.1 power-on reset (por)/power-down reset (pdr) . . . . . . . . . . . . . . . . . . 67 4.2.2 brownout reset (bor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.2.3 programmable voltage detector (pvd) . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.3 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.3.1 slowing down system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.3.2 peripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.3.3 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.3.4 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.3.5 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.3.6 programming the rtc alternate functions to wake up the device from the stop and standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.4 power control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4.4.1 pwr power control register (pwr_cr) . . . . . . . . . . . . . . . . . . . . . . . . 78 4.4.2 pwr power control/status register (pwr_csr) . . . . . . . . . . . . . . . . . . 79 4.4.3 pwr register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5 reset and clock control (rcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.1.1 system reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.1.2 power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.1.3 backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.2 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.2.1 hse clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.2.2 hsi clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.2.3 pll configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.2.4 lse clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.2.5 lsi clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.2.6 system clock (sysclk) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.2.7 clock security system (css) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.2.8 rtc/awu clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.2.9 watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 contents RM0033 4/1317 doc id 15403 rev 3 5.2.10 clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.2.11 internal/external clock measurement using tim5/tim11 . . . . . . . . . . . . 90 5.3 rcc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.3.1 rcc clock control register (rcc_cr) . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.3.2 rcc pll configuration register (rcc_pllcfgr) . . . . . . . . . . . . . . . . 94 5.3.3 rcc clock configuration register (rcc_cfgr) . . . . . . . . . . . . . . . . . . 96 5.3.4 rcc clock interrupt regist er (rcc_cir) . . . . . . . . . . . . . . . . . . . . . . . . 98 5.3.5 rcc ahb1 peripheral reset register (rcc_ahb1rstr) . . . . . . . . . . 101 5.3.6 rcc ahb2 peripheral reset register (rcc_ahb2rstr) . . . . . . . . . . 103 5.3.7 rcc ahb3 peripheral reset register (rcc_ahb3rstr) . . . . . . . . . . 104 5.3.8 rcc apb1 peripheral re set register (rcc_apb1rstr) . . . . . . . . . . 104 5.3.9 rcc apb2 peripheral re set register (rcc_apb2rstr) . . . . . . . . . . 107 5.3.10 rcc ahb1 peripheral clock register (rcc_ahb1enr) . . . . . . . . . . . 109 5.3.11 rcc ahb2 peripheral clock enable register (rcc_ahb2enr) . . . . . 111 5.3.12 rcc ahb3 peripheral clock enable register (rcc_ahb3enr) . . . . . 112 5.3.13 rcc apb1 peripheral clock enable register (rcc_apb1enr) . . . . . 112 5.3.14 rcc apb2 peripheral clock enable register (rcc_apb2enr) . . . . . 115 5.3.15 rcc ahb1 peripheral clock enable in low power mode register (rcc_ahb1lpenr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 5.3.16 rcc ahb2 peripheral clock enable in low power mode register (rcc_ahb2lpenr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 5.3.17 rcc ahb3 peripheral clock enable in low power mode register (rcc_ahb3lpenr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 5.3.18 rcc apb1 peripheral clock en able in low power mode register (rcc_apb1lpenr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 5.3.19 rcc apb2 peripheral clock enab led in low power mode register (rcc_apb2lpenr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 5.3.20 rcc backup domain control register (rcc_bdcr) . . . . . . . . . . . . . . 126 5.3.21 rcc clock control & status register (rcc_csr) . . . . . . . . . . . . . . . . 127 5.3.22 rcc spread spectrum clock generation register (rcc_sscgr) . . . . 129 5.3.23 rcc plli2s configuration register (rcc_plli2scfgr) . . . . . . . . . 130 5.3.24 rcc register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 6 general-purpose i/os (gpi o) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 6.1 gpio introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 6.2 gpio main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 6.3 gpio functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 6.3.1 general-purpose i/o (gpio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 RM0033 contents doc id 15403 rev 3 5/1317 6.3.2 i/o pin multiplexer and mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 6.3.3 i/o port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 6.3.4 i/o port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 6.3.5 i/o data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 6.3.6 gpio locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 6.3.7 i/o alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 6.3.8 external interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 6.3.9 input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 6.3.10 output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 6.3.11 alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 6.3.12 analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 6.3.13 using the osc32_in/osc32_out pins as gpio pc14/pc15 port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 6.3.14 using the osc_in/osc_out pins as gpio ph0/ph1 port pins . . . . 144 6.3.15 selection of rtc_af1 and rtc_af2 alternate functions . . . . . . . . . . 144 6.4 gpio registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 6.4.1 gpio port mode register (gpiox_moder) (x = a..i) . . . . . . . . . . . . . 145 6.4.2 gpio port ou tput type register (gpiox_otyper ) (x = a..i) . . . . . . . . 146 6.4.3 gpio port ou tput speed register (gpiox_ospeedr) (x = a..i) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 6.4.4 gpio port pull-up/pull-down register (gpiox_pupdr) (x = a..i) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 6.4.5 gpio port input data register (gpiox_idr) (x = a..i) . . . . . . . . . . . . . 147 6.4.6 gpio port output data register (gpiox_odr) (x = a..i) . . . . . . . . . . . 148 6.4.7 gpio port bit set/reset register (gpiox_bsrr) (x = a..i) . . . . . . . . . . 148 6.4.8 gpio port configuration lock register (gpiox_lckr) (x = a..i) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 6.4.9 gpio alternate function low register (gpiox_afrl) (x = a..i) . . . . . . 149 6.4.10 gpio alternate function high register (gpiox_afrh) (x = a..i) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 6.4.11 gpio register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 7 system configuration controlle r (syscfg) . . . . . . . . . . . . . . . . . . . . 153 7.1 i/o compensation cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 7.2 syscfg registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 7.2.1 syscfg memory remap register ( syscfg_memrmp) . . . . . . . . . . 153 7.2.2 syscfg peripheral mo de configuration register (syscfg_pmc) . . 155 7.2.3 syscfg external interrupt configuration register 1 (syscfg_exticr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 contents RM0033 6/1317 doc id 15403 rev 3 7.2.4 syscfg external interrupt configuration register 2 (syscfg_exticr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 7.2.5 syscfg external interrupt configuration register 3 (syscfg_exticr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 7.2.6 syscfg external interrupt configuration register 4 (syscfg_exticr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 7.2.7 compensation ce ll control register (syscfg_cmpcr) . . . . . . . . . . . 157 7.2.8 syscfg register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 8 interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 8.1 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 159 8.1.1 nvic features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 8.1.2 systick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 8.1.3 interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 8.2 external interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . . . 163 8.2.1 exti main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 8.2.2 exti block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 8.2.3 wakeup event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 8.2.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 8.2.5 external interrupt/event line mapping . . . . . . . . . . . . . . . . . . . . . . . . . 165 8.3 exti registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 8.3.1 interrupt mask register (exti_imr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 8.3.2 event mask register (exti_emr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 8.3.3 rising trigger selection register (exti_rtsr) . . . . . . . . . . . . . . . . . . 167 8.3.4 falling trigger selection re gister (exti_ftsr) . . . . . . . . . . . . . . . . . . 167 8.3.5 software interrupt event register (exti_swier) . . . . . . . . . . . . . . . . . 168 8.3.6 pending register (exti_pr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 8.3.7 exti register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 9 dma controller (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 9.1 dma introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 9.2 dma main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 9.3 dma functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 9.3.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 9.3.2 dma transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 9.3.3 channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 9.3.4 arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 RM0033 contents doc id 15403 rev 3 7/1317 9.3.5 dma streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 9.3.6 source, destination and transfer modes . . . . . . . . . . . . . . . . . . . . . . . 176 9.3.7 pointer incrementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 9.3.8 circular mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 9.3.9 double buffer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 9.3.10 programmable data width, packing/unpacking, endianess . . . . . . . . . 181 9.3.11 single and burst transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 9.3.12 fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 9.3.13 dma transfer completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 9.3.14 dma transfer suspension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 9.3.15 flow controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 9.3.16 summary of the possible dma configurations . . . . . . . . . . . . . . . . . . . 188 9.3.17 stream configuration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 9.3.18 error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 9.4 dma interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 9.5 dma registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 9.5.1 dma low interrupt status register (dma_lisr) . . . . . . . . . . . . . . . . . . 191 9.5.2 dma high interrupt status register (dma_hisr) . . . . . . . . . . . . . . . . . 192 9.5.3 dma low interrupt flag clear register (dma_lifcr) . . . . . . . . . . . . . . 193 9.5.4 dma high interrupt flag clear register (dma_hifcr) . . . . . . . . . . . . . 194 9.5.5 dma stream x configuration register (dma_sxcr) (x = 0..7) . . . . . . . 195 9.5.6 dma stream x number of data register (dma_sxndtr) (x = 0..7) . . . 198 9.5.7 dma stream x peripheral address register (dma_sxpar) (x = 0..7) . 198 9.5.8 dma stream x memory 0 address register (dma_sxm0ar) (x = 0..7) 199 9.5.9 dma stream x memory 1 address register (dma_sxm1ar) (x = 0..7) 199 9.5.10 dma stream x fifo control register (dma_sxfcr) (x = 0..7) . . . . . . 200 9.5.11 dma register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 10 analog-to-digital con verter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 10.1 adc introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 10.2 adc main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 10.3 adc functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 10.3.1 adc on-off control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 10.3.2 adc clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 10.3.3 channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 10.3.4 single conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 10.3.5 continuous conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 contents RM0033 8/1317 doc id 15403 rev 3 10.3.6 timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 10.3.7 analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 10.3.8 scan mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 10.3.9 injected channel management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 10.3.10 discontinuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 10.4 data alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 10.5 channel-wise programmable sampling time . . . . . . . . . . . . . . . . . . . . . 213 10.6 conversion on external trigger and trigger polarity . . . . . . . . . . . . . . . . 214 10.7 fast conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 10.8 data management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 10.8.1 using the dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 10.8.2 managing a sequence of conversions without using the dma . . . . . . 216 10.8.3 conversions without dma and without overrun detection . . . . . . . . . . 216 10.9 multi adc mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 10.9.1 injected simultaneous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 10.9.2 regular simultaneous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 10.9.3 interleaved mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 10.9.4 alternate trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 10.9.5 combined regular/injected simultaneous mode . . . . . . . . . . . . . . . . . . 226 10.9.6 combined regular simultaneous + alternate trigger mode . . . . . . . . . . 226 10.10 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 10.11 battery charge monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 10.12 adc interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 10.13 adc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 10.13.1 adc status register (adc_sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 10.13.2 adc control register 1 (adc_cr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 10.13.3 adc control register 2 (adc_cr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 10.13.4 adc sample time register 1 (adc_smpr1) . . . . . . . . . . . . . . . . . . . . 236 10.13.5 adc sample time register 2 (adc_smpr2) . . . . . . . . . . . . . . . . . . . . 236 10.13.6 adc injected channel data offset register x (adc_jofrx)(x=1..4) . . 237 10.13.7 adc watchdog higher threshold register (adc_htr) . . . . . . . . . . . . . 237 10.13.8 adc watchdog lower threshold register (adc_ltr) . . . . . . . . . . . . . . 237 10.13.9 adc regular sequence register 1 (adc_sqr1) . . . . . . . . . . . . . . . . . 238 10.13.10 adc regular sequence register 2 (adc_sqr2) . . . . . . . . . . . . . . . . . 238 10.13.11 adc regular sequence register 3 (adc_sqr3) . . . . . . . . . . . . . . . . . 239 10.13.12 adc injected sequence register (adc_jsqr) . . . . . . . . . . . . . . . . . . 239 RM0033 contents doc id 15403 rev 3 9/1317 10.13.13 adc injected data register x (adc_jdrx) (x= 1..4) . . . . . . . . . . . . . . 240 10.13.14 adc regular data register (adc_dr) . . . . . . . . . . . . . . . . . . . . . . . . . 240 10.13.15 adc common status register (adc_csr) . . . . . . . . . . . . . . . . . . . . . 242 10.13.16 adc common control register (adc_ccr) . . . . . . . . . . . . . . . . . . . . . 243 10.13.17 adc common regular data register for dual and triple modes (adc_cdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 10.13.18 adc register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 11 digital-to-analog converter (dac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 11.1 dac introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 11.2 dac main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 11.3 dac functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 11.3.1 dac channel enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 11.3.2 dac output buffer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 11.3.3 dac data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 11.3.4 dac conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 11.3.5 dac output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 11.3.6 dac trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 11.3.7 dma request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 11.3.8 noise generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 11.3.9 triangle-wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 11.4 dual dac channel conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 11.4.1 independent trigger without wave generation . . . . . . . . . . . . . . . . . . . 255 11.4.2 independent trigger with single lfsr generation . . . . . . . . . . . . . . . . 256 11.4.3 independent trigger with different lfsr generation . . . . . . . . . . . . . . 256 11.4.4 independent trigger with single triangle generation . . . . . . . . . . . . . . . 256 11.4.5 independent trigger with different triangle generation . . . . . . . . . . . . . 257 11.4.6 simultaneous software start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 11.4.7 simultaneous trigger without wave generation . . . . . . . . . . . . . . . . . . 257 11.4.8 simultaneous trigger with single lfsr generation . . . . . . . . . . . . . . . 258 11.4.9 simultaneous trigger with different lfsr generation . . . . . . . . . . . . . 258 11.4.10 simultaneous trigger with single triangle generation . . . . . . . . . . . . . . 258 11.4.11 simultaneous trigger with different triangle generation . . . . . . . . . . . . 259 11.5 dac registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 11.5.1 dac control register (dac_cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 11.5.2 dac software trigger register (dac_swtrigr) . . . . . . . . . . . . . . . . . 262 contents RM0033 10/1317 doc id 15403 rev 3 11.5.3 dac channel1 12-bit right-aligned data holding register (dac_dhr12r1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 11.5.4 dac channel1 12-bit left aligned data holding register (dac_dhr12l1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 11.5.5 dac channel1 8-bit right aligned data holding register (dac_dhr8r1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 11.5.6 dac channel2 12-bit right aligned data holding register (dac_dhr12r2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 11.5.7 dac channel2 12-bit left aligned data holding register (dac_dhr12l2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 11.5.8 dac channel2 8-bit right-aligned data holding register (dac_dhr8r2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 11.5.9 dual dac 12-bit right-aligned data holding register (dac_dhr12rd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 11.5.10 dual dac 12-bit left aligned data holding register (dac_dhr12ld) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 11.5.11 dual dac 8-bit right aligned data holding register (dac_dhr8rd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 11.5.12 dac channel1 data output register (dac_dor1) . . . . . . . . . . . . . . . . 266 11.5.13 dac channel2 data output register (dac_dor2) . . . . . . . . . . . . . . . . 266 11.5.14 dac status register (dac_sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 11.5.15 dac register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 12 digital camera interface (dcmi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 12.1 dcmi introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 12.2 dcmi main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 12.3 dcmi pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 12.4 dcmi clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 12.5 dcmi functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 12.5.1 dma interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 12.5.2 dcmi physical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 12.5.3 synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 12.5.4 capture modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 12.5.5 crop feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 12.5.6 jpeg format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 12.5.7 fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 12.6 data format description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 12.6.1 data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 12.6.2 monochrome format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 RM0033 contents doc id 15403 rev 3 11/1317 12.6.3 rgb format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 12.6.4 ycbcr format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 12.7 dcmi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 12.8 dcmi register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 12.8.1 dcmi control register 1 (dcmi_cr) . . . . . . . . . . . . . . . . . . . . . . . . . . 280 12.8.2 dcmi status register (dcmi_sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 12.8.3 dcmi raw interrupt status register (dcmi_ris) . . . . . . . . . . . . . . . . . . 283 12.8.4 dcmi interrupt enable register (dcmi_ier) . . . . . . . . . . . . . . . . . . . . 284 12.8.5 dcmi masked interrupt status register (dcmi_mis) . . . . . . . . . . . . . . 285 12.8.6 dcmi interrupt clear register (dcmi_icr) . . . . . . . . . . . . . . . . . . . . . . 286 12.8.7 dcmi embedded synchronization code register (dcmi_escr) . . . . . 286 12.8.8 dcmi embedded synchronization unmask register (dcmi_esur) . . 287 12.8.9 dcmi crop window start (dcmi_cwstrt) . . . . . . . . . . . . . . . . . . . . . 288 12.8.10 dcmi crop window size (dcmi_cwsize) . . . . . . . . . . . . . . . . . . . . . . 288 12.8.11 dcmi data register (dcmi_dr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 12.8.12 dcmi register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 13 advanced-control timers (tim1&tim8) . . . . . . . . . . . . . . . . . . . . . . . . 291 13.1 tim1&tim8 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 13.2 tim1&tim8 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 13.3 tim1&tim8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 13.3.1 time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 13.3.2 counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 13.3.3 repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 13.3.4 clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 13.3.5 capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 13.3.6 input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 13.3.7 pwm input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 13.3.8 forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 13.3.9 output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 13.3.10 pwm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 13.3.11 complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 315 13.3.12 using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 13.3.13 clearing the ocxref signal on an external event . . . . . . . . . . . . . . . 319 13.3.14 6-step pwm generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 13.3.15 one-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 13.3.16 encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 contents RM0033 12/1317 doc id 15403 rev 3 13.3.17 timer input xor function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 13.3.18 interfacing with hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 13.3.19 timx and external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . 327 13.3.20 timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 13.3.21 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 13.4 tim1&tim8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 13.4.1 tim1&tim8 control register 1 (timx_cr1) . . . . . . . . . . . . . . . . . . . . . 331 13.4.2 tim1&tim8 control register 2 (timx_cr2) . . . . . . . . . . . . . . . . . . . . . 332 13.4.3 tim1&tim8 slave mode control register (timx_smcr) . . . . . . . . . . . 334 13.4.4 tim1&tim8 dma/interrupt enable register (timx_dier) . . . . . . . . . . 336 13.4.5 tim1&tim8 status register (timx_sr) . . . . . . . . . . . . . . . . . . . . . . . . 338 13.4.6 tim1&tim8 event generation register (timx_egr) . . . . . . . . . . . . . . 339 13.4.7 tim1&tim8 capture/compare mode register 1 (timx_ccmr1) . . . . . 341 13.4.8 tim1&tim8 capture/compare mode register 2 (timx_ccmr2) . . . . . 344 13.4.9 tim1&tim8 capture/compare enable register (timx_ccer) . . . . . . . 345 13.4.10 tim1&tim8 counter (timx_cnt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 13.4.11 tim1&tim8 prescaler (timx_psc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 13.4.12 tim1&tim8 auto-reload register (timx_arr) . . . . . . . . . . . . . . . . . . . 349 13.4.13 tim1&tim8 re petition counter register (timx_rcr) . . . . . . . . . . . . . . 350 13.4.14 tim1&tim8 capture/compare register 1 (timx_ccr1) . . . . . . . . . . . . 350 13.4.15 tim1&tim8 capture/compare register 2 (timx_ccr2) . . . . . . . . . . . . 351 13.4.16 tim1&tim8 capture/compare register 3 (timx_ccr3) . . . . . . . . . . . . 351 13.4.17 tim1&tim8 capture/compare register 4 (timx_ccr4) . . . . . . . . . . . . 352 13.4.18 tim1&tim8 break and dead-time register (timx_bdtr) . . . . . . . . . . 352 13.4.19 tim1&tim8 dma control register (timx_dcr) . . . . . . . . . . . . . . . . . . 354 13.4.20 tim1&tim8 dma address for full transfer (timx_dmar) . . . . . . . . . . 355 13.4.21 tim1&tim8 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 14 general-purpose timers (tim2 to tim5) . . . . . . . . . . . . . . . . . . . . . . . . 358 14.1 tim2 to tim5 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 14.2 tim2 to tim5 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 14.3 tim2 to tim5 functional de scription . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 14.3.1 time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 14.3.2 counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 14.3.3 clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 14.3.4 capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 14.3.5 input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 RM0033 contents doc id 15403 rev 3 13/1317 14.3.6 pwm input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 14.3.7 forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 14.3.8 output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 14.3.9 pwm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 14.3.10 one-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 14.3.11 clearing the ocxref signal on an external event . . . . . . . . . . . . . . . 382 14.3.12 encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 14.3.13 timer input xor function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 14.3.14 timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 385 14.3.15 timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 14.3.16 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 14.4 tim2 to tim5 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 14.4.1 timx control register 1 (timx_cr1) . . . . . . . . . . . . . . . . . . . . . . . . . . 394 14.4.2 timx control register 2 (timx_cr2) . . . . . . . . . . . . . . . . . . . . . . . . . . 396 14.4.3 timx slave mode control register (timx_smcr) . . . . . . . . . . . . . . . . . 397 14.4.4 timx dma/interrupt enable register (timx_dier) . . . . . . . . . . . . . . . . 400 14.4.5 timx status register (timx_sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 14.4.6 timx event generation register (timx_egr) . . . . . . . . . . . . . . . . . . . . 403 14.4.7 timx capture/compare mode register 1 (timx_ccmr1) . . . . . . . . . . . 404 14.4.8 timx capture/compare mode register 2 (timx_ccmr2) . . . . . . . . . . . 407 14.4.9 timx capture/compare enable register (timx_ccer) . . . . . . . . . . . . . 408 14.4.10 timx counter (timx_cnt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 14.4.11 timx prescaler (timx_psc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 14.4.12 timx auto-reload register (timx_arr) . . . . . . . . . . . . . . . . . . . . . . . . 410 14.4.13 timx capture/compare register 1 (tim x_ccr1) . . . . . . . . . . . . . . . . . 411 14.4.14 timx capture/compare register 2 (tim x_ccr2) . . . . . . . . . . . . . . . . . 411 14.4.15 timx capture/compare register 3 (timx_ccr3) (only available on tim2 and tim5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 14.4.16 timx capture/compare register 4 (timx_ccr4) (only available on tim2 and tim5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 14.4.17 timx dma control register (timx_dcr) . . . . . . . . . . . . . . . . . . . . . . . 413 14.4.18 timx dma address for full transfer (timx_dmar) . . . . . . . . . . . . . . . 413 14.4.19 tim2 option register (tim2_or) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 14.4.20 tim5 option register (tim5_or) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 14.4.21 timx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 15 general-purpose timers (tim9 to tim14) . . . . . . . . . . . . . . . . . . . . . . . 418 contents RM0033 14/1317 doc id 15403 rev 3 15.1 tim9 to tim14 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 15.2 tim9 to tim14 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 15.2.1 tim9/tim12 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 15.3 tim10/tim11 and tim13/tim14 main features . . . . . . . . . . . . . . . . . . . 419 15.4 tim9 to tim14 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 15.4.1 time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 15.4.2 counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 15.4.3 clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 15.4.4 capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 15.4.5 input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 15.4.6 pwm input mode (only for tim9/12) . . . . . . . . . . . . . . . . . . . . . . . . . . 429 15.4.7 forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 15.4.8 output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 15.4.9 pwm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 15.4.10 one-pulse mode (only for tim9/12) . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 15.4.11 tim9/12 external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . . 434 15.4.12 timer synchronization (tim9/12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 15.4.13 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 15.5 tim9 and tim12 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 15.5.1 tim9/12 control register 1 (timx_cr1) . . . . . . . . . . . . . . . . . . . . . . . . 438 15.5.2 tim9/12 control register 2 (timx_cr2) . . . . . . . . . . . . . . . . . . . . . . . . 439 15.5.3 tim9/12 slave mode control register (timx_smcr) . . . . . . . . . . . . . . 440 15.5.4 tim9/12 interrupt enable register (timx_dier) . . . . . . . . . . . . . . . . . 441 15.5.5 tim9/12 status register (timx_sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 15.5.6 tim9/12 event generation register (timx_egr) . . . . . . . . . . . . . . . . . 443 15.5.7 tim9/12 capture/compare mode register 1 (timx_ccmr1) . . . . . . . . 444 15.5.8 tim9/12 capture/compare enable register (timx_ccer) . . . . . . . . . . 447 15.5.9 tim9/12 counter (timx_cnt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 15.5.10 tim9/12 prescaler (timx_psc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 15.5.11 tim9/12 auto-reload register (timx_arr) . . . . . . . . . . . . . . . . . . . . . 448 15.5.12 tim9/12 capture/compare register 1 (timx_ccr1) . . . . . . . . . . . . . . 449 15.5.13 tim9/12 capture/compare register 2 (timx_ccr2) . . . . . . . . . . . . . . 449 15.5.14 tim9/12 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 15.6 tim10/11/13/14 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 15.6.1 tim10/11/13/14 control register 1 (timx_cr1) . . . . . . . . . . . . . . . . . . 451 15.6.2 tim10/11/13/14 interrupt enable register (timx_dier) . . . . . . . . . . . 451 RM0033 contents doc id 15403 rev 3 15/1317 15.6.3 tim10/11/13/14 status register (timx_sr) . . . . . . . . . . . . . . . . . . . . . 452 15.6.4 tim10/11/13/14 event generation register (timx_egr) . . . . . . . . . . . 453 15.6.5 tim10/11/13/14 capture/compare mode register 1 (timx_ccmr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 15.6.6 tim10/11/13/14 capture/compare enable register (timx_ccer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 15.6.7 tim10/11/13/14 counter (timx_cnt) . . . . . . . . . . . . . . . . . . . . . . . . . 457 15.6.8 tim10/11/13/14 prescaler (timx_psc) . . . . . . . . . . . . . . . . . . . . . . . . 457 15.6.9 tim10/11/13/14 auto-reload register (timx_arr) . . . . . . . . . . . . . . . 457 15.6.10 tim10/11/13/14 capture/compare register 1 (timx_ccr1) . . . . . . . . 458 15.6.11 tim11 option register 1 (tim11_or) . . . . . . . . . . . . . . . . . . . . . . . . . . 458 15.6.12 tim10/11/13/14 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 16 basic timers (tim6&tim7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 16.1 tim6&tim7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 16.2 tim6&tim7 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 16.3 tim6&tim7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 16.3.1 time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 16.3.2 counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 16.3.3 clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 16.3.4 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 16.4 tim6&tim7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 16.4.1 tim6&tim7 control register 1 (timx_cr1) . . . . . . . . . . . . . . . . . . . . . 466 16.4.2 tim6&tim7 control register 2 (timx_cr2) . . . . . . . . . . . . . . . . . . . . . 467 16.4.3 tim6&tim7 dma/interrupt enable register (timx_dier) . . . . . . . . . . 467 16.4.4 tim6&tim7 status register (timx_sr) . . . . . . . . . . . . . . . . . . . . . . . . 468 16.4.5 tim6&tim7 event generation register (timx_egr) . . . . . . . . . . . . . . 468 16.4.6 tim6&tim7 counter (timx_cnt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468 16.4.7 tim6&tim7 prescaler (timx_psc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 16.4.8 tim6&tim7 auto-reload register (timx_arr) . . . . . . . . . . . . . . . . . . . 469 16.4.9 tim6&tim7 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 17 independent watchdog (iwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 17.1 iwdg introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 17.2 iwdg main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 17.3 iwdg functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 17.3.1 hardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 contents RM0033 16/1317 doc id 15403 rev 3 17.3.2 register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 17.3.3 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 17.4 iwdg registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 17.4.1 key register (iwdg_kr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 17.4.2 prescaler register (iwdg_pr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 17.4.3 reload register (iwdg_rlr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 17.4.4 status register (iwdg_sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 17.4.5 iwdg register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 18 window watchdog (wwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 18.1 wwdg introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 18.2 wwdg main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 18.3 wwdg functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 18.4 how to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . 478 18.5 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 18.6 wwdg registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 18.6.1 control register (wwdg_cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 18.6.2 configuration register (wwdg_cfr) . . . . . . . . . . . . . . . . . . . . . . . . . 482 18.6.3 status register (wwdg_sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482 18.6.4 wwdg register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 19 cryptographic processor (cryp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 19.1 cryp introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 19.2 cryp main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 19.3 cryp functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 19.3.1 des/tdes cryptographic core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 19.3.2 aes cryptographic core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 19.3.3 data type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 19.3.4 initialization vectors - cryp_iv0...1(l/r) . . . . . . . . . . . . . . . . . . . . . . 499 19.3.5 cryp busy state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 19.3.6 procedure to perform an encryption or a decryption . . . . . . . . . . . . . . 502 19.3.7 context swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 19.4 cryp interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 19.5 cryp dma interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 19.6 cryp registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 19.6.1 cryp control register (cryp_cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 RM0033 contents doc id 15403 rev 3 17/1317 19.6.2 cryp status register (cryp_sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 19.6.3 cryp data input register (cryp_din) . . . . . . . . . . . . . . . . . . . . . . . . 509 19.6.4 cryp data output register (cryp_dout) . . . . . . . . . . . . . . . . . . . . . 510 19.6.5 cryp dma control register (cryp_dmacr) . . . . . . . . . . . . . . . . . . . 511 19.6.6 cryp interrupt mask set/clear register (cryp_imscr) . . . . . . . . . . . 511 19.6.7 cryp raw interrupt status register (cryp_risr) . . . . . . . . . . . . . . . . 512 19.6.8 cryp masked interrupt status register (cryp_misr) . . . . . . . . . . . . 512 19.6.9 cryp key registers (cryp_k0...3(l/r)r) . . . . . . . . . . . . . . . . . . . . . . 513 19.6.10 cryp initialization vector registers (cryp_iv0...1(l/r)r) . . . . . . . . . 515 19.6.11 cryp register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516 20 random number generator (rng ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 20.1 rng introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 20.2 rng main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 20.3 rng functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 20.3.1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 20.3.2 error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 20.4 rng registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 20.4.1 rng control register (rng_cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 20.4.2 rng status register (rng_sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 20.4.3 rng data register (rng_dr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 20.4.4 rng register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 21 hash processor (hash) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 21.1 hash introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 21.2 hash main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 21.3 hash functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 21.3.1 duration of the processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 21.3.2 data type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 21.3.3 message digest computing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 21.3.4 message padding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 21.3.5 hash operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 21.3.6 hmac operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 21.3.7 context swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 21.3.8 hash interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 21.4 hash registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 contents RM0033 18/1317 doc id 15403 rev 3 21.4.1 hash control register (hash_cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 21.4.2 hash data input register (hash_din) . . . . . . . . . . . . . . . . . . . . . . . . 534 21.4.3 hash start register (hash_str) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 21.4.4 hash digest registers (hash_hr0...4) . . . . . . . . . . . . . . . . . . . . . . . 536 21.4.5 hash interrupt enable register (hash_imr) . . . . . . . . . . . . . . . . . . . 537 21.4.6 hash status register (hash_sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 21.4.7 hash context swap registers (hash_csr0...50) . . . . . . . . . . . . . . . 539 21.4.8 hash register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 22 real-time clock (rtc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 22.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 22.2 rtc main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 22.3 rtc functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 22.3.1 clock and prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 22.3.2 real-time clock and calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544 22.3.3 programmable alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544 22.3.4 periodic auto-wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 22.3.5 rtc initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 22.3.6 reading the calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 22.3.7 resetting the rtc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 22.3.8 rtc reference clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548 22.3.9 rtc coarse digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548 22.3.10 time-stamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 22.3.11 tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550 22.3.12 calibration clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551 22.3.13 alarm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551 22.4 rtc and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552 22.5 rtc interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552 22.6 rtc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554 22.6.1 rtc time register (rtc_tr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554 22.6.2 rtc date register (rtc_dr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555 22.6.3 rtc control register (rtc_cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 22.6.4 rtc initialization and status register (rtc_isr) . . . . . . . . . . . . . . . . . 558 22.6.5 rtc prescaler register (rtc_prer) . . . . . . . . . . . . . . . . . . . . . . . . . 560 22.6.6 rtc wakeup timer register (rtc_wutr) . . . . . . . . . . . . . . . . . . . . . . 560 22.6.7 rtc calibration register (rtc_calibr) . . . . . . . . . . . . . . . . . . . . . . . 561 RM0033 contents doc id 15403 rev 3 19/1317 22.6.8 rtc alarm a register (rtc_alrmar) . . . . . . . . . . . . . . . . . . . . . . . . 562 22.6.9 rtc alarm b register (rtc_alrmbr) . . . . . . . . . . . . . . . . . . . . . . . . 563 22.6.10 rtc write protection register (rtc_wpr) . . . . . . . . . . . . . . . . . . . . . 565 22.6.11 rtc time stamp time register (rtc_tstr) . . . . . . . . . . . . . . . . . . . . 565 22.6.12 rtc time stamp date register (rtc_tsdr) . . . . . . . . . . . . . . . . . . . . 566 22.6.13 rtc tamper and alternate function configuration register (rtc_tafcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567 22.6.14 rtc backup registers (rtc_bkpxr) . . . . . . . . . . . . . . . . . . . . . . . . . 568 22.6.15 rtc register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 23 inter-integrated circuit (i 2 c) interface . . . . . . . . . . . . . . . . . . . . . . . . . 570 23.1 i 2 c introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570 23.2 i 2 c main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570 23.3 i 2 c functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 23.3.1 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 23.3.2 i2c slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 23.3.3 i2c master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 23.3.4 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579 23.3.5 sda/scl line control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 23.3.6 smbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 23.3.7 dma requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584 23.3.8 packet error checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 23.4 i 2 c interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586 23.5 i 2 c debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 23.6 i 2 c registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 23.6.1 i 2 c control register 1 (i2c_cr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 23.6.2 i 2 c control register 2 (i2c_cr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 23.6.3 i 2 c own address register 1 (i2c_oar1) . . . . . . . . . . . . . . . . . . . . . . . 592 23.6.4 i 2 c own address register 2 (i2c_oar2) . . . . . . . . . . . . . . . . . . . . . . . 592 23.6.5 i 2 c data register (i2c_dr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 23.6.6 i 2 c status register 1 (i2c_sr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 23.6.7 i 2 c status register 2 (i2c_sr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597 23.6.8 i 2 c clock control register (i2c_ccr) . . . . . . . . . . . . . . . . . . . . . . . . . 598 23.6.9 i 2 c trise register (i2c_trise) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 23.6.10 i2c register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 contents RM0033 20/1317 doc id 15403 rev 3 24 universal synchr onous asynchronous receiver transmitter (usart) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601 24.1 usart introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601 24.2 usart main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601 24.3 usart functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602 24.3.1 usart character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605 24.3.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606 24.3.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 24.3.4 fractional baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613 24.3.5 usart receiver?s tolerance to clock deviation . . . . . . . . . . . . . . . . . . 621 24.3.6 multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621 24.3.7 parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 24.3.8 lin (local interconnection network) mode . . . . . . . . . . . . . . . . . . . . . . 624 24.3.9 usart synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626 24.3.10 single-wire half-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . 628 24.3.11 smartcard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629 24.3.12 irda sir endec block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631 24.3.13 continuous communication using dma . . . . . . . . . . . . . . . . . . . . . . . . 633 24.3.14 hardware flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 24.4 usart interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637 24.5 usart mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638 24.6 usart registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638 24.6.1 status register (usart_sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638 24.6.2 data register (usart_dr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640 24.6.3 baud rate register (usart_brr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 24.6.4 control register 1 (usart_cr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 24.6.5 control register 2 (usart_cr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644 24.6.6 control register 3 (usart_cr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645 24.6.7 guard time and prescaler register (usart_gtpr) . . . . . . . . . . . . . . 648 24.6.8 usart register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649 25 serial peripheral interface (spi ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 25.1 spi introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 25.2 spi and i 2 s main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 25.2.1 spi features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651 25.2.2 i 2 s features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652 RM0033 contents doc id 15403 rev 3 21/1317 25.3 spi functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 25.3.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 25.3.2 configuring the spi in slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656 25.3.3 configuring the spi in master mode . . . . . . . . . . . . . . . . . . . . . . . . . . 659 25.3.4 configuring the spi for simplex communication . . . . . . . . . . . . . . . . . 661 25.3.5 data transmission and reception procedures . . . . . . . . . . . . . . . . . . . 661 25.3.6 crc calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668 25.3.7 status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670 25.3.8 disabling the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671 25.3.9 spi communication using dma (direct memory addressing) . . . . . . . 672 25.3.10 error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674 25.3.11 spi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675 25.4 i 2 s functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676 25.4.1 i 2 s general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676 25.4.2 supported audio protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677 25.4.3 clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684 25.4.4 i 2 s master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686 25.4.5 i 2 s slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688 25.4.6 status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690 25.4.7 error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691 25.4.8 i 2 s interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691 25.4.9 dma features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692 25.5 spi and i 2 s registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693 25.5.1 spi control register 1 (spi_cr1) (not used in i 2 s mode) . . . . . . . . . . 693 25.5.2 spi control register 2 (spi_cr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696 25.5.3 spi status register (spi_sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697 25.5.4 spi data register (spi_dr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698 25.5.5 spi crc polynomial register (spi_crcpr) (not used in i 2 s mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698 25.5.6 spi rx crc register ( spi_rxcrcr) (not used in i 2 s mode) . . . . . . 698 25.5.7 spi tx crc register (s pi_txcrcr) (not used in i 2 s mode) . . . . . . 699 25.5.8 spi_i 2 s configuration register (spi_i2scfgr) . . . . . . . . . . . . . . . . . . 699 25.5.9 spi_i 2 s prescaler register (spi_i2spr) . . . . . . . . . . . . . . . . . . . . . . . 701 25.5.10 spi register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701 26 secure digital input/o utput interface (sdio) . . . . . . . . . . . . . . . . . . . . 703 26.1 sdio main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 contents RM0033 22/1317 doc id 15403 rev 3 26.2 sdio bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 26.3 sdio functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705 26.3.1 sdio adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707 26.3.2 sdio apb2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717 26.4 card functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718 26.4.1 card identification mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718 26.4.2 card reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718 26.4.3 operating voltage range validation . . . . . . . . . . . . . . . . . . . . . . . . . . . 718 26.4.4 card identification process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719 26.4.5 block write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 26.4.6 block read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720 26.4.7 stream access, stream write and stream read (multimediacard only) 721 26.4.8 erase: group erase and sector erase . . . . . . . . . . . . . . . . . . . . . . . . . . 722 26.4.9 wide bus selection or deselection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 26.4.10 protection management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 26.4.11 card status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726 26.4.12 sd status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729 26.4.13 sd i/o mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733 26.4.14 commands and responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734 26.5 response formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737 26.5.1 r1 (normal response command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738 26.5.2 r1b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738 26.5.3 r2 (cid, csd register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738 26.5.4 r3 (ocr register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739 26.5.5 r4 (fast i/o) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739 26.5.6 r4b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739 26.5.7 r5 (interrupt request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740 26.5.8 r6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741 26.6 sdio i/o card-specifi c operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741 26.6.1 sdio i/o read wait oper ation by sdio_d2 signalling . . . . . . . . . . . . . 741 26.6.2 sdio read wait operation by stopping sdio_ck . . . . . . . . . . . . . . . . 742 26.6.3 sdio suspend/resume operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 26.6.4 sdio interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 26.7 ce-ata specific operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742 26.7.1 command completion signal disable . . . . . . . . . . . . . . . . . . . . . . . . . . 742 26.7.2 command completion signal enable . . . . . . . . . . . . . . . . . . . . . . . . . . 743 RM0033 contents doc id 15403 rev 3 23/1317 26.7.3 ce-ata interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743 26.7.4 aborting cmd61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743 26.8 hw flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743 26.9 sdio registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743 26.9.1 sdio power control register (sdio_power) . . . . . . . . . . . . . . . . . . . 744 26.9.2 sdi clock control register (sdio_clkcr) . . . . . . . . . . . . . . . . . . . . . . 744 26.9.3 sdio argument register (sdio_arg) . . . . . . . . . . . . . . . . . . . . . . . . . 745 26.9.4 sdio command register (sdio_cmd) . . . . . . . . . . . . . . . . . . . . . . . . 746 26.9.5 sdio command re sponse register (sdio_respcmd) . . . . . . . . . . . 747 26.9.6 sdio response 1..4 regi ster (sdio_respx) . . . . . . . . . . . . . . . . . . . 747 26.9.7 sdio data timer register (sdio_dtimer) . . . . . . . . . . . . . . . . . . . . . 748 26.9.8 sdio data length register (sdio_dlen) . . . . . . . . . . . . . . . . . . . . . . 748 26.9.9 sdio data control register (sdio_dctrl) . . . . . . . . . . . . . . . . . . . . . 749 26.9.10 sdio data counter register (sdio_dcount) . . . . . . . . . . . . . . . . . . 750 26.9.11 sdio status register (sdio_sta) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 26.9.12 sdio interrupt clear register (sdio_icr) . . . . . . . . . . . . . . . . . . . . . . 752 26.9.13 sdio mask register (sdio_mask) . . . . . . . . . . . . . . . . . . . . . . . . . . . 754 26.9.14 sdio fifo counter register (sdio_fifocnt) . . . . . . . . . . . . . . . . . . 756 26.9.15 sdio data fifo register (sdio_fifo) . . . . . . . . . . . . . . . . . . . . . . . . 757 26.9.16 sdio register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757 27 controller area netwo rk (bxcan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 27.1 bxcan introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 27.2 bxcan main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 27.3 bxcan general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760 27.3.1 can 2.0b active core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760 27.3.2 control, status and configuration registers . . . . . . . . . . . . . . . . . . . . . 760 27.3.3 tx mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760 27.3.4 acceptance filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761 27.4 bxcan operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 27.4.1 initialization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763 27.4.2 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763 27.4.3 sleep mode (low power) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763 27.5 test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764 27.5.1 silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764 27.5.2 loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 contents RM0033 24/1317 doc id 15403 rev 3 27.5.3 loop back combined with silent mode . . . . . . . . . . . . . . . . . . . . . . . . . 765 27.6 stm32f20x and stm32f21x in debug mode . . . . . . . . . . . . . . . . . . . . 766 27.7 bxcan functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 27.7.1 transmission handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 27.7.2 time triggered communication mode . . . . . . . . . . . . . . . . . . . . . . . . . 768 27.7.3 reception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768 27.7.4 identifier filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769 27.7.5 message storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773 27.7.6 error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775 27.7.7 bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775 27.8 bxcan interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777 27.9 can registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779 27.9.1 register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779 27.9.2 can control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779 27.9.3 can mailbox registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789 27.9.4 can filter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796 27.9.5 bxcan register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 28 ethernet (eth): media access control (mac) with dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803 28.1 ethernet introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803 28.2 ethernet main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803 28.2.1 mac core features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804 28.2.2 dma features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805 28.2.3 ptp features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805 28.3 ethernet pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806 28.4 ethernet functional description: smi, mii and rmii . . . . . . . . . . . . . . . . 807 28.4.1 station management interface: smi . . . . . . . . . . . . . . . . . . . . . . . . . . . 807 28.4.2 media-independent interface: mii . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 28.4.3 reduced media-independent interface: rmii . . . . . . . . . . . . . . . . . . . 812 28.4.4 mii/rmii selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813 28.5 ethernet functional description: mac 802.3 . . . . . . . . . . . . . . . . . . . . . . 814 28.5.1 mac 802.3 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815 28.5.2 mac frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818 28.5.3 mac frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 28.5.4 mac interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830 RM0033 contents doc id 15403 rev 3 25/1317 28.5.5 mac filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831 28.5.6 mac loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834 28.5.7 mac management counters: mmc . . . . . . . . . . . . . . . . . . . . . . . . . . . 834 28.5.8 power management: pmt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835 28.5.9 precision time protocol (ieee1588 ptp) . . . . . . . . . . . . . . . . . . . . . . . 838 28.6 ethernet functional description: dma controller operation . . . . . . . . . . . 844 28.6.1 initialization of a transfer using dma . . . . . . . . . . . . . . . . . . . . . . . . . . 845 28.6.2 host bus burst access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845 28.6.3 host data buffer alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846 28.6.4 buffer size calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846 28.6.5 dma arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847 28.6.6 error response to dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847 28.6.7 tx dma configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847 28.6.8 rx dma configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858 28.6.9 dma interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870 28.7 ethernet interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871 28.8 ethernet register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872 28.8.1 mac register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872 28.8.2 mmc register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892 28.8.3 ieee 1588 time stamp registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898 28.8.4 dma register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905 28.8.5 ethernet register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920 29 usb on-the-go full-speed (otg_fs) . . . . . . . . . . . . . . . . . . . . . . . . . . 924 29.1 otg_fs introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924 29.2 otg_fs main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925 29.2.1 general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925 29.2.2 host-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926 29.2.3 peripheral-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926 29.3 otg_fs functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927 29.3.1 otg full-speed core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927 29.3.2 full-speed otg phy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927 29.4 otg dual role device (drd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928 29.4.1 id line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929 29.4.2 hnp dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929 29.4.3 srp dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929 contents RM0033 26/1317 doc id 15403 rev 3 29.5 usb peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930 29.5.1 srp-capable peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930 29.5.2 peripheral states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931 29.5.3 peripheral endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932 29.6 usb host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934 29.6.1 srp-capable host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935 29.6.2 usb host states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935 29.6.3 host channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936 29.6.4 host scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938 29.7 sof trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939 29.7.1 host sofs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939 29.7.2 peripheral sofs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939 29.8 power options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940 29.9 dynamic update of the otg_fs_hfir register . . . . . . . . . . . . . . . . . . . 941 29.10 usb data fifos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941 29.11 peripheral fifo architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942 29.11.1 peripheral rx fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942 29.11.2 peripheral tx fifos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943 29.12 host fifo architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943 29.12.1 host rx fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943 29.12.2 host tx fifos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944 29.13 fifo ram allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944 29.13.1 device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944 29.13.2 host mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945 29.14 usb system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945 29.15 otg_fs interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946 29.16 otg_fs control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 948 29.16.1 csr memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949 29.16.2 otg_fs global registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953 29.16.3 host-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975 29.16.4 device-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986 29.16.5 otg_fs power and clock gating control register (otg_fs_pcgcctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008 29.16.6 otg_fs register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009 29.17 otg_fs programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015 29.17.1 core initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015 RM0033 contents doc id 15403 rev 3 27/1317 29.17.2 host initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017 29.17.3 device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017 29.17.4 host programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018 29.17.5 device programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035 29.17.6 operational model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037 29.17.7 worst case response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054 29.17.8 otg programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055 30 usb on-the-go high-speed (otg_h s) . . . . . . . . . . . . . . . . . . . . . . . . 1062 30.1 otg_hs introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062 30.2 otg_hs main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063 30.2.1 general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063 30.2.2 host-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064 30.2.3 peripheral-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064 30.3 otg_hs functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065 30.3.1 high-speed otg phy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065 30.3.2 external full-speed otg phy using the i2c interface . . . . . . . . . . . 1065 30.3.3 embedded full-speed otg phy . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065 30.4 otg dual-role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066 30.4.1 id line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066 30.4.2 hnp dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066 30.4.3 srp dual-role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066 30.5 usb functional description in peripheral mode . . . . . . . . . . . . . . . . . . 1067 30.5.1 srp-capable peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067 30.5.2 peripheral states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067 30.5.3 peripheral endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068 30.6 usb functional description on host mode . . . . . . . . . . . . . . . . . . . . . . 1071 30.6.1 srp-capable host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071 30.6.2 usb host states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071 30.6.3 host channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073 30.6.4 host scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074 30.7 sof trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075 30.7.1 host sofs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075 30.7.2 peripheral sofs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075 30.8 usb_hs power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076 30.9 dynamic update of the otg_hs_hfir register . . . . . . . . . . . . . . . . . 1077 contents RM0033 28/1317 doc id 15403 rev 3 30.10 fifo ram allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077 30.10.1 peripheral mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077 30.10.2 host mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078 30.11 otg_hs interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078 30.12 otg_hs control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . 1080 30.12.1 csr memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080 30.12.2 otg_hs global registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085 30.12.3 host-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1110 30.12.4 device-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122 30.12.5 otg_hs power and clock gating control register (otg_hs_pcgcctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1149 30.12.6 otg_hs register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1150 30.13 otg_hs programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1162 30.13.1 core initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1162 30.13.2 host initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1163 30.13.3 device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1164 30.13.4 dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1164 30.13.5 host programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1164 30.13.6 device programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192 30.13.7 operational model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194 30.13.8 worst case response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1211 30.13.9 otg programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1212 31 flexible static memory controller (fsmc) . . . . . . . . . . . . . . . . . . . . 1219 31.1 fsmc main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1219 31.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1220 31.3 ahb interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1220 31.3.1 supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . 1221 31.4 external device address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1222 31.4.1 nor/psram address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1222 31.4.2 nand/pc card address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223 31.5 nor flash/psram controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1224 31.5.1 external memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1225 31.5.2 supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . 1227 31.5.3 general timing rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1228 31.5.4 nor flash/psram controller asynchronous transactions . . . . . . . . 1228 RM0033 contents doc id 15403 rev 3 29/1317 31.5.5 synchronous burst transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1245 31.5.6 nor/psram controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 1251 31.6 nand flash/pc card controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256 31.6.1 external memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1257 31.6.2 nand flash / pc card supported me mories and transactions . . . . . 1259 31.6.3 timing diagrams for nand and pc card . . . . . . . . . . . . . . . . . . . . . 1259 31.6.4 nand flash operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1260 31.6.5 nand flash pre-wait functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . 1261 31.6.6 error correction code computation ecc (nand flash) . . . . . . . . . . . 1262 31.6.7 pc card/compactflash operations . . . . . . . . . . . . . . . . . . . . . . . . . . 1262 31.6.8 nand flash/pc card controller registers . . . . . . . . . . . . . . . . . . . . . 1265 31.6.9 fsmc register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1271 32 debug support (dbg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273 32.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273 32.2 reference arm documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1274 32.3 swj debug port (serial wire and jtag) . . . . . . . . . . . . . . . . . . . . . . . . 1274 32.3.1 mechanism to select the jtag-dp or the sw-dp . . . . . . . . . . . . . . . 1275 32.4 pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1275 32.4.1 swj debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1276 32.4.2 flexible swj-dp pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1276 32.4.3 internal pull-up and pull-down on jtag pins . . . . . . . . . . . . . . . . . . . 1277 32.4.4 using serial wire and releasing the unused debug pins as gpios . . 1278 32.5 stm32f20x and stm32f21x jtag tap connection . . . . . . . . . . . . . 1278 32.6 id codes and locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1279 32.6.1 mcu device id code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1279 32.6.2 boundary scan tap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1280 32.6.3 cortex-m3 tap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1280 32.6.4 cortex-m3 jedec-106 id code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1280 32.7 jtag debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1280 32.8 sw debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1282 32.8.1 sw protocol introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1282 32.8.2 sw protocol sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1282 32.8.3 sw-dp state machine (reset, idle states, id code) . . . . . . . . . . . . . . 1283 32.8.4 dp and ap read/write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1284 32.8.5 sw-dp registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1284 contents RM0033 30/1317 doc id 15403 rev 3 32.8.6 sw-ap registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1285 32.9 ahb-ap (ahb access port) - valid for both jtag-dp and sw-dp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1285 32.10 core debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1286 32.11 capability of the debugger host to connect under system reset . . . . . 1287 32.12 fpb (flash patch breakpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1287 32.13 dwt (data watchpoint trigger) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1288 32.14 itm (instrumentation trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . 1288 32.14.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1288 32.14.2 time stamp packets, synchronization and overflow packets . . . . . . . 1288 32.15 etm (embedded trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1290 32.15.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1290 32.15.2 signal protocol, packet types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1290 32.15.3 main etm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1291 32.15.4 configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1291 32.16 mcu debug component (dbgmcu) . . . . . . . . . . . . . . . . . . . . . . . . . . 1291 32.16.1 debug support for low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . 1291 32.16.2 debug support for timers, watchdog, bxcan and i 2 c . . . . . . . . . . . . 1292 32.16.3 debug mcu configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . 1292 32.16.4 debug mcu apb1 freeze register (dbgmcu_apb1_fz) . . . . . . . . 1293 32.16.5 debug mcu apb2 freeze register (dbgmcu_apb2_fz) . . . . . . . . 1295 32.17 tpiu (trace port interface unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1296 32.17.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1296 32.17.2 trace pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1296 32.17.3 tpui formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1298 32.17.4 tpui frame synchronization packets . . . . . . . . . . . . . . . . . . . . . . . . . 1298 32.17.5 transmission of the synchronization frame packet . . . . . . . . . . . . . . 1299 32.17.6 synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1299 32.17.7 asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1299 32.17.8 traceclkin connection inside the stm32f20x and stm32f21x . 1299 32.17.9 tpiu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1301 32.17.10 example of configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1302 32.18 dbg register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1302 33 device electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1303 33.1 unique device id register (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1303 RM0033 contents doc id 15403 rev 3 31/1317 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1309 list of tables RM0033 32/1317 doc id 15403 rev 3 list of tables table 1. stm32f20x and stm32f21x register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . 50 table 2. flash module organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 3. number of wait states according to cortex-m3 clock frequency. . . . . . . . . . . . . . . . . . . . . 55 table 4. boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 5. memory mapping vs. boot mode/physical remap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 6. crc calculation unit register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 7. low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 8. sleep-now . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 9. sleep-on-exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 10. stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 11. standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 12. pwr - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 0 table 13. rcc register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 table 14. port bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 15. flexible swj-dp pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 table 16. rtc_af1 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 table 17. rtc_af2 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 table 18. gpio register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 19. syscfg register map an d reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 20. vector table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 21. external interrupt/event controller register map and reset values. . . . . . . . . . . . . . . . . . . 169 table 22. dma1 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 23. dma2 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 24. source and destination address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 table 25. source and destination address registers in double buffer mode (dbm=1). . . . . . . . . . . 181 table 26. packing/unpacking & endian behavior (bit pinc = minc = 1) . . . . . . . . . . . . . . . . . . . . . 182 table 27. restriction on ndt versus psize and msize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 table 28. fifo threshold configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 29. possible dma configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 table 30. dma interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 table 31. dma register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 table 32. adc pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 table 33. analog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 table 34. configuring the trigger polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 table 35. external trigger for regular channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 table 36. external trigger for injected channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 table 37. adc interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 table 38. adc global register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 table 39. adc register map and reset values for each adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 table 40. adc register map and reset values (common adc registers) . . . . . . . . . . . . . . . . . . . . . 247 table 41. dac pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 table 42. external triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 table 43. dac register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 table 44. dcmi pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 table 45. dcmi signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 table 46. positioning of captured data bytes in 32-bit words (8-bit width) . . . . . . . . . . . . . . . . . . . . 272 table 47. positioning of captured data bytes in 32-bit words (10-bit width) . . . . . . . . . . . . . . . . . . . 272 table 48. positioning of captured data bytes in 32-bit words (12-bit width) . . . . . . . . . . . . . . . . . . . 272 RM0033 list of tables doc id 15403 rev 3 33/1317 table 49. positioning of captured data bytes in 32-bit words (14-bit width) . . . . . . . . . . . . . . . . . . . 273 table 50. data storage in monochrome progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . . 278 table 51. data storage in rgb progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 table 52. data storage in ycbcr progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 table 53. dcmi interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 table 54. dcmi register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 table 55. counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 table 56. timx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 table 57. output control bits for complementary ocx and ocxn channels with break feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 table 58. tim1&tim8 register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 table 59. counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 table 60. timx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 table 61. output control bit for standard ocx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 table 62. tim2 to tim5 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 table 63. timx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 table 64. output control bit for standard ocx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 table 65. tim9/12 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 table 66. output control bit for standard ocx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 table 67. tim10/11/13/14 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 table 68. tim6&tim7 register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 table 69. min/max iwdg timeout period at 32 khz (lsi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 table 70. iwdg register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 table 71. timeout values at 30 mhz (f pclk1 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 table 72. wwdg register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 table 73. data types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 table 74. cryp register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516 table 75. rng register map and reset map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2 table 76. hash register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 table 77. effect of low power modes on rtc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552 table 78. interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 table 79. rtc register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8 table 80. smbus vs. i2c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 table 81. i2c interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586 table 82. i2c register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 table 83. noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2 table 84. error calculation for programmed baud rates at f pclk = 8 mhz or f pclk = 12 mhz), oversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 15 table 85. error calculation for programmed baud rates at f pclk = 8 mhz or f pclk =12 mhz), oversampling by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616 table 86. error calculation for programmed baud rates at f pclk = 16 mhz or f pclk = 24 mhz), oversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 16 table 87. error calculation for programmed baud rates at f pclk = 16 mhz or f pclk = 24 mhz), oversampling by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 table 88. error calculation for programmed baud rates at fpclk = 8 mhz or fpclk = 16 mhz), oversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 18 table 89. error calculation for programmed baud rates at fpclk = 8 mhz or fpclk = 16 mhz), oversampling by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618 table 90. error calculation for programmed baud rates at fpclk = 30 mhz or fpclk = 60 mhz), oversampling by 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 19 table 91. error calculation for programmed baud rates at fpclk = 30 mhz or fpclk = 60 mhz), oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620 list of tables RM0033 34/1317 doc id 15403 rev 3 table 92. usart receiver?s tolerance when div fraction is 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621 table 93. usart receiver?s tolerance when div_fraction is different from 0 . . . . . . . . . . . . . . . . . 621 table 94. frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 table 95. usart interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637 table 96. usart mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638 table 97. usart register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649 table 98. spi interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675 table 99. audio frequency precision (for pllm vco = 1 mhz or 2 mhz) . . . . . . . . . . . . . . . . . . . . 686 table 100. i 2 s interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 2 table 101. spi register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701 table 102. sdio i/o definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707 table 103. command format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711 table 104. short response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712 table 105. long response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712 table 106. command path status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712 table 107. data token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715 table 108. transmit fifo status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716 table 109. receive fifo status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717 table 110. card status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727 table 111. sd status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729 table 112. speed class code field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731 table 113. performance move field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731 table 114. au_size field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731 table 115. maximum au size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732 table 116. erase size field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732 table 117. erase timeout field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732 table 118. erase offset field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733 table 119. block-oriented write commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735 table 120. block-oriented write protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736 table 121. erase commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736 table 122. i/o mode commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736 table 123. lock card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737 table 124. application-specific commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737 table 125. r1 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738 table 126. r2 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738 table 127. r3 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739 table 128. r4 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739 table 129. r4b response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739 table 130. r5 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740 table 131. r6 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741 table 132. response type and sd io_respx registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 table 133. sdio register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757 table 134. transmit mailbox mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774 table 135. receive mailbox mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774 table 136. bxcan register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 table 137. alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806 table 138. management frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808 table 139. clock range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 table 140. tx interface signal encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811 table 141. rx interface signal encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811 table 142. frame statuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827 table 143. destination address filtering table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833 RM0033 list of tables doc id 15403 rev 3 35/1317 table 144. source address filtering table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834 table 145. receive descriptor 0 - encoding for bits 7, 5 and 0 (normal descriptor format only, edfe=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863 table 147. ethernet register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 0 table 148. core global control and status registers (csrs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949 table 149. host-mode control and status registers (csrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950 table 150. device-mode control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951 table 151. data fifo (dfifo) access register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953 table 152. power and clock gating control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953 table 153. minimum duration for soft disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 88 table 154. otg_fs register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009 table 155. core global control and status registers (csrs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081 table 156. host-mode control and status registers (csrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082 table 157. device-mode control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083 table 158. data fifo (dfifo) access register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085 table 159. power and clock gating control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085 table 160. minimum duration for soft disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 5 table 161. otg_hs register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1150 table 162. nor/psram bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 22 table 163. external memory address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223 table 164. memory mapping and timing registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223 table 165. nand bank selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223 table 166. programmable nor/psram access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1224 table 167. nonmultipled i/o nor flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1225 table 168. multiplexed i/o nor flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1225 table 169. nonmultiplexed i/os psram/sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1226 table 170. multiplexed i/o psram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1227 table 171. nor flash/psram supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . 1227 table 172. fsmc_bcrx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1230 table 173. fsmc_btrx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1230 table 174. fsmc_bcrx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1232 table 175. fsmc_btrx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1232 table 176. fsmc_bwtrx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1232 table 177. fsmc_bcrx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1235 table 178. fsmc_btrx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1235 table 179. fsmc_bwtrx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1235 table 180. fsmc_bcrx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1237 table 181. fsmc_btrx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1238 table 182. fsmc_bwtrx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1238 table 183. fsmc_bcrx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1240 table 184. fsmc_btrx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1240 table 185. fsmc_bwtrx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1240 table 186. fsmc_bcrx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1242 table 187. fsmc_btrx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1242 table 188. fsmc_bcrx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1247 table 189. fsmc_btrx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1248 table 190. fsmc_bcrx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1250 table 191. fsmc_btrx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1250 table 192. programmable nand/pc card access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1257 table 193. 8-bit nand flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1257 table 194. 16-bit nand flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1258 table 195. 16-bit pc card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1258 list of tables RM0033 36/1317 doc id 15403 rev 3 table 196. supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259 table 197. 16-bit pc-card signals and access type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263 table 198. ecc result relevant bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1270 table 199. fsmc register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1271 table 200. swj debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1276 table 201. flexible swj-dp pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 6 table 202. jtag debug port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1280 table 203. 32-bit debug port registers addressed through the shifted value a[3:2] . . . . . . . . . . . . . 1281 table 204. packet request (8-bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1282 table 205. ack response (3 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1283 table 206. data transfer (33 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1283 table 207. sw-dp registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1284 table 208. cortex-m3 ahb-ap registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1286 table 209. core debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1286 table 210. main itm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1289 table 211. main etm registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1291 table 212. asynchronous trace pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1296 table 213. synchronous trace pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1297 table 214. flexible trace pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 97 table 215. important tpiu registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1301 table 216. dbg register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 2 table 217. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1309 RM0033 list of figures doc id 15403 rev 3 37/1317 list of figures figure 1. system architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 2. crc calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 3. power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 4. backup sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 5. power-on reset/power-down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 6. bor thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 7. pvd thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 8. simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 9. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 10. hse/ lse clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 11. frequency measurement with tim5 in input capture mode . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 12. frequency measurement with tim11 in input capture mode . . . . . . . . . . . . . . . . . . . . . . . 91 figure 13. basic structure of a five-volt tolerant i/o port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 35 figure 14. selecting an alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 figure 15. input floating/pull up/pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 figure 16. output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 figure 17. alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 figure 18. high impedance-analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 figure 19. external interrupt/event controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 figure 20. external interrupt/event gpio mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 figure 21. dma block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 figure 22. system implementation of two dma controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 figure 23. channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 figure 24. peripheral-to-memory mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 figure 25. memory-to-peripheral mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 figure 26. memory-to-memory mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 figure 27. fifo structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 figure 28. single adc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 figure 29. timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 figure 30. analog watchdog?s guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 09 figure 31. injected conversion latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 figure 32. right alignment of 12-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 figure 33. left alignment of 12-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 figure 34. left alignment of 6-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 figure 35. multi adc block diagram (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 figure 36. injected simultaneous mode on 4 channels: dual adc mode . . . . . . . . . . . . . . . . . . . . . 221 figure 37. injected simultaneous mode on 4 channels: triple adc mode . . . . . . . . . . . . . . . . . . . . . 221 figure 38. regular simultaneous mode on 16 channels: dual adc mode . . . . . . . . . . . . . . . . . . . . 222 figure 39. regular simultaneous mode on 16 channels: triple adc mode . . . . . . . . . . . . . . . . . . . . 222 figure 40. interleaved mode on 1 channel in contin uous conversion mode: dual adc mode. . . . . . 223 figure 41. interleaved mode on 1 channel in continuous conversion mode: triple adc mode . . . . . 224 figure 42. alternate trigger: injected group of each adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 figure 43. alternate trigger: 4 injected channels (each adc) in discontinuous mode . . . . . . . . . . . . 225 figure 44. alternate trigger: injected group of each adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 figure 45. alternate + regular simultaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 figure 46. case of trigger occurring during injected conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 figure 47. temperature sensor and vrefint channel block diagram . . . . . . . . . . . . . . . . . . . . . . 228 figure 48. dac channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 list of figures RM0033 38/1317 doc id 15403 rev 3 figure 49. data registers in single dac channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 figure 50. data registers in dual dac channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 figure 51. timing diagram for conversion with trigger disabled ten = 0 . . . . . . . . . . . . . . . . . . . . . 251 figure 52. dac lfsr register calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 figure 53. dac conversion (sw trigger enabled) with lfsr wave generation. . . . . . . . . . . . . . . . . 254 figure 54. dac triangle wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 figure 55. dac conversion (sw trigger enabled) with triangle wave generation . . . . . . . . . . . . . . . 255 figure 56. dcmi block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 figure 57. top-level block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 figure 58. dcmi signal waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 figure 59. timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 figure 60. frame capture waveforms in snapshot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 figure 61. frame capture waveforms in continuous grab mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 figure 62. coordinates and size of the window after cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 figure 63. data capture waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 figure 64. pixel raster scan order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 figure 65. advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 figure 66. counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 294 figure 67. counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 294 figure 68. counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 figure 69. counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 figure 70. counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 figure 71. counter timing diagram, internal clock divided by n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 figure 72. counter timing diagram, update even t when arpe=0 (timx_arr not preloaded) . . . . . 296 figure 73. counter timing diagram, update event when arpe=1 (timx_arr preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 figure 74. counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 figure 75. counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 figure 76. counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 figure 77. counter timing diagram, internal clock divided by n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 figure 78. counter timing diagram, update event when repetition counter is not used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 figure 79. counter timing diagram, internal clock divided by 1, timx_arr = 0x6 . . . . . . . . . . . . . . 300 figure 80. counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 figure 81. counter timing diagram, internal clock divided by 4, timx_arr=0x36 . . . . . . . . . . . . . . 301 figure 82. counter timing diagram, internal clock divided by n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 figure 83. counter timing diagram, update event with arpe=1 (counter underflow) . . . . . . . . . . . . 302 figure 84. counter timing diagram, update event with arpe=1 (counter overflow) . . . . . . . . . . . . . 302 figure 85. update rate examples depending on mode and timx_rcr register settings . . . . . . . . . 303 figure 86. control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 304 figure 87. ti2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4 figure 88. control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 figure 89. external trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 figure 90. control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 figure 91. capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 307 figure 92. capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 figure 93. output stage of capture/compare channel (channel 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . 308 figure 94. output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 308 figure 95. pwm input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 figure 96. output compare mode, toggle on oc1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 figure 97. edge-aligned pwm waveforms (arr=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 figure 98. center-aligned pwm waveforms (arr=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 RM0033 list of figures doc id 15403 rev 3 39/1317 figure 99. complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 figure 100. dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . . 315 figure 101. dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 316 figure 102. output behavior in response to a break.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 18 figure 103. clearing timx ocxref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 figure 104. 6-step generation, com example (ossr=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 figure 105. example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 figure 106. example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 324 figure 107. example of encoder interface mode with ti1fp1 polarity inverted. . . . . . . . . . . . . . . . . . 324 figure 108. example of hall sensor interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 figure 109. control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 figure 110. control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 figure 111. control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 figure 112. control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 330 figure 113. general-purpose timer block diagram (tim2 to tim5) . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 figure 114. counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 360 figure 115. counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 361 figure 116. counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 figure 117. counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 figure 118. counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 figure 119. counter timing diagram, internal clock divided by n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 figure 120. counter timing diagram, update event when arpe=0 (timx_arr not preloaded). . . . . 363 figure 121. counter timing diagram, update event when arpe=1 (timx_arr preloaded). . . . . . . . 364 figure 122. counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 figure 123. counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 figure 124. counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 figure 125. counter timing diagram, internal clock divided by n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 figure 126. counter timing diagram, update event when repetition counter is not used . . . . . . . . . . 366 figure 127. counter timing diagram, internal clock divided by 1, timx_arr=0x6 . . . . . . . . . . . . . . . 367 figure 128. counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 figure 129. counter timing diagram, internal clock divided by 4, timx_arr=0x36 . . . . . . . . . . . . . . 368 figure 130. counter timing diagram, internal clock divided by n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 figure 131. counter timing diagram, update event with arpe=1 (counter underflow). . . . . . . . . . . . 369 figure 132. counter timing diagram, update event with arpe=1 (counter overflow) . . . . . . . . . . . . . 369 figure 133. control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 370 figure 134. ti2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 71 figure 135. control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 figure 136. external trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 figure 137. control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 figure 138. capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 373 figure 139. capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 figure 140. output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 374 figure 141. pwm input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 figure 142. output compare mode, toggle on oc1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 figure 143. edge-aligned pwm waveforms (arr=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 figure 144. center-aligned pwm waveforms (arr=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 figure 145. example of one-pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 figure 146. clearing timx ocxref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 figure 147. example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 384 figure 148. example of encoder interface mode with ti1fp1 polarity inverted . . . . . . . . . . . . . . . . . 385 figure 149. control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 figure 150. control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 list of figures RM0033 40/1317 doc id 15403 rev 3 figure 151. control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 figure 152. control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 388 figure 153. master/slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 figure 154. gating timer 2 with oc1ref of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 0 figure 155. gating timer 2 with enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 figure 156. triggering timer 2 with update of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 figure 157. triggering timer 2 with enable of timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 figure 158. triggering timer 1 and 2 with timer 1 ti1 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 figure 159. general-purpose timer block diagram (tim9 and tim12) . . . . . . . . . . . . . . . . . . . . . . . . 419 figure 160. general-purpose timer block diagram (tim10/11/13/14) . . . . . . . . . . . . . . . . . . . . . . . . . 420 figure 161. counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 422 figure 162. counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 422 figure 163. counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 figure 164. counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 figure 165. counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 figure 166. counter timing diagram, internal clock divided by n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 figure 167. counter timing diagram, update event when arpe=0 (timx_arr not preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 figure 168. counter timing diagram, update event when arpe=1 (timx_arr preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 figure 169. control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 426 figure 170. ti2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 26 figure 171. control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 figure 172. capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 427 figure 173. capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 figure 174. output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 428 figure 175. pwm input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 figure 176. output compare mode, toggle on oc1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 figure 177. edge-aligned pwm waveforms (arr=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 figure 178. example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 figure 179. control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 figure 180. control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436 figure 181. control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 figure 182. basic timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 figure 183. counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 462 figure 184. counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 462 figure 185. counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 figure 186. counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 figure 187. counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 figure 188. counter timing diagram, internal clock divided by n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 figure 189. counter timing diagram, update event when arpe = 0 (timx_arr not preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 figure 190. counter timing diagram, update event when arpe=1 (timx_arr preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 figure 191. control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 465 figure 192. independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 figure 193. watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 figure 194. window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 79 figure 195. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 figure 196. des/tdes-ecb mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 figure 197. des/tdes-ecb mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 figure 198. des/tdes-cbc mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 RM0033 list of figures doc id 15403 rev 3 41/1317 figure 199. des/tdes-cbc mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 figure 200. aes-ecb mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 figure 201. aes-ecb mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 figure 202. aes-cbc mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 figure 203. aes-cbc mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 figure 204. aes-ctr mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 figure 205. aes-ctr mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 figure 206. initial counter block structure for the counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 figure 207. 64-bit block construction according to datatype . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 figure 208. initialization vectors use in the tdes-cbc encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 figure 209. cryp interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 figure 210. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 figure 211. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 figure 212. bit, byte and half-word swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 figure 213. hash interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 figure 214. rtc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 figure 215. i2c bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 figure 216. i2c block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 figure 217. transfer sequence diagram for slave transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574 figure 218. transfer sequence diagram for slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 figure 219. transfer sequence diagram for master transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 figure 220. transfer sequence diagram for master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579 figure 221. i2c interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587 figure 222. usart block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 figure 223. word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605 figure 224. configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 figure 225. tc/txe behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 08 figure 226. start bit detection when oversampling by 16 or 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 figure 227. data sampling when oversampling by 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612 figure 228. data sampling when oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612 figure 229. mute mode using idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622 figure 230. mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 figure 231. break detection in lin mode (11-bit break length - lbdl bit is set) . . . . . . . . . . . . . . . . . 625 figure 232. break detection in lin mode vs. framing error detection. . . . . . . . . . . . . . . . . . . . . . . . . 626 figure 233. usart example of synchronous transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627 figure 234. usart data clock timing diagram (m=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627 figure 235. usart data clock timing diagram (m=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628 figure 236. rx data setup/hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628 figure 237. iso 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 29 figure 238. parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 30 figure 239. irda sir endec- block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 32 figure 240. irda data modulation (3/16) -normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632 figure 241. transmission using dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634 figure 242. reception using dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 figure 243. hardware flow control between 2 usarts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 figure 244. rts flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636 figure 245. cts flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636 figure 246. usart interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 37 figure 247. spi block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 figure 248. single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 figure 249. hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 figure 250. data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656 list of figures RM0033 42/1317 doc id 15403 rev 3 figure 251. ti mode - slave mode, single transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658 figure 252. ti mode - slave mode, continuous transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658 figure 253. ti mode - master mode, single transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 60 figure 254. ti mode - master mode, continuous transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660 figure 255. txe/rxne/bsy behavior in master / full-duplex mo de (bidimode=0 and rxonly=0) in the case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664 figure 256. txe/rxne/bsy behavior in slave / fu ll-duplex mode (bidimode=0, rxonly=0) in the case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664 figure 257. txe/bsy behavior in master transmit-only mode (bid imode=0 and rxonly=0) in the case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665 figure 258. txe/bsy in slave transmit-only mode (bidimode=0 and rxonly=0) in the case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 66 figure 259. rxne behavior in receive-only mode (bidirmode=0 and rxonly=1) in the case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 67 figure 260. txe/bsy behavior when transmitting (bidirmode=0 and rxonly=0) in the case of discontinuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 8 figure 261. transmission using dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 figure 262. reception using dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 figure 263. ti mode frame format error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675 figure 264. i 2 s block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6 figure 265. i 2 s phillips protocol waveforms (16/32 -bit full accuracy, cp ol = 0) . . . . . . . . . . . . . . . . 678 figure 266. i 2 s phillips standard waveforms (24-bit frame with cpol = 0) . . . . . . . . . . . . . . . . . . . . 678 figure 267. transmitting 0x8eaa33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679 figure 268. receiving 0x8eaa33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679 figure 269. i 2 s phillips standard (16-bit extended to 32-bit pack et frame with cpol = 0) . . . . . . . . . 679 figure 270. example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680 figure 271. msb justified 16-bit or 32-bit full-accuracy length with cpol = 0 . . . . . . . . . . . . . . . . . . 680 figure 272. msb justified 24-bit frame length with cpol = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681 figure 273. msb justified 16-bit extended to 32-bit packet frame with cpol = 0 . . . . . . . . . . . . . . . 681 figure 274. lsb justified 16-bit or 32-bit full-accuracy with cpol = 0 . . . . . . . . . . . . . . . . . . . . . . . . 681 figure 275. lsb justified 24-bit frame length with cpol = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682 figure 276. operations required to transmit 0x3478ae. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682 figure 277. operations required to receive 0x3478ae . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682 figure 278. lsb justified 16-bit extended to 32-bit packet frame with cpol = 0 . . . . . . . . . . . . . . . . 683 figure 279. example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683 figure 280. pcm standard waveforms (16-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684 figure 281. pcm standard waveforms (16-bit extended to 32-bit packet frame). . . . . . . . . . . . . . . . . 684 figure 282. audio sampling frequency definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685 figure 283. i 2 s clock generator architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685 figure 284. sdio ?no response? and ?no data? operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704 figure 285. sdio (multiple) block read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704 figure 286. sdio (multiple) block write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704 figure 287. sdio sequential read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705 figure 288. sdio sequential write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705 figure 289. sdio block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706 figure 290. sdio adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707 figure 291. control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 figure 292. sdio adapter command path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709 figure 293. command path state machine (cpsm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710 figure 294. sdio command transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711 figure 295. data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713 figure 296. data path state machine (dpsm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 RM0033 list of figures doc id 15403 rev 3 43/1317 figure 297. can network topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760 figure 298. dual can block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 figure 299. bxcan operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764 figure 300. bxcan in silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 figure 301. bxcan in loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 figure 302. bxcan in combined mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 figure 303. transmit mailbox states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767 figure 304. receive fifo states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768 figure 305. filter bank scale configuration - register organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 771 figure 306. example of filter numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772 figure 307. filtering mechanism - example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773 figure 308. can error state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774 figure 309. bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776 figure 310. can frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777 figure 311. event flags and interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778 figure 312. eth block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807 figure 313. smi interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808 figure 314. mdio timing and frame structure - write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809 figure 315. mdio timing and frame structure - read cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809 figure 316. media independent interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 figure 317. mii clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812 figure 318. reduced media-independent interface signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813 figure 319. rmii clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813 figure 320. clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814 figure 321. address field format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816 figure 322. mac frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817 figure 323. tagged mac frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818 figure 324. transmission bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824 figure 325. transmission with no collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824 figure 326. transmission with collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 figure 327. frame transmission in mmi and rmii modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 figure 328. receive bit order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829 figure 329. reception with no error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830 figure 330. reception with errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830 figure 331. reception with false carrier indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830 figure 332. mac core interrupt masking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 1 figure 333. wakeup frame filter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836 figure 334. networked time synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839 figure 335. system time update using the fine correction method. . . . . . . . . . . . . . . . . . . . . . . . . . . 841 figure 336. ptp trigger output to tim2 itr1 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843 figure 337. pps output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844 figure 338. descriptor ring and chain structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845 figure 339. txdma operation in default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849 figure 340. txdma operation in osf mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851 figure 341. normal transmit descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852 figure 342. enhanced transmit descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857 figure 343. receive dma operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859 figure 344. normal rx dma descriptor structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 61 figure 345. enhanced receive descriptor field format with ieee1588 time stamp enabled. . . . . . . . . 868 figure 346. interrupt scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871 figure 347. ethernet mac remote wakeup frame filter register (eth_macrwuffr). . . . . . . . . . . . 882 figure 348. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927 list of figures RM0033 44/1317 doc id 15403 rev 3 figure 349. otg a-b device connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928 figure 350. usb peripheral-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930 figure 351. usb host-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935 figure 352. sof connectivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939 figure 353. updating otg_fs_hfir dynamically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941 figure 354. device-mode fifo address mapping and ahb fifo access mapping . . . . . . . . . . . . . . 942 figure 355. host-mode fifo address mapping and ahb fifo access mapping . . . . . . . . . . . . . . . . 943 figure 356. interrupt hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947 figure 357. csr memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949 figure 358. transmit fifo write task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1019 figure 359. receive fifo read task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1020 figure 360. normal bulk/control out/setup and bulk/control in transactions . . . . . . . . . . . . . . . . 1022 figure 361. bulk/control in transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025 figure 362. normal interrupt out/in transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7 figure 363. normal isochronous out/in transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032 figure 364. receive fifo packet read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1038 figure 365. processing a setup packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1040 figure 366. bulk out transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046 figure 367. trdt max timing case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055 figure 368. a-device srp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056 figure 369. b-device srp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057 figure 370. a-device hnp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058 figure 371. b-device hnp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060 figure 372. usb otg interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5 figure 373. updating otg_hs_hfir dynamically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077 figure 374. interrupt hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1079 figure 375. csr memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081 figure 376. transmit fifo write task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1167 figure 377. receive fifo read task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1168 figure 378. normal bulk/control out/setup and bulk/control in transactions - dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1170 figure 379. normal bulk/control out/setup and bulk/control in transactions - slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171 figure 380. bulk/control in transactions - dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1174 figure 381. bulk/control in transactions - slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175 figure 382. normal interrupt out/in transactions - dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177 figure 383. normal interrupt out/in transactions - slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 1178 figure 384. normal isochronous out/in transactions - dma mode . . . . . . . . . . . . . . . . . . . . . . . . . 1183 figure 385. normal isochronous out/in transactions - slave mode . . . . . . . . . . . . . . . . . . . . . . . . 1184 figure 386. receive fifo packet read in slave mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195 figure 387. processing a setup packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1197 figure 388. slave mode bulk out transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 03 figure 389. trdt max timing case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1212 figure 390. a-device srp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1213 figure 391. b-device srp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1214 figure 392. a-device hnp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1215 figure 393. b-device hnp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1217 figure 394. fsmc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1220 figure 395. fsmc memory banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1222 figure 396. mode1 read accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1229 figure 397. mode1 write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1229 figure 398. modea read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1231 RM0033 list of figures doc id 15403 rev 3 45/1317 figure 399. modea write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1231 figure 400. mode2/b read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1233 figure 401. mode2 write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1234 figure 402. modeb write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1234 figure 403. modec read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1236 figure 404. modec write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1237 figure 405. moded read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1239 figure 406. moded write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1239 figure 407. multiplexed read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1241 figure 408. multiplexed write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1242 figure 409. asynchronous wait during a read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1244 figure 410. asynchronous wait during a write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1244 figure 411. wait configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246 figure 412. synchronous multiplexed read mode - nor, psram (cram) . . . . . . . . . . . . . . . . . . . 1247 figure 413. synchronous multiplexed write mode - psram (cram) . . . . . . . . . . . . . . . . . . . . . . . . 1249 figure 414. nand/pc card controller timing for common memory access . . . . . . . . . . . . . . . . . . . 1260 figure 415. access to non ?ce don?t care? nand-flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1261 figure 416. block diagram of stm32 mcu and cortex-m3-level debug support . . . . . . . . . . . . . . . 1273 figure 417. swj debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1275 figure 418. jtag tap connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1279 figure 419. tpiu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1296 documentation conventions RM0033 46/1317 doc id 15403 rev 3 1 documentation conventions 1.1 list of abbreviations for registers the following abbreviations are used in register descriptions: 1.2 peripheral availability for peripheral availability a nd number across all stm32f20 x and stm32f21x sales types, please refer to the stm32f20x and stm32f21x datasheets. read/write (rw) software can read and write to these bits. read-only (r) software can only read these bits. write-only (w) software can only write to this bit. reading the bit returns the reset value. read/clear (rc_w1) software can read as well as clear this bit by writing 1. writing ?0? has no effect on the bit value. read/clear (rc_w0) software can read as well as clear this bit by writing 0. writing ?1? has no effect on the bit value. read/clear by read (rc_r) software can read this bit. reading this bit automatically clears it to ?0?. writing ?0? has no effect on the bit value. read/set (rs) software can read as well as set this bit. writing ?0? has no effect on the bit value. read-only write trigger (rt_w) software can read this bit. writing ?0? or ?1? triggers an event but has no effect on the bit value. toggle (t) software can only toggle this bit by writing ?1?. writing ?0? has no effect. reserved (res.) reserved bit, must be kept at reset value. RM0033 memory and bus architecture doc id 15403 rev 3 47/1317 2 memory and bus architecture 2.1 system architecture the main system consists of 32-bit mult ilayer ahb bus matrix that interconnects: height masters: ? cortex-m3 core i-bus, d-bus and s-bus ? dma1 memory bus ? dma2 memory bus ? dma2 peripheral bus ? ethernet dma bus ? usb otg hs dma bus seven slaves: ? internal flash memory icode bus ? internal flash memory dcode bus ? main internal sram1 (112 kb) ? auxiliary internal sram2 (16 kb) ? ahb1peripherals including ahb to apb bridges and apb peripherals ? ahb2 peripherals ?fsmc the bus matrix provides access from a master to a slave, enabling concurrent access and efficient operation even when several high-speed peripherals work simultaneously. this architecture is shown in figure 1 . memory and bus architecture RM0033 48/1317 doc id 15403 rev 3 figure 1. system architecture 2.1.1 s0: i-bus this bus connects the instruction bus of the cortex-m3 core to the busmatrix. this bus is used by the core to fetch instructions. the target of this bus is a memory containing code (internal flash memory/sram or exte rnal memories through the fsmc). 2.1.2 s1: d-bus this bus connects the databus of the cortex-m3 to the busmatrix. this bus is used by the core for literal load and debug access. the target of this bus is a memory containing code or data (internal flash memory /sram or external memories through the fsmc). 2.1.3 s2: s-bus this bus connects the system bus of the cortex-m3 core to a busmatrix. this bus is used to access data located in a peripheral or in sram. instructions may also be fetch on this bus (less efficient than icode). the targets of this bus are the 112 kb & 16 kb internal srams, the ahb1 peripherals including the apb peripher als, the ahb2 peripher als and the external memories through the fsmc. 2.1.4 s3, s4: dma memory bus this bus connects the dma memory bus master interface to the busmatrix. it is used by the dma to perform transfer to/from memories. the targets of this bus are data memories: internal sram and external memories through the fsmc. ! 2 - # o r t e x - ' 0 $ - ! ' 0 $ - ! - ! # % t h e r n e t 5 3 " / 4 ' ( 3 " u s m a t r i x 3 3 3 3 3 3 3 3 3 ) # / $ % $ # / $ % ! 2 4 ! # # % , & l a s h m e m o r y 3 2 ! - + b y t e 3 2 ! - + b y t e ! ( " p e r i p h ! ( " p e r i p h & 3 - # 3 t a t i c - e m # t l - - - - - - - ) b u s $ b u s 3 b u s $ - ! ? 0 $ - ! ? - % - $ - ! ? - % - $ - ! ? 0 % 4 ( % 2 . % 4 ? - 5 3 " ? ( 3 ? - a i b ! 0 " ! 0 " RM0033 memory and bus architecture doc id 15403 rev 3 49/1317 2.1.5 s5: dma peripheral bus this bus connects the dma peripheral master bus interface to the busmatrix. this bus is used by the dma to access ahb peripherals or to perform memory-to-memory transfers. the targets of this bus are the ahb and apb peripherals plus data memories: internal sram and external memories through the fsmc. 2.1.6 s6: ethernet dma bus this bus connects the ethernet dma master interface to the busmatrix. this bus is used by the ethernet dma to load/store data to a memory. the targets of this bus are data memories: internal sram and external memories through the fsmc. 2.1.7 s7: usb otg hs dma bus this bus connects the usb otg hs dma master interface to the busmatrix. this bus is used by the usb otg dma to load/store data to a memory. the targets of this bus are data memories: internal sram and external memories through the fsmc. 2.1.8 busmatrix the busmatrix manages the access arbitration between masters. the arbitration uses a round-robin algorithm. 2.1.9 ahb/apb bridges (apb) the two ahb/apb bridges provide full synchro nous connections bet ween the ahb and the two apb buses, allowing flexible sele ction of the peri pheral frequency: apb1, limited to 30 mhz for low-speed peripherals apb2, limited to 60 mhz for high-speed peripherals refer to table 1 on page 50 for the address mapping of ahb and apb peripherals. after each device reset, all peripheral clocks are disabled (except for the sram and flash memory interface). before using a peripheral you have to enable its clock in the rcc_ahbxenr or rcc_apbxenr register. note: when a 16- or an 8-bit access is performed on an apb register, the access is transformed into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector. 2.2 memory organization program memory, data memory, registers and i/o ports are organized within the same linear 4 gbyte address space. the bytes are coded in memory in little endian format. the lowest numbered byte in a word is considered the word?s least significant byte and the highest numbered byte, the word?s most significant. for the detailed mapping of peripheral registers, please refer to the related chapters. the addressable memory space is divided into 8 main blocks, each of 512 mb. all the memory areas that are not allocated to on-chip memories and peripherals are considered ?reserved?). refer to the memory map figure in the product datasheet. memory and bus architecture RM0033 50/1317 doc id 15403 rev 3 2.3 memory map see the datasheet corresponding to your device for a comprehensive diagram of the memory map. ta bl e 1 gives the boundary addresses of the peripherals available in all stm32f20x and stm32f21x devices. table 1. stm32f20x and stm32f21x register boundary addresses boundary address peripheral bus register map 0xa000 0000 - 0xa000 0fff fsmc control register ahb3 section 31.6.9: fsmc re gister map on page 1271 0x5006 0800 - 0x5006 0bff rng ahb2 section 20.4.4: rng r egister map on page 522 0x5006 0400 - 0x5006 07ff hash section 21.4.8: hash register map on page 540 0x5006 0000 - 0x5006 03ff cryp section 19.6.11: cryp r egister map on page 516 0x5005 0000 - 0x5005 03ff dcmi section 12.8.12: dcmi regi ster map on page 289 0x5000 0000 - 0x5003 ffff usb otg fs section 29.16.6: otg_ fs register map on page 1009 0x4004 0000 - 0x4007 ffff usb otg hs ahb1 section 30.12.6: otg_hs register map on page 1150 0x4002 9000 - 0x4002 93ff ethernet mac section 28.8.5: etherne t register maps on page 920 0x4002 8c00 - 0x4002 8fff 0x4002 8800 - 0x4002 8bff 0x4002 8400 - 0x4002 87ff 0x4002 8000 - 0x4002 83ff 0x4002 6400 - 0x4002 67ff dma2 section 9.5.11: dma r egister map on page 201 0x4002 6000 - 0x4002 63ff dma1 0x4002 4000 - 0x4002 4fff bkpsram 0x4002 3c00 - 0x4002 3fff flash interface register see flash programming manual 0x4002 3800 - 0x4002 3bff rcc section 5.3.24: rcc register map on page 132 0x4002 3000 - 0x4002 33ff crc section 3.4.4: crc register map on page 62 0x4002 2000 - 0x4002 23ff gpioi section 6.4.11: gpio register map on page 151 0x4002 1c00 - 0x4002 1fff gpioh 0x4002 1800 - 0x4002 1bff gpiog 0x4002 1400 - 0x4002 17ff gpiof 0x4002 1000 - 0x4002 13ff gpioe 0x4002 0c00 - 0x4002 0fff gpiod 0x4002 0800 - 0x4002 0bff gpioc 0x4002 0400 - 0x4002 07ff gpiob 0x4002 0000 - 0x4002 03ff gpioa RM0033 memory and bus architecture doc id 15403 rev 3 51/1317 0x4001 4800 - 0x4001 4bff tim11 apb2 section 15.6.12: tim10/11/ 13/14 register map on page 458 0x4001 4400 - 0x4001 47ff tim10 0x4001 4000 - 0x4001 43ff tim9 section 15.5.14: tim9 /12 register map on page 449 0x4001 3c00 - 0x4001 3fff exti section 8.3.7: exti register map on page 169 0x4001 3800 - 0x4001 3bff syscfg section 7.2.8: sysc fg register ma ps on page 158 0x4001 3000 - 0x4001 33ff spi1 section 25.5.10: spi r egister map on page 701 0x4001 2c00 - 0x4001 2fff sdio section 26.9.16: sdio register map on page 757 0x4001 2000 - 0x4001 23ff adc1 - adc2 - adc3 section 10.13.18: adc r egister map on page 245 0x4001 1400 - 0x4001 17ff usart6 section 24.6.8: usart register map on page 649 0x4001 1000 - 0x4001 13ff usart1 0x4001 0400 - 0x4001 07ff tim8 section 13.4.21: tim1&t im8 register map on page 356 0x4001 0000 - 0x4001 03ff tim1 table 1. stm32f20x and stm32f21x register boundary addresses (continued) boundary address peripheral bus register map memory and bus architecture RM0033 52/1317 doc id 15403 rev 3 2.3.1 embedded sram the stm32f20x and stm32f21x feature 4 kbytes of backup sram (see section 4.1.2: battery backup domain ) plus 128 kbytes of system sram. the system sram can be accessed as bytes, half-words (16 bits) or full words (32 bits). the start address of the sram is 0x2000 0000. read and write operations are performed at cpu speed with 0 wait state. the system sram is split up into two bloc ks, of 112 kb and 16 kb, with a capability for concurrent access from by the ahb masters (like the ethernet or the usb otg hs): for instance, the ethernet mac can read/write from/to the 16 kb sram while the cpu is reading/writing from /to the 112 kb sram. the cpu can access the system sram through the system bus or through the i-code/d- code buses when boot from sram is sele cted or when physical remap is selected 0x4000 7400 - 0x4000 77ff dac apb1 section 11.5.15: dac register map on page 268 0x4000 7000 - 0x4000 73ff pwr section 4.4.3: pwr register map on page 80 0x4000 6800 - 0x4000 6bff can2 section 27.9.5: bxcan re gister map on page 800 0x4000 6400 - 0x4000 67ff can1 0x4000 5c00 - 0x4000 5fff i2c3 section 23.6.10: i2c re gister map on page 600 0x4000 5800 - 0x4000 5bff i2c2 0x4000 5400 - 0x4000 57ff i2c1 0x4000 5000 - 0x4000 53ff uart5 section 24.6.8: usart register map on page 649 0x4000 4c00 - 0x4000 4fff uart4 0x4000 4800 - 0x4000 4bff usart3 0x4000 4400 - 0x4000 47ff usart2 0x4000 3c00 - 0x4000 3fff spi3 / i2s3 section 25.5.10: spi r egister map on page 701 0x4000 3800 - 0x4000 3bff spi2 / i2s2 0x4000 3000 - 0x4000 33ff iwdg section 17.4.5: iwdg register map on page 475 0x4000 2c00 - 0x4000 2fff wwdg section 18.6.4: wwdg re gister map on page 483 0x4000 2800 - 0x4000 2bff rtc & bkp registers section 22.6.15: rtc re gister map on page 568 0x4000 2000 - 0x4000 23ff tim14 section 15.6.12: tim10/11/ 13/14 register map on page 458 0x4000 1c00 - 0x4000 1fff tim13 0x4000 1800 - 0x4000 1bff tim12 section 15.5.14: tim9 /12 register map on page 449 0x4000 1400 - 0x4000 17ff tim7 section 16.4.9: tim6&t im7 register map on page 470 0x4000 1000 - 0x4000 13ff tim6 0x4000 0c00 - 0x4000 0fff tim5 section 14.4.21: timx r egister map on page 416 0x4000 0800 - 0x4000 0bff tim4 0x4000 0400 - 0x4000 07ff tim3 0x4000 0000 - 0x4000 03ff tim2 table 1. stm32f20x and stm32f21x register boundary addresses (continued) boundary address peripheral bus register map RM0033 memory and bus architecture doc id 15403 rev 3 53/1317 ( syscfg memory remap register (syscfg_memrmp) in the syscfg controller). to get the max performance on sram execution, physical remap should be selected (boot or software selection). 2.3.2 bit banding the cortex?-m3 memory map includes two bit-band regions. these regions map each word in an alias region of memory to a bit in a bit-band region of memory. writing to a word in the alias region has the same effect as a read-modify-write operation on the targeted bit in the bit-band region. in the stm32f20x and stm32f21x both the peripheral registers and the sram are mapped to a bit-band region, so that single bit-band write and read operations are allowed. the operations are only available for cortex-m3 accesses, and not from other bus masters (e.g. dma). a mapping formula shows how to reference each word in the alias region to a corresponding bit in the bit-band region. the mapping formula is: bit_word_addr = bit_band_base + ( byte_offset x 32) + ( bit_number 4) where: ? bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit ? bit_band_base is the starting address of the alias region ? byte_offset is the number of the byte in the bit-band region that contains the targeted bit ? bit_number is the bit position (0-7) of the targeted bit example the following example shows how to map bit 2 of the byte located at sram address 0x20000300 to the alias region: 0x22006008 = 0x22000000 + (0x300*32) + (2*4) writing to address 0x22006008 has the same effect as a read-modify-write operation on bit 2 of the byte at sram address 0x20000300. reading address 0x22006008 returns the value (0x01 or 0x00) of bit 2 of the byte at sram address 0x20000300 (0x01: bit set; 0x00: bit reset). for more information on bit-banding, please refer to the cortex-m3 programming manual (see related documents on page 1 ). memory and bus architecture RM0033 54/1317 doc id 15403 rev 3 2.3.3 embedded flash memory the flash memory has the following main features: capacity up to 1 mbyte 128 bits wide data read byte, half-word, word and double word write sector and mass erase memory organization the flash memory is organized as follows: ? a main memory block divided into 4 sectors of 16 kbytes, 1 sector of 64 kbytes, and 7 sectors of 128 kbytes ? system memory from which the device boots in system memory boot mode ? 512 otp (one-time programmable) bytes for user data the otp area contains 16 additional bytes used to lock the corresponding otp data block . ? option bytes to configure read and write protection, bor level, watchdog software/hardware and reset when the device is in standby or stop mode 2.3.4 flash memory read interface relation between cpu clock frequency and flash memory read time to correctly read data from flash memory, the number of wait states (latency) must be correctly programmed in the flash access control register (flash_acr) according to the frequency of the cortex-m3 clock and the supply voltage of the device. ta bl e 3 shows the table 2. flash module organization block name block base addresses size main memory sector 0 0x0800 0000 - 0x0800 3fff 16 kbyte sector 1 0x0800 4000 - 0x0800 7fff 16 kbyte sector 2 0x0800 8000 - 0x0800 bfff 16 kbyte sector 3 0x0800 c000 - 0x0800 ffff 16 kbyte sector 4 0x0801 0000 - 0x0801 ffff 64 kbyte sector 5 0x0802 0000 - 0x0803 ffff 128 kbyte sector 6 0x0804 0000 - 0x0805 ffff 128 kbyte . . . . . . . . . sector 11 0x080e 0000 - 0x080f ffff 128 kbyte system memory 0x1fff 0000 - 0x1fff 77ff 30 kbyte otp 0x1fff 7800 - 0x1fff 7a0f 528 bytes option bytes 0x1fff c000 - 0x1fff c00f 16 bytes RM0033 memory and bus architecture doc id 15403 rev 3 55/1317 correspondence between wait states and core clock frequency. after reset, the cpu clock frequency is 16 mhz and 0 wait state (ws) is configured in the flash_acr register. it is highly recommended to use the following software sequences to tune the number of wait states needed to access the flash memory with the cpu frequency. increasing the cpu frequency program the new number of wait states to the latency bits in the flash_acr register check that the new number of wait states is used to access the flash memory by reading the flash_acr register modify the cpu clock source by writing the sw bits in the rcc clock configuration register (rcc_cfgr) if needed, modify the cpu clock prescale r by writing the hpre bits in rcc_cfgr check that the new cpu clock source or/and the new cpu clock prescaler value is/are taken into account by reading the clock source status (sws bits) or/and the ahb prescaler value (hpre bits), respec tively, in the rcc_cfgr register decreasing the cpu frequency modify the cpu clock source by writing the sw bits in the rcc_cfgr register if needed, modify the cpu clock prescale r by writing the hpre bits in rcc_cfgr check that the new cpu clock source or/and the new cpu clock prescaler value is/are taken into account by reading the clock source status (sws bits) or/and the ahb prescaler value (hpre bits), respec tively, in the rcc_cfgr register program the new number of wait states to the latency bits in flash_acr check that the new number of wait states is used to access the flash memory by reading the flash_acr register table 3. number of wait states according to cortex-m3 clock frequency wait states (ws) (latency) hclk - cortex-m3 clock frequency (mhz) voltage range 2.7 to 3.6 v voltage range 2.4 to 2.7 v voltag e rang e 2.1 to 2.4 v voltag e rang e 1.8 (1) to 2.1 v 1. if irroff is set to v dd on stm32f20xx devcies , this value can be lowered to 1.65 v when the device operates in a reduced temperature range. 0 ws (1 cpu cycle) 0 < hclk 30 0 < hclk 24 0 < hclk 18 0 < hclk 16 1 ws (2 cpu cycles) 30 RM0033 memory and bus architecture doc id 15403 rev 3 57/1317 2.3.5 adaptive real-time memory accelerator (art accelerator?) the art accelerator? is a memory accelera tor which is optimized for stm32 industry- standard arm ? cortex?-m3 processors. it balances the inherent performance advantage of the arm cortex-m3 over flash memory technologies, which normally requires the processor to wait for the flash memory at higher operating frequencies. thanks to the art accelerator?, the cpu can operate up to 120 mhz without wait states, thereby increasing the overall system speed and efficiency. to release the processor full 150 dmips performance at this frequency the accelerator implements an instruction prefetch queue and branch cache, which enables program execution from flash memory at up to 120 mhz without wait states. 2.4 boot configuration due to its fixed memory map, the code area starts from address 0x0000 0000 (accessed through the icode/dcode buses) while the data area (sram) starts from address 0x2000 0000 (accessed through the system bus). the cortex-m3 cpu always fetches the reset vector on the icode bus, which implies to have the boot space available only in the code area (typically, flash memory). stm32f20x and stm32f21x microcontrollers implement a special mechanism to be able to boot from other memories (like the internal sram). in the stm32f20x and stm32f21x, three different boot modes can be selected through the boot[1:0] pins as shown in ta b l e 4 . bit 8 prften: prefetch enable 0: prefetch is disabled 1: prefetch is enabled bits 7:3 reserved, must be kept cleared. bits 2:0 latency: latency these bits represent the ratio of the cpu clock period to the flash memory access time. 000: zero wait state 001: one wait state 010: two wait states 011: three wait states 100: four wait states 101: five wait states 110: six wait states 111: seven wait states table 4. boot modes boot mode selection pins boot mode aliasing boot1 boot0 x 0 main flash memory main flash memory is selected as the boot space 0 1 system memory system memory is selected as the boot space 1 1 embedded sram embedded sram is selected as the boot space memory and bus architecture RM0033 58/1317 doc id 15403 rev 3 the values on the boot pins are latched on the 4th rising edge of sysclk after a reset. it is up to the user to set the boot1 and boot0 pins after reset to select the required boot mode. boot0 is a dedicated pin while boot1 is shared with a gpio pin. once boot1 has been sampled, the corresponding gpio pin is free and can be used for other purposes. the boot pins are also resampled when the device exits the standby mode. consequently, they must be kept in the required boot mode configuration when the device is in the standby mode. after this startup delay is over, the cp u fetches the top-of-stack value from address 0x0000 0000, then starts code execution from the boot memory starting from 0x0000 0004. note: when the device boots from sram, in the application initialization code, you have to relocate the vector table in sram using the nvic exception table and the offset register. physical remap once the boot pins are selected, the application software can modify the memory accessible in the code area (in this way the code can be executed through the icode bus in place of the system bus). this modification is performed by programming the section 7.2.1: syscfg memory remap re gister (syscfg_memrmp) in the syscfg controller. the following memories can thus be remapped: main flash memory system memory embedded sram1 (112 kb) fsmc bank 1 (nor/psram 1 and 2) table 5. memory mapping vs. boot mode/physical remap addresses boot/remap in main flash memory boot/remap in embedded sram boot/remap in system memory remap in fsmc 0x2001 c000 - 0x2001 ffff sram2 (16 kb) sram2 (16 kb) sram2 (16 kb) sram2 (16 kb) 0x2000 0000 - 0x2001 bfff sram1 (112 kb) sram1 (112 kb) sram1 (112 kb) sram1 (112 kb) 0x1fff 0000 - 0x1fff 77ff system memory s ystem memory system memory system memory 0x0810 0000 - 0x0fff ffff reserved reserved reserved reserved 0x0800 0000 - 0x080f ffff flash memory flash memory flash memory flash memory 0x0400 0000 - 0x07ff ffff reserved reserved reserved fsmc bank1 nor/psram 2 (aliased) 0x0000 0000 - 0x03ff ffff (1)(2) flash (1 mb) aliased sram1 (112 kb) aliased system memory (30 kb) aliased fsmc bank1 nor/psram 1 (aliased) 1. when the fsmc is remapped at address 0x0000 0000, only the fi rst two regions of bank 1 memory controller (bank1 nor/psram 1 and nor/psram 2) can be remapped. in remap mode, the cpu can access the external memory via icode bus instead of system bus which boosts up the perfo rmance. however, in remap mode, the fsmc addressing is fixed to the remap address area only (bank1 nor/psram 1 and nor/psram 2) and fsmc control regist ers are not accessible. the fsmc remap function must be disabled to allows addressing other memo ry devices through the fsmc and/or to access fsmc control registers. 2. even when aliased in the boot memory space, the related me mory is still acce ssible at its original memory space. RM0033 memory and bus architecture doc id 15403 rev 3 59/1317 embedded bootloader the embedded bootloader mode is used to reprogram the flash memory using one of the following serial interfaces: usart1(pa9/pa10) usart3(pb10/11 and pc10/11) can2(pb5/13) usb otg fs(pa11/12) in device mode (dfu: device firmware upgrade). the usart peripherals operate at the internal 16 mhz oscillator (hsi) frequency, while the can and usb otg fs require an external clock (hse) multiple of 1 mhz (ranging from 4 to 26 mhz). the embedded bootloader code is located in system memory. it is programmed by st during production. for additional information, refer to application note an2606. crc calculation unit RM0033 60/1317 doc id 15403 rev 3 3 crc calculation unit th is sect ion a pplie s t o t he who l e stm32 f 20 x a nd stm3 2f2 1 x f a mily , unle s s ot he rwise spec ified. 3. 1 crc intr oducti on th e crc ( c yclic r e d und ancy ch ec k) calcula t ion u n it is used to get a crc code fr om a 3 2 - b it d a t a w o rd a nd a f i x e d ge ner at or p o lyno mial. am on g ot he r ap p licat ion s , c rc- ba se d te ch niq u e s ar e us ed to v e r i fy d a t a t r an sm issio n o r st or a ge int e g r ity . i n th e sco p e o f t he en/i ec 6 0 3 35- 1 sta nda rd , t h e y o f f e r a mea n s of v e r i fying the flash memor y i n teg r ity . the crc ca lculation unit helps co mpute a signature of t h e sof t w ar e du r i ng r u nt ime , t o be co mpa r e d wit h a r e f e r ence sign at ur e ge ner a t ed at link- t i me a nd sto r e d at a giv e n m e mo r y locat i on . 3. 2 crc main f eatures use s crc- 3 2 ( e th er net ) p o lynom ial: 0 x 4c11db7 ?x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 +x 8 + x 7 + x 5 + x 4 + x 2 + x +1 single inpu t / o u t put 32 -bit da ta r e g i st er cr c c o mputation done in 4 ahb c l oc k cyc les (h clk) ge ner al- pur po se 8 - b i t r egist er ( can be used f o r t e m por ar y sto r ag e) th e b l oc k d i ag r a m is sho w n in fig u r e 2 . figure 2. crc calculati on unit b l oc k dia gram 3. 3 crc functional description th e crc ca lculat ion unit main ly con s ist s o f a single 32- bit dat a r egist er , wh ich : is u s e d as an inp u t re giste r t o ent e r ne w d a t a in t he crc calculat o r (whe n wr itin g int o t he r egist er ) ho lds t h e re su lt of th e pr e viou s crc calcula t io n (whe n re adin g t he r egist er ) ahb bus 32-bit (read access) data register (output) crc computation (polynomial: 0x4c11db7) 32-bit (write access) data register (input) ai14968 RM0033 crc calculation unit doc id 15403 rev 3 61/1317 ea ch wr ite o per a t ion int o th e d a t a reg i ste r cr eat e s a com b ina t ion of t h e pr e v iou s crc v a lue and the ne w one (crc computatio n is done on the w h ole 32-bit da ta w o rd, and not b y te per by t e ) . th e wr ite o p e r at ion is st a lled un til t h e e nd o f t he crc comp ut at ion , t hus allo wing b a c k-t o- b a c k wr it e accesses o r conse c u t iv e wr it e an d re ad accesses . the crc calculator ca n be reset to 0xffff ff ff with the reset control bit in the crc_ c r re gist er . th is o per at ion d oes not af f e ct t h e con t e n t s o f t he crc_ i dr reg i ste r . 3. 4 crc regi ster s th e crc ca lculat ion unit co nt ain s t w o d a t a re giste r s and a co nt ro l r e g i st er . 3.4.1 data register (crc_dr) ad dre ss of f s e t : 0x00 reset v a lue : 0 x f fff fff f 3.4.2 independent data r egister (crc_idr) ad dre ss of f s e t : 0x04 reset v a lue : 0 x 0 000 000 0 3 1 3 0 29 28 27 26 2 5 24 23 22 21 2 0 19 18 17 16 dr [31 : 16 ] rw rw rw rw r w rw rw rw rw r w rw rw rw rw r w r w 1 5 1 4 1 3 1 2 1 1 1 0 98765 43210 dr [ 15: 0] rw rw rw r w rw rw rw rw r w rw rw rw rw rw r w rw bits 31:0 data register bits used a s an i npu t regi ster whe n wr iting ne w data into th e crc calcul ator . ho lds th e p r e v i ous crc calcul ation resul t whe n it is read . 1 5 1 4 1 3 1 2 1 1 1 0 98765 43210 reser v e d idr[7:0 ] r w rw rw rw rw rw r w rw bits 31:8 r eser v e d bi ts 7: 0 g e neral - pu rp ose 8-bi t d a ta regi ster b i ts c an be used a s a temporar y stor ag e locatio n f o r one b y te . this regi ste r is not aff e cted by crc resets generated by the reset bit in the crc_cr register. crc calculation unit RM0033 62/1317 doc id 15403 rev 3 3.4.3 contr o l register (crc_cr) ad dre s s of f s e t : 0x08 reset v a lue : 0 x 0 000 000 0 3.4.4 crc register map th e f o llo wing t a b l e pr o v id es th e crc re giste r ma p and r e set v a lu es . 3 1 3 0 29 28 27 26 2 5 24 23 22 21 2 0 19 18 17 16 reser v ed 1 5 1 4 1 3 1 2 1 1 1 0 98765 43210 reser v ed rese t w bit s 31 :1 re ser ve d bit 0 reset bit rese ts th e crc calcul ati on un it an d se ts the data regi ster to 0xffff ffff . th is bit ca n o n ly be set, it is a u tomaticall y cle a red b y hard w are . t a b l e 6. crc calculation unit re gister map and reset v a lues offset regis t er 3 1 -24 23-16 15-8 7 6 5 4 3 2 1 0 0x 0 0 cr c_dr reset v a lue data re gister 0 x f fff ff ff 0x 0 4 cr c_idr reset value reser v e d indep endent data register 0x00 0x 0 8 cr c_cr reset value reser v ed rese t 0 RM0033 power control (pwr) doc id 15403 rev 3 63/1317 4 power control (pwr) 4.1 power supplies the device requires a 1.8-to-3.6 v operating voltage supply (v dd ). an embedded linear voltage regulator is used to supply the internal 1.2 v digital power. the real-time clock (rtc), the rtc backup registers, and the ba ckup sram (bkp sram) can be powered from the v bat voltage when the main v dd supply is powered off. note: depending on the operating power supply range, some peripheral may be used with limited functionality and performance. for more details refer to section "general operating conditions" in stm32f2xx datasheets. figure 3. power supply overview 1. v dda and v ssa must be connected to v dd and v ss , respectively. 2. irroff is only available on wlcsp package. a i d 6 $ $ ! n a l o g 2 # s 0 , , 0 o w e r s w i t c h 6 " ! 4 ' 0 ) / s / 5 4 ) . + e r n e l l o g i c # 0 5 d i g i t a l 2 ! - " a c k u p c i r c u i t r y / 3 # + 2 4 # " a c k u p r e g i s t e r s b a c k u p 2 ! - 7 a k e u p l o g i c n & ? & 6 6 o l t a g e r e g u l a t o r 6 3 3 6 $ $ ! 6 2 % & 6 2 % & 6 3 3 ! ! $ # , e v e l s h i f t e r ) / , o g i c 6 $ $ n & ? & 6 2 % & n & ? & 6 $ $ & l a s h m e m o r y 6 # ! 0 ? 6 # ! 0 ? ? & 2 % ' / & & ) 2 2 / & & power control (pwr) RM0033 64/1317 doc id 15403 rev 3 4.1.1 independent a/d converter supply and reference voltage to improve conversion accuracy, the adc has an independent power supply which can be separately filtered and shielded from noise on the pcb. the adc voltage supply input is available on a separate v dda pin. an isolated supply ground connection is provided on pin v ssa . to ensure a better accuracy of low voltage inputs, the user can connect a separate external reference voltage adc input on v ref . the voltage on v ref ranges from 1.8 v to v dda . 4.1.2 battery backup domain backup domain description to retain the content of the rtc backup registers, backup sram, and supply the rtc when v dd is turned off, v bat pin can be connected to an optional standby voltage supplied by a battery or by another source. to allow the rtc to operate even when the main digital supply (v dd ) is turned off, the v bat pin powers the following blocks: the rtc the lse oscillator the backup sram when the low power backup regulator is enabled pc13 to pc15 i/os, plus pi8 i/o (when available) the switch to the v bat supply is controlled by the power-down reset embedded in the reset block. warning: during t rsttempo (temporization at v dd startup) or after a pdr is detected, the power switch between v bat and v dd remains connected to v bat . during the startup phase, if v dd is established in less than t rsttempo (refer to the datasheet for the value of t rsttempo ) and v dd > v bat + 0.6 v, a current may be injected into v bat through an internal diode connected between v dd and the power switch (v bat ). if the power supply/battery connected to the v bat pin cannot support this current injection, it is strongly recommended to connect an external low-drop diode between this power supply and the v bat pin. RM0033 power control (pwr) doc id 15403 rev 3 65/1317 if no external battery is used in the application, it is recommended to connect v bat externally to v dd through a 100 nf external ceramic capacitor. when the backup domain is supplied by v dd (analog switch connected to v dd ), the following functions are available: pc14 and pc15 can be used as either gpio or lse pins pc13 can be used as a gpio or as the rtc_af1 pin (refer to table 16: rtc_af1 pin for more details about this pin configuration) pi8 can be used as a gpio or as the rtc_af2 pin (refer to table 17: rtc_af2 pin for more details about this pin configuration) note: due to the fact that the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 and pi8 are restricted: only one i/o at a time can be used as an output, the speed has to be limited to 2 mhz with a maximum load of 30 pf and these i/os must not be used as a current source (e.g. to drive an led). when the backup domain is supplied by v bat (analog switch connected to v bat because v dd is not present), the following functions are available: pc14 and pc15 can be used as lse pins only pc13 can be used as the rtc_af1 pin (refer to table 16: rtc_af1 pin ) for more details about this pin configuration) pi8 can be used as the rtc_af2 pin (refer to table 17: rtc_af2 pin for more details about this pin configuration) backup domain access after reset, the backup domain (rtc registers, rtc backup register and backup sram) is protected against possible unwanted write accesses. to enable access to the backup domain, proceed as follows: access to the rtc and rtc backup registers 1. enable the power interface clock by setting the pwren bits in the rcc apb1 peripheral clock enable register (rcc_apb1enr) 2. set the dbp bit in the pwr power control register (pwr_cr) to enable access to the backup domain 3. select the rtc clock source: see section 5.2.8: rtc/awu clock 4. enable the rtc clock by programming the rtcen [15] bit in the rcc backup domain control register (rcc_bdcr) access to the backup sram 1. enable the power interface clock by setting the pwren bits in the rcc apb1 peripheral clock enable register (rcc_apb1enr) 2. set the dbp bit in the pwr power control register (pwr_cr) to enable access to the backup domain 3. enable the backup sram cloc k by setting bkpsramen bit in the rcc ahb1 peripheral clock register (rcc_ahb1enr) rtc and rtc backup registers the real-time clock (rtc) is an independent bcd timer/counter. the rtc provides a time- of-day clock/calendar, two programmable alarm interrupts, and a periodic programmable wakeup flag with interrupt capability. the rtc co ntains 20 backup data registers (80 bytes) power control (pwr) RM0033 66/1317 doc id 15403 rev 3 which are reset when a tamper detection event occurs. for more details refer to section 22: real-time clock (rtc) . backup sram the backup domain includes 4 kbytes of backup sram accessible only from the cpu, and address in 32-bit, 16-bit or 8-bit mode. its content is retained even in standby or v bat mode when the low power backup regulator is enabled. it can be considered as an internal eeprom when v bat is always present. when the backup domain is supplied by v dd (analog switch connected to v dd ), the backup sram is powered from v dd which replaces the v bat power supply to save battery life. when the backup domain is supplied by v bat (analog switch connected to v bat because v dd is not present), the backup sram is powered by a dedicated low power regulator. this regulator can be on or off depending whether the application needs the backup sram function in standby and v bat modes or not. the power down of this regulator is controlled by a dedicated bit, the bre control bit of the pwr_csr register (see section 4.4.2: pwr power control/status register (pwr_csr) ). the backup sram is not mass erased by an tamper event. it is read protected to prevent confidential data, such as cryptographic private key, from being accessed. the backup sram can be erased only through the flash in terface when a protection level change from level 1 to level 0 is requested. refer to the description of read protection (rdp) in the flash programming manual. figure 4. backup sram 4.1.3 voltage regulator an embedded linear voltage regulator supplies all the digital circuitries except for the backup domain and the standby circuitry. the regulator output voltage is 1.2 v. this voltage regulator requires two external capacitors to be connected to two dedicated pins, v cap_1 and v cap_2 available in all packages. voltage regulator backup domain 1.2 v domain backup sram 1.2 v backup sram interface 3.3->1.2 lp voltage regulator 3.3->1.2 rtc lse 32.768 hz power switch RM0033 power control (pwr) doc id 15403 rev 3 67/1317 the voltage regulator is always enabled after reset. it works in three different modes depending on the application modes. in run mode, the regulator supplies full power to the 1.2 v domain (core, memories and digital peripherals). in stop mode the regulator supplies low power to the 1.2 v domain, preserving the content of registers and internal sram. in standby mode, the regulator is powered down. the content of the registers and sram are lost except for the standby circuitry and the backup domain. note: depending on the selected package, the voltage regulator can be deactivated. for more details, refer to the voltage regulator section in stm32f2xx datasheets. 4.2 power supply supervisor 4.2.1 power-on reset (por)/power-down reset (pdr) the device has an integrated por/pdr circuitry that allows proper operation starting from/down to 1.8 v. the device remains in reset mode when v dd /v dda is below a specified threshold, v por/pdr , without the need for an external reset circuit. for more details concerning the power on/power-down reset threshold, refer to the electrical characteristics of the datasheet. figure 5. power-on reset/power-down reset waveform v dd /v dda reset 40 mv hysteresis por pdr temporization t rsttempo power control (pwr) RM0033 68/1317 doc id 15403 rev 3 4.2.2 brownout reset (bor) during power on, the brownout reset (bor) keeps the device under reset until the supply voltage reaches the specified v bor threshold. v bor is configured through device option bytes. by default, bor is off. 4 programmable v bor thresholds can be selected. bor off (v bor0 ): reset threshold level for 1.8 to 2.10 v voltage range bor level 1 (v bor1 ): reset threshold level for 2.10 to 2.40 v voltage range bor level 2 (v bor2 ): reset threshold level for 2.40 to 2.70 v voltage range bor level 3 (v bor3 ): reset threshold level for 2.70 to 3.60 v voltage range when the supply voltage (v dd ) drops below the selected v bor threshold, a device reset is generated. bor can be disabled by programming the device option bytes. to disable the bor function, v dd must have been higher than v bor0 to start the device option byte programming sequence. the power down is then monitored by the pdr (see section 4.2.1: power-on reset (por)/power-down reset (pdr) ) the bor threshold hysteresis is ~100 mv (between the rising and the falling edge of the supply voltage). figure 6. bor thresholds 4.2.3 programmable vo ltage detector (pvd) you can use the pvd to monitor the v dd /v dda power supply by comparing it to a threshold selected by the pls[2:0] bits in the pwr power control register (pwr_cr) . the pvd is enabled by setting the pvde bit. a pvdo flag is available, in the pwr power control/status register (pwr_csr) , to indicate if v dd /v dda is higher or lower than the pvd threshold. this event is internally connected to the exti line16 and can generate an interrupt if enabled through the exti registers. the pvd output interrupt can be generated when v dd /v dda drops below the pvd threshold and/or when v dd /v dda rises above the pvd threshold depending on exti line16 v dd /v dda reset 100 mv hysteresis bor threshold RM0033 power control (pwr) doc id 15403 rev 3 69/1317 rising/falling edge configuration. as an example the service routine could perform emergency shutdown tasks. figure 7. pvd thresholds 4.3 low-power modes by default, the microcontroller is in run mode after a system or a power-on reset. in run mode the cpu is clocked by hclk and the program code is executed. several low-power modes are available to save power when the cpu does not need to be kept running, for example when waiting for an external event. it is up to the user to select the mode that gives the best compromise between low-power consumption, short startup time and available wakeup sources. the devices feature three low-power modes: sleep mode (cortex-m3 core stopped, peripherals kept running) stop mode (all clocks are stopped) standby mode (1.2 v domain powered off) in addition, the power consumption in run mode can be reduce by one of the following means: slowing down the system clocks gating the clocks to the apbx and ahbx peripherals when they are unused. v dd /v dda pvd output 100 mv hysteresis pvd threshold power control (pwr) RM0033 70/1317 doc id 15403 rev 3 4.3.1 slowing down system clocks in run mode the speed of the system clocks (sysclk, hclk, pclk1, pclk2) can be reduced by programming the prescaler registers. these prescalers can also be used to slow down peripherals before entering sleep mode. for more details refer to section 5.3.3: rcc clock config uration register (rcc_cfgr) . 4.3.2 peripheral clock gating in run mode, the hclkx and pclkx for individual peripherals and memories can be stopped at any time to reduce power consumption. to further reduce power consumption in sle ep mode the peripheral clocks can be disabled prior to executing the wf i or wfe instructions. peripheral clock gating is controlled by the ahb1 peripheral clock enable register (rcc_ahb1enr), ahb2 peripheral clock enable register (rcc_ahb2enr), ahb3 peripheral clock enable register (rcc_ahb3enr) (see rcc apb1 peripheral clock enable register (rcc_apb1enr) and rcc apb2 peripheral clock enable register (rcc_apb2enr) ). disabling the peripherals clocks in sleep mode can be performed automatically by resetting the corresponding bit in rcc_ahbx lpenr and rcc_apbxlpenr registers. table 7. low-power mode summary mode name entry wakeup effect on 1.2 v domain clocks effect on v dd domain clocks voltage regulator sleep (sleep now or sleep-on-exit) wfi any interrupt (1) cpu clk off no effect on other clocks or analog clock sources none on wfe wakeup event (1) stop pdds and lpds bits + sleepdeep bit + wfi or wfe any exti line (configured in the exti registers, internal and external lines) (2) all 1.2 v domain clocks off hsi and hse oscillators off on or in low- power mode (depends on pwr power control register (pwr_cr) ) standby pdds bit + sleepdeep bit + wfi or wfe wkup pin rising edge, rtc alarm (alarm a or alarm b), rtc wakeup event, rtc tamper event, rtc time stamp event, external reset in nrst pin, iwdg reset (3) off 1. when the microcontroller is supplied from v bat , the device cannot be woken up from sl eep mode by an external interrupt or a wakeup event. 2. when the microcontroller is supplied from v bat , the device cannot be woken up from stop mode by an external interrupt or a wakeup event. 3. when the microcontroller is supplied from v bat , only an rtc alarm/event or an external reset can wake up the device provided v dd is supplied by an external battery. RM0033 power control (pwr) doc id 15403 rev 3 71/1317 4.3.3 sleep mode entering sleep mode the sleep mode is entered by executing the wfi (wait for interrupt) or wfe (wait for event) instructions. two options are available to select the sleep mode entry mechanism, depending on the sleeponexit bit in t he cortex-m3 system control register: sleep-now: if the sleeponexit bit is cleared, the mcu enters sleep mode as soon as wfi or wfe instruction is executed. sleep-on-exit: if the sleeponexit bit is se t, the mcu enters sleep mode as soon as it exits the lowest priority isr. refer to ta b l e 8 and ta bl e 9 for details on how to enter sleep mode. exiting sleep mode if the wfi instruction is used to enter sleep mode, any peripheral interrupt acknowledged by the nested vectored interrupt controller (nvic) can wake up the device from sleep mode. if the wfe instruction is used to enter sleep mode, the mcu exits sleep mode as soon as an event occurs. the wakeup event can be generated either by: enabling an interrupt in the peripheral control register but not in the nvic, and enabling the sevonpend bit in the cortex-m3 system control register. when the mcu resumes from wfe, the peripheral interrupt pending bit and the peripheral nvic irq channel pending bit (in the nvic interrupt clear pending register) have to be cleared. or configuring an external or internal exti line in event mode. when the cpu resumes from wfe, it is not necessary to clear the peripheral interrupt pending bit or the nvic irq channel pending bit as the pending bit corresponding to the event line is not set. this mode offers the lowest wakeup time as no time is wasted in interrupt entry/exit. refer to ta b l e 8 and ta bl e 9 for more details on how to exit sleep mode. table 8. sleep-now sleep-now mode description mode entry wfi (wait for interrupt) or wfe (wait for event) while: ? sleepdeep = 0 and ? sleeponexit = 0 refer to the cortex?-m3 system control register. mode exit if wfi was used for entry: interrupt: refer to table 20: vector table if wfe was used for entry wakeup event: refer to section 8.2.3: wakeup event management wakeup latency none power control (pwr) RM0033 72/1317 doc id 15403 rev 3 4.3.4 stop mode the stop mode is based on the cortex-m3 deepsleep mode combined with peripheral clock gating. the voltage regulator can be configured either in normal or low-power mode. in stop mode, all clocks in the 1.2 v domain are stopped, the plls, the hsi and the hse rc oscillators are disabled. internal sram and register contents are preserved. by setting the fpds bit in the pwr_cr register, the flash memory also enters power down mode when the device enters stop mode. when the flash memory is in power down mode, an additional startup delay is incurred when waking up from stop mode. entering stop mode refer to ta b l e 1 0 for details on how to enter the stop mode. to further reduce power consumption in stop mode, the internal voltage regulator can be put in low-power mode. this is configured by the lpds bit of the pwr power control register (pwr_cr) . if flash memory programming is ongoing, the stop mode entry is delayed until the memory access is finished. if an access to the apb domain is ongoing, the stop mo de entry is delayed until the apb access is finished. in stop mode, the following features can be selected by programming individual control bits: independent watchdog (iwdg): the iwdg is started by writing to its key register or by hardware option. once started it cannot be stopped except by a reset. see section 17.3 in section 17: independent watchdog (iwdg) . real-time clock (rtc): this is co nfigured by the rtcen bit in the rcc backup domain control register (rcc_bdcr) internal rc oscillator (lsi rc): this is configured by the lsion bit in the rcc clock control & status register (rcc_csr) . external 32.768 khz oscillator (lse osc): th is is configured by the lseon bit in the rcc backup domain cont rol register (rcc_bdcr) . the adc or dac can also consume power during the stop mode, unless they are disabled before entering it. to disable them, the adon bit in the adc_cr2 register and the enx bit in the dac_cr register must both be written to 0. table 9. sleep-on-exit sleep-on-exit description mode entry wfi (wait for interrupt) while: ? sleepdeep = 0 and ? sleeponexit = 1 refer to the cortex?-m3 system control register. mode exit interrupt: refer to table 20: vector table . wakeup latency none RM0033 power control (pwr) doc id 15403 rev 3 73/1317 exiting stop mode refer to ta b l e 1 0 for more details on how to exit stop mode. when exiting stop mode by issuin g an interrupt or a wakeup event, the hsi rc oscillator is selected as system clock. when the voltage regulator operates in low-power mode, an additional startup delay is incurred when waking up from stop mode. by keeping the internal regulator on during stop mode, the consumption is higher al though the startup time is reduced. 4.3.5 standby mode the standby mode allows to achieve the lowest power consumption. it is based on the cortex-m3 deepsleep mode, with the voltage regulator disabled. the 1.2 v domain is consequently powered off. the plls, the hs i oscillator and the h se oscillator are also switched off. sram and register contents are lost except for registers in the backup domain (rtc registers, rtc backup register and backup sram), and standby circuitry (see figure 3 ). table 10. stop mode stop mode description mode entry wfi (wait for interrupt) or wfe (wait for event) while: ? set sleepdeep bit in cortex? -m3 system control register ? clear pdds bit in power control register (pwr_cr) ? select the voltage regulator mode by configuring lpds bit in pwr_cr note: to enter the stop mode, all exti line pending bits (in pending register (exti_pr) ), the rtc alarm (alarm a and alarm b), rtc wakeup, rtc tamper, and rtc time stamp flags, must be reset. otherwise, the stop mode entry procedure is ignored and program execution continues. mode exit if wfi was used for entry: all exti lines configured in interrupt mode (the corresponding exti interrupt vector must be enabled in the nvic). refer to table 20: vector table on page 159 . if wfe was used for entry: all exti lines configured in event mode. refer to section 8.2.3: wakeup event management on page 164 wakeup latency hsi rc wakeup time + regulator wakeup time from low-power mode power control (pwr) RM0033 74/1317 doc id 15403 rev 3 entering standby mode refer to ta b l e 1 1 for more details on how to enter standby mode. in standby mode, the following features can be selected by programming individual control bits: independent watchdog (iwdg): the iwdg is started by writing to its key register or by hardware option. once started it cannot be stopped except by a reset. see section 17.3 in section 17: independent watchdog (iwdg) . real-time clock (rtc): this is configur ed by the rtcen bit in the backup domain control register (rcc_bdcr) internal rc oscillator (lsi rc): this is configured by the lsio n bit in the control/status register (rcc_csr). external 32.768 khz oscillator (lse osc): th is is configured by the lseon bit in the backup domain control register (rcc_bdcr) exiting standby mode the microcontroller exits standby mode when an external reset (nrst pin), an iwdg reset, a rising edge on wkup pin, an rtc alarm, a tamper event, or a time stamp event is detected. all registers are reset after wakeup from standby except for pwr power control/status register (pwr_csr) . after waking up from standby mode, program execution restarts in the same way as after a reset (boot pins sampling, vector reset is fetched, etc.). the sbf status flag in the pwr power control/status register (pwr_csr) indicates that the mcu was in standby mode. refer to ta b l e 1 1 for more details on how to exit standby mode. i/o states in standby mode in standby mode, all i/o pins are high impedance except for: reset pad (still available) rtc_af1 pin (pc13) if configured for tamper, time stamp, rtc alarm out, or rtc clock calibration out rtc_af2 pin (pi8) if configured for tamper or time stamp wkup pin (pa0), if enabled table 11. standby mode standby mode description mode entry wfi (wait for interrupt) or wfe (wait for event) while: ? set sleepdeep in cortex?-m3 system control register ? set pdds bit in power control register (pwr_cr) ? clear wuf bit in power control/status register (pwr_csr) ? clear the rtc flag corresponding to the chosen wakeup source (rtc alarm a, rtc alarm b, rtc wakeup, tamper or timestamp flags) mode exit wkup pin rising edge, rtc alarm (alarm a and alarm b), rtc wakeup, tamper event, time stamp event, extern al reset in nrst pin, iwdg reset. wakeup latency reset phase. RM0033 power control (pwr) doc id 15403 rev 3 75/1317 debug mode by default, the debug connection is lost if the application puts the mcu in stop or standby mode while the debug features are used. this is due to the fact that the cortex?-m3 core is no longer clocked. however, by setting some configuration bits in the dbgmcu_cr register, the software can be debugged even when using the low-power modes extensively. for more details, refer to section 32.16.1: debug support for low-power modes . 4.3.6 programming the rtc alternate functions to wa ke up the device from the stop and standby modes the mcu can be woken up from a low-power mode by an rtc alternate function. the rtc alternate functions are the rtc alarms (alarm a and alarm b), rtc wakeup, rtc tamper event detection and rtc time stamp event detection. these rtc alternate functions can wake up the system from the stop and standby low- power modes. the system can also wake up from low-power modes without depending on an external interrupt (auto-wakeup mode), by using the rtc alarm or the rtc wakeup events. the rtc provides a programmable time base for waking up from the stop or standby mode at regular intervals. for this purpose, two of the three alternate rtc clock sources can be selected by programming the rtcsel[1:0] bits in the rcc backup domain control register (rcc_bdcr) : low-power 32.768 khz external crystal oscillator (lse osc) this clock source provides a precise time base with a very low-power consumption (additional consumption of less than 1 a under typical conditions) low-power internal rc oscillator (lsi rc) this clock source has the advantage of savi ng the cost of the 32.768 khz crystal. this internal rc oscillator is de signed to use minimum power. power control (pwr) RM0033 76/1317 doc id 15403 rev 3 rtc alternate functions to wake up the device from the stop mode to wake up the device from the stop mode with an rtc alarm event, it is necessary to: a) configure the exti line 17 to be sensitive to rising edges (interrupt or event modes) b) enable the rtc alarm interrupt in the rtc_cr register c) configure the rtc to generate the rtc alarm to wake up the device from the stop mode with an rtc tamper or time stamp event, it is necessary to: a) configure the exti line 21 to be sensitive to rising edges (interrupt or event modes) b) enable the rtc time stamp interrupt in the rtc_cr register or the rtc tamper interrupt in the rtc_tafcr register c) configure the rtc to detect the tamper or time stamp event to wake up the device from the stop mode with an rtc wakeup event, it is necessary to: a) configure the exti line 22 to be sensitive to rising edges (interrupt or event modes) b) enable the rtc wakeup interrupt in the rtc_cr register c) configure the rtc to generate the rtc wakeup event rtc alternate functions to wake up the device from the standby mode to wake up the device from the standby mode with an rtc alarm event, it is necessary to: a) enable the rtc alarm interrupt in the rtc_cr register b) configure the rtc to generate the rtc alarm to wake up the device from the standby mode with an rtc tamper or time stamp event, it is necessary to: a) enable the rtc time stamp interrupt in the rtc_cr register or the rtc tamper interrupt in the rtc_tafcr register b) configure the rtc to detect the tamper or time stamp event to wake up the device from the standby mode with an rtc wakeup event, it is necessary to: a) enable the rtc wakeup interrupt in the rtc_cr register b) configure the rtc to generate the rtc wakeup event RM0033 power control (pwr) doc id 15403 rev 3 77/1317 safe rtc alternate function wakeup flag clearing sequence if the selected rtc alternate function is set before the pwr wakeup flag (wutf) is cleared, it will not be detected on the next event as detection is made on ce on the rising edge. to avoid bouncing on the pins onto which the rtc alternate functions are mapped, and exit correctly from the stop and standby modes, it is recommended to follow the sequence below before entering the standby mode: when using rtc alarm to wake up the device from the low-power modes: a) disable the rtc alarm interrupt (alraie or alrbie bits in the rtc_cr register) b) clear the rtc alarm (alraf/alrbf) flag c) clear the pwr wakeup (wuf) flag d) enable the rtc alarm interrupt e) re-enter the low-power mode when using rtc wakeup to wake up the device from the low-power modes: a) disable the rtc wakeup interrupt (wutie bit in the rtc_cr register) b) clear the rtc wakeup (wutf) flag c) clear the pwr wakeup (wuf) flag d) enable the rtc wakeup interrupt e) re-enter the low power mode when using rtc tamper to wake up the device from the low-power modes: a) disable the rtc tamper interrupt (tampie bit in the rtc_tafcr register) b) clear the tamper (tamp1f/tsf) flag c) clear the pwr wakeup (wuf) flag d) enable the rtc tamper interrupt e) re-enter the low-power mode when using rtc time stamp to wake up the device from the low-power modes: a) disable the rtc time stamp interrupt (tsie bit in rtc_cr) b) clear the rtc time stamp (tsf) flag c) clear the pwr wakeup (wuf) flag d) enable the rtc timestamp interrupt e) re-enter the low-power mode power control (pwr) RM0033 78/1317 doc id 15403 rev 3 4.4 power control registers 4.4.1 pwr power contro l register (pwr_cr) address offset: 0x00 reset value: 0x0000 0000 (reset by wakeup from standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 reserved fpds dbp pls[2:0] pvde csbf cwuf pdds lpds rw rw rw rw rw rw rc_w1 rc_w1 rw rw bits 31:10 reserved, always read as 0. bit 9 fpds : flash power down in stop mode when set, the flash memory enters power down mode when the device enters stop mode. this allows to achieve a lower consumption in stop mode but a longer restart time. 0: flash memory not in power down when the device is in stop mode 1: flash memory in power down when the device is in stop mode bit 8 dbp : disable backup domain write protection in reset state, the rcc_bdcr register, the rtc re gisters (including the backup registers), and the bre bit of the pwr_csr register, are protected against parasitic write access. this bit must be set to enable write access to these registers. 0: access to rtc and rtc backup registers and backup sram disabled 1: access to rtc and rtc backup registers and backup sram enabled bits 7:5 pls[2:0]: pvd level selection these bits are written by software to select the voltage threshold detected by the power voltage detector 000: 2.0 v 001: 2.1 v 010: 2.3 v 011: 2.5 v 100: 2.6 v 101: 2.7 v 110: 2.8 v 111: 2.9 v note: refer to the electrical characteri stics of the datasheet for more details. bit 4 pvde: power voltage detector enable this bit is set and cleared by software. 0: pvd disabled 1: pvd enabled bit 3 csbf : clear standby flag this bit is always read as 0. 0: no effect 1: clear the sbf standby flag (write). RM0033 power control (pwr) doc id 15403 rev 3 79/1317 4.4.2 pwr power control/stat us register (pwr_csr) address offset: 0x04 reset value: 0x0000 0000 (not reset by wakeup from standby mode) additional apb cycles are neede d to read this register versus a standard apb read. bit 2 cwuf: clear wakeup flag this bit is always read as 0. 0: no effect 1: clear the wuf wakeup flag after 2 system clock cycles bit 1 pdds : power down deepsleep this bit is set and cleared by software. it works together with the lpds bit. 0: enter stop mode when the cpu enters deepsleep. the regulator status depends on the lpds bit. 1: enter standby mode when the cpu enters deepsleep. bit 0 lpds: low-power deep sleep this bit is set and cleared by software. it works together with the pdds bit. 0: voltage regulator on during stop mode 1: voltage regulator in low-power mode during stop mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved res. 1514131211109876543210 reserved res. bre ewup reserved res. brr pvdo sbf wuf rw rw r r r r bits 31:10 reserved, always read as 0. bit 9 bre : backup regulator enable when set, the backup regulator (used to main tain backup sram content in standby and v bat modes) is enabled. if bre is reset, the backup regulator is switched off. the backup sram can still be used but its content will be lost in the standby and v bat modes. once set, the application must wait that the backup regulator ready flag (brr) is set to indicate that the data written into the ram will be maintained in the standby and v bat modes. 0: backup regulator disabled 1: backup regulator enabled note: this bit is not reset when the device wakes up from standby mode, by a system reset, or by a power reset. bit 8 ewup : enable wkup pin this bit is set and cleared by software. 0: wkup pin is used for general purpose i/o. an event on the wkup pin does not wakeup the device from standby mode. 1: wkup pin is used for wakeup from standby mode and forced in input pull down configuration (rising edge on wkup pin wa kes-up the system from standby mode). note: this bit is reset by a system reset. bits 7:4 reserved, always read as 0. power control (pwr) RM0033 80/1317 doc id 15403 rev 3 4.4.3 pwr register map the following table summarizes the pwr registers. refer to table 1 on page 50 for the register boundary addresses. bit 3 brr : backup regulator ready set by hardware to indicate that the backup regulator is ready. 0: backup regulator not ready 1: backup regulator ready note: this bit is not reset when the device wake s up from standby mode or by a system reset or power reset. bit 2 pvdo: pvd output this bit is set and cleared by hardware. it is valid only if pvd is enabled by the pvde bit. 0: v dd /v dda is higher than the pvd threshold selected with the pls[2:0] bits. 1: v dd /v dda is lower than the pvd threshold selected with the pls[2:0] bits. note: the pvd is stopped by standby mode. for this reason, this bit is equal to 0 after standby or reset until the pvde bit is set. bit 1 sbf: standby flag this bit is set by hardware and cleared only by a por/pdr (power-on reset/power-down reset) or by setting the csbf bit in the pwr power control register (pwr_cr) 0: device has not been in standby mode 1: device has been in standby mode bit 0 wuf: wakeup flag this bit is set by hardware and cleared only by a por/pdr (power-on reset/power-down reset) or by setting the cwuf bit in the pwr power control register (pwr_cr) 0: no wakeup event occurred 1: a wakeup event was received from the wkup pin or from the rtc alarm (alarm a or alarm b), rtc tamper event, rtc timestamp event or rtc wakeup). note: an additional wakeup event is detected if the wkup pin is enabled (by setting the ewup bit) when the wkup pin level is already high. table 12. pwr - register map and reset values offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x000 pwr_cr reserved fpds dbp pls[2:0] pvde csbf cwuf pdds lpds reset value 0000000000 0x004 pwr_csr reserved bre ewup reserved brr pvdo sbf wuf reset value 00 0000 RM0033 reset and clock control (rcc) doc id 15403 rev 3 81/1317 5 reset and clock control (rcc) 5.1 reset there are three types of reset, defined as system reset, power reset and backup domain reset. 5.1.1 system reset a system reset sets all register s to their reset values except the reset flags in the clock controller csr register and the registers in the backup domain (see figure 4 ). a system reset is generated when one of the following events occurs: 1. a low level on the nrst pin (external reset) 2. window watchdog end of count condition (wwdg reset) 3. independent watchdog end of count condition (iwdg reset) 4. a software reset (sw reset) (see software reset ) 5. low-power management reset (see low-power management reset ) software reset the reset source can be identified by checking the reset flags in the rcc clock control & status register (rcc_csr) . the sysresetreq bit in cortex?-m3 applicatio n interrupt and rese t control register must be set to force a software reset on the device. refer to the cortex?-m3 technical reference manual for more details. reset and clock control (rcc) RM0033 82/1317 doc id 15403 rev 3 low-power management reset there are two ways of generating a low-power management reset: 1. reset generated when entering the standby mode: this type of reset is enabled by resetting the nrst_stdby bit in the user option bytes. in this case, whenever a standby mode entry sequence is successfully executed, the device is reset instead of entering the standby mode. 2. reset when entering the stop mode: this type of reset is enabled by resetting the nrst_stop bit in the user option bytes. in this case, whenever a stop mode entry sequence is successfully executed, the device is reset instead of entering the stop mode. for further information on the user option bytes, refer to the stm32f20x and stm32f21x flash programming manual available from your st sales office. 5.1.2 power reset a power reset is generated when one of the following events occurs: 1. power-on/power-down reset (por/pdr reset) or brownout (bor) reset 2. when exiting the standby mode a power reset sets all registers to their reset values except the backup domain (see figure 4 ) these sources act on the nrst pin and it is always kept low during the delay phase. the reset service routine vect or is fixed at address 0x0000_0004 in the memory map. for more details, refer to table 20: vector table on page 159 . the system reset signal provided to the device is output on the nrst pin. the pulse generator guarantees a minimum reset pulse duration of 20 s for each reset source (external or internal reset). in case of an external reset, the reset pulse is generated while the nrst pin is asserted low. figure 8. simplified diagram of the reset circuit the backup domain has two specific resets that affect only the backup domain (see figure 4 ). . 2 3 4 2 0 5 6 $ $ 6 $ $ ! 7 7 $ ' r e s e t ) 7 $ ' r e s e t 0 u l s e g e n e r a t o r 0 o w e r r e s e t % x t e r n a l r e s e t m i n ? s 3 y s t e m r e s e t & i l t e r 3 o f t w a r e r e s e t , o w p o w e r m a n a g e m e n t r e s e t a i b RM0033 reset and clock control (rcc) doc id 15403 rev 3 83/1317 5.1.3 backup domain reset the backup domain reset sets all rtc regist ers and the rcc_bdcr regi ster to their reset values. the bkpsram is not affected by th is reset. the only way of resetting the bkpsram is through the fl ash interface by requ esting a protection le vel change from 1 to 0. a backup domain reset is generated when one of the following events occurs: 1. software reset, triggered by setting the bdrst bit in the rcc backup domain control register (rcc_bdcr) . 2. v dd or v bat power on, if both supplies have previously been powered off. 5.2 clocks three different clock sources can be us ed to drive the system clock (sysclk): hsi oscillator clock hse oscillator clock main pll (pll) clock the devices have the two following secondary clock sources: 32 khz low-speed internal rc (lsi rc) which drives the independent watchdog and, optionally, the rtc used for auto-wakeup from the stop/standby mode. 32.768 khz low-speed external crystal (lse crystal) which optionally drives the rtc clock (rtcclk) each clock source can be switched on or off independently when it is not used, to optimize power consumption. reset and clock control (rcc) RM0033 84/1317 doc id 15403 rev 3 figure 9. clock tree 1. for full details about the internal and ex ternal clock source characteristics, refer to the el ectrical charac teristics sectio n in 0 , , 6 # / x . 0 1 2 - t o 0 ( 9 % t h e r n e t t o - ( z 5 3 " 0 ( 9 t o - ( z - ) ) ? 2 - ) ) ? 3 % , i n 3 9 3 # & ' ? 0 - # ! ( " 0 2 % 3 # ! 0 " x 0 2 % 3 # i f ! 0 " x p r e s c x e l s e x , 3 % % 4 ( ? - ) ) ? 4 8 ? # , + ? - ) ) / 4 ' ? ( 3 ? 3 # , 0 , , ) 3 # , + & # , + # o r t e x f r e e r u n n i n g c l o c k ! 0 " x p e r i p h e r a l c l o c k s ! 0 " x t i m e r c l o c k s - ( z c l o c k s 5 3 " ( 3 5 , 0 ) c l o c k % t h e r n e t 0 4 0 c l o c k - # / 0 e r i p h e r a l c l o c k e n a b l e t o - # / a i c % 4 ( ? - ) ) ? 2 8 ? # , + ? - ) ) / 3 # ? ) . / 3 # ? / 5 4 , 3 % / 3 # k ( z , 3 ) 2 # k ( z t o i n d e p e n d e n t w a t c h d o g , 3 % , 3 ) t o 2 4 # 2 4 # # , + 2 4 # 3 % , ; = ) 7 $ ' # , + ( 3 % / 3 # - ( z / 3 # ? ) . / 3 # ? / 5 4 ( 3 ) 2 # - ( z 0 , , # , + ( 3 ) ( 3 ) ( 3 % 3 7 3 9 3 # , + - ( z m a x ( # , + t o ! ( " b u s c o r e m e m o r y a n d $ - ! - ( z m a x t o # o r t e x 3 y s t e m t i m e r # l o c k % n a b l e 0 e r i p h e r a l c l o c k e n a b l e 0 , , # + ) 3 c l o c k s 0 e r i p h e r a l c l o c k e n a b l e 0 e r i p h e r a l c l o c k e n a b l e - ! # 2 - ) ) # , + - ! # 4 8 # , + - ! # 2 8 # , + t o % t h e r n e t - ! # 0 e r i p h e r a l c l o c k e n a b l e 0 e r i p h e r a l c l o c k e n a b l e 7 a t c h d o g e n a b l e 2 4 # e n a b l e 0 e r i p h e r a l c l o c k e n a b l e 0 e r i p h e r a l c l o c k e n a b l e 0 e r i p h e r a l c l o c k e n a b l e t o 0 , , ) 3 6 # / x . 0 1 2 3 9 3 # , + % x t c l o c k ) 3 ? # + ) . ) 3 3 2 # ( 3 % ? 2 4 # ( 3 % RM0033 reset and clock control (rcc) doc id 15403 rev 3 85/1317 the device datasheet the clock controller provides a high degree of fl exibility to the application in the choice of the external crystal or the oscillator to run the core and peripherals at the highest frequency and, guarantee the appropriate frequency for peripherals that need a specific clock like ethernet, usb otg fs and hs, i2s and sdio. several prescalers are used to configure the ahb frequency, th e high-speed apb (apb2) and the low-speed apb (apb1) do mains. the maximum frequen cy of the ahb domain is 120 mhz. the maximum allowed frequency of the high-speed apb2 domain is 60 mhz. the maximum allowed freque ncy of the low-speed apb1 domain is 30 mhz all peripheral clocks are derived from the system clock (sysclk) except for: the usb otg fs clock (48 mhz), the random analog generator (rng) clock ( 48 mhz) and the sdio clock ( 48 mhz) which are coming from a specific output of pll (pll48clk) the i2s clock to achieve high-quality audio performance, the i2s clock can be derived either from a specific pll (plli2s) or from an external clock mapped on the i2s_ckin pin. for more information about i2s clock frequency and precision, refer to section 25.4.3: clock generator . the usb otg hs (60 mhz) clock which is provided from the external phy the ethernet mac clocks (tx, rx and rmii) which are provided from the external phy. for further information on the ethernet configuration, please refer to section 28.4.4: mi i/rmii selection in the ethernet peripheral description. when the ethernet is used, the ahb clock frequency must be at least 25 mhz. the rcc feeds the external clock of the cortex system timer (systick) with the ahb clock (hclk) divided by 8. the systick can work either with this clock or with the cortex clock (hclk), configurable in the systick control and status register. the timer clock frequencies are automatically set by hardware. there are two cases: 1. if the apb prescaler is 1, the timer clock fr equencies are set to th e same frequency as that of the apb domain to which the timers are connected. 2. otherwise, they are set to twice (2) the frequency of the apb domain to which the timers are connected. fclk acts as cortex?-m3 free-running clock. for more details, refer to the cortex?-m3 technical reference manual. 5.2.1 hse clock the high speed external clock signal (hse) can be generated from two possible clock sources: hse external crystal/ceramic resonator hse external user clock the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to mi nimize output distortion and startup stabilization time. the loading capacitance values must be adjust ed according to the selected oscillator. reset and clock control (rcc) RM0033 86/1317 doc id 15403 rev 3 external source (hse bypass) in this mode, an external clock source must be provided. you select this mode by setting the hsebyp and hseon bits in the rcc clock control register (rcc_cr) . the external clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the osc_in pin while the osc_out pin should be left hi-z. see figure 10 . external crystal/ceramic resonator (hse crystal) the hse has the advantage of producing a very accurate rate on the main clock. the associated hardware configuration is shown in figure 10 . refer to the electrical characteristics section of the datasheet for more details. the hserdy flag in the rcc clock control register (rcc_cr) indicates if the high-speed external oscillator is stable or not. at startup, the clock is not released until this bit is set by hardware. an interrupt can be generated if enabled in the rcc clock interrupt register (rcc_cir) . the hse crystal can be switched on and off using the hseon bit in the rcc clock control register (rcc_cr) . 5.2.2 hsi clock the hsi clock signal is genera ted from an internal 16 mhz rc oscillator an d can be used directly as a system clock, or used as pll input. the hsi rc oscillator has the advantage of provid ing a clock source at low cost (no external components). it also has a faster startup time than the hse crystal oscillator however, even with calibration the frequency is less accurate th an an external crystal oscillator or ceramic resonator. figure 10. hse/ lse clock sources hardware configuration external clock crystal/ceramic resonators osc_out external source (hiz) osc_in osc_out load capacitors c l2 c l1 RM0033 reset and clock control (rcc) doc id 15403 rev 3 87/1317 calibration rc oscillator frequencies can vary from one ch ip to another due to manufacturing process variations, this is why each device is factory calibrated by st for 1% accuracy at t a = 25 c. after reset, the factory calibration value is loaded in the hsical[7:0] bits in the rcc clock control register (rcc_cr) . if the application is subject to voltage or temperature variations this may affect the rc oscillator speed. you can trim the hsi frequency in the applic ation using the hsitrim[4:0] bits in the rcc clock control register (rcc_cr) . the hsirdy flag in the rcc clock control register (rcc_cr) indicates if the hsi rc is stable or not. at startup, the hsi rc output clock is not released until this bit is set by hardware. the hsi rc can be switched on and off using the hsion bit in the rcc clock control register (rcc_cr) . the hsi signal can also be used as a backup source (auxiliary clock) if the hse crystal oscillator fails. refer to section 5.2.7: clock security system (css) on page 88 . 5.2.3 pll configuration the stm32f2xx devices feature two plls: a main pll (pll) clocked by the hse or hsi oscillator and feat uring two different output clocks: ? the first output is used to generate the high speed system clock (up to 120 mhz) ? the second output is used to generate the clock for the usb otg fs (48 mhz), the random analog generator ( 48 mhz) and the sdio ( 48 mhz). a dedicated pll (plli2s) used to generate an accurate clock to achieve high-quality audio performance on the i2s interface. since the main-pll configuration parameters cannot be changed once pll is enabled, it is recommended to configure pll be fore enabling it (selection of the hsi or hse oscillator as pll clock source, and configuration of division factors m, n, p, and q). the plli2s uses the same input clock as pl l (pllm[5:0] and pllsrc bits are common to both plls). however, the plli2s has dedicated enable/disable and division factors (n and r) configuration bits. once the plli2s is enabled, the configuration parameters cannot be changed. the two plls are disabled by hardware when entering stop and standby modes, or when an hse failure occurs when hse or pll (clocked by hse) are used as system clock. rcc pll configuration register (rcc_pllcfgr) and rcc clock configuration register (rcc_cfgr) can be used to configure pll and plli2s, respectively. 5.2.4 lse clock the lse crystal is a 32.768 khz low-speed external (lse) crystal or ceramic resonator. it has the advantage providing a low-power but highly accurate clock source to the real-time clock peripheral (rtc) for clock/calendar or other timing functions. the lse crystal is switched on and off using the lseon bit in rcc backup domain control register (rcc_bdcr) . reset and clock control (rcc) RM0033 88/1317 doc id 15403 rev 3 the lserdy flag in the rcc backup domain cont rol register (rcc_bdcr) indicates if the lse crystal is stable or not. at startup, the lse crystal output clock signal is not released until this bit is set by hardware. an interrupt can be generated if enabled in the rcc clock interrupt register (rcc_cir) . external source (lse bypass) in this mode, an external clock source must be provided. it must have a frequency up to 1 mhz. you select this mode by setting the lsebyp and lseon bits in the rcc backup domain control re gister (rcc_bdcr) . the external clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the osc32_in pin while the osc32_out pin should be left hi-z. see figure 10 . 5.2.5 lsi clock the lsi rc acts as an low-power clock source that can be kept running in stop and standby mode for the independent watchdog (iwdg) and auto-wakeup unit (awu). the clock frequency is around 32 khz. for more det ails, refer to the electrical characteristics section of the datasheets. the lsi rc can be switched on and off using the lsion bit in the rcc clock control & status register (rcc_csr) . the lsirdy flag in the rcc clock control & status register (rcc_csr) indicates if the low- speed internal oscillator is stable or not. at startup, the cloc k is not released until this bit is set by hardware. an interrupt can be generated if enabled in the rcc clock interrupt register (rcc_cir) . 5.2.6 system clock (sysclk) selection after a system reset, the hsi osc illator is selected as the syst em clock. when a clock source is used directly or through pll as the system clock, it is not possible to stop it. a switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or pll locked) . if a clock source that is not yet ready is selected, the switch occurs when the clock source is ready. status bits in the rcc clock control register (rcc_cr) indicate which clock(s) is (are) ready and which clock is currently used as the system clock. 5.2.7 clock securit y system (css) the clock security system can be activated by software. in this case, the clock detector is enabled after the hse oscillator startup delay, and disabled when this oscillator is stopped. if a failure is detected on the hse oscillator clock, this o scillator is automatically disabled, a clock failure event is sent to the break inputs of advanced-control timers tim1 and tim8, and an interrupt is generated to inform the software about the failure (clock security system interrupt cssi), allowing the mcu to perform rescue operations. the cssi is linked to the cortex?-m3 nmi (non-maskable interrupt) exception vector. note: when the css is enabled, if the hse clock happens to fail, the css generates an interrupt, which causes the automatic generation of an nmi. the nmi is executed indefinitely unless the css interrupt pending bit is cleared. as a consequence, the application has to clear the css interrupt in the nmi isr by setting the cssc bit in the clock interrupt register (rcc_cir). RM0033 reset and clock control (rcc) doc id 15403 rev 3 89/1317 if the hse oscillator is used dire ctly or indirectly as the syste m clock (indirectly meaning that it is directly used as pll input clock, and that pll clock is the system clock) and a failure is detected, then the syste m clock switches to the hsi o scillator and the external hse oscillator is disabled. if the hse oscillator clock was the clock source of pll used as the system clock when the failure occurred, pll is also disabled. in this case, if the plli2s was enabled, it is also disabled when the hse fails. 5.2.8 rtc/awu clock once the rtcclk clock source has been selected, the only possible way of modifying the selection is to reset the power domain. the rtcclk clock source can be either the hse 1 mhz (hse divided by a programmable prescaler), the lse or the lsi clock. this is selected by programming the rtcsel[1:0] bits in the rcc backup domain contro l register (rcc_bdcr) and the rtcpre[4:0] bits in rcc clock configuration register (rcc_cfgr) . this selection cannot be modified without resetting the backup domain. if the lse is selected as the rtc clock, the rtc will work normally if the backup or the system supply disappears. if the lsi is selected as the awu clock, the awu state is not guaranteed if the system suppl y disappears. if the hse os cillator divided by a value between 2 and 31 is used as the rtc clock, the rtc state is not guaranteed if the backup or the system supply disappears. the lse clock is in the backup domain, wher eas the hse and lsi clocks are not. as a consequence: if lse is selected as the rtc clock: ? the rtc continues to work even if the v dd supply is switched off, provided the v bat supply is maintained. if lsi is selected as the auto-wakeup unit (awu) clock: ? the awu state is not guaranteed if the v dd supply is powered off. refer to section 5.2.5: lsi clock on page 88 for more details on lsi calibration. if the hse clock is used as the rtc clock: ? the rtc state is not guaranteed if the v dd supply is powered off or if the internal voltage regulator is powered off (removing power from the 1.2 v domain). note: to read the rtc calendar register when th e apb1 clock frequency is less than seven times the rtc clock frequency (f apb1 < 7xf rtclck ), the software must read the calendar time and date registers twice. the data are correct if the second read access to rtc_tr gives the same result than the first one. otherwise a third read access must be performed. 5.2.9 watchdog clock if the independent watchdog (iwdg) is started by either hardware option or software access, the lsi oscillator is fo rced on and cannot be disa bled. after the lsi oscillator temporization, the clock is provided to the iwdg. reset and clock control (rcc) RM0033 90/1317 doc id 15403 rev 3 5.2.10 clock-out capability two microcontroller clock output (mco) pins are available: mco1 you can output four different clock sources onto the mco1 pin (pa8) using the configurable prescaler (from 1 to 5): ?hsi clock ? lse clock ?hse clock ? pll clock the desired clock source is selected using the mco1pre[2:0] and mco1[1:0] bits in the rcc clock configuration register (rcc_cfgr) . mco2 you can output four different clock sources onto the mco2 pin (pc9) using the configurable prescaler (from 1 to 5): ? hse clock ? pll clock ? system clock (sysclk) ? plli2s clock the desired clock source is selected using the mco2pre[2:0] and mco2 bits in the rcc clock configuration register (rcc_cfgr) . for the different mco pins, the corresponding gpio port has to be programmed in alternate function mode. the selected clock to output onto mco must not exceed 100 mhz (the maximum i/o speed). 5.2.11 internal/external cloc k measurement using tim5/tim11 it is possible to indirectly measure the frequencies of all on-board clock source generators by means of the input capture of tim5 channel4 and tim11 channel1 as shown in figure 11 and figure 11 . internal/external clock measurement using tim5 channel4 tim5 has an input multiplexer which allows ch oosing whether the input capture is triggered by the i/o or by an internal clock. this selection is performed through the ti4_rmp [1:0] bits in the tim5_or register. the primary purpose of having the lse connec ted to the channel4 input capture is to be able to precisely measure the hsi (this requires to have the hsi used as the system clock source). the number of hsi clock counts be tween consecutive edges of the lse signal provides a measurement of the internal clock period. taking advantage of the high precision of lse crystals (typically a few tens of ppm) we can determine the internal clock frequency with the same resolution, and trim the source to compensate for manufacturing-process and/or temperature- and voltage-related frequency deviations. the hsi oscillator has dedicat ed, user-accessible calibration bits for this purpose. RM0033 reset and clock control (rcc) doc id 15403 rev 3 91/1317 the basic concept consists in providing a relative measurement (e.g. hsi/lse ratio): the precision is therefore tightly linked to the ratio between the two clock sources. the greater the ratio, the better the measurement. it is also possible to measure the lsi frequency: this is useful for applications that do not have a crystal. the ultralow-power lsi o scillator has a large manufacturing process deviation: by measuring it versus the hsi cl ock source, it is possible to determine its frequency with the precision of the hsi. the measured value can be used to have more accurate rtc time base timeouts (when lsi is used as the rtc clock source) and/or an iwdg timeout with an acceptable accuracy. use the following procedure to measure the lsi frequency: 1. enable the tim5 timer and configure channel4 in input capture mode. 2. set the ti4_rmp bits in the tim5_or register to 0x01 to connect the lsi clock internally to tim5 channel4 input capture for calibration purposes. 3. measure the lsi clock frequency using the tim5 capture/compare 4 event or interrupt. 4. use the measured lsi frequency to update the prescaler of the rtc depending on the desired time base and/or to compute the iwdg timeout. figure 11. frequency measurement with tim5 in input capture mode internal/external clock measurement using tim11 channel1 tim11 has an input multiplexer which allows choosing whether the input capture is triggered by the i/o or by an internal clock. this selection is performed through ti1_rmp [1:0] bits in the tim11_or register. the hse_rtc clock (hse divided by a programmable prescaler) is connected to channel 1 input capture to have a rough indication of the external crystal frequency. this requires that the hsi is th e system clock source. this can be useful for instance to ensure compliance with the iec 60730/iec 61335 standards which require to be able to determine harmonic or subharmonic frequencies (?50/+100% deviations). figure 12. frequency measurement with tim11 in input capture mode 4 ) - 4 ) 4 ) ? 2 - 0 ; = ' 0 ) / 2 4 # ? / 5 4 , 3 % , 3 ) a i 4 ) - 4 ) 4 ) ? 2 - 0 ; = ' 0 ) / ( 3 % ? 2 4 # - ( z a i reset and clock control (rcc) RM0033 92/1317 doc id 15403 rev 3 5.3 rcc registers refer to section 1.1 on page 46 for a list of abbreviations used in register descriptions. 5.3.1 rcc clock contro l register (rcc_cr) address offset: 0x00 reset value: 0x0000 xx83 where x is undefined. access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved plli2s rdy plli2s on pllrdy pllon reserved css on hse byp hse rdy hse on r rw r rw rw rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 hsical[7:0] hsitrim[4:0] res. hsi rdy hsion rrrrrr r rrwrwrwrwrw rrw bits 31:28 reserved, always read as 0. bit 27 plli2srdy : plli2s clock ready flag set by hardware to indicate that the plli2s is locked. 0: plli2s unlocked 1: plli2s locked bit 26 plli2son : plli2s enable set and cleared by software to enable plli2s. cleared by hardware when entering stop or standby mode. 0: plli2s off 1: plli2s on bit 25 pllrdy : main pll (pll) clock ready flag set by hardware to indicate that pll is locked. 0: pll unlocked 1: pll locked bit 24 pllon : main pll (pll) enable set and cleared by software to enable pll. cleared by hardware when entering stop or standby mode. this bit cannot be reset if pll clock is used as the system clock. 0: pll off 1: pll on bits 23:20 reserved, always read as 0. bit 19 csson : clock security system enable set and cleared by software to enable the clock security system. when csson is set, the clock detector is enabled by hardware when the hse oscillator is ready, and disabled by hardware if an oscillator failure is detected. 0: clock security system off (clock detector off) 1: clock security system on ( clock detector on if hse osci llator is stable, off if not) RM0033 reset and clock control (rcc) doc id 15403 rev 3 93/1317 bit 18 hsebyp : hse clock bypass set and cleared by software to bypass the oscillator with an external clock. the external clock must be enabled with the hseon bit, to be used by the device. the hsebyp bit can be written only if the hse oscillator is disabled. 0: hse oscillator not bypassed 1: hse oscillator bypassed with an external clock bit 17 hserdy : hse clock ready flag set by hardware to indicate that the hse oscill ator is stable. after t he hsion bit is cleared, hserdy goes low after 6 hse oscillator clock cycles. 0: hse oscillator not ready 1: hse oscillator ready bit 16 hseon : hse clock enable set and cleared by software. cleared by hardware to stop the hse oscillator when entering stop or standby mode. this bit cannot be reset if the hse oscillator is used directly or indirectly as the system clock. 0: hse oscillator off 1: hse oscillator on bits 15:8 hsical[7:0] : internal high-speed clock calibration these bits are initialized automatically at startup. bits 7:3 hsitrim[4:0] : internal high-speed clock trimming these bits provide an additional user-programmable trimming value that is added to the hsical[7:0] bits. it can be programmed to adjust to variations in voltage and temperature that influence the frequency of the internal hsi rc. bit 2 reserved, always read as 0. bit 1 hsirdy : internal high-speed clock ready flag set by hardware to indicate that the hsi oscill ator is stable. after t he hsion bit is cleared, hsirdy goes low after 6 hsi clock cycles. 0: hsi oscillator not ready 1: hsi oscillator ready bit 0 hsion : internal high-speed clock enable set and cleared by software. set by hardware to force the hsi oscillator on when leaving the stop or standby mode or in case of a failure of the hse oscillator used dire ctly or indirectly as the system clock. this bit cannot be cleared if the hsi is used directly or indirectly as the system clock. 0: hsi oscillator off 1: hsi oscillator on reset and clock control (rcc) RM0033 94/1317 doc id 15403 rev 3 5.3.2 rcc pll conf iguration regist er (rcc_pllcfgr) address offset: 0x04 reset value: 0x24003010 access: no wait state, word, half-word and byte access. this register is used to configure the pll clock outputs according to the formulas: f (vco clock) = f (pll clock input) (plln / pllm) f (pll general clock output) = f (vco clock) / pllp f (usb otg fs, sdio, rng clock output) = f (vco clock) / pllq 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved pllq3 pllq2 pllq1 pllq0 reserv ed pllsr c reserved pllp1 pllp0 rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserv ed plln8 plln7 plln6 plln5 plln4 plln3 plln2 plln1 plln0 pllm5 pllm4 pllm3 pllm2 pllm1 pllm0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bit 31:28 reserved, always read as 0. bits 27:24 pllq: main pll (pll) division factor for usb otg fs, sdio and random number generator clocks set and cleared by software to control the frequency of usb otg fs clock, the random number generator clock and the sdio clock. t hese bits should be written only if pll is disabled. caution: the usb otg fs requires a 48 mhz clock to work correctly. the sdio and the random number generator need a frequency lo wer than or equal to 48 mhz to work correctly. usb otg fs clock frequency = vco frequency / pllq with 4 <= pllq <= 15 0000: pllq = 0, wrong configuration ... 0011: pllq = 3, wrong configuration 0100: pllq = 4 0101: pllq = 5 ... 1111: pllq = 15 bit 23 reserved, always read as 0. bit 22 pllsrc: main pll(pll) and audio pll (plli2s) entry clock source set and cleared by software to select pll and plli2s clock source. this bit can be written only when pll and plli2s are disabled. 0: hsi clock selected as pll and plli2s clock entry 1: hse oscillator clock selected as pll and plli2s clock entry bits 21:18 reserved, always read as 0. RM0033 reset and clock control (rcc) doc id 15403 rev 3 95/1317 bits 17:16 pllp: main pll (pll) division fa ctor for main system clock set and cleared by software to control the fr equency of the general pl l output clock. these bits can be written only if pll is disabled. caution: the software has to set these bits correctl y not to exceed 120 mhz on this domain. pll output clock frequency = vco frequency / pllp with pllp = 2, 4, 6, or 8 00: pllp = 2 01: pllp = 4 10: pllp = 6 11: pllp = 8 bits 14:6 plln: main pll (pll) multiplication factor for vco set and cleared by software to control the multip lication factor of the vco. these bits can be written only when pll is disabled. only half-word and word accesses are allowed to write these bits. caution: the software has to set these bits co rrectly to ensure that the vco output frequency is between 192 and 432 mhz. vco output frequency = vco input frequency plln with 192 plln 432 000000000: plln = 0, wrong configuration 000000001: plln = 1, wrong configuration ... 011000000: plln = 192 011000001: plln = 193 011000010: plln = 194 ... 110110000: plln = 432 110110000: plln = 433, wrong configuration ... 111111111: plln = 511, wrong configuration bits 5:0 pllm: division factor for the main pll (pll) and audio pll (plli2s) input clock set and cleared by software to divide the pll and plli2s input clock before the vco. these bits can be written only when the pll and plli2s are disabled. caution: the software has to set these bits correctl y to ensure that the vco input frequency ranges from 1 to 2 mhz. it is recommended to select a frequency of 2 mhz to limit pll jitter. vco input frequency = pll input clock frequency / pllm with 2 pllm 63 000000: pllm = 0, wrong configuration 000001: pllm = 1, wrong configuration 000010: pllm = 2 000011: pllm = 3 000100: pllm = 4 ... 111110: pllm = 62 111111: pllm = 63 reset and clock control (rcc) RM0033 96/1317 doc id 15403 rev 3 5.3.3 rcc clock configurat ion register (rcc_cfgr) address offset: 0x08 reset value: 0x0000 0000 access: 0 wait state 2, word, half-word and byte access 1 or 2 wait states inserted only if the access occurs during a clock source switch. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mco2 mco2 pre[2:0] mco1 pre[2:0] i2ssc r mco1 rtcpre[4:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ppre2[2:0] ppre1[2:0] reserved hpre[3:0] sws1 sws0 sw1 sw0 rw rw rw rw rw rw rw rw rw rw r r rw rw bits 31:30 mco2[1:0]: microcontroller clock output 2 set and cleared by software. clock source selection may generate glitches on mco2. it is highly recommended to configure these bits only after reset before enabling the external oscillators and the plls. 00: system clock (sysclk) selected 01: plli2s clock selected 10: hse oscillator clock selected 11: pll clock selected bits 27:29 mco2pre: mco2 prescaler set and cleared by software to configure the prescaler of the mco2. modification of this prescaler may generate glitches on mco2. it is highly recommended to change this prescaler only after reset before enabling the external oscillators and the plls. 0xx: no division 100: division by 2 101: division by 3 110: division by 4 111: division by 5 bits 24:26 mco1pre: mco1 prescaler set and cleared by software to configure the prescaler of the mco1. modification of this prescaler may generate glitches on mco1. it is highly recommended to change this prescaler only after reset before enabling the external oscillators and the pll. 0xx: no division 100: division by 2 101: division by 3 110: division by 4 111: division by 5 bit 23 i2ssrc : i2s clock selection set and cleared by software. this bit allows to select the i2s clock source between the plli2s clock and the external clock. it is hi ghly recommended to change this bit only after reset and before enabling the i2s module. 0: plli2s clock used as i2s clock source 1: external clock mapped on the i2s_ckin pin used as i2s clock source RM0033 reset and clock control (rcc) doc id 15403 rev 3 97/1317 bits 22:21 mco1: microcontroller clock output 1 set and cleared by software. clock source selection may generate glitches on mco1. it is highly recommended to configure these bits only after reset before enabling the external oscillators and pll. 00: hsi clock selected 01: lse oscillator selected 10: hse oscillator clock selected 11: pll clock selected bits 20:16 rtcpre: hse division factor for rtc clock set and cleared by software to divide the hse clock input clock to generate a 1 mhz clock for rtc. caution: the software has to set these bits correctly to ensure that the clock supplied to the rtc is 1 mhz. these bits must be conf igured if needed before selecting the rtc clock source. 00000: no clock 00001: no clock 00010: hse/2 00011: hse/3 00100: hse/4 ... 11110: hse/30 11111: hse/31 bits 15:13 ppre2: apb high-speed prescaler (apb2) set and cleared by software to contro l apb high-speed clock division factor. caution: the software has to set these bits correctl y not to exceed 60 mhz on this domain. the clocks are divided with the new prescaler factor from 1 to 16 ahb cycles after ppre2 write. 0xx: ahb clock not divided 100: ahb clock divided by 2 101: ahb clock divided by 4 110: ahb clock divided by 8 111: ahb clock divided by 16 bits 12:10 ppre1: apb low speed prescaler (apb1) set and cleared by software to contro l apb low-speed clock division factor. caution: the software has to set these bits correc tly not to exceed 30 mhz on this domain. the clocks are divided with the new prescaler factor from 1 to 16 ahb cycles after ppre1 write. 0xx: ahb clock not divided 100: ahb clock divided by 2 101: ahb clock divided by 4 110: ahb clock divided by 8 111: ahb clock divided by 16 bits 9:8 reserved reset and clock control (rcc) RM0033 98/1317 doc id 15403 rev 3 5.3.4 rcc clock interrupt register (rcc_cir) address offset: 0x0c reset value: 0x0000 0000 access: no wait state, word, half-word and byte access bits 7:4 hpre: ahb prescaler set and cleared by software to control ahb clock division factor. caution: the clocks are divided with the new prescaler factor from 1 to 16 ahb cycles after hpre write. caution: the ahb clock frequency must be at leas t 25 mhz when the ethernet is used. 0xxx: system clock not divided 1000: system clock divided by 2 1001: system clock divided by 4 1010: system clock divided by 8 1011: system clock divided by 16 1100: system clock divided by 64 1101: system clock divided by 128 1110: system clock divided by 256 1111: system clock divided by 512 bits 3:2 sws: system clock switch status set and cleared by hardware to indicate which clock source is used as the system clock. 00: hsi oscillator used as the system clock 01: hse oscillator us ed as the system clock 10: pll used as the system clock 11: not applicable bits 1:0 sw: system clock switch set and cleared by software to select the system clock source. set by hardware to force the hsi selection when leaving the stop or standby mode or in case of failure of the hse oscillator used directly or indirectly as the system clock. 00: hsi oscillator sele cted as system clock 01: hse oscillator selected as system clock 10: pll selected as system clock 11: not allowed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved cssc reser ved plli2s rdyc pll rdyc hse rdyc hsi rdyc lse rdyc lsi rdyc wwwwwww 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved plli2s rdyie pll rdyie hse rdyie hsi rdyie lse rdyie lsi rdyie cssf reser ved plli2s rdyf pll rdyf hse rdyf hsi rdyf lse rdyf lsi rdyf rw rw rw rw rw rw r r r r r r r RM0033 reset and clock control (rcc) doc id 15403 rev 3 99/1317 bits 31:24 reserved, always read as 0. bit 23 cssc: clock security sys tem interrupt clear this bit is set by software to clear the cssf flag. 0: no effect 1: clear cssf flag bits 22 reserved, always read as 0. bit 21 plli2srdyc: plli2s ready interrupt clear this bit is set by software to clear the plli2srdyf flag. 0: no effect 1: plli2srdyf cleared bit 20 pllrdyc: main pll(pll) ready interrupt clear this bit is set by software to clear the pllrdyf flag. 0: no effect 1: pllrdyf cleared bit 19 hserdyc: hse ready interrupt clear this bit is set by software to clear the hserdyf flag. 0: no effect 1: hserdyf cleared bit 18 hsirdyc: hsi ready interrupt clear this bit is set software to clear the hsirdyf flag. 0: no effect 1: hsirdyf cleared bit 17 lserdyc: lse ready interrupt clear this bit is set by software to clear the lserdyf flag. 0: no effect 1: lserdyf cleared bit 16 lsirdyc: lsi ready interrupt clear this bit is set by software to clear the lsirdyf flag. 0: no effect 1: lsirdyf cleared bits 15:12 reserved, always read as 0. bit 13 plli2srdyie: plli2s ready interrupt enable set and cleared by software to enable/disable interrupt caused by plli2s lock. 0: plli2s lock interrupt disabled 1: plli2s lock interrupt enabled bit 12 pllrdyie: main pll (pll) ready interrupt enable set and cleared by software to enable/disable interrupt caused by pll lock. 0: pll lock interrupt disabled 1: pll lock interrupt enabled bit 11 hserdyie: hse ready interrupt enable set and cleared by software to enable/disable interrupt caused by the hse oscillator stabilization. 0: hse ready interrupt disabled 1: hse ready interrupt enabled reset and clock control (rcc) RM0033 100/1317 doc id 15403 rev 3 bit 10 hsirdyie: hsi ready interrupt enable set and cleared by software to enable/disable interrupt caused by the hsi oscillator stabilization. 0: hsi ready interrupt disabled 1: hsi ready interrupt enabled bit 9 lserdyie: lse ready interrupt enable set and cleared by software to enable/disable interrupt caused by the lse oscillator stabilization. 0: lse ready interrupt disabled 1: lse ready interrupt enabled bit 8 lsirdyie: lsi ready interrupt enable set and cleared by software to enable/disable interrupt caused by lsi oscillator stabilization. 0: lsi ready interrupt disabled 1: lsi ready interrupt enabled bit 7 cssf: clock security system interrupt flag set by hardware when a failure is detected in the hse oscillator. cleared by software setting the cssc bit. 0: no clock security interrupt caused by hse clock failure 1: clock security interrupt caused by hse clock failure bits 6 reserved, always read as 0. bit 5 plli2srdyf: plli2s ready interrupt flag set by hardware when the plli2s locks and plli2srdydie is set. cleared by software setting the pllri2sdyc bit. 0: no clock ready interrupt caused by plli2s lock 1: clock ready interrupt caused by plli2s lock bit 4 pllrdyf: main pll (pll) ready interrupt flag set by hardware when pll locks and pllrdydie is set. cleared by software setting the pllrdyc bit. 0: no clock ready interrupt caused by pll lock 1: clock ready interrupt caused by pll lock bit 3 hserdyf: hse ready interrupt flag set by hardware when external low speed clock becomes stable and hserdydie is set. cleared by software setting the hserdyc bit. 0: no clock ready interrupt caused by the hse oscillator 1: clock ready interrupt caused by the hse oscillator bit 2 hsirdyf: hsi ready interrupt flag set by hardware when the internal high speed clock becomes stable and hsirdydie is set. cleared by software setting the hsirdyc bit. 0: no clock ready interrupt caused by the hsi oscillator 1: clock ready interrupt caused by the hsi oscillator bit 1 lserdyf: lse ready interrupt flag set by hardware when the external low speed clock becomes stable and lserdydie is set. cleared by software setting the lserdyc bit. 0: no clock ready interrupt caused by the lse oscillator 1: clock ready interrupt caused by the lse oscillator RM0033 reset and clock control (rcc) doc id 15403 rev 3 101/1317 5.3.5 rcc ahb1 peri pheral reset regist er (rcc_ahb1rstr) address offset: 0x10 reset value: 0x0000 0000 access: no wait state, word, half-word and byte access. bit 0 lsirdyf: lsi ready interrupt flag set by hardware when the internal low speed clock becomes stable and lsirdydie is set. cleared by software setting the lsirdyc bit. 0: no clock ready interrupt caused by the lsi oscillator 1: clock ready interrupt caused by the lsi oscillator 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved otghs rst reserved ethmac rst reserved dma2 rst dma1 rst reserved rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved crcrs t reserved gpioi rst gpioh rst gpiogg rst gpiof rst gpioe rst gpiod rst gpioc rst gpiob rst gpioa rst rw rw rw rw rw rw rw rw rw rw bits 31:30 reserved, always read as 0. bit 29 otghsrst: usb otg hs module reset set and cleared by software. 0: does not reset the usb otg hs module 1: resets the usb otg hs module bits 28:26 reserved, always read as 0. bit 25 ethmacrst: ethernet mac reset set and cleared by software. 0: does not reset ethernet mac 1: resets ethernet mac bits 24:23 reserved, always read as 0 bit 22 dma2rst: dma2 reset set and cleared by software. 0: does not reset dma2 1: resets dma2 bit 21 dma1rst: dma2 reset set and cleared by software. 0: does not reset dma2 1: resets dma2 bits 20:13 reserved, always read as 0. bit 12 crcrst: crc reset set and cleared by software. 0: does not reset crc 1: resets crc bits 11:9 reserved, always read as 0 reset and clock control (rcc) RM0033 102/1317 doc id 15403 rev 3 bit 8 gpioirst: io port i reset set and cleared by software. 0: does not reset io port i 1: resets io port i bit 7 gpiohrst: io port h reset set and cleared by software. 0: does not reset io port h 1: resets io port h bits 6 gpiogrst: io port g reset set and cleared by software. 0: does not reset io port g 1: resets io port g bit 5 gpiofrst: io port f reset set and cleared by software. 0: does not reset io port f 1: resets io port f bit 4 gpioerst: io port e reset set and cleared by software. 0: does not reset io port e 1: resets io port e bit 3 gpiodrst: io port d reset set and cleared by software. 0: does not reset io port d 1: resets io port d bit 2 gpiocrst: io port c reset set and cleared by software. 0: does not reset io port c 1: resets io port c bit 1 gpiobrst: io port b reset set and cleared by software. 0: does not reset io port b 1:resets io port b bit 0 gpioarst: io port a reset set and cleared by software. 0: does not reset io port a 1: resets io port a RM0033 reset and clock control (rcc) doc id 15403 rev 3 103/1317 5.3.6 rcc ahb2 peri pheral reset regist er (rcc_ahb2rstr) address offset: 0x14 reset value: 0x0000 0000 access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved otgfs rst rng rst hash rst cryp rst reserved dcmi rst rw rw rw rw rw bits 31:8 reserved, always read as 0. bit 7 otgfsrst: usb otg fs module reset set and cleared by software. 0: does not reset the usb otg fs module 1: resets the usb otg fs module bit 6 rngrst: random number generator module reset set and cleared by software. 0: does not reset the random number generator module 1: resets the random number generator module bit 5 hashrst: hash module reset set and cleared by software. 0: does not reset the hash module 1: resets the hash module bit 4 cryprst: cryptographic module reset set and cleared by software. 0: does not reset the cryptographic module 1: resets the cryptographic module bit 3:1 reserved, always read as 0 bit 0 dcmirst: camera interface reset set and cleared by software. 0: does not reset the camera interface 1: resets the camera interface reset and clock control (rcc) RM0033 104/1317 doc id 15403 rev 3 5.3.7 rcc ahb3 peri pheral reset regist er (rcc_ahb3rstr) address offset: 0x18 reset value: 0x0000 0000 access: no wait state, word, half-word and byte access. 5.3.8 rcc apb1 peri pheral reset regist er (rcc_apb1rstr) address offset: 0x20 reset value: 0x0000 0000 access: no wait state, word, half-word and byte access. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109 8 765432 1 0 reserved fsmcrst rw bits 31:1 reserved, always read as 0. bit 0 fsmcrst: flexible static memory controller module reset set and cleared by software. 0: does not reset the fsmc module 1: resets the fsmc module 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved dacrst pwr rst reser- ved can2 rst can1 rst reser- ved i2c3 rst i2c2 rst i2c1 rst uart5 rst uart4 rst uart3 rst uart2 rst reser- ved rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 spi3 rst spi2 rst reserved wwdg rst reserved tim14 rst tim13 rst tim12 rst tim7 rst tim6 rst tim5 rst tim4 rst tim3 rst tim2 rst rw rw rw rw rw rw rw rw rw rw rw rw bits 31:30 reserved, always read as 0. bit 29 dacrst: dac reset set and cleared by software. 0: does not reset the dac interface 1: resets the dac interface bit 28 pwrrst: power interface reset set and cleared by software. 0: does not reset the power interface 1: resets the power interface bit 27 reserved, always read as 0 RM0033 reset and clock control (rcc) doc id 15403 rev 3 105/1317 bit 26 can2rst: can2 reset set and cleared by software. 0: does not reset can2 1: resets can2 bit 25 can1rst: can1 reset set and cleared by software. 0: does not reset can1 1: resets can1 bit 24 reserved, always read as 0. bit 23 i2c3rst: i2c3 reset set and cleared by software. 0: does not reset i2c3 1: resets i2c3 bit 22 i2c2rst: i2c 2 reset set and cleared by software. 0: does not reset i2c2 1: resets i2c 2 bit 21 i2c1rst: i2c 1 reset set and cleared by software. 0: does not reset i2c1 1: resets i2c1 bit 20 uart5rst: usart 5 reset set and cleared by software. 0: does not reset uart5 1: resets uart5 bit 19 uart4rst: usart 4 reset set and cleared by software. 0: does not reset uart4 1: resets uart4 bit 18 usart3rst: usart 3 reset set and cleared by software. 0: does not reset usart3 1: resets usart3 bit 17 usart2rst: usart 2 reset set and cleared by software. 0: does not reset usart2 1: resets usart2 bit 16 reserved, always read as 0. bit 15 spi3rst: spi 3 reset set and cleared by software. 0: does not reset spi3 1: resets spi3 bit 14 spi2rst: spi 2 reset set and cleared by software. 0: does not reset spi2 1: resets spi2 reset and clock control (rcc) RM0033 106/1317 doc id 15403 rev 3 bits 13:12 reserved, always read as 0. bit 11 wwdgrst: window watchdog reset set and cleared by software. 0: does not reset the window watchdog 1: resets the window watchdog bits 10:9 reserved, always read as 0. bit 8 tim14rst: tim14 reset set and cleared by software. 0: does not reset tim14 1: resets tim14 bit 7 tim13rst: tim13 reset set and cleared by software. 0: does not reset tim13 1: resets tim13 bit 6 tim12rst: tim12 reset set and cleared by software. 0: does not reset tim12 1: resets tim12 bit 5 tim7rst: tim7 reset set and cleared by software. 0: does not reset tim7 1: resets tim7 bit 4 tim6rst: tim6 reset set and cleared by software. 0: does not reset tim6 1: resets tim6 bit 3 tim5rst: tim5 reset set and cleared by software. 0: does not reset tim5 1: resets tim5 bit 2 tim4rst: tim4 reset set and cleared by software. 0: does not reset tim4 1: resets tim4 bit 1 tim3rst: tim3 reset set and cleared by software. 0: does not reset tim3 1: resets tim3 bit 0 tim2rst: tim2 reset set and cleared by software. 0: does not reset tim2 1: resets tim2 RM0033 reset and clock control (rcc) doc id 15403 rev 3 107/1317 5.3.9 rcc apb2 peri pheral reset regist er (rcc_apb2rstr) address offset: 0x24 reset value: 0x0000 0000 access: no wait state, word, half-word and byte access. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved tim11 rst tim10 rst tim9 rst rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reser- ved syscf g rst reser- ved spi1 rst sdio rst reserved adc rst reserved usart6 rst usart1 rst reserved tim8 rst tim1 rst rw rw rw rw rw rw rw rw bits 31:19 reserved, always read as 0. bit 18 tim11rst: tim11 reset set and cleared by software. 0: does not reset tim11 1: resets tim14 bit 17 tim10rst: tim10 reset set and cleared by software. 0: does not reset tim10 1: resets tim10 bit 16 tim9rst: tim9 reset set and cleared by software. 0: does not reset tim9 1: resets tim9 bit 15 reserved, always read as 0. bit 14 syscfgrst: system configuration controller reset set and cleared by software. 0: does not reset the system configuration controller 1: resets the system configuration controller bit 13 reserved, always read as 0. bit 12 spi1rst: spi 1 reset set and cleared by software. 0: does not reset spi1 1: resets spi1 bit 11 sdiorst: sdio reset set and cleared by software. 0: does not reset the sdio module 1: resets the sdio module bits 10:9 reserved, always read as 0 bit 8 adcrst: adc interface reset (common to all adcs) set and cleared by software. 0: does not reset the adc interface 1: resets the adc interface reset and clock control (rcc) RM0033 108/1317 doc id 15403 rev 3 bits 7:6 reserved, always read as 0. bit 5 usart6rst: usart6 reset set and cleared by software. 0: does not reset usart6 1: resets usart6 bit 4 usart1rst: usart1 reset set and cleared by software. 0: does not reset usart1 1: resets usart1 bits 3:2 reserved, always read as 0. bit 1 tim8rst: tim8 reset set and cleared by software. 0: does not reset tim8 1: resets tim8 bit 0 tim1rst: tim1 reset set and cleared by software. 0: does not reset tim1 1: resets tim1 RM0033 reset and clock control (rcc) doc id 15403 rev 3 109/1317 5.3.10 rcc ahb1 per ipheral clock register (rcc_ahb1enr) address offset: 0x30 reset value: 0x0000 0000 access: no wait state, word, half-word and byte access. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reser- ved otghs ulpien otghs en ethma cptpe n ethma crxen ethma ctxen ethma cen reserved dma2en dma1en reserved bkpsr amen reserved rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved crcen reserved gpioie n gpioh en gpioge n gpiofe n gpioe en gpiod en gpioc en gpiob en gpioa en rw rw rw rw rw rw rw rw rw rw bits 31 reserved, always read as 0. bit 30 otghsulpien: usb otg hsulpi clock enable set and cleared by software. 0: usb otg hs ulpi clock disabled 1: usb otg hs ulpi clock enabled bit 29 otghsen: usb otg hs clock enable set and cleared by software. 0: usb otg hs clock disabled 1: usb otg hs clock enabled bit 28 ethmacptpen: ethernet ptp clock enable set and cleared by software. 0: ethernet ptp clock disabled 1: ethernet ptp clock enabled bit 27 ethmacrxen: ethernet reception clock enable set and cleared by software. 0: ethernet reception clock disabled 1: ethernet reception clock enabled bit 26 ethmactxen: ethernet transmission clock enable set and cleared by software. 0: ethernet transmission clock disabled 1: ethernet transmission clock enabled bit 25 ethmacen: ethernet mac clock enable set and cleared by software. 0: ethernet mac clock disabled 1: ethernet mac clock enabled bits 24:23 reserved, always read as 0. bit 22 dma2en: dma2 clock enable set and cleared by software. 0: dma2 clock disabled 1: dma2 clock enabled reset and clock control (rcc) RM0033 110/1317 doc id 15403 rev 3 bit 21 dma1en: dma1 clock enable set and cleared by software. 0: dma1 clock disabled 1: dma1 clock enabled bits 20:19 reserved, always read as 0. bit 18 bkpsramen: backup sram interface clock enable set and cleared by software. 0: backup sram interface clock disabled 1: backup sram interface clock enabled bits 17:13 reserved, always read as 0. bit 12 crcen: crc clock enable set and cleared by software. 0: crc clock disabled 1: crc clock enabled bits 11:9 reserved, always read as 0. bit 8 gpioien: io port i clock enable set and cleared by software. 0: io port i clock disabled 1: io port i clock enabled bit 7 gpiohen: io port h clock enable set and cleared by software. 0: io port h clock disabled 1: io port h clock enabled bit 6 gpiogen: io port g clock enable set and cleared by software. 0: io port g clock disabled 1: io port g clock enabled bit 5 gpiofen: io port f clock enable set and cleared by software. 0: io port f clock disabled 1: io port f clock enabled bit 4 gpioeen: io port e clock enable set and cleared by software. 0: io port e clock disabled 1: io port e clock enabled bit 3 gpioden: io port d clock enable set and cleared by software. 0: io port d clock disabled 1: io port d clock enabled bit 2 gpiocen: io port c clock enable set and cleared by software. 0: io port c clock disabled 1: io port c clock enabled RM0033 reset and clock control (rcc) doc id 15403 rev 3 111/1317 5.3.11 rcc ahb2 peri pheral clock enable re gister (rcc_ahb2enr) address offset: 0x34 reset value: 0x0000 0000 access: no wait state, word, half-word and byte access. bit 1 gpioben: io port b clock enable set and cleared by software. 0: io port b clock disabled 1: io port b clock enabled bit 0 gpioaen: io port a clock enable set and cleared by software. 0: io port a clock disabled 1: io port a clock enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved otgfs en rng en hash en cryp en reserved dcmi en rw rw rw rw rw bits 31:8 reserved, always read as 0. bit 7 otgfsen: usb otg fs clock enable set and cleared by software. 0: usb otg fs clock disabled 1: usb otg fs clock enabled bit 6 rngen: random number generator clock enable set and cleared by software. 0: random number generator clock disabled 1: random number generator clock enabled bit 5 hashen: hash modules clock enable set and cleared by software. 0: hash modules clock disabled 1: hash modules clock enabled bit 4 crypen: cryptographic modules clock enable set and cleared by software. 0: cryptographic module clock disabled 1: cryptographic module clock enabled bit 3:1 reserved, always read as 0 bit 0 dcmien: camera interface enable set and cleared by software. 0: camera interface clock disabled 1: camera interface clock enabled reset and clock control (rcc) RM0033 112/1317 doc id 15403 rev 3 5.3.12 rcc ahb3 peri pheral clock enable re gister (rcc_ahb3enr) address offset: 0x38 reset value: 0x0000 0000 access: no wait state, word, half-word and byte access. 5.3.13 rcc apb1 peri pheral clock enable re gister (rcc_apb1enr) address offset: 0x40 reset value: 0x0000 0000 access: no wait state, word, half-word and byte access. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109 8 765432 1 0 reserved fsmcen rw bits 31:1 reserved, always read as 0. bit 0 fsmcen: flexible static memory controller module clock enable set and cleared by software. 0: fsmc module clock disabled 1: fsmc module clock enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved dac en pwr en reser- ved can2 en can1 en reser- ved i2c3 en i2c2 en i2c1 en uart5 en uart4 en usart3 en usart2 en reser- ved rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 spi3 en spi2 en reserved wwdg en reserved tim14 en tim13 en tim12 en tim7 en tim6 en tim5 en tim4 en tim3 en tim2 en rw rw rw rw rw rw rw rw rw rw rw rw bits 31:30 reserved, always read as 0. bit 29 dacen: dac interface clock enable set and cleared by software. 0: dac interface clock disabled 1: dac interface clock enable bit 28 pwren: power interface clock enable set and cleared by software. 0: power interface clock disabled 1: power interface clock enable bit 27 reserved, always read as 0. bit 26 can2en: can 2 clock enable set and cleared by software. 0: can 2 clock disabled 1: can 2 clock enabled RM0033 reset and clock control (rcc) doc id 15403 rev 3 113/1317 bit 25 can1en: can 1 clock enable set and cleared by software. 0: can 1 clock disabled 1: can 1 clock enabled bit 24 reserved, always read as 0. bit 23 i2c3en: i2c3 clock enable set and cleared by software. 0: i2c3 clock disabled 1: i2c3 clock enabled bit 22 i2c2en: i2c2 clock enable set and cleared by software. 0: i2c2 clock disabled 1: i2c2 clock enabled bit 21 i2c1en: i2c1 clock enable set and cleared by software. 0: i2c1 clock disabled 1: i2c1 clock enabled bit 20 uart5en: uart5 clock enable set and cleared by software. 0: uart5 clock disabled 1: uart5 clock enabled bit 19 uart4en: uart4 clock enable set and cleared by software. 0: uart4 clock disabled 1: uart4 clock enabled bit 18 usart3en: usart3 clock enable set and cleared by software. 0: usart3 clock disabled 1: usart3 clock enabled bit 17 usart2en: usart 2 clock enable set and cleared by software. 0: usart2 clock disabled 1: usart2 clock enabled bit 16 reserved, always read as 0. bit 15 spi3en: spi3 clock enable set and cleared by software. 0: spi3 clock disabled 1: spi3 clock enabled bit 14 spi2en: spi2 clock enable set and cleared by software. 0: spi2 clock disabled 1: spi2 clock enabled bits 13:12 reserved, always read as 0. reset and clock control (rcc) RM0033 114/1317 doc id 15403 rev 3 bit 11 wwdgen: window watchdog clock enable set and cleared by software. 0: window watchdog clock disabled 1: window watchdog clock enabled bit 10:9 reserved, always read as 0. bit 8 tim14en: tim14 clock enable set and cleared by software. 0: tim14 clock disabled 1: tim14 clock enabled bit 7 tim13en: tim13 clock enable set and cleared by software. 0: tim13 clock disabled 1: tim13 clock enabled bit 6 tim12en: tim12 clock enable set and cleared by software. 0: tim12 clock disabled 1: tim12 clock enabled bit 5 tim7en: tim7 clock enable set and cleared by software. 0: tim7 clock disabled 1: tim7 clock enabled bit 4 tim6en: tim6 clock enable set and cleared by software. 0: tim6 clock disabled 1: tim6 clock enabled bit 3 tim5en: tim5 clock enable set and cleared by software. 0: tim5 clock disabled 1: tim5 clock enabled bit 2 tim4en: tim4 clock enable set and cleared by software. 0: tim4 clock disabled 1: tim4 clock enabled bit 1 tim3en: tim3 clock enable set and cleared by software. 0: tim3 clock disabled 1: tim3 clock enabled bit 0 tim2en: tim2 clock enable set and cleared by software. 0: tim2 clock disabled 1: tim2 clock enabled RM0033 reset and clock control (rcc) doc id 15403 rev 3 115/1317 5.3.14 rcc apb2 peri pheral clock enable re gister (rcc_apb2enr) address offset: 0x44 reset value: 0x0000 0000 access: no wait state, word, half-word and byte access. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved tim11 en tim10 en tim9 en rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reser- ved syscf g en reser- ved spi1 en sdio en adc3 en adc2 en adc1 en reserved usart6 en usart1 en reserved tim8 en tim1 en rw rw rw rw rw rw rw rw rw rw bits 31:19 reserved, always read as 0. bit 18 tim11en: tim11 clock enable set and cleared by software. 0: tim11 clock disabled 1: tim11 clock enabled bit 17 tim10en: tim10 clock enable set and cleared by software. 0: tim10 clock disabled 1: tim10 clock enabled bit 16 tim9en: tim9 clock enable set and cleared by software. 0: tim9 clock disabled 1: tim9 clock enabled bit 15 reserved, always read as 0. bit 14 syscfgen: system configuration controller clock enable set and cleared by software. 0: system configuration controller clock disabled 1: system configuration controller clock enabled bit 13 reserved, always read as 0. bit 12 spi1en: spi1 clock enable set and cleared by software. 0: spi1 clock disabled 1: spi1 clock enabled bit 11 sdioen: sdio clock enable set and cleared by software. 0: sdio module clock disabled 1: sdio module clock enabled bit 10 adc3en: adc3 clock enable set and cleared by software. 0: adc3 clock disabled 1: adc3 clock disabled reset and clock control (rcc) RM0033 116/1317 doc id 15403 rev 3 bit 9 adc2en: adc2 clock enable set and cleared by software. 0: adc2 clock disabled 1: adc2 clock disabled bit 8 adc1en: adc1 clock enable set and cleared by software. 0: adc1 clock disabled 1: adc1 clock disabled bits 7:6 reserved, always read as 0. bit 5 usart6en: usart6 clock enable set and cleared by software. 0: usart6 clock disabled 1: usart6 clock enabled bit 4 usart1en: usart1 clock enable set and cleared by software. 0: usart1 clock disabled 1: usart1 clock enabled bits 3:2 reserved, always read as 0. bit 1 tim8en: tim8 clock enable set and cleared by software. 0: tim8 clock disabled 1: tim8 clock enabled bit 0 tim1en: tim1 clock enable set and cleared by software. 0: tim1 clock disabled 1: tim1 clock enabled RM0033 reset and clock control (rcc) doc id 15403 rev 3 117/1317 5.3.15 rcc ahb1 peri pheral clock enable in low power mode register (rcc_ahb1lpenr) address offset: 0x50 reset value: 0x7e67 91ff access: no wait state, word, half-word and byte access. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reser- ved otghs ulpilpen otghs lpen ethptp lpen ethrx lpen ethtx lpen ethmac lpen reserved dma2 lpen dma1 lpen reserved bkpsra m lpen sram2 lpen sram1 lpen rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 flitf lpen reserved crc lpen reserved gpioi lpen gpioh lpen gpiogg lpen gpiof lpen gpioe lpen gpiod lpen gpioc lpen gpiob lpen gpioa lpen rw rw rw rw rw rw rw rw rw rw rw bit 31 reserved, always read as 0. bit 30 otghsulpilpen: usb otg hs ulpi clock enable during sleep mode set and cleared by software. 0: usb otg hs ulpi clock disabled during sleep mode 1: usb otg hs ulpi clock enabled during sleep mode bit 29 otghslpen: usb otg hs clock enable during sleep mode set and cleared by software. 0: usb otg hs clock disabled during sleep mode 1: usb otg hs clock enabled during sleep mode bit 28 ethmacptplpen: ethernet ptp clock enable during sleep mode set and cleared by software. 0: ethernet ptp clock disabled during sleep mode 1: ethernet ptp clock enabled during sleep mode bit 27 ethmacrxlpen: ethernet reception clock enable during sleep mode set and cleared by software. 0: ethernet reception clock disabled during sleep mode 1: ethernet reception clock enabled during sleep mode bit 26 ethmactxlpen: ethernet transmission clock enable during sleep mode set and cleared by software. 0: ethernet transmission clock disabled during sleep mode 1: ethernet transmission clock enabled during sleep mode bit 25 ethmaclpen: ethernet mac clock enable during sleep mode set and cleared by software. 0: ethernet mac clock disabled during sleep mode 1: ethernet mac clock enabled during sleep mode bits 24:23 reserved, always read as 0 bit 22 dma2lpen: dma2 clock enable during sleep mode set and cleared by software. 0: dma2 clock disabled during sleep mode 1: dma2 clock enabled during sleep mode reset and clock control (rcc) RM0033 118/1317 doc id 15403 rev 3 bit 21 dma1lpen: dma1 clock enable during sleep mode set and cleared by software. 0: dma1 clock disabled during sleep mode 1: dma1 clock enabled during sleep mode bits 20:19 reserved, always read as 0. bit 18 bkpsramlpen: backup sram interface clock enable during sleep mode set and cleared by software. 0: backup sram interface clock disabled during sleep mode 1: backup sram interface clock enabled during sleep mode bit 17 sram2lpen: sram 2 interface clock enable during sleep mode set and cleared by software. 0: sram 2 interface clock disabled during sleep mode 1: sram 2 interface clock enabled during sleep mode bit 16 sram1lpen: sram 1interface clock enable during sleep mode set and cleared by software. 0: sram 1 interface clock disabled during sleep mode 1: sram 1 interface clock enabled during sleep mode bit 15 flitflpen: flash interface clock enable during sleep mode set and cleared by software. 0: flash interface clock disabled during sleep mode 1: flash interface clock enabled during sleep mode bits 14:13 reserved, always read as 0 bit 12 crclpen: crc clock enable during sleep mode set and cleared by software. 0: crc clock disabled during sleep mode 1: crc clock enabled during sleep mode bits 11:9 reserved, always read as 0 bit 8 gpioilpen: io port i clock enable during sleep mode set and cleared by software. 0: io port i clock disabled during sleep mode 1: io port i clock enabled during sleep mode bit 7 gpiohlpen: io port h clock enable during sleep mode set and cleared by software. 0: io port h clock disabled during sleep mode 1: io port h clock enabled during sleep mode bits 6 gpioglpen: io port g clock enable during sleep mode set and cleared by software. 0: io port g clock disabled during sleep mode 1: io port g clock enabled during sleep mode bit 5 gpioflpen: io port f clock enable during sleep mode set and cleared by software. 0: io port f clock disabled during sleep mode 1: io port f clock enabled during sleep mode RM0033 reset and clock control (rcc) doc id 15403 rev 3 119/1317 5.3.16 rcc ahb2 peri pheral clock enable in low power mode register (rcc_ahb2lpenr) address offset: 0x54 reset value: 0x0000 00f1 access: no wait state, word, half-word and byte access. bit 4 gpioelpen: io port e clock enable during sleep mode set and cleared by software. 0: io port e clock disabled during sleep mode 1: io port e clock enabled during sleep mode bit 3 gpiodlpen: io port d clock enable during sleep mode set and cleared by software. 0: io port d clock disabled during sleep mode 1: io port d clock enabled during sleep mode bit 2 gpioclpen: io port c clock enable during sleep mode set and cleared by software. 0: io port c clock disabled during sleep mode 1: io port c clock enabled during sleep mode bit 1 gpioblpen: io port b clock enable during sleep mode set and cleared by software. 0: io port b clock disabled during sleep mode 1: io port b clock enabled during sleep mode bit 0 gpioalpen: io port a clock enable during sleep mode set and cleared by software. 0: io port a clock disabled during sleep mode 1: io port a clock enabled during sleep mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved otgfs lpen rng lpen hash lpen cryp lpen reserved dcmi lpen rw rw rw rw rw bits 31:8 reserved, always read as 0. bit 7 otgfslpen: usb otg fs clock enable during sleep mode set and cleared by software. 0: usb otg fs clock disabled during sleep mode 1: usb otg fs clock enabled during sleep mode bit 6 rnglpen: random number generator clock enable during sleep mode set and cleared by software. 0: random number generator clock disabled during sleep mode 1: random number generator clock enabled during sleep mode reset and clock control (rcc) RM0033 120/1317 doc id 15403 rev 3 5.3.17 rcc ahb3 peri pheral clock enable in low power mode register (rcc_ahb3lpenr) address offset: 0x58 reset value: 0x0000 0001 access: no wait state, word, half-word and byte access. bit 5 hashlpen: hash modules clock enable during sleep mode set and cleared by software. 0: hash modules clock disabled during sleep mode 1: hash modules clock enabled during sleep mode bit 4 cryplpen: cryptography modules clock enable during sleep mode set and cleared by software. 0: cryptography modules cloc k disabled during sleep mode 1: cryptography modules clock enabled during sleep mode bit 3:1 reserved, always read as 0 bit 0 dcmilpen: camera interface enable during sleep mode set and cleared by software. 0: camera interface clock disabled during sleep mode 1: camera interface clock enabled during sleep mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved fsmc lpen rw bits 31:1 reserved, always read as 0. bit 0 fsmclpen: flexible static memory controller module clock enable during sleep mode set and cleared by software. 0: fsmc module clock disabled during sleep mode 1: fsmc module clock enabled during sleep mode RM0033 reset and clock control (rcc) doc id 15403 rev 3 121/1317 5.3.18 rcc apb1 peri pheral clock enable in low power mode register (rcc_apb1lpenr) address offset: 0x60 reset value: 0x36fe c9ff access: no wait state, word, half-word and byte access. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved dac lpen pwr lpen reser ved can2 lpen can1 lpen reser- ved i2c3 lpen i2c2 lpen i2c1 lpen uart5 lpen uart4 lpen usart3 lpen usart2 lpen reser- ved rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 spi3 lpen spi2 lpen reserved wwdg lpen reserved tim14 lpen tim13 lpen tim12 lpen tim7 lpen tim6 lpen tim5 lpen tim4 lpen tim3 lpen tim2 lpen rw rw rw rw rw rw rw rw rw rw rw rw bits 31:30 reserved, always read as 0. bit 29 daclpen: dac interface clock enable during sleep mode set and cleared by software. 0: dac interface clock disabled during sleep mode 1: dac interface clock enabled during sleep mode bit 28 pwrlpen: power interface clock enable during sleep mode set and cleared by software. 0: power interface clock disabled during sleep mode 1: power interface clock enabled during sleep mode bit 27 reserved, always read as 0. bit 26 can2lpen: can 2 clock enable during sleep mode set and cleared by software. 0: can 2 clock disabled during sleep mode 1: can 2 clock enabled during sleep mode bit 25 can1lpen: can 1 clock enable during sleep mode set and cleared by software. 0: can 1 clock disabled during sleep mode 1: can 1 clock enabled during sleep mode bit 24 reserved, always read as 0. bit 23 i2c3lpen: i2c3 clock enable during sleep mode set and cleared by software. 0: i2c3 clock disabled during sleep mode 1: i2c3 clock enabled during sleep mode bit 22 i2c2lpen: i2c2 clock enable during sleep mode set and cleared by software. 0: i2c2 clock disabled during sleep mode 1: i2c2 clock enabled during sleep mode bit 21 i2c1lpen: i2c1 clock enable during sleep mode set and cleared by software. 0: i2c1 clock disabled during sleep mode 1: i2c1 clock enabled during sleep mode reset and clock control (rcc) RM0033 122/1317 doc id 15403 rev 3 bit 20 uart5lpen: uart5 clock enable during sleep mode set and cleared by software. 0: uart5 clock disabled during sleep mode 1: uart5 clock enabled during sleep mode bit 19 uart4lpen: uart4 clock enable during sleep mode set and cleared by software. 0: uart4 clock disabled during sleep mode 1: uart4 clock enabled during sleep mode bit 18 usart3lpen: usart3 clock enable during sleep mode set and cleared by software. 0: usart3 clock disabled during sleep mode 1: usart3 clock enabled during sleep mode bit 17 usart2lpen: usart2 clock enable during sleep mode set and cleared by software. 0: usart2 clock disabled during sleep mode 1: usart2 clock enabled during sleep mode bit 16 reserved, always read as 0. bit 15 spi3lpen: spi3 clock enable during sleep mode set and cleared by software. 0: spi3 clock disabled during sleep mode 1: spi3 clock enabled during sleep mode bit 14 spi2lpen: spi2 clock enable during sleep mode set and cleared by software. 0: spi2 clock disabled during sleep mode 1: spi2 clock enabled during sleep mode bits 13:12 reserved, always read as 0. bit 11 wwdglpen: window watchdog clock enable during sleep mode set and cleared by software. 0: window watchdog clock disabled during sleep mode 1: window watchdog clock enabled during sleep mode bits 10:9 reserved, always read as 0. bit 8 tim14lpen: tim14 clock enable during sleep mode set and cleared by software. 0: tim14 clock disabled during sleep mode 1: tim14 clock enabled during sleep mode bit 7 tim13lpen: tim13 clock enable during sleep mode set and cleared by software. 0: tim13 clock disabled during sleep mode 1: tim13 clock enabled during sleep mode bit 6 tim12lpen: tim12 clock enable during sleep mode set and cleared by software. 0: tim12 clock disabled during sleep mode 1: tim12 clock enabled during sleep mode RM0033 reset and clock control (rcc) doc id 15403 rev 3 123/1317 bit 5 tim7lpen: tim7 clock enable during sleep mode set and cleared by software. 0: tim7 clock disabled during sleep mode 1: tim7 clock enabled during sleep mode bit 4 tim6lpen: tim6 clock enable during sleep mode set and cleared by software. 0: tim6 clock disabled during sleep mode 1: tim6 clock enabled during sleep mode bit 3 tim5lpen: tim5 clock enable during sleep mode set and cleared by software. 0: tim5 clock disabled during sleep mode 1: tim5 clock enabled during sleep mode bit 2 tim4lpen: tim4 clock enable during sleep mode set and cleared by software. 0: tim4 clock disabled during sleep mode 1: tim4 clock enabled during sleep mode bit 1 tim3lpen: tim3 clock enable during sleep mode set and cleared by software. 0: tim3 clock disabled during sleep mode 1: tim3 clock enabled during sleep mode bit 0 tim2lpen: tim2 clock enable during sleep mode set and cleared by software. 0: tim2 clock disabled during sleep mode 1: tim2 clock enabled during sleep mode reset and clock control (rcc) RM0033 124/1317 doc id 15403 rev 3 5.3.19 rcc apb2 peri pheral clock enabled in low power mode register (rcc_apb2lpenr) address offset: 0x64 reset value: 0x0007 5f33 access: no wait state, word, half-word and byte access. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved tim11 lpen tim10 lpen tim9 lpen rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reser- ved sysc fg lpen reser- ved spi1 lpen sdio lpen adc3 lpen adc2 lpen adc1 lpen reserved usart6 lpen usart1 lpen reserved tim8 lpen tim1 lpen rw rw rw rw rw rw rw rw rw rw bits 31:19 reserved, always read as 0. bit 18 tim11lpen: tim11 clock enable during sleep mode set and cleared by software. 0: tim11 clock disabled during sleep mode 1: tim11 clock enabled during sleep mode bit 17 tim10lpen: tim10 clock enable during sleep mode set and cleared by software. 0: tim10 clock disabled during sleep mode 1: tim10 clock enabled during sleep mode bit 16 tim9lpen: tim9 clock enable during sleep mode set and cleared by software. 0: tim9 clock disabled during sleep mode 1: tim9 clock enabled during sleep mode bit 15 reserved, always read as 0. bit 14 syscfglpen: system configuration controller clock enable during sleep mode set and cleared by software. 0: system configuration controller clock disabled during sleep mode 1: system configuration controller clock enabled during sleep mode bits 13 reserved, always read as 0. bit 12 spi1lpen: spi 1 clock enable during sleep mode set and cleared by software. 0: spi 1 clock disabled during sleep mode 1: spi 1 clock enabled during sleep mode bit 11 sdiolpen: sdio clock enable during sleep mode set and cleared by software. 0: sdio module clock disabled during sleep mode 1: sdio module clock enabled during sleep mode RM0033 reset and clock control (rcc) doc id 15403 rev 3 125/1317 bit 10 adc3lpen: adc 3 clock enable during sleep mode set and cleared by software. 0: adc 3 clock disabled during sleep mode 1: adc 3 clock disabled during sleep mode bit 9 adc2lpen: adc2 clock enable during sleep mode set and cleared by software. 0: adc2 clock disabled during sleep mode 1: adc2 clock disabled during sleep mode bit 8 adc1lpen: adc1 clock enable during sleep mode set and cleared by software. 0: adc1 clock disabled during sleep mode 1: adc1 clock disabled during sleep mode bits 7:6 reserved, always read as 0. bit 5 usart6lpen: usart6 clock enable during sleep mode set and cleared by software. 0: usart6 clock disabled during sleep mode 1: usart6 clock enabled during sleep mode bit 4 usart1lpen: usart1 clock enable during sleep mode set and cleared by software. 0: usart1 clock disabled during sleep mode 1: usart1 clock enabled during sleep mode bits 3:2 reserved, always read as 0. bit 1 tim8lpen: tim8 clock enable during sleep mode set and cleared by software. 0: tim8 clock disabled during sleep mode 1: tim8 clock enabled during sleep mode bit 0 tim1lpen: tim1 clock enable during sleep mode set and cleared by software. 0: tim1 clock disabled during sleep mode 1: tim1 clock enabled during sleep mode reset and clock control (rcc) RM0033 126/1317 doc id 15403 rev 3 5.3.20 rcc backup domain co ntrol register (rcc_bdcr) address offset: 0x70 reset value: 0x0000 0000, reset by backup domain reset. access: 0 wait state 3, word, half-word and byte access wait states are inserted in case of successive accesses to this register. the lseon, lsebyp, rtcsel and rtcen bits in the rcc backup domain control register (rcc_bdcr) are in the backup domain. as a result, after reset, these bits are write-protected and the dbp bit in the power control register (pwr_cr) has to be set before these can be modified. refer to section 5.1.2 on page 67 for further information. these bits are only reset after a backup domain reset (see section 5.1.3: backup domain reset ). any internal or external reset will not have any effect on these bits. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved bdrst rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rtcen reserved rtcsel[1:0] reserved lsebyp lserdy lseon rw rw rw rw r rw bits 31:17 reserved, always read as 0. bit 16 bdrst: backup domain software reset set and cleared by software. 0: reset not activated 1: resets the entire backup domain note: the bkpsram is not affected by this reset, the only wa y of resetting the bkpsram is through the flash interface when a protection level change from level 1 to level 0 is requested. bit 15 rtcen: rtc clock enable set and cleared by software. 0: rtc clock disabled 1: rtc clock enabled bits 14:10 reserved, always read as 0. bits 9:8 rtcsel[1:0]: rtc clock source selection set by software to select the clock source for the rtc. once the rtc clock source has been selected, it cannot be changed anymore unless the backup domain is reset. the bdrst bit can be used to reset them. 00: no clock 01: lse oscillator clock used as the rtc clock 10: lsi oscillator clock used as the rtc clock 11: hse oscillator clock divided by a programmable prescaler (selection through the rtcpre[4:0] bits in the rcc clock configuration register (rcc_cfgr)) used as the rtc clock bits 7:3 reserved, always read as 0. bit 2 lsebyp: external low-speed oscillator bypass set and cleared by software to bypass oscillator in debug mode. this bit can be written only when the lse clock is disabled. 0: lse oscillator not bypassed 1: lse oscillator bypassed RM0033 reset and clock control (rcc) doc id 15403 rev 3 127/1317 5.3.21 rcc clock control & st atus register (rcc_csr) address offset: 0x74 reset value: 0x0e00 0000, reset by system rese t, except reset flags by power reset only. access: 0 wait state 3, word, half-word and byte access wait states are inserted in case of successive accesses to this register. bit 1 lserdy: external low-speed oscillator ready set and cleared by hardware to indicate when the external 32 khz oscillator is stable. after the lseon bit is cleared, lserdy goes low after 6 external low-speed oscillator clock cycles. 0: lse clock not ready 1: lse clock ready bit 0 lseon: external low-speed oscillator enable set and cleared by software. 0: lse clock off 1: lse clock on 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 lpwr rstf wwdg rstf iwdg rstf sft rstf por rstf pin rstf borrs tf rmvf reserved rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved lsirdy lsion rrw bit 31 lpwrrstf: low-power reset flag set by hardware when a low-power management reset occurs. cleared by writing to the rmvf bit. 0: no low-power management reset occurred 1: low-power management reset occurred for further information on low-power management reset, refer to low-power management reset . bit 30 wwdgrstf: window watchdog reset flag set by hardware when a window watchdog reset occurs. cleared by writing to the rmvf bit. 0: no window watchdog reset occurred 1: window watchdog reset occurred bit 29 iwdgrstf: independent watchdog reset flag set by hardware when an independent watchdog reset from v dd domain occurs. cleared by writing to the rmvf bit. 0: no watchdog reset occurred 1: watchdog reset occurred bit 28 sftrstf: software reset flag set by hardware when a software reset occurs. cleared by writing to the rmvf bit. 0: no software reset occurred 1: software reset occurred reset and clock control (rcc) RM0033 128/1317 doc id 15403 rev 3 bit 27 porrstf: por/pdr reset flag set by hardware when a por/pdr reset occurs. cleared by writing to the rmvf bit. 0: no por/pdr reset occurred 1: por/pdr reset occurred bit 26 pinrstf: pin reset flag set by hardware when a reset from the nrst pin occurs. cleared by writing to the rmvf bit. 0: no reset from nrst pin occurred 1: reset from nrst pin occurred bit 25 borrstf: bor reset flag cleared by software by writing the rmvf bit. set by hardware when a por/pdr or bor reset occurs. 0: no por/pdr or bor reset occurred 1: por/pdr or bor reset occurred bit 24 rmvf: remove reset flag set by software to clear the reset flags. 0: no effect 1: clear the reset flags bits 23:2 reserved, always read as 0. bit 1 lsirdy: internal low-speed oscillator ready set and cleared by hardware to indicate when the internal rc 40 khz oscillator is stable. after the lsion bit is cleared, lsirdy goes low after 3 lsi clock cycles. 0: lsi rc oscillator not ready 1: lsi rc oscillator ready bit 0 lsion: internal low-speed oscillator enable set and cleared by software. 0: lsi rc oscillator off 1: lsi rc oscillator on RM0033 reset and clock control (rcc) doc id 15403 rev 3 129/1317 5.3.22 rcc spread spectrum cloc k generation regi ster (rcc_sscgr) address offset: 0x80 reset value: 0x0000 0000 access: no wait state, word, half-word and byte access. the spread spectrum clock generation is available only for the main pll. the rcc_sscgr register must be written either before the main pll is enabled or after the main pll disabled. note: for full details about pll spread spectrum clock generation (sscg) characteristics, refer to the ?electrical characteristics? se ction in your device datasheet. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 sscg en spr ead sel reserved incstep rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109 8 765432 1 0 modper rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31 sscgen: spread spectrum modulation enable set and cleared by software. 0: spread spectrum modulation disable. (to write after clearing cr[24]=pllon bit) 1: spread spectrum modulation enable. (to write before setting cr[24]=pllon bit) bit 30 spreadsel: spread select set and cleared by software. to write before to set cr[24]=pllon bit. 0: center spread 1: down spread bit 29:28 reserved bit 27:13 incstep: incrementation step set and cleared by software. to write before setting cr[24]=pllon bit. configuration input for mo dulation profile amplitude. bit 12:0 modper: modulation period set and cleared by software. to write before setting cr[24]=pllon bit. configuration input for modulation profile period. reset and clock control (rcc) RM0033 130/1317 doc id 15403 rev 3 5.3.23 rcc plli2s configuratio n register (rcc_plli2scfgr) address offset: 0x84 reset value: 0x2000 3000 access: no wait state, word, half-word and byte access. this register is used to configure the plli2s clock outputs according to the formulas: f (vco clock) = f (plli2s clock input) (plli2sn / pllm) f (pll i2s clock output) = f (vco clock) / plli2sr 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserv ed plli2s r2 plli2s r1 plli2s r0 reserved rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserv ed plli2sn 8 plli2sn 7 plli2sn 6 plli2sn 5 plli2sn 4 plli2sn 3 plli2sn 2 plli2sn 1 plli2sn 0 reserved rw rw rw rw rw rw rw rw rw bit 31 reserved, always read as 0. bits 30:28 plli2sr: plli2s division factor for i2s clocks set and cleared by software to control the i2s clock frequency. these bits should be written only if the plli2s is disabled. the factor must be chosen in accordance with the prescaler values inside the i2s peripherals, to reach 0.3% error when using standard crystals and 0% error with audio crystals. for more information about i2s clock frequency and precision, refer to section 25.4.3: clock generator in the i2s chapter. caution: the i2ss requires a frequency lower than or equal to 192 mhz to work correctly. i2s clock frequency = vco frequency / pllr with 2 pllr 7 000: pllr = 0, wrong configuration 001: pllr = 1, wrong configuration 010: pllr = 2 ... 111: pllr = 7 RM0033 reset and clock control (rcc) doc id 15403 rev 3 131/1317 bits 27:15 reserved, always read as 0. bits 14:6 plli2sn: plli2s multiplication factor for vco set and cleared by software to control the multip lication factor of the vco. these bits can be written only when the plli2s is disabled. only half-word and word accesses are allowed to write these bits. caution: the software has to set these bits co rrectly to ensure that the vco output frequency is between 192 and 432 mhz. vco output frequency = vco input frequency plli2sn with 192 plli2sn 432 000000000: plli2sn = 0, wrong configuration 000000001: plli2sn = 1, wrong configuration ... 011000000: plli2sn = 192 011000001: plli2sn = 193 011000010: plli2sn = 194 ... 110110000: plli2sn = 432 110110000: plli2sn = 433, wrong configuration ... 111111111: plli2sn = 511, wrong configuration bits 5:0 reserved, always read as 0. reset and clock control (rcc) RM0033 132/1317 doc id 15403 rev 3 5.3.24 rcc register map ta bl e 1 3 gives the register map and reset values. table 13. rcc register map and reset values addr. offset register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 rcc_cr reserved pll i2srdy pll i2son pll rdy pll on reserved csson hsebyp hserdy hseon hsical 7 hsical 6 hsical 5 hsical 4 hsical 3 hsical 2 hsical 1 hsical 0 hsitrim 4 hsitrim 3 hsitrim 2 hsitrim 1 hsitrim 0 reserved hsirdy hsion 0x04 rcc_pllcf gr reserved pllq 3 pllq 2 pllq 1 pllq 0 reserved pllsrc reserved pllp 1 pllp 0 reserved plln 8 plln 7 plln 6 plln 5 plln 4 plln 3 plln 2 plln 1 plln 0 pllm 5 pllm 4 pllm 3 pllm 2 pllm 1 pllm 0 0x08 rcc_cfgr mco2 1 mco2 0 mco2pre2 mco2pre1 mco2pre0 mco1pre2 mco1pre1 mco1pre0 i2ssrc mco1 1 mco1 0 rtcpre 4 rtcpre 3 rtcpre 2 rtcpre 1 rtcpre 0 ppre2 2 ppre2 1 ppre2 0 ppre1 2 ppre1 1 ppre1 0 reserved hpre 3 hpre 2 hpre 1 hpre 0 sws 1 sws 0 sw 1 sw 0 0x0c rcc_cir reserved cssc reserved plli2srdyc pllrdyc hserdyc hsirdyc lserdyc lsirdyc reserved plli2srdyie pllrdyie hserdyie hsirdyie lserdyie lsirdyie cssf reserved plli2srdyf pllrdyf hserdyf hsirdyf lserdyf lsirdyf 0x10 rcc_ahb1r str reserved otghsrst reserved ethmacrst reserved dma2rst dma1rst reserved crcrst reserved gpioirst gpiohrst gpiogrst gpiofrst gpioerst gpiodrst gpiocrst gpiobrst gpioarst 0x14 rcc_ahb2r str reserved otgfsrst rngrst hsahrst cryprst reserved dcmirst 0x18 rcc_ahb3r str reserved fsmcrst 0x1c reserved reserved 0x20 rcc_apb1r str reserved dacrst pwrrst reserved can2rst can1rst reserved i2c3rst i2c2rst i2c1rst uart5rst uart4rst uart3rst uart2rst reserved spi3rst spi2rst reserved wwdgrst reserved tim14rst tim13rst tim12rst tim7rst tim6rst tim5rst tim4rst tim3rst tim2rst 0x24 rcc_apb2r str reserved tim11rst tim10rst tim9rst reserved syscfgrst reserved spi1rst sdiorst reserved adcrst reserved usart6rst usart1rst reserved tim8rst tim1rst 0x28 reserved reserved 0x2c reserved reserved 0x30 rcc_ahb1e nr reserved otghsulpien otghsen ethmacptpen ethmacrxen ethmactxen ethmacen reserved dma2en dma1en reserved bkpsramen reserved crcen reserved gpioien gpiohen gpiogen gpiofen gpioeen gpioden gpiocen gpioben gpioaen 0x34 rcc_ahb2e nr reserved otgfsen rngen hashen crypen reserved dcmien 0x38 rcc_ahb3e nr reserved fsmcen 0x3c reserved reserved RM0033 reset and clock control (rcc) doc id 15403 rev 3 133/1317 refer to table 1 on page 50 for the register boundary addresses. 0x40 rcc_apb1e nr reserved dacen pwren reserved can2en can1en reserved i2c3en i2c2en i2c1en uart5en uart4en usart3en usart2en reserved spi3en spi2en reserved wwdgen reserved tim14en tim13en tim12en tim7en tim6en tim5en tim4en tim3en tim2en 0x44 rcc_apb2e nr reserved tim11en tim10en tim9en reserved syscfgen reserved spi1en sdioen adc3en adc2en adc1en reserved usart6en usart1en reserved tim8en tim1en 0x48 reserved reserved 0x4c reserved reserved 0x50 rcc_ahb1l penr reserved otghsulpilpen otghslpen ethmacptplpen ethmacrxlpen ethmactxlpen ethmaclpen reserved dma2lpen dma1lpen reserved bkpsramlpen sram2lpen sram1lpen flitflpen reserved crclpen reserved gpioilpen gpiohlpen gpioglpen gpioflpen gpioelpen gpiodlpen gpioclpen gpioblpen gpioalpen 0x54 rcc_ahb2l penr reserved otgfslpen rnglpen hashlpen cryplpen reserved dcmilpen 0x58 rcc_ahb3l penr reserved fsmclpen 0x5c reserved reserved 0x60 rcc_apb1l penr reserved daclpen pwrlpen reserved can2lpen can1lpen reserved i2c3lpen i2c2lpen i2c1lpen uart5lpen uart4lpen usart3lpen usart2lpen reserved spi3lpen spi2lpen reserved wwdglpen reserved tim14lpen tim13lpen tim12lpen tim7lpen tim6lpen tim5lpen tim4lpen tim3lpen tim2lpen 0x64 rcc_apb2l penr reserved tim11lpen tim10lpen tim9lpen reserved syscfglpen reserved spi1lpen sdiolpen adc3lpen adc2lpen adc1lpen reserved usart6lpen usart1lpen reserved tim8lpen tim1lpen 0x68 reserved reserved 0x6c reserved reserved 0x70 rcc_bdcr reserved bdrst rtcen reserved rtcsel 1 rtcsel 0 reserved lsebyp lserdy lseon 0x74 rcc_csr lpwrrstf wwdgrstf wdgrstf sftrstf porrstf padrstf borrstf rmvf reserved lsirdy lsion 0x78 reserved reserved 0x7c reserved reserved 0x80 rcc_sscgr sscgen spreadsel reserved incstep modper 0x84 rcc_plli2s cfgr reserved plli2srx reserved plli2snx reserved table 13. rcc register map and reset values (continued) addr. offset register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 general-purpose i/os (gpio) RM0033 134/1317 doc id 15403 rev 3 6 general-purpose i/os (gpio) 6.1 gpio introduction each general-purpose i/o port has four 32-bit configuration registers (gpiox_moder, gpiox_otyper, gpiox_ospeedr and gpiox _pupdr), two 32-bit data registers (gpiox_idr and gpiox_odr), a 32-bit set/reset register (gpiox_bsrr), a 32-bit locking register (gpiox_lckr) and two 32-bit alternate function selection register (gpiox_afrh and gpiox_afrl). 6.2 gpio main features up to 16 i/os under control output states: push-pull or open drain + pull-up/down output data from output data register (gpiox_odr) or peripheral (alternate function output) speed selection for each i/o input states: floating, pull-up/down, analog input data to input data register (gpiox_idr) or peripheral (alternate function input) bit set and reset register (gpiox_bsrr) for bitwise write access to gpiox_odr locking mechanism (gpiox_lckr) provided to freeze the i/o configuration analog function alternate function input/output selection registers (at most 16 afs per i/o) fast toggle capable of changing every two clock cycles highly flexible pin multiplexing allows the use of i/o pins as gpios or as one of several peripheral functions 6.3 gpio functional description subject to the specific hardware characteristics of each i/o port listed in the datasheet, each port bit of the general-purpose i/o (gpio) ports can be individually configured by software in several modes: input floating input pull-up input-pull-down analog output open-drain wi th pull-up or pull-down capability output push-pull wit h pull-up or pull-down capability alternate function push-pull with pull-up or pull-down capability alternate functi on open-drain with pull-up or pull-down capability each i/o port bit is freely programmable, however the i/o port registers have to be accessed as 32-bit words, half-words or bytes. the purpose of the gpiox_bsrr register is to allow atomic read/modify accesses to any of the gpio registers. in this way, there is no risk of an irq occurring between the read and the modify access. RM0033 general-purpose i/os (gpio) doc id 15403 rev 3 135/1317 figure 13 shows the basic structure of a 5 v tolerant i/o port bit. ta b l e 1 8 gives the possible port bit configurations. figure 13. basic structure of a five-volt tolerant i/o port bit 1. v dd_ft is a potential specific to five-vol t tolerant i/os and different from v dd . table 14. port bit configuration table (1) moder(i) [1:0] otyper(i) ospeedr(i) [b:a] pupdr(i) [1:0] i/o configuration 01 0 speed [b:a] 0 0 gp output pp 0 0 1 gp output pp + pu 0 1 0 gp output pp + pd 0 1 1 reserved 1 0 0 gp output od 1 0 1 gp output od + pu 1 1 0 gp output od + pd 1 1 1 reserved (gp output od) ! l t e r n a t e f u n c t i o n o u t p u t ! l t e r n a t e f u n c t i o n i n p u t 0 u s h p u l l o p e n d r a i n o r d i s a b l e d / u t p u t d a t a r e g i s t e r 2 e a d w r i t e & r o m o n c h i p p e r i p h e r a l 4 o o n c h i p p e r i p h e r a l / u t p u t c o n t r o l ! n a l o g o n o f f 0 u l l 0 u l l o n o f f ) / p i n 6 $ $ 6 $ $ 6 3 3 6 3 3 4 4 , 3 c h m i t t t r i g g e r 6 3 3 6 $ $ ? & 4 0 r o t e c t i o n d i o d e 0 r o t e c t i o n d i o d e o n o f f ) n p u t d r i v e r / u t p u t d r i v e r d o w n u p 0 - / 3 . - / 3 2 e a d " i t s e t r e s e t r e g i s t e r s 7 r i t e ! n a l o g ) n p u t d a t a r e g i s t e r a i b general-purpose i/os (gpio) RM0033 136/1317 doc id 15403 rev 3 6.3.1 general-purpose i/o (gpio) during and just after reset, the alternate functions are not active and the i/o ports are configured in input floating mode. the jtag pins are in input pull-up/pull-down after reset: pa15: jtdi in pull-up pa14: jtck in pull-down pa13: jtms in pull-up pb4: njtrst in pull-up when the pin is configured as output, the value written to the output data register (gpiox_odr) is output on the i/o pin. it is possible to use the output driver in push-pull mode or open-drain mode (only the n-mos is activated when 0 is output). the input data register (gpiox_idr) captures the data present on the i/o pin at every ahb1 clock cycle. all gpio pins have weak internal pull-up and pull-down resistors, which can be activated or not depending on the value in the gpiox_pupdr register. 10 0 speed [b:a] 0 0 af pp 0 0 1 af pp + pu 0 1 0 af pp + pd 011reserved 100afod 101afod + pu 110afod + pd 111reserved 00 x x x 0 0 input floating x x x 0 1 input pu x x x 1 0 input pd x x x 1 1 reserved (input floating) 11 x x x 0 0 input/output analog xxx01 reserved xxx10 xxx11 1. gp = general-purpose, pp = push-pull, pu = pull-up, pd = pull-down, od = open-drain, af = alternate function. table 14. port bit configuration table (1) (continued) moder(i) [1:0] otyper(i) ospeedr(i) [b:a] pupdr(i) [1:0] i/o configuration RM0033 general-purpose i/os (gpio) doc id 15403 rev 3 137/1317 6.3.2 i/o pin multiplexer and mapping the stm32f20x and stm32f21x i/o pins are connected to onboard peripherals/modules through a multiplexer that allows only one peripheral?s alternate function (af) connected to an i/o pin at a time. in this way, there can be no conflict between peripherals sharing the same i/o pin. each i/o pin has a multiplexer with sixteen alternate function inputs (af0 to af15) that can be configured through the gpiox_afrl (for pin 0 to 7) and gpiox_afrh (for pin 8 to 15) registers: after reset all i/os are connected to th e system?s alternate function 0 (af0) the peripherals? alternate functions are mapped from af1 to af13 cortex-m3 eventout is mapped on af15 this structure is shown in figure 14 below. in addition to this flexible i/o multiplexing architecture, each peripheral has alternate functions mapped onto different i/o pins to optimize the number of peripherals available in smaller packages. to use an i/o in a given configuration, you have to proceed as follows: system function: you have to connect the i/o to af0 and configure it depending on the function used: ? jtag/swd, after each device reset these pins are assigned as dedicated pins immediately usable by the debugger host (not controlled by the gpio controller) ? rtc_50hz: this pin should be configured in input floating mode ? mco1 and mco2: these pins have to be configured in alternate function mode. note: you can disable some or all of the jtag/swd pins and so release the associated pins for gpio usage. for more details please refer to section 5.2.10: clo ck-out capability . gpio: configure the desired i/o as output or input in the gpiox_moder register. table 15. flexible swj-dp pin assignment available debug ports swj i/o pin assigned pa13 / jtms/ swdio pa14 / jtck/ swclk pa15 / jtdi pb3 / jtdo pb4/ njtrst full swj (jtag-dp + sw-dp) - reset state x x x x x full swj (jtag-dp + sw-dp) but without njtrst xxxx jtag-dp disabled and sw-dp enabled x x jtag-dp disabled and sw-dp disabled released general-purpose i/os (gpio) RM0033 138/1317 doc id 15403 rev 3 peripheral?s alternate function: for the adc and dac, configure the desired i/o as analog in the gpiox_moder register. for other peripherals: ? configure the desired i/o as an alternate function in the gpiox_moder register ? select the type, pull-up/pull-down and output speed via the gpiox_otyper, gpiox_pupdr and gpiox_ospeeder registers, respectively ? connect the i/o to the desired afx in the gpiox_afrl or gpiox_afrh register eventout: you can configure the i/o pin used to output the cortex-m3 eventout signal by connecting it to af15 note: eventout is not mapped on to the following i/o pins: pc13, pc14, pc15, ph0, ph1 and pi8. please refer to the ?alternate function mapping? table in the stm32f20x and stm32f21x datasheets for the detailed mapping of the system and peripherals? alternate function i/o pins. RM0033 general-purpose i/os (gpio) doc id 15403 rev 3 139/1317 figure 14. selecting an alternate function 1. configured in fs. 6.3.3 i/o port con trol registers each of the gpios has four 32-bit memory-mapped control registers (gpiox_moder, gpiox_otyper, gpiox_ospeedr, gpiox_pupdr) to configure up to 16 i/os. the gpiox_moder register is used to select the i/o direction (input, output, af, analog). the gpiox_otyper and gpiox_ospeedr registers are used to select the output type (push- pull or open-drain) and speed (the i/o speed pins are directly connected to the corresponding gpiox_ospeedr register bits what ever the i/o direction). the gpiox_pupdr register is used to select the pull-up/pull-down whatev er the i/o direction. 6.3.4 i/o port data registers each gpio has two 16-bit memory-mapped data registers: input and output data registers (gpiox_idr and gpiox_odr). gpiox_odr stores the data to be output, it is read/write accessible. the data input through the i/o are stored into the input data register (gpiox_idr), a read-only register. a i175 38 for pin s 0 to 7, the gpiox_afrl[ 3 1:0] regi s ter s elect s the dedic a ted a ltern a te f u nction af0 ( s y s tem) af1 (tim1/tim2) af2 (tim 3 ..5) af 3 (tim 8 ..11) af4 (i2c1.. 3 ) af5 ( s pi1/ s pi2) af6 ( s pi 3 ) af7 (u s art1.. 3 ) af 8 (u s art4..6) af9 (can1/can2, tim12..14) af10 (otg_f s , otg_h s ) af11 (eth) af12 (f s mc, s dio, otg_h s (1) ) af1 3 (dcmi) af14 af15 (eventout) pin x (x = 0..7) afrl[ 3 1:0] for pin s 8 to 15, the gpiox_afrh[ 3 1:0] regi s ter s elect s the dedic a ted a ltern a te f u nction af0 ( s y s tem) af1 (tim1/tim2) af2 (tim 3 ..5) af 3 (tim 8 ..11) af4 (i2c1.. 3 ) af5 ( s pi1/ s pi2) af6 ( s pi 3 ) af7 (u s art1.. 3 ) af 8 (u s art4..6) af9 (can1/can2, tim12..14) af10 (otg_f s , otg_h s ) af11 (eth) af12 (f s mc, s dio, otg_h s (1) ) af1 3 (dcmi) af14 af15 (eventout) pin x (x = 8 ..15) afrh[ 3 1:0] 1 1 general-purpose i/os (gpio) RM0033 140/1317 doc id 15403 rev 3 see section 6.4.5: gpio port input data register (gpiox_idr) (x = a..i) and section 6.4.6: gpio port output data register (gpiox_odr) (x = a..i) for the register descriptions. 6.3.5 i/o data bitwise handling the bit set reset register (gpiox_bsrr) is a 32-bit register which allows the application to set and reset each individual bit in the output data register (gpiox_odr). the bit set reset register has twice the size of gpiox_odr. to each bit in gpiox_odr, correspond two control bits in gpiox_bsrr: bsrr(i) and bsrr(i+size). when writ ten to 1, bit bsrr(i) sets the corresponding odr(i) bit. when written to 1, bit bsrr(i+size) resets the odr(i) corresponding bit. writing any bit to 0 in gpiox_bsrr does not have any effect on the corresponding bit in gpiox_odr. if there is an attempt to both set and reset a bit in gpiox_bsrr, the set action takes priority. using the gpiox_bsrr register to change the va lues of individual bits in gpiox_odr is a ?one-shot? effect that does not lock the gpiox_odr bits. the gpiox_odr bits can always be accessed directly. the gpiox_bsrr register provides a way of performing atomic bitwise handling. there is no need for the software to disable interrupts when programming the gpiox_odr at bit level: it is possible to modify one or more bits in a single atomic ahb1 write access. 6.3.6 gpio locking mechanism it is possible to freeze the gpio control register s by applying a specific write sequence to the gpiox_lckr register. the frozen re gisters are gpiox_moder, gpiox_otyper, gpiox_ospeedr, gpiox_pupdr, gpiox_afrl and gpiox_afrh. to write the gpiox_lckr register, a specific write / read sequence has to be applied. when the right lock sequence is applied to bit 16 in this register, the value of lckr[15:0] is used to lock the configuration of the i/os (during the write sequence the lckr[15:0] value must be the same). when the lock sequence has been applied to a port bit, the value of the port bit can no longer be modified until the next reset. each gpiox_lckr bit freezes the corresponding bit in the control register s (gpiox_moder, gpiox_otyper, gpiox_ospeedr, gpiox_pupdr, gpiox_afrl and gpiox_afrh). the lock sequence (refer to section 6.4.8: gpio port configuration lock register (gpiox_lckr) (x = a..i) ) can only be performed using a word (32-bit long) access to the gpiox_lckr register due to the fact that gpiox_lckr bit 16 has to be set at the same time as the [15:0] bits. for more details please refer to lckr register description in section 6.4.8: gpio port configuration lock register (gpiox_lckr) (x = a..i) . 6.3.7 i/o alternate function input/output two registers are provided to select one out of the sixteen alternate function inputs/outputs available for each i/o. with these registers, you can connect an alternate function to some other pin as required by your application. this means that a number of possible peripheral functions are multiplexed on each gpio using the gpiox_afrl and gpiox_afrh alternate function registers. the application can thus select any one of the possible functions for each i/o. the af selection signal being RM0033 general-purpose i/os (gpio) doc id 15403 rev 3 141/1317 common to the alternate function input and alternate function output, a single channel is selected for the alternate function input/output of one i/o. to know which functions are multiplexed on each gpio pin, refer to the stm32f20x and stm32f21x datasheets. note: the application is allowed to select one of the possible peripheral functions for each i/o at a time. 6.3.8 external in terrupt/wakeup lines all ports have external interrupt capability. to use external interrupt lines, the port must be configured in input mode, refer to section 8.2: external interrupt/event controller (exti) and section 8.2.3: wakeup event management . 6.3.9 input configuration when the i/o port is programmed as input: the output buffer is disabled the schmitt trigger input is activated the pull-up and pull-down resistors are activated depending on the value in the gpiox_pupdr register the data present on the i/o pin are sampled into the input data register every ahb1 clock cycle a read access to the input data register provides the i/o state figure 15 shows the input configuration of the i/o port bit. figure 15. input floating/pull up/pull down configurations o n o f f p u l l p u l l o n o f f ) / p i n 6 $ $ 6 3 3 4 4 , 3 c h m i t t t r i g g e r 6 3 3 6 $ $ p r o t e c t i o n d i o d e p r o t e c t i o n d i o d e o n i n p u t d r i v e r o u t p u t d r i v e r d o w n u p ) n p u t d a t a r e g i s t e r / u t p u t d a t a r e g i s t e r 2 e a d w r i t e 2 e a d " i t s e t r e s e t r e g i s t e r s 7 r i t e a i b general-purpose i/os (gpio) RM0033 142/1317 doc id 15403 rev 3 6.3.10 output configuration when the i/o port is programmed as output: the output buffer is enabled: ? open drain mode: a ?0? in the output register activates the n-mos whereas a ?1? in the output register leaves the port in hi-z (the p-mos is never activated) ? push-pull mode: a ?0? in the output register activates the n-mos whereas a ?1? in the output register activates the p-mos the schmitt trigger input is activated the weak pull-up and pull-down resistors are activated or not depending on the value in the gpiox_pupdr register the data present on the i/o pin are sampled into the input data register every ahb1 clock cycle a read access to the input data register gets the i/o state a read access to the output data register gets the last written value in push-pull mode figure 16 shows the output configuration of the i/o port bit. figure 16. output configuration 6.3.11 alternate function configuration when the i/o port is programmed as alternate function: the output buffer is turned on in open-drain or push-pull configuration the output buffer is driven by the signal coming from the peripheral (alternate function out) the schmitt trigger input is activated the weak pull-up and pull-down resistors are activated or not depending on the value in the gpiox_pupdr register the data present on the i/o pin are sampled into the input data register every ahb1 clock cycle a read access to the input data register gets the i/o state a read access to the output data register gets the last value written in push-pull mode 0 u s h p u l l o r / p e n d r a i n / u t p u t c o n t r o l 6 $ $ 6 3 3 4 4 , 3 c h m i t t t r i g g e r o n ) n p u t d r i v e r / u t p u t d r i v e r 0 - / 3 . - / 3 ) n p u t d a t a r e g i s t e r / u t p u t d a t a r e g i s t e r 2 e a d w r i t e 2 e a d " i t s e t r e s e t r e g i s t e r s 7 r i t e o n o f f p u l l p u l l o n o f f 6 $ $ 6 3 3 6 3 3 6 $ $ p r o t e c t i o n d i o d e p r o t e c t i o n d i o d e d o w n u p ) / p i n a i b RM0033 general-purpose i/os (gpio) doc id 15403 rev 3 143/1317 figure 17 shows the alternate function configuration of the i/o port bit. figure 17. alternate function configuration 6.3.12 analog configuration when the i/o port is programmed as analog configuration: the output buffer is disabled the schmitt trigger input is deactivated, providing zero consumption for every analog value of the i/o pin. the output of the schmitt trigger is forced to a constant value (0). the weak pull-up and pull-down resistors are disabled read access to the input data register gets the value ?0? note: in the analog configuration, the i/o pins cannot be 5 volt tolerant. figure 18 shows the high-impedance, analog-input configuration of the i/o port bit. figure 18. high impedance-analog configuration ! l t e r n a t e f u n c t i o n o u t p u t ! l t e r n a t e f u n c t i o n i n p u t p u s h p u l l o r o p e n d r a i n & r o m o n c h i p p e r i p h e r a l 4 o o n c h i p p e r i p h e r a l / u t p u t c o n t r o l 6 $ $ 6 3 3 4 4 , 3 c h m i t t t r i g g e r o n ) n p u t d r i v e r / u t p u t d r i v e r 0 - / 3 . - / 3 ) n p u t d a t a r e g i s t e r / u t p u t d a t a r e g i s t e r 2 e a d w r i t e 2 e a d " i t s e t r e s e t r e g i s t e r s 7 r i t e o n o f f o n o f f 6 $ $ 6 3 3 6 3 3 6 $ $ p r o t e c t i o n d i o d e p r o t e c t i o n d i o d e 0 u l l 0 u l l ) / p i n d o w n u p a i b & r o m o n c h i p p e r i p h e r a l 4 o o n c h i p p e r i p h e r a l ! n a l o g t r i g g e r o f f ) n p u t d r i v e r ) n p u t d a t a r e g i s t e r / u t p u t d a t a r e g i s t e r 2 e a d w r i t e 2 e a d " i t s e t r e s e t r e g i s t e r s 7 r i t e ! n a l o g 6 3 3 6 $ $ p r o t e c t i o n d i o d e p r o t e c t i o n d i o d e ) / p i n a i 4 4 , 3 c h m i t t general-purpose i/os (gpio) RM0033 144/1317 doc id 15403 rev 3 6.3.13 using the osc32_in/o sc32_out pins as gpio pc14/pc15 port pins the lse oscillator pins osc32_in and osc 32_out can be used as general-purpose pc14 and pc15 i/os, respective ly, when the lse oscillator is off. the pc14 and pc15 i/os are only configured as l se oscillator pins osc32_in and osc32_out when the lse oscillator is on. this is done by setting the lseon bit in the rcc_bdcr register. the lse has priority over the gpio function. note: the pc14/pc15 gpio functionality is lost when the 1.2 v domain is powered off (by the device entering the standby mode) or when the backup domain is supplied by v bat (v dd no more supplied). in this case the i/os are set in analog input mode. 6.3.14 using the osc_in/osc_out pins as gpio ph0 /ph1 port pins the hse oscillator pins osc_in/osc_out can be used as general-purpose ph0/ph1 i/os, respectively, when the hse oscillator is of f. (after reset, the hse oscillator is off). the ph0/ph1 i/os are only conf igured as osc_in/osc_out h se oscillator pins when the hse oscillator is on. this is done by setting the hseon bi t in the rcc_cr register. the hse has priority over the gpio function. 6.3.15 selection of rtc_af1 and rtc_af2 alte rnate functions the stm32f20xxx features two gpio pins rtc_af1 and rtc_af2 that can be used for the detection of a tamper or time stamp event, or afo_alarm, or afo_calib rtc outputs. the rtc_af1 (pc13) can be used for the following purposes: rtc afo_alarm output: this output can be rtc alarm a, rtc alarm b or rtc wakeup depending on the osel[1:0] bits in the rtc_cr register rtc afo_calib output: this feature is enabl ed by setting the coe[23] in the rtc_cr register rtc afi_tamper1: tamper event detection rtc afi_timestamp: time stamp event detection the rtc_af2 (pi8) can be used for the following purposes: rtc afi_tamper1: tamper event detection rtc afi_timestamp: time stamp event detection the selection of the corresponding pin is performed through the rtc_tafcr register as follows: tamp1insel is used to select which pin is used as the afi_tamper1 tamper input tsinsel is used to select which pin is used as the afi_timestamp time stamp input alarmouttype is used to se lect whether the rtc afo_ alarm is output in push- pull or open-drain mode the output mechanism follows the priority order listed in ta bl e 1 6 and ta b l e 1 7 . RM0033 general-purpose i/os (gpio) doc id 15403 rev 3 145/1317 6.4 gpio registers this section gives a detailed description of the gpio registers. for a summary of register bits, register address offsets and reset values, refer to ta b l e 1 8 . 6.4.1 gpio port m ode register (gpiox _moder) (x = a..i) address offset: 0x00 reset values: 0xa800 0000 for port a 0x0000 0280 for port b 0x0000 0000 for other ports table 16. rtc_af1 pin (1) pin configuration and function afo_alarm enabled afo_calib enabled tamper enabled time stamp enabled tamp1insel tamper1 pin selection tsinsel timestamp pin selection alarmouttype afo_alarm configuration alarm out output od 1 don?t care don?t care don?t care don?t care don?t care 0 alarm out output pp 1 don?t care don?t care don?t care don?t care don?t care 1 calibration out output pp 01don?t care don?t care don?t care don?t care don?t care tamper1 input floating 0 0 1 0 0 don?t care don?t care timestamp and tamper1 input floating 001100don?t care timestamp input floating 0 0 0 1 don?t care 0 don?t care standard gpio 0 0 0 0 don?t care don?t care don?t care 1. od: open drain; pp: push-pull. table 17. rtc_af2 pin pin configuration and function tamper enabled time stamp enabled tamp1insel tamper1 pin selection tsinsel timestamp pin selection alarmouttype afo_alarm configuration tamper1 input floating 1 0 1 don?t care don?t care timestamp and tamper1 input floating 11 1 1 don?t care timestamp input floating 0 1 don?t care 1 don?t care standard gpio 0 0 don?t care don?t care don?t care general-purpose i/os (gpio) RM0033 146/1317 doc id 15403 rev 3 6.4.2 gpio port output type r egister (gpiox_otyper) (x = a..i) address offset: 0x04 reset value: 0x0000 0000 6.4.3 gpio port output speed register (gpiox_ospeedr) (x = a..i) address offset: 0x08 reset values: 0x0000 00c0 for port b 0x0000 0000 for other ports 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 moder15[1:0] moder14[1:0] moder13[1:0] moder12[1:0] moder11[1:0] moder10[1:0] moder9[1:0] moder8[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 moder7[1:0] moder6[1:0] moder5[1:0] moder4[1:0] moder3[1:0] moder2[1:0] moder1[1:0] moder0[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 2y:2y+1 modery[1:0]: port x configuration bits (y = 0..15) these bits are written by software to configure the i/o direction mode. 00: input (reset state) 01: general purpose output mode 10: alternate function mode 11: analog mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 ot15 ot14 ot13 ot12 ot11 ot10 ot9 ot8 ot7 ot6 ot5 ot4 ot3 ot2 ot1 ot0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:16 reserved, always read as 0. bits 15:0 oty[1:0]: port x configuration bits (y = 0..15) these bits are written by software to c onfigure the output ty pe of the i/o port. 0: output push-pull (reset state) 1: output open-drain 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ospeedr15[1:0] ospeedr14[1:0] ospeedr13[1:0] ospeedr12[1:0] ospeedr11[1:0] ospeedr10[1:0] ospeedr9[1:0] ospeedr8[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ospeedr7[1:0] ospeedr6[1:0] ospeedr5[1:0] ospeedr4[1:0] ospeedr3[1:0] ospeedr2[1:0] ospeedr1[1:0] ospeedr0[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw RM0033 general-purpose i/os (gpio) doc id 15403 rev 3 147/1317 6.4.4 gpio port pu ll-up/pull-down regi ster (gpiox_pupdr) (x = a..i) address offset: 0x0c reset values: 0x6400 0000 for port a 0x0000 0100 for port b 0x0000 0000 for other ports 6.4.5 gpio port input data register (gpi ox_idr) (x = a..i) address offset: 0x10 reset value: 0x0000 xxxx (where x means undefined) bits 2y:2y+1 ospeedry[1:0]: port x configuration bits (y = 0..15) these bits are written by software to configure the i/o output speed. 00: 2 mhz low speed 01: 25 mhz medium speed 10: 50 mhz fast speed 11: 100 mhz high speed on 30 pf (80 mhz output max speed on 15 pf) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 pupdr15[1:0] pupdr14[1:0] pupdr13[1:0] pupdr12[1:0] pupdr11[1:0] pupdr10[1:0] pupdr9[1:0] pupdr8[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 pupdr7[1:0] pupdr6[1:0] pupdr5[1:0] pupdr4[1:0 ] pupdr3[1:0] pupdr2[1:0] pupdr1[1:0] pupdr0[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 2y:2y+1 pupdry[1:0]: port x configuration bits (y = 0..15) these bits are written by software to configure the i/o pull-up or pull-down 00: no pull-up, pull-down 01: pull-up 10: pull-down 11: reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 idr15 idr14 idr13 idr12 idr11 idr10 idr9 idr8 idr7 idr6 idr5 idr4 idr3 idr2 idr1 idr0 rrrrrr r r r r rrrrrr bits 31:16 reserved, always read as 0. bits 15:0 idry[15:0]: port input data (y = 0..15) these bits are read-only and can be accessed in word mode only. they contain the input value of the corresponding i/o port. general-purpose i/os (gpio) RM0033 148/1317 doc id 15403 rev 3 6.4.6 gpio port output data r egister (gpiox_o dr) (x = a..i) address offset: 0x14 reset value: 0x0000 0000 6.4.7 gpio port bit se t/reset register (gpi ox_bsrr) (x = a..i) address offset: 0x18 reset value: 0x0000 0000 6.4.8 gpio port c onfiguration lock register (gpiox_lckr) (x = a..i) this register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (lckk). the value of bits [1 5:0] is used to lock the configuration of the gpio. during the write sequence, the value of lckr[15:0] must not change. when the 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 odr15 odr14 odr13 odr12 odr11 odr10 odr9 odr8 odr7 odr6 odr5 odr4 odr3 odr2 odr1 odr0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:16 reserved, always read as 0. bits 15:0 odry[15:0]: port output data (y = 0..15) these bits can be read and written by software. note: for atomic bit set/reset, the odr bits can be individually set and reset by writing to the gpiox_bsrr register (x = a..i). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 br15 br14 br13 br12 br11 br10 br9 br8 br7 br6 br5 br4 br3 br2 br1 br0 wwwwwwwwwwwwwwww 1514131211109876543210 bs15 bs14 bs13 bs12 bs11 bs10 bs9 bs8 bs7 bs6 bs5 bs4 bs3 bs2 bs1 bs0 wwwwwwwwwwwwwwww bits 31:16 bry: port x reset bit y (y = 0..15) these bits are write-only and can be accessed in word, half-word or byte mode. a read to these bits returns the value 0x0000. 0: no action on the corresponding odrx bit 1: resets the corresponding odrx bit note: if both bsx and brx are set, bsx has priority. bits 15:0 bsy: port x set bit y (y= 0..15) these bits are write-only and can be accessed in word, half-word or byte mode. a read to these bits returns the value 0x0000. 0: no action on the corresponding odrx bit 1: sets the corresponding odrx bit RM0033 general-purpose i/os (gpio) doc id 15403 rev 3 149/1317 lock sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next reset. note: a specific write sequence is used to write to the gpiox_lckr register. only word access (32-bit long) is allowed during this write sequence. each lock bit freezes a specific configuration register (control and alternate function registers). address offset: 0x1c reset value: 0x0000 0000 access: 32-bit word only, read/write register 6.4.9 gpio alternate f unction low register (g piox_afrl) (x = a..i) address offset: 0x20 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved lckk rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lck15 lck14 lck13 lck12 lck11 lck10 lck9 lc k8 lck7 lck6 lck5 lck4 lck3 lck2 lck1 lck0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:17 reserved bit 16 lckk[16]: lock key this bit can be read any time. it can only be modified using the lock key write sequence. 0: port configuration lock key not active 1: port configuration lock key active. the gp iox_lckr register is locked until an mcu reset occurs. lock key write sequence: wr lckr[16] = ?1? + lckr[15:0] wr lckr[16] = ?0? + lckr[15:0] wr lckr[16] = ?1? + lckr[15:0] rd lckr rd lckr[16] = ?1? (this read operation is optiona l but it confirms that the lock is active) note: during the lock key write sequence, the value of lck[15:0] must not change. any error in the lock sequence aborts the lock. after the first lock sequence on any bit of the port, any read access on the lckk bit will return ?1? until the next cpu reset. bits 15:0 lcky: port x lock bit y (y= 0..15) these bits are read/write but can only be written when the lckk bit is ?0. 0: port configuration not locked 1: port configuration locked 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 afrl7[3:0] afrl6[3:0] afrl5[3:0] afrl4[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw general-purpose i/os (gpio) RM0033 150/1317 doc id 15403 rev 3 6.4.10 gpio altern ate function high regi ster (gpiox_afrh) (x = a..i) address offset: 0x24 reset value: 0x0000 0000 1514131211109876543210 afrl3[3:0] afrl2[3:0] afrl1[3:0] afrl0[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:0 afrly: alternate function selection for port x bit y (y = 0..7) these bits are written by software to configure alternate function i/os afrly selection: 0000: af0 0001: af1 0010: af2 0011: af3 0100: af4 0101: af5 0110: af6 0111: af7 1000: af8 1001: af9 1010: af10 1011: af11 1100: af12 1101: af13 1110: af14 1111: af15 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 afrh15[3:0] afrh14[3:0] afrh13[3:0] afrh12[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 afrh11[3:0] afrh10[3:0] afrh9[3:0] afrh8[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:0 afrhy: alternate function selection for port x bit y (y = 8..15) these bits are written by software to configure alternate function i/os afrhy selection: 0000: af0 0001: af1 0010: af2 0011: af3 0100: af4 0101: af5 0110: af6 0111: af7 1000: af8 1001: af9 1010: af10 1011: af11 1100: af12 1101: af13 1110: af14 1111: af15 RM0033 general-purpose i/os (gpio) doc id 15403 rev 3 151/1317 6.4.11 gpio register map table 18. gpio register map and reset values offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 gpioa_moder moder15[1:0] moder14[1:0] moder13[1:0] moder12[1:0] moder11[1:0] moder10[1:0] moder9[1:0] moder8[1:0] moder7[1:0] moder6[1:0] moder5[1:0] moder4[1:0] moder3[1:0] moder2[1:0] moder1[1:0] moder0[1:0] reset value 10101000000000000000000000000000 0x00 gpiob_moder moder15[1:0] moder14[1:0] moder13[1:0] moder12[1:0] moder11[1:0] moder10[1:0] moder9[1:0] moder8[1:0] moder7[1:0] moder6[1:0] moder5[1:0] moder4[1:0] moder3[1:0] moder2[1:0] moder1[1:0] moder0[1:0] reset value 00000000000000000000001010000000 0x00 gpiox_moder (where x = c..i) moder15[1:0] moder14[1:0] moder13[1:0] moder12[1:0] moder11[1:0] moder10[1:0] moder9[1:0] moder8[1:0] moder7[1:0] moder6[1:0] moder5[1:0] moder4[1:0] moder3[1:0] moder2[1:0] moder1[1:0] moder0[1:0] reset value 00000000000000000000000000000000 0x04 gpiox_otyper (where x = a..i) reserved ot15 ot14 ot13 ot12 ot11 ot10 ot9 ot8 ot7 ot6 ot5 ot4 ot3 ot2 ot1 ot0 reset value 0100010001000100 0x08 gpiox_ospeed er (where x = a..i except b) ospeedr15[1:0] ospeedr14[1:0] ospeedr13[1:0] ospeedr12[1:0] ospeedr11[1:0] ospeedr10[1:0] ospeedr9[1:0] ospeedr8[1:0] ospeedr7[1:0] ospeedr6[1:0] ospeedr5[1:0] ospeedr4[1:0] ospeedr3[1:0] ospeedr2[1:0] ospeedr1[1:0] ospeedr0[1:0] reset value 00000000000000000000000000000000 0x08 gpiob_ospeed er ospeedr15[1:0] ospeedr14[1:0] ospeedr13[1:0] ospeedr12[1:0] ospeedr11[1:0] ospeedr10[1:0] ospeedr9[1:0] ospeedr8[1:0] ospeedr7[1:0] ospeedr6[1:0] ospeedr5[1:0] ospeedr4[1:0] ospeedr3[1:0] ospeedr2[1:0] ospeedr1[1:0] ospeedr0[1:0] reset value 00000000000000000000000011000000 0x0c gpioa_pupdr pupdr15[1:0] pupdr14[1:0] pupdr13[1:0] pupdr12[1:0] pupdr11[1:0] pupdr10[1:0] pupdr9[1:0] pupdr8[1:0] pupdr7[1:0] pupdr6[1:0] pupdr5[1:0] pupdr4[1:0] pupdr3[1:0] pupdr2[1:0] pupdr1[1:0] pupdr0[1:0] reset value 01100100000000000000000000000000 0x0c gpiob_pupdr pupdr15[1:0] pupdr14[1:0] pupdr13[1:0] pupdr12[1:0] pupdr11[1:0] pupdr10[1:0] pupdr9[1:0] pupdr8[1:0] pupdr7[1:0] pupdr6[1:0] pupdr5[1:0] pupdr4[1:0] pupdr3[1:0] pupdr2[1:0] pupdr1[1:0] pupdr0[1:0] reset value 00000000000000000000000100000000 0x0c gpiox_pupdr (where x = c..i) pupdr15[1:0] pupdr14[1:0] pupdr13[1:0] pupdr12[1:0] pupdr11[1:0] pupdr10[1:0] pupdr9[1:0] pupdr8[1:0] pupdr7[1:0] pupdr6[1:0] pupdr5[1:0] pupdr4[1:0] pupdr3[1:0] pupdr2[1:0] pupdr1[1:0] pupdr0[1:0] reset value 00000000000000000000000000000000 0x10 gpiox_idr (where x = a..i) reserved idr15 idr14 idr13 idr12 idr11 idr10 idr9 idr8 idr7 idr6 idr5 idr4 idr3 idr2 idr1 idr0 reset value xxxxxxxxxxxxxxxx general-purpose i/os (gpio) RM0033 152/1317 doc id 15403 rev 3 refer to table 1 on page 50 for the register boundary addresses. the following tables give the gpio register map and the reset values. 0x14 gpiox_odr (where x = a..i) reserved odr15 odr14 odr13 odr12 odr11 odr10 odr9 odr8 odr7 odr6 odr5 odr4 odr3 odr2 odr1 odr0 reset value 0000000000000000 0x18 gpiox_bsrr (where x = a..i) br15 br14 br13 br12 br11 br10 br9 br8 br7 br6 br5 br4 br3 br2 br1 br0 bs15 bs14 bs13 bs12 bs11 bs10 bs9 bs8 bs7 bs6 bs5 bs4 bs3 bs2 bs1 bs0 reset value 00000000000000000000000000000000 0x1c gpiox_lckr (where x = a..i) reserved lckk lck15 lck14 lck13 lck12 lck11 lck10 lck9 lck8 lck7 lck6 lck5 lck4 lck3 lck2 lck1 lck0 reset value 0 0000000000000000 0x20 gpiox_afrl (where x = a..i) afrl7[3:0] afrl6[3:0] afrl5[3:0] afrl4[3:0] afrl3[3:0] afrl2[3:0] afrl1[3:0] afrl0[3:0] reset value 00000000000000000000000000000000 0x24 gpiox_afrh (where x = a..i) afrh15[3:0] afrh14[3:0] afrh13[3:0] afrh12[3:0] a frh11[3:0] afrh10[3:0] afrh9[3:0] afrh8[3:0] reset value 00000000000000000000000000000000 table 18. gpio register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RM0033 system configurat ion controller (syscfg) doc id 15403 rev 3 153/1317 7 system configuration controller (syscfg) the system configuration contro ller is mainly used to remap the memory accessible in the code area, select the ethernet phy interface and manage the external interrupt line connection to the gpios. 7.1 i/o compensation cell by default the i/o compensation cell is not used. however when the i/o output buffer speed is configured in 50 mhz or 100 mhz mode, it is recommended to use the compensation cell for slew rate control on i/o t f(io)out )/t r(io)out commutation to reduce the i/o noise on power supply. when the compensation cell is enabled, a ready flag is set to indicate that the compensation cell is ready and can be used. the i/o compensation cell can be used only when the supply voltage ranges from 2.4 to 3.6 v. 7.2 syscfg registers 7.2.1 syscfg memory rem ap register (syscfg_memrmp) this register is used for specific configurations on memory remap: two bits are used to configure the type of memory accessible at address 0x0000 0000. these bits are used to select the physical remap by software and so, bypass the boot pins. after reset these bits take the value selected by the boot pins. when booting from main flash memory with boot pins set to 10 [(boot1,boot0) = (1,0)] this register takes the value 0x00. when the fsmc is remapped at address 0x0000 0000, only the first two regions of bank 1 memory controller (bank1 nor/psram 1 and nor/psram 2) can be remapped. in remap mode, the cpu can access the external memory via icode bus instead of system bus which boosts up the performance. however, in remap mode, the fsmc addressing is fixed to the remap address area only (bank1 nor/psram 1 and nor/psram 2) and fsmc control registers are not accessible. the fsmc remap function must be disabled to allows addressing other memory devices through the fsmc and/or to access fsmc control registers address offset: 0x00 reset value: 0x0000 000x (x is the memory mode selected by the boot pins ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 reserved mem_mode rw rw system configuration controller (syscfg) RM0033 154/1317 doc id 15403 rev 3 bits 31:2 reserved bits 1:0 mem_mode : memory mapping selection set and cleared by software. this bit controls the memory internal mapping at address 0x0000 0000. after reset these bits take on the memory mapping selected by the boot pins. 00: main flash memory mapped at 0x0000 0000 01: system flash memory mapped at 0x0000 0000 10: fsmc bank1 (nor/psram 1 and 2) mapped at 0x0000 0000 11: embedded sram (112kb) mapped at 0x0000 0000 RM0033 system configurat ion controller (syscfg) doc id 15403 rev 3 155/1317 7.2.2 syscfg peripheral mode configuration r egister (syscfg_pmc) address offset: 0x04 reset value: 0x0000 0000 7.2.3 syscfg external interr upt configuration register 1 (syscfg_exticr1) address offset: 0x08 reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved mii_rmii _sel reserved rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved bits 31:24 reserved bit 23 mii_rmii_sel : ethernet phy interface selection set and cleared by software.these bits contro l the phy interface for the ethernet mac. 0: mii interface is selected 1: rmii why interface is selected note: this configuration must be done while th e mac is under reset and before enabling the mac clocks. bits 22:0 reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 exti3[3:0] exti2[3:0] exti1[3:0] exti0[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:16 reserved bits 15:0 extix[3:0] : exti x configuration (x = 0 to 3) these bits are written by software to select t he source input for the extix external interrupt. 0000: pa[x] pin 0001: pb[x] pin 0010: pc[x] pin 0011: pd[x] pin 0100: pe[x] pin 0101: pf[c] pin 0110: pg[x] pin 0111: ph[x] pin 1000: pi[x] pin system configuration controller (syscfg) RM0033 156/1317 doc id 15403 rev 3 7.2.4 syscfg external interr upt configuration register 2 (syscfg_exticr2) address offset: 0x0c reset value: 0x0000 7.2.5 syscfg external interr upt configuration register 3 (syscfg_exticr3) address offset: 0x10 reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 exti7[3:0] exti6[3:0] exti5[3:0] exti4[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:16 reserved bits 15:0 extix[3:0] : exti x configuration (x = 4 to 7) these bits are written by software to select t he source input for the extix external interrupt. 0000: pa[x] pin 0001: pb[x] pin 0010: pc[x] pin 0011: pd[x] pin 0100: pe[x] pin 0101: pf[x] pin 0110: pg[x] pin 0111: ph[x] pin 1000: pi[x] pin 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 exti11[3:0] exti10[3:0] exti9[3:0] exti8[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:16 reserved bits 15:0 extix[3:0] : exti x configuration (x = 8 to 11) these bits are written by software to select th e source input for the extix external interrupt. 0000: pa[x] pin 0001: pb[x] pin 0010: pc[x] pin 0011: pd[x] pin 0100: pe[x] pin 0101: pf[x] pin 0110: pg[x] pin 0111: ph[x] pin 1000: pi[x] pin RM0033 system configurat ion controller (syscfg) doc id 15403 rev 3 157/1317 7.2.6 syscfg external interr upt configuration register 4 (syscfg_exticr4) address offset: 0x14 reset value: 0x0000 7.2.7 compensation cell control register (syscfg_cmpcr) address offset: 0x20 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 exti15[3:0] exti14[3:0] exti13[3:0] exti12[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:16 reserved bits 15:0 extix[3:0] : exti x configuration (x = 12 to 15) these bits are written by software to select th e source input for the extix external interrupt. 0000: pa[x] pin 0001: pb[x] pin 0010: pc[x] pin 0011: pd[x] pin 0100: pe[x] pin 0101: pf[x] pin 0110: pg[x] pin 0111: ph[x] pin note: pi[15:12] are not used. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ready reserved cmp_ pd r rw bits 31:9 reserved bit 8 ready : compensation cell ready flag 0: i/o compensati on cell not ready 1: o compensation cell ready bits 7:2 reserved bit 0 cmp_pd : compensation cell power-down 0: i/o compensation cell power-down mode 1: i/o compensation cell enabled system configuration controller (syscfg) RM0033 158/1317 doc id 15403 rev 3 7.2.8 syscfg register maps the following table gives the syscfg re gister map and th e reset values. refer to table 1 on page 50 for the register boundary addresses. table 19. syscfg register map and reset values offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 syscfg_memrm reserved mem_mode reset value xx 0x04 syscfg_pmc reserved mii_rmii_sel reserved reset value 0 0x08 syscfg_exticr1 reserved exti3[3:0] exti2[3:0] exti1[3:0] exti0[3:0] reset value 0000000000000000 0x0c syscfg_exticr2 reserved exti7[3:0] exti6[3:0] exti5[3:0] exti4[3:0] reset value 0000000000000000 0x10 syscfg_exticr3 reserved exti11[3:0] exti10[3:0] exti9[3:0] exti8[3:0] reset value 0000000000000000 0x14 syscfg_exticr4 reserved exti15[3:0] exti14[3:0] exti13[3:0] exti12[3:0] reset value 0000000000000000 0x20 syscfg_cmpcr reserved ready reserved cmp_pd reset value 00 RM0033 interrupts and events doc id 15403 rev 3 159/1317 8 interrupts and events this section applies to the whole stm32f20x and stm32f21x family, unless otherwise specified. 8.1 nested vectored interrupt controller (nvic) 8.1.1 nvic features the nested vector interrupt controller nvic includes the following features: 87 maskable interrupt channels (not including the 16 interrupt lines of cortex?-m3) 16 programmable priority levels (4 bits of interrupt priority are used) low-latency exception and interrupt handling power management control implementation of system control registers the nvic and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. all interrupts including the core exceptions are managed by the nvic. for more information on exceptions and nvic programming see chapter 5: exceptions & chapter 8: nested vectored interrupt controller in the arm cortex?-m3 technical reference manual . 8.1.2 systick calibra tion value register the systick calibration value is fixed to 15000, which gives a reference time base of 1 ms with the systick clock set to 15 mhz (max hclk/8). 8.1.3 interrupt and exception vectors ta bl e 2 0 is the vector table for the stm32f20x and stm32f21x devices. table 20. vector table position priority type of priority acronym description address - - - reserved 0x0000_0000 -3 fixed reset reset 0x0000_0004 -2 fixed nmi non maskable interrupt. the rcc clock security system (css) is linked to the nmi vector. 0x0000_0008 -1 fixed hardfault all class of fault 0x0000_000c 0 settable memmanage memory management 0x0000_0010 1 settable busfault pre-fetch fault, memory access fault 0x0000_0014 2 settable usagefault undefined instruction or illegal state 0x0000_0018 interrupts and events RM0033 160/1317 doc id 15403 rev 3 - - - reserved 0x0000_001c - 0x0000_002b 3 settable svcall system service call via swi instruction 0x0000_002c 4 settable debug monitor debug monitor 0x0000_0030 - - - reserved 0x0000_0034 5 settable pendsv pendable request for system service 0x0000_0038 6 settable systick system tick timer 0x0000_003c 0 7 settable wwdg window watchdog interrupt 0x0000_0040 1 8 settable pvd pvd through exti line detection interrupt 0x0000_0044 2 9 settable tamp_stamp tamper and timestamp interrupts through the exti line 0x0000_0048 310settablertc_wkup rtc wakeup interrupt through the exti line 0x0000_004c 4 11 settable flash flash global interrupt 0x0000_0050 5 12 settable rcc rcc global interrupt 0x0000_0054 6 13 settable exti0 exti line0 interrupt 0x0000_0058 7 14 settable exti1 exti line1 interrupt 0x0000_005c 8 15 settable exti2 exti line2 interrupt 0x0000_0060 9 16 settable exti3 exti line3 interrupt 0x0000_0064 10 17 settable exti4 exti line4 interrupt 0x0000_0068 11 18 settable dma1_stream0 dma1 stream0 global interrupt 0x0000_006c 12 19 settable dma1_stream1 dma1 stream1 global interrupt 0x0000_0070 13 20 settable dma1_stream2 dma1 stream2 global interrupt 0x0000_0074 14 21 settable dma1_stream3 dma1 stream3 global interrupt 0x0000_0078 15 22 settable dma1_stream4 dma1 st ream4 global interrupt 0x0000_007c 16 23 settable dma1_stream5 dma1 stream5 global interrupt 0x0000_0080 17 24 settable dma1_stream6 dma1 stream6 global interrupt 0x0000_0084 18 25 settable adc adc1, adc2 and adc3 global interrupts 0x0000_0088 19 26 settable can1_tx can1 tx interrupts 0x0000_008c 20 27 settable can1_rx0 can1 rx0 interrupts 0x0000_0090 21 28 settable can1_rx1 can1 rx1 interrupt 0x0000_0094 22 29 settable can1_sce can1 sce interrupt 0x0000_0098 23 30 settable exti9_5 exti line[9:5] interrupts 0x0000_009c table 20. vector table (continued) position priority type of priority acronym description address RM0033 interrupts and events doc id 15403 rev 3 161/1317 24 31 settable tim1_brk_tim9 tim1 break interrupt and tim9 global interrupt 0x0000_00a0 25 32 settable tim1_up_tim10 tim1 update interrupt and tim10 global interrupt 0x0000_00a4 26 33 settable tim1_trg_com_ tim11 tim1 trigger and commutation interrupts and tim11 global interrupt 0x0000_00a8 27 34 settable tim1_cc tim1 captur e compare interrupt 0x0000_00ac 28 35 settable tim2 tim2 global interrupt 0x0000_00b0 29 36 settable tim3 tim3 global interrupt 0x0000_00b4 30 37 settable tim4 tim4 global interrupt 0x0000_00b8 31 38 settable i2c1_ev i 2 c1 event interrupt 0x0000_00bc 32 39 settable i2c1_er i 2 c1 error interrupt 0x0000_00c0 33 40 settable i2c2_ev i 2 c2 event interrupt 0x0000_00c4 34 41 settable i2c2_er i 2 c2 error interrupt 0x0000_00c8 35 42 settable spi1 spi1 global interrupt 0x0000_00cc 36 43 settable spi2 spi2 global interrupt 0x0000_00d0 37 44 settable usart1 usart1 global interrupt 0x0000_00d4 38 45 settable usart2 usart2 global interrupt 0x0000_00d8 39 46 settable usart3 usart3 global interrupt 0x0000_00dc 40 47 settable exti15_10 exti line[ 15:10] interrupts 0x0000_00e0 41 48 settable rtc_alarm rtc alarms (a and b) through exti line interrupt 0x0000_00e4 42 49 settable otg_fs_wkup usb on-the-go fs wakeup through exti line interrupt 0x0000_00e8 43 50 settable tim8_brk_tim12 tim8 break interrupt and tim12 global interrupt 0x0000_00ec 44 51 settable tim8_up_tim13 tim8 update interrupt and tim13 global interrupt 0x0000_00f0 45 52 settable tim8_trg_com_ tim14 tim8 trigger and commutation interrupts and tim14 global interrupt 0x0000_00f4 46 53 settable tim8_cc tim8 captur e compare interrupt 0x0000_00f8 47 54 settable dma1_stream7 dma1 st ream7 global interrupt 0x0000_00fc 48 55 settable fsmc fsmc global interrupt 0x0000_0100 49 56 settable sdio sdio global interrupt 0x0000_0104 50 57 settable tim5 tim5 global interrupt 0x0000_0108 table 20. vector table (continued) position priority type of priority acronym description address interrupts and events RM0033 162/1317 doc id 15403 rev 3 51 58 settable spi3 spi3 global interrupt 0x0000_010c 52 59 settable uart4 uart4 global interrupt 0x0000_0110 53 60 settable uart5 uart5 global interrupt 0x0000_0114 54 61 settable tim6_dac tim6 global interrupt, dac1 and dac2 underrun error interrupts 0x0000_0118 55 62 settable tim7 tim7 global interrupt 0x0000_011c 56 63 settable dma2_stream0 dma2 st ream0 global interrupt 0x0000_0120 57 64 settable dma2_stream1 dma2 stream1 global interrupt 0x0000_0124 58 65 settable dma2_stream2 dma2 stream2 global interrupt 0x0000_0128 59 66 settable dma2_stream3 dma2 st ream3 global interrupt 0x0000_012c 60 67 settable dma2_stream4 dma2 stream4 global interrupt 0x0000_0130 61 68 settable eth ethernet global interrupt 0x0000_0134 62 69 settable eth_wkup ethernet wakeup through exti line interrupt 0x0000_0138 63 70 settable can2_tx can2 tx interrupts 0x0000_013c 64 71 settable can2_rx0 can2 rx0 interrupts 0x0000_0140 65 72 settable can2_rx1 can2 rx1 interrupt 0x0000_0144 66 73 settable can2_sce can2 sce interrupt 0x0000_0148 67 74 settable otg_fs usb on the go fs global interrupt 0x0000_014c 68 75 settable dma2_stream5 dma2 st ream5 global interrupt 0x0000_0150 69 76 settable dma2_stream6 dma2 st ream6 global interrupt 0x0000_0154 70 77 settable dma2_stream7 dma2 st ream7 global interrupt 0x0000_0158 71 78 settable usart6 usart6 global interrupt 0x0000_015c 72 79 settable i2c3_ev i 2 c3 event interrupt 0x0000_0160 73 80 settable i2c3_er i 2 c3 error interrupt 0x0000_0164 74 81 settable otg_hs_ep1_ou t usb on the go hs end point 1 out global interrupt 0x0000_0168 75 82 settable otg_hs_ep1_in usb on the go hs end point 1 in global interrupt 0x0000_016c 76 83 settable otg_hs_wkup usb on the go hs wakeup through exti interrupt 0x0000_0170 77 84 settable otg_hs usb on the go hs global interrupt 0x0000_0174 78 85 settable dcmi dcmi global interrupt 0x0000_0178 79 86 settable cryp cryp crypto global interrupt 0x0000_017c 80 87 settable hash_rng hash and rng global interrupt 0x0000_0180 table 20. vector table (continued) position priority type of priority acronym description address RM0033 interrupts and events doc id 15403 rev 3 163/1317 8.2 external interrupt/event controller (exti) the external interrupt/event controller consists of up to 23 edge detectors for generating event/interrupt requests. each input line can be independently configured to select the type (pulse or pending) and the corresponding trigger event (rising or falling or both). each line can also masked independently. a pending register maintains the status line of the interrupt requests 8.2.1 exti main features the main features of the exti controller are the following: independent trigger and mask on each interrupt/event line dedicated status bit for each interrupt line generation of up to 23 software event/interrupt requests detection of external signals with a pulse width lower than the apb2 clock period. refer to the electrical characteristics section of the stm32f20x and stm32f21x datasheets for details on this parameter. 8.2.2 exti block diagram figure 19 shows the block diagram. figure 19. external interrupt/event controller block diagram t r i g g e r s e l e c t i o n 0 e r i p h e r a l i n t e r f a c e m a s k r e g i s t e r % d g e d e t e c t ! - " ! ! 0 " b u s 0 # , + c i r c u i t 0 e n d i n g r e g i s t e r i n t e r r u p t r e q u e s t 4 o . 6 ) # ) n t e r r u p t 3 o f t w a r e # o n t r o l l e r t r i g g e r s e l e c t i o n 2 i s i n g & a l l i n g event mask 0 u l s e g e n e r a t o r ) n p u t l i n e ) n t e r r u p t r e g i s t e r r e g i s t e r register e v e n t r e g i s t e r a i interrupts and events RM0033 164/1317 doc id 15403 rev 3 8.2.3 wakeup event management the stm32f20x and stm32f21x are able to handle external or internal events in order to wake up the core (wfe). the wakeup event can be generated either by: enabling an interrupt in the peripheral control register but not in the nvic, and enabling the sevonpend bit in the cortex-m3 system control register. when the mcu resumes from wfe, the peripheral interrupt pending bit and the peripheral nvic irq channel pending bit (in the nvic interrupt clear pending register) have to be cleared. or configuring an external or internal exti line in event mode. when the cpu resumes from wfe, it is not necessary to clear the peripheral interrupt pending bit or the nvic irq channel pending bit as the pending bit corresponding to the event line is not set. to use an external line as a wakeup event, refer to section 8.2.4: functional description . 8.2.4 functional description to generate the interrupt, the interrupt line should be configured and enabled. this is done by programming the two trigger registers with the desired edge detection and by enabling the interrupt request by writing a ?1? to the corresponding bit in the interrupt mask register. when the selected edge occurs on the external interrupt line, an interrupt request is generated. the pending bit corresponding to the interrupt line is also set. this request is reset by writing a ?1? in the pending register. to generate the event, the event line should be configured and enabled. this is done by programming the two trigger registers with the desired edge detection and by enabling the event request by writing a ?1? to the corresponding bit in the event mask register. when the selected edge occurs on the event line, an event pulse is generated. the pending bit corresponding to the event line is not set. an interrupt/event request can also be generated by software by writing a ?1? in the software interrupt/event register. hardware interrupt selection to configure the 23 lines as interrupt sources, use the following procedure: configure the mask bits of the 23 interrupt lines (exti_imr) configure the trigger selection bits of the interrupt lines (exti_rtsr and exti_ftsr) configure the enable and mask bits that control the nvic irq channel mapped to the external interrupt controller (exti) so that an interrupt coming from one of the 23 lines can be correctly acknowledged. hardware event selection to configure the 23 lines as event sources, use the following procedure: configure the mask bits of the 23 event lines (exti_emr) configure the trigger selection bits of the event lines (exti_rtsr and exti_ftsr) software interrupt/event selection the 23 lines can be configured as software interrupt/event lines. the following is the procedure to generate a software interrupt. configure the mask bits of the 23 interrupt/event lines (exti_imr, exti_emr) set the required bit in the software interrupt register (exti_swier) RM0033 interrupts and events doc id 15403 rev 3 165/1317 8.2.5 external interr upt/event line mapping the 140 gpios are connected to the 16 external interrupt/event lines in the following manner: figure 20. external interrupt/event gpio mapping the seven other exti lines are connected as follows: exti line 16 is connected to the pvd output exti line 17 is connected to the rtc alarm event exti line 18 is connected to the usb otg fs wakeup event exti line 19 is connected to the ethernet wakeup event exti line 20 is connected to the usb otg hs (configured in fs) wakeup event exti line 21 is connected to the rtc tamper and timestamp events exti line 22 is connected to the rtc wakeup event 0 ! 0 " 0 # 0 $ 0 % 0 & 0 ' 0 ( 0 ) 0 ! 0 " 0 # 0 $ 0 % 0 & 0 ' 0 ( 0 ) 0 ! 0 " 0 # 0 $ 0 % 0 & 0 ' 0 ( % 8 4 ) % 8 4 ) % 8 4 ) % 8 4 ) ; = b i t s i n t h e 3 9 3 # & ' ? % 8 4 ) # 2 r e g i s t e r % 8 4 ) ; = b i t s i n t h e 3 9 3 # & ' ? % 8 4 ) # 2 r e g i s t e r % 8 4 ) ; = b i t s i n t h e 3 9 3 # & ' ? % 8 4 ) # 2 r e g i s t e r a i interrupts and events RM0033 166/1317 doc id 15403 rev 3 8.3 exti registers refer to section 1.1 on page 46 for a list of abbreviations used in register descriptions. 8.3.1 interrupt mask register (exti_imr) address offset: 0x00 reset value: 0x0000 0000 8.3.2 event mask r egister (exti_emr) address offset: 0x04 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved mr22 mr21 mr20 mr19 mr18 mr17 mr16 rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mr15 mr14 mr13 mr12 mr11 mr10 mr9 mr8 mr7 mr6 mr5 mr4 mr3 mr2 mr1 mr0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:23 reserved, must be kept at reset value (0). bits 22:0 mrx: interrupt mask on line x 0: interrupt request from line x is masked 1: interrupt request from line x is not masked 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved mr22 mr21 mr20 mr19 mr18 mr17 mr16 rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mr15 mr14 mr13 mr12 mr11 mr10 mr9 mr8 mr7 mr6 mr5 mr4 mr3 mr2 mr1 mr0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:23 reserved, must be kept at reset value (0). bits 22:0 mrx: event mask on line x 0: event request from line x is masked 1: event request from line x is not masked RM0033 interrupts and events doc id 15403 rev 3 167/1317 8.3.3 rising trigger select ion register (exti_rtsr) address offset: 0x08 reset value: 0x0000 0000 note: the external wakeup lines are edge triggered, no glitch must be generated on these lines. if a rising edge occurs on the external interrupt line while writing to the exti_rtsr register, the pending bit is be set. rising and falling edge triggers can be set for the same interrupt line. in this configuration, both generate a trigger condition. 8.3.4 falling trigger sel ection register (exti_ftsr) address offset: 0x0c reset value: 0x0000 0000 note: the external wakeup lines are edge triggered, no glitch must be generated on these lines. if a falling edge occurs on the external interrup t line while writing to the exti_ftsr register, the pending bit is not set. rising and falling edge triggers can be set for the same interrupt line. in this configuration, both generate a trigger condition. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved tr22 tr21 tr20 tr19 tr18 tr17 tr16 rw rw rw rw rw rw rw 1514131211109 8 765432 1 0 tr15 tr14 tr13 tr12 tr11 tr10 tr9 tr8 tr7 tr6 tr5 tr4 tr3 tr2 tr1 tr0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:23 reserved, must be kept at reset value (0). bits 22:0 trx: rising trigger event configuration bit of line x 0: rising trigger disabled (for event and interrupt) for input line 1: rising trigger enabled (for event and interrupt) for input line 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved tr22 tr21 tr20 tr19 tr18 tr17 tr16 rw rw rw rw rw rw rw 1514131211109 8 765432 1 0 tr15 tr14 tr13 tr12 tr11 tr10 tr9 tr8 tr7 tr6 tr5 tr4 tr3 tr2 tr1 tr0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:23 reserved, must be kept at reset value (0). bits 22:0 trx: falling trigger event configuration bit of line x 0: falling trigger disabled (for event and interrupt) for input line 1: falling trigger enabled (for event and interrupt) for input line. interrupts and events RM0033 168/1317 doc id 15403 rev 3 8.3.5 software interrupt e vent register (exti_swier) address offset: 0x10 reset value: 0x0000 0000 8.3.6 pending register (exti_pr) address offset: 0x14 reset value: undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved swier 22 swier 21 swier 20 swier 19 swier 18 swier 17 swier 16 rw rw rw rw rw rw rw 1514131211109 8 765432 1 0 swier 15 swier 14 swier 13 swier 12 swier 11 swier 10 swier 9 swier 8 swier 7 swier 6 swier 5 swier 4 swier 3 swier 2 swier 1 swier 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:23 reserved, must be kept at reset value (0). bits 22:0 swierx: software interrupt on line x writing a 1 to this bit when it is at 0 sets the corresponding pending bit in exti_pr. if the interrupt is enabled on this line on the exti_i mr and exti_emr, an interrupt request is generated. this bit is cleared by clearing the corresponding bit in exti_pr (by writing a 1 to the bit). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved pr22 pr21 pr20 pr19 pr18 pr17 pr16 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 1514131211109 8 765432 1 0 pr15 pr14 pr13 pr12 pr11 pr10 pr9 pr8 pr7 pr6 pr5 pr4 pr3 pr2 pr1 pr0 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 bits 31:23 reserved, must be kept at reset value (0). bits 22:0 prx: pending bit 0: no trigger request occurred 1: selected trigger request occurred this bit is set when the selected edge event arrives on the external interrupt line. this bit is cleared by writing a 1 to the bit or by ch anging the sensitivity of the edge detector. RM0033 interrupts and events doc id 15403 rev 3 169/1317 8.3.7 exti register map ta bl e 2 1 gives the exti register map and the reset values. refer to table 1 on page 50 for the register boundary addresses. table 21. external interrupt/event controller register map and reset values offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 exti_imr reserved mr[22:0] reset value 00000000000000000000000 0x04 exti_emr reserved mr[22:0] reset value 00000000000000000000000 0x08 exti_rtsr reserved tr[22:0] reset value 00000000000000000000000 0x0c exti_ftsr reserved tr[22:0] reset value 00000000000000000000000 0x10 exti_swier reserved swier[22:0] reset value 00000000000000000000000 0x14 exti_pr reserved pr[22:0] reset value 00000000000000000000000 dma controller (dma) RM0033 170/1317 doc id 15403 rev 3 9 dma controller (dma) 9.1 dma introduction direct memory access (dma) is used in order to provide high-speed data transfer between peripherals and memory and between memory and memory. data can be quickly moved by dma without any cpu action. this keeps cpu resources free for other operations. the dma controller combines a powerful dual ahb master bus architecture with independent fifo to optimize the bandwidth of the system, based on a complex bus matrix architecture. the two dma controllers have 16 streams in total (8 for each controller), each dedicated to managing memory access requests from one or more peripherals. each stream can have up to 8 channels (requests) in total. and each has an arbiter for handling the priority between dma requests. RM0033 dma controller (dma) doc id 15403 rev 3 171/1317 9.2 dma main features dual ahb master bus architecture, one dedicated to memory accesses and one dedicated to peripheral accesses ahb slave programming interface supporting only 32-bit accesses 8 streams for each dma controller, up to 8 channels (requests) per stream four separate 32 first-in, first-out memory buffers (fifos) per stream, that can be used in fifo mode or direct mode: ? fifo mode: with threshold level software selectable between 1/4, 1/2 or 3/4 of the fifo size ? direct mode: where each dma request immediately initiates a transfer from/to the memory each stream can be configured by hardware to be: ? a regular channel that supports peripheral-to-memory, memory-to-peripheral and memory-to-memory transfers ? a double buffer channel that also supports double buffering on the memory side each of the 8 streams are connected to dedicated hardware dma channels (requests) priorities between dma stream requests are software-programmable (4 levels consisting of very high, high, medium, low) or hardware in case of equality (request 0 has priority over request 1, etc.) each stream also supports software trigger for memory-to-memory transfers (only available for the dma2 controller) each stream request can be selected among up to 8 possible channel requests. this selection is software-configurable and allo ws several peripherals to initiate dma requests the number of data items to be transferred can be managed either by the dma controller or by the peripheral: ? dma flow controller: the number of data items to be transferred is software- programmable from 1 to 65535 ? peripheral flow controller: the number of data items to be transferred is unknown and controlled by the source or the destination peripheral that signals the end of the transfer by hardware independent source and destination transfer width (byte, half-word, word): when the data widths of the source and destination are not equal, the dma automatically packs/unpacks the necessary transfers to optimize the bandwidth. this feature is only available in fifo mode incrementing or nonincrementing addressing for source and destination supports incremental burst transfers of 4, 8 or 16 beats. the size of the burst is software-configurable, usually equal to half the fifo size of the peripheral each stream supports circular buffer management 5 event flags (dma half transfer, dma transfer complete, dma transfer error, dma fifo error, direct mode error) logically ored together in a single interrupt request for each stream dma controller (dma) RM0033 172/1317 doc id 15403 rev 3 9.3 dma functional description 9.3.1 general description figure 21 shows the block diagram of a dma. figure 21. dma block diagram the dma controller performs direct memory transfer: as an ahb master, it can take the control of the ahb bus matrix to initiate ahb transactions. it can carry out the following transactions: peripheral-to-memory memory-to-peripheral memory-to-memory the dma controller provides two ahb master ports: the ahb memory port , intended to be connected to memories and the ahb peripheral port , intended to be connected to peripherals. however, to allow memory-to-memory transfers, the ahb peripheral port must also have access to the memories. the ahb slave port is used to program the dma controller (it supports only 32-bit accesses). figure 22 illustrates the implement ation of the system of two dma controllers. ahb m as ter memory port fifo ahb m as ter peripher a l port s tream 0 fifo s tream 1 s tream 0 s tream 1 fifo s tream 2 s tream 2 fifo s tream 7 s tream 7 req_ s tream0 req_ s tr0_ch0 req_ s tr0_ch1 dma controller fifo s tream 3 s tream 3 fifo s tream 4 s tream 4 fifo s tream 5 s tream 5 fifo s tream 6 s tream 6 ar b iter req_ s tream1 req_ s tream2 req_ s tream 3 req_ s tream4 req_ s tream5 req_ s tream6 req_ s tream7 req_ s tr0_ch7 req_ s tr1_ch0 req_ s tr1_ch1 req_ s tr1_ch7 req_ s tr7_ch0 req_ s tr7_ch1 req_ s tr7_ch7 ahb s l a ve progr a mming interf a ce progr a mming port ch a nnel s election a i15945 RM0033 dma controller (dma) doc id 15403 rev 3 173/1317 figure 22. system implementation of two dma controllers 1. the dma1 controller ahb peripheral port is not connecte d to the bus matrix like in the case of the dma2 controller, thus only dma2 streams are abl e to perform memory-to-memory transfers. 9.3.2 dma transactions a dma transaction consists of a sequence of a given number of data transfers. the number of data items to be transferred and their width (8-bit, 16-bit or 32-bit) are software- programmable. each dma transfer consists of three operations: a loading from the peripheral data register or a location in memory, addressed through the dma_sxpar or dma_sxm0ar register a storage of the data loaded to the peripheral data register or a location in memory addressed through the dma_sxpar or dma_sxm0ar register a post-decrement of the dma_sxndtr re gister, which contains the number of transactions that still have to be performed after an event, the peripheral sends a request signal to the dma controller. the dma controller serves the request depending on the channel priorities. as soon as the dma controller accesses the peripheral, an acknowledge signal is sent to the peripheral by the dma controller 1 ahb periph ar b iter ahb memory fifo cortex-m 3 dma controller 2 icode ahb memory dcode s y s tem b us m a trix (ahb ar b iter ahb periph mapping fifo extern a l memory fl as h memory 112 kb s ram ahb2 peripher a l s m u ltil a yer) ahb-apb b ridge2 (d ua l ahb) apb2 apb2 ahb-apb b ridge1 (d ua l ahb) apb1 apb1 peripher a l s ahb s l a ve ahb s l a ve port port port port controller (f s mc) dma re qu e s t peripher a l s a i15946 16 kb s ram ahb1 peripher a l s u s b h s ethernet to ahb2 peripher a l s to ahb2 peripher a l s dma controller (dma) RM0033 174/1317 doc id 15403 rev 3 dma controller. the peripheral releases its request as soon as it gets the acknowledge signal from the dma controller. once the request has been deasserted by the peripheral, the dma controller releases the acknowledge signal. if there are more requests, the peripheral can initiate the next transaction. 9.3.3 channel selection each stream is associated with a dma request that can be selected out of 8 possible channel requests. the selectio n is controlled by the chsel[2:0] bits in the dma_sxcr register. figure 23. channel selection the 8 requests from the peripherals (tim, adc, spi, i2c, etc.) are independently connected to each channel and their connection depends on the product implementation. ta bl e 2 2 and ta bl e 2 3 give examples of dma request mappings. req_ s treamx req_ s trx_ch7 req_ s trx_ch6 req_ s trx_ch5 req_ s trx_ch4 req_ s trx_ch 3 req_ s trx_ch2 req_ s trx_ch1 req_ s trx_ch0 ch s el[2:0] 3 12927 0 dma_ s xcr a i15947 table 22. dma1 request mapping peripheral requests stream 0 stream 1 stream 2 stream 3 stream 4 stream 5 stream 6 stream 7 channel 0 spi3_rx spi3_rx spi2_rx spi2_tx spi3_tx spi3_tx channel 1 i2c1_rx tim7_up tim7_up i2c1_rx i2c1_tx i2c1_tx channel 2 tim4_ch1 tim4_ch2 tim4_up tim4_ch3 channel 3 tim2_up tim2_ch3 i2c3_rx i2c3_tx tim2_ch1 tim2_ch2 tim2_ch4 tim2_up tim2_ch4 channel 4 uart5_rx usart3_rx uart4_rx usart3_tx uart4_tx usart2_rx usart2_tx uart5_tx channel 5 tim3_ch4 tim3_up tim3_ch1 tim3_trig tim3_ch2 tim3_ch3 channel 6 tim5_ch3 tim5_up tim5_ch4 tim5_trig tim5_ch1 tim5_ch4 tim5_trig tim5_ch2 tim5_up channel 7 tim6_up i2c2_rx i2c2_rx usart3_tx dac1 dac2 i2c2_tx RM0033 dma controller (dma) doc id 15403 rev 3 175/1317 9.3.4 arbiter an arbiter manages the 8 dma stream requests based on their priority for each of the two ahb master ports (memory and peripheral ports) and launches the peripheral/memory access sequences. priorities are managed in two stages: software: each stream priority can be configured in the dma_sxcr register. there are four levels: ? very high priority ? high priority ? medium priority ?low priority hardware: if two requests have the same software priority level, the stream with the lower number takes priority over the stream with the higher number. for example, stream 2 takes priority over stream 4. 9.3.5 dma streams each of the 8 dma controller streams provides a unidirectional transfer link between a source and a destination. each stream can be configured to perform: regular type transactions: memory-to-peripherals, peripherals-to-memory or memory- to-memory transfers double-buffer type transactions: double buffer transfers using two memory pointers for the memory (while the dma is reading/writing from/to a buffer, the application can write/read to/from the other buffer). the amount of data to be transferred (up to 65535) is programmable and related to the source width of the peripheral that requests the dma transfer connected to the peripheral table 23. dma2 request mapping peripheral requests stream 0 stream 1 stream 2 stream 3 s tream 4 stream 5 stream 6 stream 7 channel 0 adc1 tim8_ch1 tim8_ch2 tim8_ch3 adc1 tim1_ch1 tim1_ch2 tim1_ch3 channel 1 dcmi adc2 adc2 dcmi channel 2 adc3 adc3 cryp_out cryp_in hash_in channel 3 spi1_rx spi1_rx spi1_tx spi1_tx channel 4 usart1_rx sdio usart1_rx sdio usart1_tx channel 5 usart6_rx usart6_rx usart6_tx usart6_tx channel 6 tim1_trig tim1_ch1 tim1_ch2 tim1_ch1 tim1_ch4 tim1_trig tim1_com tim1_up tim1_ch3 channel 7 tim8_up tim8_ch1 tim8_ch2 tim8_ch3 tim8_ch4 tim8_trig tim8_com dma controller (dma) RM0033 176/1317 doc id 15403 rev 3 ahb port. the register that contains the amount of data items to be transferred is decremented after each transaction. 9.3.6 source, destina tion and transfer modes both source and destination transfers can address peripherals and memories in the entire 4 gb area, at addresses comprised between 0x0000 0000 and 0xffff ffff. the direction is configured using the dir[1:0] bits in the dma_sxcr register and offers three possibilities: memory-to-peripheral, peripheral-to-memory or memory-to-memory transfers. ta bl e 2 4 describes the corresponding source and destination addresses. when the data width (programmed in the psize or msize bits in the dma_sxcr register) is a half-word or a word, respectively, the peripheral or memory address written into the dma_sxpar or dma_sxm0ar/m1ar registers has to be aligned on a word or half-word address boundary, respectively. peripheral-to-memory mode figure 24 describes this mode. when this mode is enabled (by setting the bi t en in the dma_sxcr register), each time a peripheral request occurs, the stream initiates a transfer from the source to fill the fifo. when the threshold level of the fifo is reached, the contents of the fifo are drained and stored into the destination. the transfer stops once the dma_sxndtr register reaches zero, when the peripheral requests the end of transfers (in case of a peripheral flow controller) or when the en bit in the dma_sxcr register is cleared by software. in direct mode (when the dmdis value in the dma_sxfcr register is ?0?), the threshold level of the fifo is not used: after each single data transfer from the peripheral to the fifo, the corresponding data are immediately drained and stored into the destination. the stream has access to the ahb source or destination port only if the arbitration of the corresponding stream is won. this arbitration is performed using the priority defined for each stream using the pl[1:0] bits in the dma_sxcr register. table 24. source and destination address bits dir[1:0] of the dma_sxcr register direction source address destination address 00 peripheral-to-memory dma_sxpar dma_sxm0ar 01 memory-to-peripheral dma_sxm0ar dma_sxpar 10 memory-to-memory dma_sxpar dma_sxm0ar 11 reserved - - RM0033 dma controller (dma) doc id 15403 rev 3 177/1317 figure 24. peripheral-to-memory mode 1. for double-buffer mode. memory-to-peripheral mode figure 25 describes this mode. when this mode is enabled (by setting the en bit in the dma_sxcr register), the stream immediately initiates transfers from th e source to entire ly fill the fifo. each time a peripheral request occurs, the contents of the fifo are drained and stored into the destination. when the level of the fifo is lower than or equal to the predefined threshold level, the fifo is fully reloaded with data from the memory. the transfer stops once the dma_sxndtr re gister reaches zero, when the peripheral requests the end of transfers (in case of a peripheral flow controller) or when the en bit in the dma_sxcr register is cleared by software. in direct mode (when the dmdis value in the dma_sxfcr register is ?0?), the threshold level of the fifo is not used: once the stream has been enabled, only a single data transfer is initiated from the memory to the fifo. when the corresponding peripheral transfer is complete, the fifo is empty and the stream initiates a new single transfer from the source to the fifo. the stream has access to the ahb source or destination port only if the arbitration of the corresponding stream is won. this arbitration is performed using the priority defined for each stream using the pl[1:0] bits in the dma_sxcr register. memory bus peripher a l bus req_ s treamx ar b iter dma_ s xm1ar (1) fifo ahb memory port ahb peripher a l port dma_ s xpar fifo level dma controller dma_ s xm0ar de s tin a tion s o u rce peripher a l memory peripher a l dma re qu e s t a i1594 8 dma controller (dma) RM0033 178/1317 doc id 15403 rev 3 figure 25. memory-to-peripheral mode 1. for double-buffer mode. memory-to-memory mode the dma channels can also work without being triggered by a request from a peripheral. this is the memory-to-me mory mode, described in figure 26 . when the stream is enabled by setting the en able bit (en) in the dma_sxcr register, the stream immediately starts to f ill the fifo up to the threshold le vel. when the threshold level is reached, the fifo contents are drained and stored into the destination. the transfer stops once the dma_sxndtr regist er reaches zero or when the en bit in the dma_sxcr register is cleared by software. the stream has access to the ahb source or destination port only if the arbitration of the corresponding stream is won. this arbitration is performed using the priority defined for each stream using the pl[1:0] bits in the dma_sxcr register. note: 1 when memory-to-memory mode is used, the circular and direct modes are not allowed. 2 only the dma2 controller is able to perform memory-to-memory transfers. peripher a l bus memory bus req_ s treamx ar b iter dma_ s xm1ar (1) fifo ahb memory port ahb peripher a l port dma_ s xpar fifo level dma controller dma_ s xm0ar s o u rce de s tin a tion peripher a l memory peripher a l dma re qu e s t a i15949 RM0033 dma controller (dma) doc id 15403 rev 3 179/1317 figure 26. memory-to-memory mode 1. for double-buffer mode. 9.3.7 pointer incrementation peripheral and memory pointers can optionally be automatically post-incremented or kept constant after each transfer depending on the pinc and minc bits in the dma_sxcr register. disabling the increment mode is useful when the peripheral source or destination data are accessed through a single register. if the increment mode is enabled, the address of the next transfer will be the address of the previous one incremented by 1 (for bytes), 2 (for half-words) or 4 (for words) depending on the data width programmed in the psize or msize bits in the dma_sxcr register. in order to optimize the packing operation, it is possible to fix the increment offset size for the peripheral address whatever the size of the data transferred on the ahb peripheral port. the pincos bit in the dma_sxcr register is us ed to align the increment offset size with the data size on the peripheral ahb port, or on a 32-bit address (the address is then incremented by 4). the pincos bit has an impact on the ahb peripheral port only. if pincos bit is set, the address of the next transfer is the address of the previous one incremented by 4 (automatically aligned on a 32-bit address) whatever the psize value. the ahb memory port, however, is not impacted by this operation. the pinc or the minc bit needs to be set if the burst transaction is requested on the ahb peripheral port or the ahb memory port, respectively, to satisfy the amba protocol (burst is not allowed in the fixed address mode). memory bus peripher a l bus s tre a m en ab le ar b iter dma_ s xm1ar (1) fifo ahb memory port ahb peripher a l port dma_ s xpar fifo level dma controller dma_ s xm0ar de s tin a tion s o u rce memory 1 memory 2 fifo a i15950 dma controller (dma) RM0033 180/1317 doc id 15403 rev 3 9.3.8 circular mode the circular mode is available to handle circular buffers and continuous data flows (e.g. adc scan mode). this feature can be enable d using the circ bit in the dma_sxcr register. when the circular mode is activated, the number of data items to be transferred is automatically reloaded with the initial value programmed during the stream configuration phase, and the dma requests continue to be served. note: in the circular mode, it is mandatory to respect the following rule in case of a burst mode configured for memory: dma_sxndtr = multiple of ((mburst beat) (msize)/(psize)), where: ? (mburst beat) = 4, 8 or 16 (depending on the mburst bits in the dma_sxcr register) ? ((msize)/(psize)) = 1, 2, 4, 1/2 or 1/4 (msize and psize represent the msize and psize bits in the dma_sxcr register. they are byte dependent) ? dma_sxndtr = number of data items to transfer on the ahb peripheral port for example: mburst beat = 8 (incr8), msize = ?00? (byte) and psize = ?01? (half-word), in this case: dma_sxndtr must be a multiple of (8 1/2 = 4). if this formula is not respected, the dma behavior and data integrity are not guaranteed. ndtr must also be a multiple of the peripheral burst size multiplied by the peripheral data size, otherwise this could result in a bad dma behavior. 9.3.9 double buffer mode this mode is available for a ll the dma1 and dma2 streams. the double buffer mode is enabled by setting the dbm bit in the dma_sxcr register. a double-buffer stream works as a regular (single buffer) stream with the difference that it has two memory pointers. when the double buffer mode is enabled, the circular mode is automatically enabled (circ bit in dma_sxcr is don?t care) and at each end of transaction, the memory pointers are swapped. in this mode, the dma controller swaps from one memory target to another at each end of transaction. this allows the software to process one memory area while the second memory area is being filled/used by the dma transfer. the double-buffer stream can work in both directions (the memory can be either the source or the destination) as described in table 25: source and destination address registers in double buffer mode (dbm=1) . note: in double buffer mode, it is possible to update the base address for the ahb memory port on-the-fly ( dma_sxm0ar or dma_sxm1ar ) when the stream is enabled, by respecting the following conditions: when the ct bit is ?0? in the dma_sxcr register, the dma_sxm1ar register can be written. attempting to write to this register while ct = '1' sets an error flag (teif) and the stream is automatically disabled. when the ct bit is ?1? in the dma_sxcr register, the dma_sxm0ar register can be written. attempting to write to this register while ct = '0', sets an error flag (teif) and the stream is automatically disabled. to avoid any error condition, it is advised to change the base address as soon as the tcif flag is asserted because, at this point, the targeted memory must have changed from RM0033 dma controller (dma) doc id 15403 rev 3 181/1317 memory 0 to 1 (or from 1 to 0) depending on the value of ct in the dma_sxcr register in accordance with one of the two above conditions. for all the other modes (except the double buffer mode), the memory address registers are write-protected as soon as the stream is enabled. 9.3.10 programmable data widt h, packing/unpacking, endianess the number of data items to be transferred has to be programmed into dma_sxndtr (number of data items to transfer bit, ndt) before enabling the stream (except when the flow controller is the peripheral, pfct rl bit in dma_sxcr is set). when using the internal fifo, the data widths of the source and destination data are programmable through the psize and msize bits in the dma_sxcr register (can be 8-, 16- or 32-bit). when psize and msize are not equal: the data width of the number of data items to transfer, configured in the dma_sxndtr register is equal to the width of the peripheral bus (configured by the psize bits in the dma_sxcr register). for instance, in case of peripheral-to-memory, memory-to- peripheral or memory-to-memory transfers and if the psize[1:0] bits are configured for half-word, the number of bytes to be transferred is equal to 2 ndt. the dma controller only copes with little-endian addressing for both source and destination. this is described in table 26: packing/unpacking & endian behavior (bit pinc = minc = 1) . this packing/unpacking procedure may present a risk of data corruption when the operation is interrupted before the data are completely packed/unpacked. so, to ensure data coherence, the stream may be configured to generate burst transfers: in this case, each group of transfers belonging to a burst are indivisible (refer to section 9.3.11: single and burst transfers ). in direct mode (dmdis = 0 in the dma_sxfcr register), the packing/unpacking of data is not possible. in this case, it is not allowed to have different source and destination transfer data widths: both are equal and defined by the psize bits in the dma_sxcr msize bits are don?t care). table 25. source and destination address registers in double buffer mode (dbm=1) bits dir[1:0] of the dma_sxcr register direction source address destination address 00 peripheral-to-memory dma_sxpar dma_sxm0ar / dma_sxm1ar 01 memory-to-peripheral dma_sxm0ar / dma_sxm1ar dma_sxpar 10 not allowed (1) 1. when the double buffer mode is enabled, the circular mode is automatically enabled. since the memory- to-memory mode is not compatible with the circular mode, when the double buffer mode is enabled, it is not allowed to configure the memory-to-memory mode. 11 reserved - - dma controller (dma) RM0033 182/1317 doc id 15403 rev 3 note: peripheral port may be the source or the destination (it could also be the memory source in the case of memory-to-memory transfer). psize, msize and ndt[15:0] have to be configured so as to ensure that the last transfer will not be incomplete. this can occur when t he data width of the peripheral port (psize bits) is lower than the data width of the me mory port (msize bits). this constraint is summarized in ta b l e 2 7 . table 26. packing/unpacking & endian behavior (bit pinc = minc = 1) ahb memor y port width ahb peripher al port width number of data items to transfer (ndt) memor y transfe r numbe r memory port address / byte lane peripher al transfer number peripheral port address / byte lane pincos = 1 pincos = 0 88 4 1 2 3 4 0x0 / b0[7:0] 0x1 / b1[7:0] 0x2 / b2[7:0] 0x3 / b3[7:0] 1 2 3 4 0x0 / b0[7:0] 0x4 / b1[7:0] 0x8 / b2[7:0] 0xc / b3[7:0] 0x0 / b0[7:0] 0x1 / b1[7:0] 0x2 / b2[7:0] 0x3 / b3[7:0] 816 2 1 2 3 4 0x0 / b0[7:0] 0x1 / b1[7:0] 0x2 / b2[7:0] 0x3 / b3[7:0] 1 2 0x0 / b1|b0[15:0] 0x4 / b3|b2[15:0] 0x0 / b1|b0[15:0] 0x2 / b3|b2[15:0] 832 1 1 2 3 4 0x0 / b0[7:0] 0x1 / b1[7:0] 0x2 / b2[7:0] 0x3 / b3[7:0] 1 0x0 / b3|b2|b1|b0[31:0] 0x0 / b3|b2|b1|b0[31:0] 16 8 4 1 2 0x0 / b1|b0[15:0] 0x2 / b3|b2[15:0] 1 2 3 4 0x0 / b0[7:0] 0x4 / b1[7:0] 0x8 / b2[7:0] 0xc / b3[7:0] 0x0 / b0[7:0] 0x1 / b1[7:0] 0x2 / b2[7:0] 0x3 / b3[7:0] 16 16 2 1 2 0x0 / b1|b0[15:0] 0x2 / b1|b0[15:0] 1 2 0x0 / b1|b0[15:0] 0x4 / b3|b2[15:0] 0x0 / b1|b0[15:0] 0x2 / b3|b2[15:0] 16 32 1 1 2 0x0 / b1|b0[15:0] 0x2 / b3|b2[15:0] 1 0x0 / b3|b2|b1|b0[31:0] 0x0 / b3|b2|b1|b0[31:0] 32 8 4 1 0x0 / b3|b2|b1|b0[31:0] 1 2 3 4 0x0 / b0[7:0] 0x4 / b1[7:0] 0x8 / b2[7:0] 0xc / b3[7:0] 0x0 / b0[7:0] 0x1 / b1[7:0] 0x2 / b2[7:0] 0x3 / b3[7:0] 32 16 2 1 0x0 /b3|b2|b1|b0[31:0] 1 2 0x0 / b1|b0[15:0] 0x4 / b3|b2[15:0] 0x0 / b1|b0[15:0] 0x2 / b3|b2[15:0] 32 32 1 1 0x0 /b3|b2|b1|b0 [31:0] 1 0x0 /b3|b2|b1|b0 [31:0] 0x0 / b3|b2|b1|b0[31:0] table 27. restriction on ndt versus psize and msize psize[1:0] of dma_sxcr msize[1:0] of dma_sxcr ndt[15:0] of dma_sxndtr 00 (8-bit) 01 (16-bit) must be a multiple of 2 00 (8-bit) 10 (32-bit) must be a multiple of 4 01 (16-bit) 10 (32-bit) must be a multiple of 2 RM0033 dma controller (dma) doc id 15403 rev 3 183/1317 9.3.11 single and burst transfers the dma controller can generate single transfers or incremental burst transfers of 4, 8 or 16 beats. the size of the burst is configured by software independently for the two ahb ports by using the mburst[1:0] and pburst[1:0] bits in the dma_sxcr register. the burst size indicates the number of beats in the burst, not the number of bytes transferred. to ensure data coherence, each group of transfers that form a burst are indivisible: ahb transfers are locked and the arbiter of the ahb bus matrix does not degrant the dma master during the sequence of the burst transfer. depending on the single or burst configuration, each dma request initiates a different number of transfers on the ahb peripheral port: when the ahb peripheral port is configured for single transfers, each dma request generates a data transfer of a byte, half-word or word depending on the psize[1:0] bits in the dma_sxcr register when the ahb peripheral port is configured for burst transfers, each dma request generates 4,8 or 16 beats of byte, half word or word transfers depending on the pburst[1:0] and psize[1:0] bits in the dma_sxcr register. the same as above has to be considered for the ahb memory port considering the mburst and msize bits. in direct mode, the stream can only generate single transfers and the mburst[1:0] and pburst[1:0] bits are forced by hardware. the address pointers (dma_sxpar or dma_sxm0 ar registers) must be chosen so as to ensure that all transfers within a burst block are aligned on the address boundary equal to the size of the transfer. the burst configuration has to be selected in order to respect the ahb protocol, where bursts must not cross the 1 kb address boundary because the minimum address space that can be allocated to a single slave is 1 kb. this means that the 1 kb address boundary should not be crossed by a burst block transfer, otherwise an ahb error would be generated, that is not reported by the dma registers. note: the burst mode is allowed only when incremetation is enabled: ? when the pinc bit is at ?0?, the pburst bits should also be cleared to ?00? ? when the minc bit is at ?0?, the mburst bits should also be cleared to ?00?. 9.3.12 fifo fifo structure the fifo is used to temporarily store data coming from the source before transmitting them to the destination. each stream has an independent 4-word fifo and the threshold level is software- configurable between 1/4, 1/2, 3/4 or full. to enable the use of the fifo threshold level, the direct mode must be disabled by setting the dmdis bit in the dma_sxfcr register. the structure of the fifo differs depending on the source and destination data widths, and is described in figure 27: fifo structure . dma controller (dma) RM0033 184/1317 doc id 15403 rev 3 figure 27. fifo structure fifo threshold and burst configuration caution is required when choosing the fifo threshold (bits fth[1: 0] of the dma_sxfcr register) and the size of the memory burst (mburst[1:0] of the dma_sxcr register): the content pointed by the fifo threshold must exactly match to an integer number of memory burst transfers. if this is not in the case, a fifo error (flag feifx of the dma_hisr or dma_lisr register) will be generated when th e stream is enabled, then the stream will be automatically disabled. the allowed and forbidden configurations are described in the table 28: fifo threshold configurations . table 28. fifo threshold configurations msize fifo level mburst = incr4 mburst = incr8 mburst = incr16 byte 1/4 1 burst of 4 beats forbidden forbidden 1/2 2 bursts of 4 beats 1 burst of 8 beats 3/4 3 bursts of 4 beats forbidden full 4 bursts of 4 beats 2 bursts of 8 beats 1 burst of 16 beats s o u rce: b yte 4 word s b yte l a ne 0 b yte l a ne 1 b yte l a ne 2 b yte l a ne 3 1/4 1/2 3 /4 f u ll empty b0 b1 b2 b 3 b4 b5 b6 b7 b 8 b9 b10 b 11 b12 b1 3 b14 b15 de s tin a tion: word s o u rce: b yte de s tin a tion: h a lf-word 4 word s b yte l a ne 0 b yte l a ne 1 b yte l a ne 2 b yte l a ne 3 1/4 1/2 3 /4 f u ll empty b0 b1 b2 b 3 b4 b5 b6 b7 b 8 b9 b10 b 11 b12 b1 3 b14 b15 w0 w1 w2 w 3 h0 h1 h2 h 3 h4 h5 h6 h7 s o u rce: h a lf-word de s tin a tion: word 4 word s b yte l a ne 0 b yte l a ne 1 b yte l a ne 2 b yte l a ne 3 1/4 1/2 3 /4 f u ll empty h0 w0 w1 w2 w 3 h1 h2 h 3 h4 h5 h6 h7 b15 b14 b1 3 b12 b11 b10 b9 b 8 b7 b6 b5 b4 b 3 b2 b1 b0 b15 b14 b1 3 b12 b11 b10 b9 b 8 b7 b6 b5 b4 b 3 b2 b1 b0 h7 h6 h5 h4 h 3 h2 h1 h0 h7, h6, h5, h4, h 3 , h2, h1, h0 w 3 , w2, w1, w0 w 3 , w2, w1, w0 s o u rce: h a lf-word 4-word s b yte l a ne 0 b yte l a ne 1 b yte l a ne 2 b yte l a ne 3 1/4 1/2 3 /4 f u ll empty de s tin a tion: b yte h7 h6 h5 h4 h 3 h2 h1 h0 b0 b1 b2 b 3 b4 b5 b6 b7 b 8 b9 b10 b 11 b12 b1 3 b14 b15 h0 h1 h2 h 3 h4 h5 h6 h7 b15 b14 b1 3 b12 b11 b10 b9 b 8 b7 b6 b5 b4 b 3 b2 b1 b0 a i15951 RM0033 dma controller (dma) doc id 15403 rev 3 185/1317 in all cases, the burst size multiplied by the data size must not exceed the fifo size (data size can be: 1 (byte), 2 (half-word) or 4 (word)). incomplete burst transfer at the end of a dma transfer may happen if one of the following conditions occurs: for the ahb peripheral port configuration: the total number of data items (set in the dma_sxndtr register) is not a multiple of the burst size multiplied by the data size for the ahb memory port configuration: the number of remaining data items in the fifo to be transferred to the memory is not a multiple of the burst size multiplied by the data size in such cases, the remaining da ta to be transferred will be ma naged in single mode by the dma, even if a burst transaction was requested during the dma stream configuration. note: when burst transfers are requested on the peripheral ahb port and the fifo is used (dmdis = 1 in the dma_sxcr register), it is ma ndatory to respect the following rule to avoid permanent underrun or overrun conditions, depending on the dma stream direction: if (pburst psize) = fifo_size (4 words), fifo_threshold = 3/4 is forbidden with psize = 1, 2 or 4 and pburst = 4, 8 or 16. this rule ensures that enough fifo space at a time will be free to serve the request from the peripheral. fifo flush the fifo can be flushed when the stream is disabled by resetting the en bit in the dma_sxcr register and when the stream is configured to manage peripheral-to-memory or memory-to-memory transfers: if some data are still present in the fifo when the stream is disabled, the dma controller continues transferring the remaining data to the destination (even though stream is effectively disabled). when this flush is completed, the transfer complete status bit (tcifx) in the dma_lisr or dma_hisr register is set. the remaining data counter dm a_sxndtr keeps the value in this case to indicate how many data items are currently ava ilable in the destination memory. note that during the fifo flush operation, if the number of remaining data items in the fifo to be transferred to memory (in bytes) is less than the memory data width (for example 2 bytes in fifo while msize is configured to wo rd), data will be sent with the data width set in the msize bit in the dma_sxcr register. this means that memory will be written with an half-word 1/4 forbidden forbidden forbidden 1/2 1 burst of 4 beats 3/4 forbidden full 2 bursts of 4 beats 1 burst of 8 beats word 1/4 forbidden forbidden 1/2 3/4 full 1 burst of 4 beats table 28. fifo threshold configurations (continued) msize fifo level mburst = incr4 mburst = incr8 mburst = incr16 dma controller (dma) RM0033 186/1317 doc id 15403 rev 3 undesired value. the software may read the dma_sxndtr register to determine the memory area that contains the good data (start address and last address). if the number of remaining data items in the fifo is lower than a burst size (if the mburst bits in dma_sxcr register are set to configure the stream to manage burst on the ahb memory port), single transactions will be generated to complete the fifo flush. direct mode by default, the fifo operates in direct mode (dmdis bit in the dma_sxfcr is reset) and the fifo threshold level is not used. this m ode is useful when the system requires an immediate and single transfer to or from the memory after each dma request. to avoid saturating the fifo, it is recommended to configure the corresponding stream with a high priority. this mode is restricted to transfers where: the source and destination transfer widths are equal and both defined by the psize[1:0] bits in dma_sxcr (msize[1:0] bits are don?t care) burst transfers are not possible (pburst[1:0] and mburst[1:0] bits in dma_sxcr are don?t care) direct mode must not be used when implementing memory-to-memory transfers. 9.3.13 dma transfer completion different events can generate an end of transfer by setting the tcifx bit in the dma_lisr or dma_hisr status register: in dma flow controller mode: ? the dma_sxndtr counter has reached zero in the memory-to-peripheral mode ? the stream is disabled before the end of transfer (by clearing the en bit in the dma_sxcr register) and (when transfers are peripheral-to-memory or memory- to-memory) all the remaining data have been flushed from the fifo into the memory in peripheral flow controller mode: ? the last external burst or single request has been generated from the peripheral and (when the dma is operating in peripheral-to-memory mode) the remaining data have been transferred from the fifo into the memory ? the stream is disabled by software, and (when the dma is operating in peripheral- to-memory mode) the remaining data have been transferred from the fifo into the memory note: the transfer completion is dependent on the remaining data in fifo to be transferred into memory only in the case of peripheral-to-memory mode. this condition is not applicable in memory-to-peripheral mode. if the stream is configured in noncircular mode, after the end of the transfer (that is when the number of data to be transferred reaches zero), the dma is stopped (en bit in dma_sxcr register is cleared by hardware) and no dma request is served unless the software reprograms the stream and re-enables it (by setting the en bit in the dma_sxcr register). RM0033 dma controller (dma) doc id 15403 rev 3 187/1317 9.3.14 dma transfer suspension at any time, a dma transfer can be suspended to be restarted later on or to be definitively disabled before the end of the dma transfer. there are two cases: the stream disables the transfer with no later-on restart from the point where it was stopped. there is no particular action to do, except to clear the en bit in the dma_sxcr register to disable the stream. the stream may take time to be disabled (ongoing transfer is completed first). the transfer complete interrupt flag (tcif in the dma_lisr or dma_hisr register) is set in order to indicate the end of transfer. the value of the en bit in dma_sxcr is now ?0? to confirm the stream interruption. the dma_sxndtr register contains the number of remaining data items at the moment when the stream was stopped so that the software can determine how many data items have been transferred before the stream was interrupted. the stream suspends the transfer before the number of remaining data items to be transferred in the dma_sxndtr register reaches 0. the aim is to restart the transfer later by re-enabling the stream. in order to restart from the point where the transfer was stopped, the software has to read the dma_sxndtr register after disabling the stream by writing the en bit in dma_sxcr register (and then checking that it is at ?0?) to know the number of data items already collected. then: ? the peripheral and/or memory addresses have to be updated in order to adjust the address pointers ? the sxndtr register has to be updated with the remaining number of data items to be transferred (the value read when the stream was disabled) ? the stream may then be re-enabled to restart the transfer from the point it was stopped note: note that a transfer complete interrupt flag (tcif in dma_lisr or dma_hisr) is set to indicate the end of transfer due to the stream interruption. 9.3.15 flow controller the entity that controls the number of data to be transferred is known as the flow controller. this flow controller is configured independently for each stream using the pfctrl bit in the dma_sxcr register. the flow controller can be: the dma controller: in this case, the number of data items to be transferred is programmed by software into the dma_sxndtr register before the dma stream is enabled. the peripheral source or destination: this is the case when the number of data items to be transferred is unknown. the peripheral indicates by hardware to the dma controller when the last data are being transferred. this feature is only supported for peripherals which are able to signal the end of the transfer, that is: ?sdio when the peripheral flow controller is used for a given stream, the value written into the dma_sxndtr has no effect on th e dma transfer. actually, whatever the value written, it will dma controller (dma) RM0033 188/1317 doc id 15403 rev 3 be forced by hardware to 0xffff as soon as the stream is enabled, to respect the following schemes: anticipated stream interruption: en bit in dma_sxcr register is reset to 0 by the software to stop the stream before the last data hardware signal (single or burst) is sent by the peripheral. in such a case, the stream is switched off and the fifo flush is triggered in the case of a peripheral-to-memory dma transfer. the tcifx flag of the corresponding stream is set in the status register to indicate the dma completion. to know the number of data items transferred during the dma transfer, read the dma_sxndtr register and apply the following formula: ? number_of_data_transferred = 0xffff ? dma_sxndtr normal stream interruption due to the reception of a last data hardware signal: the stream is automatically interrupted when the peripheral requests the last transfer (single or burst) and when this transfer is complete. the tcifx flag of the corresponding stream is set in the status register to indicate the dma transfer completion. to know the number of data items transferred, read the dma_sxndtr register and apply the same formula as above. the dma_sxndtr register reaches 0: the tcifx flag of the corresponding stream is set in the status register to indicate the forced dma transfer completion. the stream is automatically switched off even though the last data hardware signal (single or burst) has not been yet asserted. th e already transferred data w ill not be lost. this means that a maximum of 65535 data items can be managed by the dma in a single transaction, even in peripheral flow control mode. note: 1 when configured in memory-to-memory mode, the dma is always the flow controller and the pfctrl bit is forced to 0 by hardware. 2 the circular mode is forbidden in the peripheral flow controller mode. 9.3.16 summary of the poss ible dma configurations ta bl e 2 9 summarizes the different possible dma configurations. table 29. possible dma configurations dma transfer mode source destination flow controller circular mode transfer type direct mode double buffer mode peripheral-to- memory ahb peripheral port ahb memory port dma possible single possible possible burst forbidden peripheral forbidden single possible forbidden burst forbidden memory-to- peripheral ahb memory port ahb peripheral port dma possible single possible possible burst forbidden peripheral forbidden single possible forbidden burst forbidden memory-to- memory ahb peripheral port ahb memory port dma only forbidden single forbidden forbidden burst RM0033 dma controller (dma) doc id 15403 rev 3 189/1317 9.3.17 stream con figuration procedure the following sequence should be followed to configure a dma stream x (where x is the stream number): 1. if the stream is enabled, disable it by resetting the en bit in the dma_sxcr register, then read this bit in order to confirm that there is no ongoing stream operation. writing this bit to 0 is not immediately effective since it is actually written to 0 once all the current transfers have finished. when the en bit is read as 0, this means that the stream is ready to be configured. it is therefore necessary to wait for the en bit to be cleared before starting any stream configuration. all the stream dedicated bits set in the status register (dma_lisr and dma_hisr) from the previous data block dma transfer should be cleared before the stream can be re-enabled. 2. set the peripheral port re gister address in the dma_ sxpar register. the data will be moved from/ to this address to/ from the peripheral port after the peripheral event. 3. set the memory address in the dma_sxma0r register (and in the dma_sxma1r register in the case of a doub le buffer mode). the data will be written to or read from this memory after the peripheral event. 4. configure the total number of data items to be transferred in the dma_sxndtr register. after each peripheral event or each beat of the burst, this value is decremented. 5. select the dma channel (request) usin g chsel[2:0] in the dma_sxcr register. 6. if the peripheral is intended to be the flow controller and if it supports this feature, set the pfctrl bit in the dma_sxcr register. 7. configure the stream priority using the pl[1:0] bits in the dma_sxcr register. 8. configure the fifo usage (enable or disable, threshold in transmission and reception) 9. configure the data transfer direction, peripheral and memory incremented/fixed mode, single or burst transactions, peripheral and memory data widths, circular mode, double buffer mode and interrupts after half and/or full transfer, and/or errors in the dma_sxcr register. 10. activate the stream by setting the en bit in the dma_sxcr register. as soon as the stream is enabled, it can serve any dma request from the peripheral connected to the stream. once half the data have been transferred on the ahb destination port, the half-transfer flag (htif) is set and an interrupt is generated if the half-transfer interrupt enable bit (htie) is set. at the end of the transfer, the transfer complete flag (tcif) is set and an interrupt is generated if the transfer complete interrupt enable bit (tcie) is set. warning: to switch off a peripheral connected to a dma stream request, it is mandatory to, first, switch off the dma stream to which the peripheral is connected, then to wait for en bit = 0. only then can the peripheral be safely disabled. dma controller (dma) RM0033 190/1317 doc id 15403 rev 3 9.3.18 error management the dma controller can dete ct the following errors: transfer error : the transfer error interrupt flag (teifx) is set when: ? a bus error occurs during a dma read or a write access ? a write access is requested by software on a memory address register in double buffer mode whereas the stream is enabled and the current target memory is the one impacted by the write into the memory address register (refer to section 9.3.9: double buffer mode ) fifo error : the fifo error interrupt flag (feifx) is set if: ? a fifo underrun condition is detected ? a fifo overrun condition is detected (no detection in memory-to-memory mode because requests and transfers are internally managed by the dma) ? the stream is enabled while the fifo th reshold level is not compatible with the size of the memory burst (refer to table 28: fifo threshold configurations ) direct mode error : the direct mode error interrupt flag (dmeifx) can only be set in the peripheral-to-memory mode while operatin g in direct mode and when the minc bit in the dma_sxcr register is cleared. this fl ag is set when a dma request occurs while the previous data have not yet been fully transferred into the memory (because the memory bus was not granted). in this case, the flag indicates that 2 data items were be transferred successively to the same destination address, which could be an issue if the destination is not able to manage this situation in direct mode, the fifo error flag can also be set under the following conditions: in the peripheral-to-memory mode, the fifo can be saturated (overrun) if the memory bus is not granted for several peripheral requests in the memory-to-peripheral mode, an underrun condition may occur if the memory bus has not been granted before a peripheral request occurs if the teifx or the feifx flag is set due to incompatibility between burst size and fifo threshold level, the faulty stream is automatically disabled through a hardware clear of its en bit in the corresponding stream configuration register (dma_sxcr). if the dmeifx or the feifx flag is set due to an overrun or underrun condition, the faulty stream is not automatically disabled and it is up to the software to disable or not the stream by resetting the en bit in the dma_sxcr register. this is because there is no data loss when this kind of errors occur. when the stream's error interrupt flag (teif, feif, dmeif) in the dma_lisr or dma_hisr register is set, an interrupt is generated if the corresponding interrupt enable bit (teie, feie, dmie) in the dma_sxcr or dma_sxfcr register is set. note: when a fifo overrun or underrun condition occurs, the data are not lost because the peripheral request is not acknowledged by the stream until the overrun or underrun condition is cleared. if this acknowledge takes too much time, the peripheral itself may detect an overrun or underrun condition of its internal buffer and data might be lost. RM0033 dma controller (dma) doc id 15403 rev 3 191/1317 9.4 dma interrupts for each dma stream, an interrupt can be produced on the following events: half-transfer reached transfer complete transfer error fifo error (overrun, underrun or fifo level error) direct mode error separate interrupt enable control bits ar e available for flexibility as shown in ta b l e 3 0 . note: before setting an enable control bit to ?1?, the corresponding event flag should be cleared, otherwise an interrupt is immediately generated. 9.5 dma registers note: the dma registers should always be accessed in word format, otherwise a bus error is generated. 9.5.1 dma low interrupt st atus register (dma_lisr) address offset: base_address + 0d0 reset value: 0x0000 0000 table 30. dma interrupt requests interrupt event event flag enable control bit half-transfer htif htie transfer complete tcif tcie transfer error teif teie fifo overrun/underrun feif feie direct mode error dmeif dmeie 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved tcif3 htif3 teif3 dmeif3 reserv ed feif3 tcif2 htif2 teif2 dmeif2 reserv ed feif2 r rrrr r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved tcif1 htif1 teif1 dmeif1 reserv ed feif1 tcif0 htif0 teif0 dmeif0 reserv ed feif0 r rrrr r r r r r r r r r bits 31:28, 15:12 reserved, always read as 0. bits 27, 21, 11, 5 tcifx : stream x transfer complete interrupt flag (x = 3..0) this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the dma_lifcr register. 0: no transfer complete event on stream x 1: a transfer complete event occurred on stream x dma controller (dma) RM0033 192/1317 doc id 15403 rev 3 9.5.2 dma high interrupt st atus register (dma_hisr) address offset: base_address + 0d4 reset value: 0x0000 0000 bits 26, 20, 10, 4 htifx : stream x half transfer interrupt flag (x=3..0) this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the dma_lifcr register. 0: no half transfer event on stream x 1: a half transfer event occurred on stream x bits 25, 19, 9, 3 teifx : stream x transfer error interrupt flag (x=3..0) this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the dma_lifcr register. 0: no transfer error on stream x 1: a transfer error occurred on stream x bits 24, 18, 8, 2 dmeifx : stream x direct mode er ror interrupt flag (x=3..0) this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the dma_lifcr register. 0: no direct mode error on stream x 1: a direct mode erro r occurred on stream x bits 23, 17, 7, 1 reserved, always read as 0 bits 22, 16, 6, 0 feifx : stream x fifo error interrupt flag (x=3..0) this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the dma_lifcr register. 0: no fifo error event on stream x 1: a fifo error event occurred on stream x 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved tcif7 htif7 teif7 dmeif7 reserv ed feif7 tcif6 htif6 teif6 dmeif6 reserv ed feif6 rr r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved tcif5 htif5 teif5 dmeif5 reserv ed feif5 tcif4 htif4 teif4 dmeif4 reserv ed feif4 rr r r r r r r r r bits 31:28, 15:12 reserved, always read as 0. bits 27, 21, 11, 5 tcifx : stream x transfer comple te interrupt flag (x=7..4) this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the dma_hifcr register. 0: no transfer complete event on stream x 1: a transfer complete event occurred on stream x bits 26, 20, 10, 4 htifx : stream x half transfer interrupt flag (x=7..4) this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the dma_hifcr register. 0: no half transfer event on stream x 1: a half transfer event occurred on stream x RM0033 dma controller (dma) doc id 15403 rev 3 193/1317 9.5.3 dma low interrupt flag clear register (dma_lifcr) address offset: base_address + 0d8 reset value: 0x0000 0000 bits 25, 19, 9, 3 teifx : stream x transfer error interrupt flag (x=7..4) this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the dma_hifcr register. 0: no transfer error on stream x 1: a transfer error occurred on stream x bits 24, 18, 8, 2 dmeifx : stream x direct mode erro r interrupt flag (x=7..4) this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the dma_hifcr register. 0: no direct mode error on stream x 1: a direct mode error occurred on stream x bits 23, 17, 7, 1 reserved, always read as 0 bits 22, 16, 6, 0 feifx : stream x fifo error interrupt flag (x=7..4) this bit is set by hardware. it is cleared by software writing 1 to the corresponding bit in the dma_hifcr register. 0: no fifo error event on stream x 1: a fifo error event occurred on stream x 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved ctcif3 chtif3 cteif3 cdmeif3 reserved cfeif3 ctcif2 chtif2 cteif2 cdmeif2 reserved cfeif2 rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ctcif1 chtif1 cteif1 cdmeif1 reserved cfeif1 ctcif0 chtif0 cteif0 cdmeif0 reserved cfeif0 rw rw rw rw rw rw rw rw rw rw bits 31:28, 15:12 reserved, always read as 0. bits 27, 21, 11, 5 ctcifx : stream x clear transfer comple te interrupt flag (x = 3..0) this bit is set and cleared by software. 0: no effect 1: clears the corresponding tcifx flag in the dma_lisr register bits 26, 20, 10, 4 chtifx : stream x clear half transfer interrupt flag (x = 3..0) this bit is set and cleared by software. 0: no effect 1: clears the corresponding htifx flag in the dma_lisr register bits 25, 19, 9, 3 cteifx : stream x clear transfer error interrupt flag (x = 3..0) this bit is set and cleared by software. 0: no effect 1: clears the corresponding teif x flag in the dma_lisr register bits 24, 18, 8, 2 cdmeifx : stream x clear direct mode error interrupt flag (x = 3..0) this bit is set and cleared by software. 0: no effect 1: clears the corresponding dmeifx flag in the dma_lisr register bits 23, 17, 7, 1 reserved, always read as 0. dma controller (dma) RM0033 194/1317 doc id 15403 rev 3 9.5.4 dma high interrupt flag clear register (dma_hifcr) address offset: base_address + 0d12 reset value: 0x0000 0000 bits 22, 16, 6, 0 cfeifx : stream x clear fifo error interrupt flag (x = 3..0) this bit is set and cleared by software. 0: no effect 1: clears the corresponding cfeifx flag in the dma_lisr register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved ctcif7 chtif7 cteif7 cdmeif7 reserved cfeif7 ctcif6 chtif6 cteif6 cdmeif6 reserved cfeif6 rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ctcif5 chtif5 cteif5 cdmeif5 reserved cfeif5 ctcif4 chtif4 cteif4 cdmeif4 reserved cfeif4 rw rw rw rw rw rw rw rw rw rw bits 31:28, 15:12 reserved, always read as 0. bits 27, 21, 11, 5 ctcifx : stream x clear transfer complete interrupt flag (x = 7..4) this bit is set and cleared by software. 0: no effect 1: clears the corresponding tcifx flag in the dma_hisr register bits 26, 20, 10, 4 chtifx : stream x clear half transfer interrupt flag (x = 7..4) this bit is set and cleared by software. 0: no effect 1: clears the corresponding htifx flag in the dma_hisr register bits 25, 19, 9, 3 cteifx : stream x clear transfer error interrupt flag (x = 7..4) this bit is set and cleared by software. 0: no effect 1: clears the corresponding teifx flag in the dma_hisr register bits 24, 18, 8, 2 cdmeifx : stream x clear direct mode error interrupt flag (x = 7..4) this bit is set and cleared by software. 0: no effect 1: clears the corresponding dmeifx flag in the dma_hisr register bits 23, 17, 7, 1 reserved, always read as 0 bits 22, 16, 6, 0 cfeifx : stream x clear fifo error interrupt flag (x = 7..4) this bit is set and cleared by software. 0: no effect 1: clears the corresponding cfeifx flag in the dma_hisr register RM0033 dma controller (dma) doc id 15403 rev 3 195/1317 9.5.5 dma stream x conf iguration register (d ma_sxcr) (x = 0..7) this register is used to configure the concerned stream. address offset: base_address + 0d16 + 0d24 stream number reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved chsel[3:0] mburst [1:0] pburst[1:0] reserv ed ct dbm or reserved pl[1:0] rw rw rw rw rw rw rw rw rw or r rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pincos msize[1:0] psize[1:0] minc pinc circ dir[1:0] pfctrl tcie htie teie dmeie en rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:28 reserved, always read as 0. bits 27:25 chsel[2:0] : channel selection these bits are set and cleared by software. 000: channel 0 selected 001: channel 1 selected 010: channel 2 selected 011: channel 3 selected 100: channel 4 selected 101: channel 5 selected 110: channel 6 selected 111: channel 7 selected these bits are protected and can be written only if en is ?0? bits 24:23 mburst : memory burst transfer configuration these bits are set and cleared by software. 00: single transfer 01: incr4 (incremental burst of 4 beats) 10: incr8 (incremental burst of 8 beats) 11: incr16 (incremental burst of 16 beats) these bits are protected and can be written only if en is ?0? in direct mode, these bits are forced to 0x0 by hardware as soon as bit en= '1'. bits 22:21 pburst[1:0] : peripheral burst transfer configuration these bits are set and cleared by software. 00: single transfer 01: incr4 (incremental burst of 4 beats) 10: incr8 (incremental burst of 8 beats) 11: incr16 (incremental burst of 16 beats) these bits are protected and can be written only if en is ?0? in direct mode, these bits are forced to 0x0 by hardware. bits 20 reserved. dma controller (dma) RM0033 196/1317 doc id 15403 rev 3 bits 19 ct : current target (only in double buffer mode) this bits is set and cleared by hardwa re. it can also be written by software. 0: the current target memory is memory 0 (addressed by the dma_sxm0ar pointer) 1: the current target memory is memory 1 (addressed by the dma_sxm1ar pointer) this bit can be written only if en is ?0? to indicate the target memory area of the first transfer. once the stream is enabled, this bit operates as a status flag indicating which memory area is the current target. bits 18 dbm : double buffer mode this bits is set and cleared by software. 0: no buffer switching at the end of transfer 1: memory target switched at the end of the dma transfer this bit is protected and can be written only if en is ?0?. bits 17:16 pl[1:0] : priority level these bits are set and cleared by software. 00: low 01: medium 10: high 11: very high these bits are protected and can be written only if en is ?0?. bits 15 pincos : peripheral increment offset size this bit is set and cleared by software 0: the offset size for the peripheral add ress calculation is linked to the psize 1: the offset size for the peripheral address calculation is fixed to 4 (32-bit alignment). this bit has no meaning if bit pinc = '0'. this bit is protected and can be written only if en = '0'. this bit is forced low by hardware when the stream is enabled (bit en = '1 ') if the direct mode is selected or if pburst are different from ?00?. bits 14:13 msize[1:0] : memory data size these bits are set and cleared by software. 00: byte (8-bit) 01: half-word (16-bit) 10: word (32-bit) 11: reserved these bits are protected and can be written only if en is ?0?. in direct mode, msize is forced by hardware to the same value as psize as soon as bit en = '1'. bits 12:11 psize[1:0] : peripheral data size these bits are set and cleared by software. 00: byte (8-bit) 01: half-word (16-bit) 10: word (32-bit) 11: reserved these bits are protected and can be written only if en is ?0? bits 10 minc : memory increment mode this bit is set and cleared by software. 0: memory address pointer is fixed 1: memory address pointer is incremented af ter each data transfer (increment is done according to msize) this bit is protected and can be written only if en is ?0?. RM0033 dma controller (dma) doc id 15403 rev 3 197/1317 bits 9 pinc : peripheral increment mode this bit is set and cleared by software. 0: peripheral address pointer is fixed 1: peripheral address pointer is incremented a fter each data transfer (increment is done according to psize) this bit is protected and can be written only if en is ?0?. bits 8 circ : circular mode this bit is set and cleared by software and can be cleared by hardware. 0: circular mode disabled 1: circular mode enabled when the peripheral is the flow controller (b it pfctrl=1) and the st ream is enabled (bit en=1), then this bit is automatically forced by hardware to 0. it is automatically forced by ha rdware to 1 if the dbm bit is set, as soon as the stream is enabled (bit en ='1'). bits 7:6 dir[1:0] : data transfer direction these bits are set and cleared by software. 00: peripheral-to-memory 01: memory-to-peripheral 10: memory-to-memory 11: reserved these bits are protected and can be written only if en is ?0?. bits 5 pfctrl : peripheral flow controller this bit is set and cleared by software. 0: the dma is the flow controller 1: the peripheral is the flow controller this bit is protected and can be written only if en is ?0?. when the memory-to-memory mode is selected (bits dir[1:0]=10), then this bit is automatically forced to 0 by hardware. bits 4 tcie : transfer complete interrupt enable this bit is set and cleared by software. 0: tc interrupt disabled 1: tc interrupt enabled bits 3 htie : half transfer interrupt enable this bit is set and cleared by software. 0: ht interrupt disabled 1: ht interrupt enabled bits 2 teie : transfer error interrupt enable this bit is set and cleared by software. 0: te interrupt disabled 1: te interrupt enabled bits 1 dmeie : direct mode error interrupt enable this bit is set and cleared by software. 0: dme interrupt disabled 1: dme interrupt enabled dma controller (dma) RM0033 198/1317 doc id 15403 rev 3 9.5.6 dma stream x number of data register (dma_sx ndtr) (x = 0..7) address offset: base_address + 0d20 + 0d24 stream number reset value: 0x0000 0000 9.5.7 dma stream x peri pheral address register (d ma_sxpar) (x = 0..7) address offset: base_address + 0d24 + 0d24 stream number reset value: 0x0000 0000 bits 0 en : stream enable / flag stream ready when read low this bit is set and cleared by software. 0: stream disabled 1: stream enabled this bit may be cleared by hardware: ? on a dma end of transfer (stream ready to be configured) ? if a transfer error occurs on the ahb master buses ? when the fifo threshold on memory ahb port is not compatible with the size of the burst when this bit is read as 0, the software is a llowed to program the conf iguration and fifo bits registers. it is forbidden to write these registers when the en bit is read as 1. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ndt[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:16 reserved, always read as 0. bits 15:0 ndt[15:0] : number of data items to transfer number of data items to be transferred (0 up to 65535). this register can be written only when the stream is disabled. when the stream is enabl ed, this register is read-only, indicating the remaining data items to be transmitted. this register decrements after each dma transfer. once the transfer has completed, this register can either stay at zero or be reloaded automatically with the previous ly programmed value if the stream is configured in circular mode. if the value of this register is zero, no transact ion can be served even if the stream is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 pa r [ 3 1 : 1 6 ] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 par[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:0 par[31:0] : peripheral address base address of the peripheral data register from/to which the data will be read/written. these bits are write-protected and can be written only when bit en = '0' in the dma_sxcr register. RM0033 dma controller (dma) doc id 15403 rev 3 199/1317 9.5.8 dma stream x memory 0 address register (dma_sxm0ar) (x = 0..7) address offset: base_address + 0d28 + 0d24 stream number reset value: 0x0000 0000 9.5.9 dma stream x memory 1 address register (dma_sxm1ar) (x = 0..7) address offset: base_address + 0d32 + 0d24 stream number reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 m0a[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 m0a[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:0 m0a[31:0] : memory 0 address base address of memory area 0 from/to which the data will be read/written. these bits are write-protected. they can be written only if: ? the stream is disabled (bit en = '0' in the dma_sxcr register) or ? the stream is enabled (en=?1? in dma_sxcr register) and bit ct = '1' in the dma_sxcr register (in double buffer mode). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 m1a[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 m1a[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:0 m1a[31:0] : memory 1 address (used in case of double buffer mode) base address of memory area 1 from /to which the data will be read/written. this register is used only for the double buffer mode. these bits are write-protected. they can be written only if: ? the stream is disabled (bit en= '0' in the dma_sxcr register) or ? the stream is enabled (en=?1? in dma_sxcr register) and bit ct = '0' in the dma_sxcr register. dma controller (dma) RM0033 200/1317 doc id 15403 rev 3 9.5.10 dma stream x fi fo control register (d ma_sxfcr) (x = 0..7) address offset: base_address + 0d16 + 0d36 stream number reset value: 0x0000 0021 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved feie reser ved fs[2:0] dmdis fth[1:0] rw r r r rw rw rw bits 31:8 reserved, always read as 0. bits 7 feie : fifo error interrupt enable this bit is set and cleared by software. 0: fe interrupt disabled 1: fe interrupt enabled bits 6 reserved, always read as 0 bits 5:3 fs[2:0] : fifo status these bits are read-only. 000: 0 < fifo_level < 1/4 001: 1/4 fifo_level < 1/2 010: 1/2 fifo_level < 3/4 011: 3/4 fifo_level < full 100: fifo is empty 101: fifo is full others: no meaning these bits are not relevant in the direct mode (dmdis bit is zero). bits 2 dmdis : direct mode disable this bit is set and cleared by software. it can be set by hardware. 0: direct mode enabled 1: direct mode disabled this bit is protected and can be written only if en is ?0?. this bit is set by hardware if the memory-to- memory mode is selected (dir bit in dma_sxcr are ?10?) and the en bit in the dma_sxcr regi ster is ?1? because the direct mode is not allowed in the memory-to-memory configuration. bits 1:0 fth[1:0] : fifo thres hold selection these bits are set and cleared by software. 00: 1/4 full fifo 01: 1/2 full fifo 10: 3/4 full fifo 11: full fifo these bits are not used in the direct mode when the dmis value is zero. these bits are protected and ca n be written only if en is ?1?. RM0033 dma controller (dma) doc id 15403 rev 3 201/1317 9.5.11 dma register map ta bl e 3 1 summarizes the dma registers. table 31. dma register map and reset values offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x0000 dma_lisr reserved tcif3 htif3 teif3 dmeif3 reserved feif3 tcif2 htif2 teif2 dmeif2 reserved feif2 reserved tcif1 htif1 teif1 dmeif1 reserved feif1 tcif0 htif0 teif0 dmeif0 reserved feif0 reset value 0000 00000 0 0000 00000 0 0x0004 dma_hisr reserved tcif7 htif7 teif7 dmeif7 reserved feif7 tcif6 htif6 teif6 dmeif6 reserved feif6 reserved tcif5 htif5 teif5 dmeif5 reserved feif5 tcif4 htif4 teif4 dmeif4 reserved feif4 reset value 0000 00000 0 0000 00000 0 0x0008 dma_lifcr reserved ctcif3 chtif3 teif3 cdmeif3 reserved cfeif3 ctcif2 chtif2 cteif2 cdmeif2 reserved cfeif2 reserved ctcif1 chtif1 cteif1 cdmeif1 reserved cfeif1 ctcif0 chtif0 cteif0 cdmeif0 reserved cfeif0 reset value 0000 00000 0 0000 00000 0 0x000c dma_hifcr reserved ctcif7 chtif7 cteif7 cdmeif7 reserved cfeif7 ctcif6 chtif6 cteif6 cdmeif6 reserved cfeif6 reserved ctcif5 chtif5 cteif5 cdmeif5 reserved cfeif5 ctcif4 chtif4 cteif4 cdmeif4 reserved cfeif4 reset value 0000 00000 0 0000 00000 0 0x0010 dma_s0cr reserved chsel[2:0] mburst[1:0] pburst[1:0] reserved ct dbm pl[1:0] pincos msize[1:0] psize[1:0] minc pinc circ dir[1:0] pfctrl tcie htie teie dmeie en reset value 0000000 00000000000000000000 0x0014 dma_s0ndtr reserved ndt[15:.] reset value 0000000000000000 0x0018 dma_s0par pa[31:0] reset value 00000000000000000000000000000000 0x001c dma_s0m0ar m0a[31:0] reset value 00000000000000000000000000000000 0x0020 dma_s0m1ar m1a[31:0] reset value 00000000000000000000000000000000 0x0024 dma_s0fcr reserved feie reserved fs[2:0] dmdis fth [1:0] reset value 0 100001 0x0028 dma_s1cr reserved chsel [2:0] mburst[1:] pburst[1:0] ack ct dbm pl[1:0] pincos msize[1:0] psize[1:0] minc pinc circ dir[1:0] pfctrl tcie htie teie dmeie en reset value 0000000000000000000000000000 0x002c dma_s1ndtr reserved ndt[15:.] reset value 0000000000000000 0x0030 dma_s1par pa[31:0] reset value 00000000000000000000000000000000 dma controller (dma) RM0033 202/1317 doc id 15403 rev 3 0x0034 dma_s1m0ar m0a[31:0] reset value 00000000000000000000000000000000 0x0038 dma_s1m1ar m1a[31:0] reset value 00000000000000000000000000000000 0x003c dma_s1fcr reserved feie reserved fs[2:0] dmdis fth [1:0] reset value 0 100001 0x0040 dma_s2cr reserved chsel [2:0] mburst[1:0] pburst[1:0] ack ct dbm pl[1:0] pincos msize[1:0] psize[1:0] minc pinc circ dir [1:0] pfctrl tcie htie teie dmeie en reset value 0000000000000000000000000000 0x0044 dma_s2ndtr reserved ndt[15:.] reset value 0000000000000000 0x0048 dma_s2par pa[31:0] reset value 00000000000000000000000000000000 0x004c dma_s2m0ar m0a[31:0] reset value 00000000000000000000000000000000 0x0050 dma_s2m1ar m1a[31:0] reset value 00000000000000000000000000000000 0x0054 dma_s2fcr reserved feie reserved fs[2:0] dmdis fth [1:0] reset value 0 100001 0x0058 dma_s3cr reserved chsel[2:0] mburst[1:0] pburst[1:0] ack ct dbm pl[1:0] pincos msize[1:0] psize[1:0] minc pinc circ dir[1:0] pfctrl tcie htie teie dmeie en reset value 0000000000000000000000000000 0x005c dma_s3ndtr reserved ndt[15:.] reset value 0000000000000000 0x0060 dma_s3par pa[31:0] reset value 00000000000000000000000000000000 0x0064 dma_s3m0ar m0a[31:0] reset value 00000000000000000000000000000000 0x0068 dma_s3m1ar m1a[31:0] reset value 00000000000000000000000000000000 0x006c dma_s3fcr reserved feie reserved fs[2:0] dmdis fth [1:0] reset value 0 100001 table 31. dma register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RM0033 dma controller (dma) doc id 15403 rev 3 203/1317 0x0070 dma_s4cr reserved chsel[2:0] mburst[1:0] pburst[1:0] ack ct dbm pl[1:0] pincos msize[1:0] psize[1:0] minc pinc circ dir [1:0] pfctrl tcie htie teie dmeie en reset value 0000000000000000000000000000 0x0074 dma_s4ndtr reserved ndt[15:.] reset value 0000000000000000 0x0078 dma_s4par pa[31:0] reset value 00000000000000000000000000000000 0x007c dma_s4m0ar m0a[31:0] reset value 00000000000000000000000000000000 0x0080 dma_s4m1ar m1a[31:0] reset value 00000000000000000000000000000000 0x0084 dma_s4fcr reserved feie reserved fs[2:0] dmdis fth [1:0] reset value 0 100001 0x0088 dma_s5cr reserved chsel[2:0] mburst[1:0] pburst[1:0] ack ct dbm pl[1:0] pincos msize[1:0] psize[1:0] minc pinc circ dir[1:0] pfctrl tcie htie teie dmeie en reset value 0000000000000000000000000000 0x008c dma_s5ndtr reserved ndt[15:.] reset value 0000000000000000 0x0090 dma_s5par pa[31:0] reset value 00000000000000000000000000000000 0x0094 dma_s5m0ar m0a[31:0] reset value 00000000000000000000000000000000 0x0098 dma_s5m1ar m1a[31:0] reset value 00000000000000000000000000000000 0x009c dma_s5fcr reserved feie reserved fs[2:0] dmdis fth [1:0] reset value 0 100001 0x00a0 dma_s6cr reserved chsel[2:0] mburst[1:0] pburst[1:0] ack ct dbm pl[1:0] pincos msize[1:0] psize[1:0] minc pinc circ dir[1:0] pfctrl tcie htie teie dmeie en reset value 0000000000000000000000000000 0x00a4 dma_s6ndtr reserved ndt[15:.] reset value 0000000000000000 0x00a8 dma_s6par pa[31:0] reset value 00000000000000000000000000000000 0x00ac dma_s6m0ar m0a[31:0] reset value 00000000000000000000000000000000 0x00b0 dma_s6m1ar m1a[31:0] reset value 00000000000000000000000000000000 0x00b4 dma_s6fcr reserved feie reserved fs[2:0] dmdis fth [1:0] reset value 0 100001 table 31. dma register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dma controller (dma) RM0033 204/1317 doc id 15403 rev 3 refer to table 1 on page 50 for the register boundary addresses. 0x00b8 dma_s7cr reserved chsel[2:0] mburst[1:0] pburst[1:0] ack ct dbm pl[1:0] pincos msize[1:0] psize[1:0] minc pinc circ dir[1:0] pfctrl tcie htie teie dmeie en reset value 000000000000 000000000000000 0x00bc dma_s7ndtr reserved ndt[15:.] reset value 0000000000000000 0x00c0 dma_s7par pa[31:0] reset value 00000000000000000000000000000000 0x00c4 dma_s7m0ar m0a[31:0] reset value 00000000000000000000000000000000 0x00c8 dma_s7m1ar m1a[31:0] reset value 00000000000000000000000000000000 0x00cc dma_s7fcr reserved feie reserved fs[2:0] dmdis fth [1:0] reset value 0 100001 table 31. dma register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RM0033 analog-to-digital converter (adc) doc id 15403 rev 3 205/1317 10 analog-to-digital converter (adc) this section applies to the whole stm32f20x and stm32f21x family, unless otherwise specified. 10.1 adc introduction the 12-bit adc is a successive approximation analog-to-digital converter. it has up to 19 multiplexed channels allowing it to measure signals from 16 external sources, two internal sources, and the v bat channel. the a/d conversion of the channels can be performed in single, continuous, scan or discontinuous mode. the result of the adc is stored into a left- or right-aligned 16-bit data register. the analog watchdog feature allows the application to detect if the input voltage goes beyond the user-defined, higher or lower thresholds. 10.2 adc main features 12-bit, 10-bit, 8-bit or 6-bit configurable resolution interrupt generation at the end of conversion, end of injected conversion, and in case of analog watchdog or overrun events single and continuous conversion modes scan mode for automatic conversion of channel 0 to channel ?n? data alignment with in-b uilt data coherency channel-wise programmable sampling time external trigger option with configurable polarity for both regular and injected conversions discontinuous mode dual/triple mode (on devices with 2 adcs or more) configurable dma data storage in dual/triple adc mode configurable delay between conversions in dual/triple interleaved mode adc conversion time: 0.5 s with apb2 at 60 mhz adc supply requirements: 2.4 v to 3.6 v at full speed and down to 1.8 v at slower speed adc input range: v ref ? v in v ref+ dma request generation during regular channel conversion figure 28 shows the block diagram of the adc. note: v ref? , if available (depending on package), must be tied to v ssa . 10.3 adc functional description figure 28 shows a single adc block diagram and ta bl e 3 2 gives the adc pin description. analog-to-digital converter (adc) RM0033 206/1317 doc id 15403 rev 3 figure 28. single adc block diagram ! $ # x ? ) . ! $ # x ? ) . ! n a l o g t o d i g i t a l c o n v e r t e r ! $ # x ? ) . ! n a l o g m u x ! $ # # , + ! $ # ) n t e r r u p t t o . 6 ) # ' 0 ) / p o r t s ! n a l o g w a t c h d o g ! d d r e s s d a t a b u s , o w e r t h r e s h o l d b i t s # o m p a r e r e s u l t ( i g h e r t h r e s h o l d b i t s & l a g s e n a b l e b i t s % / # ! 7 $ ! n a l o g w a t c h d o g e v e n t 6 $ $ ! 6 3 3 ! 6 2 % & 6 2 % & ) n t e r r u p t % 8 4 ) ? 4 ) - ? # ( & r o m ! $ # p r e s c a l e r b i t s % n d o f c o n v e r s i o n c h a n n e l s ) n j e c t e d c h a n n e l s % n d o f i n j e c t e d c o n v e r s i o n * % / # % / # ) % ! 7 $ ) % * % / # ) % u p t o u p t o 2 e g u l a r d a t a r e g i s t e r x b i t s ) n j e c t e d d a t a r e g i s t e r s 2 e g u l a r 3 t a r t t r i g g e r r e g u l a r g r o u p % 8 4 3 % , ; = b i t s % 8 4 % . 4 ) - ? # ( % 8 4 ) ? 4 ) - ? 4 2 ' / 4 ) - ? # ( 4 ) - ? 4 2 ' / 3 t a r t t r i g g e r i n j e c t e d g r o u p * % 8 4 3 % , ; = b i t s 4 ) - ? # ( * % 8 4 % . ; = b i t s ; = b i t s $ - ! r e q u e s t 4 e m p s e n s o r 6 2 % & ) . 4 / 6 2 / 6 2 ) % $ - ! o v e r r u n 6 " ! 4 4 ) - ? # ( 4 ) - ? 4 2 ' / 4 ) - ? # ( 4 ) - ? # ( 4 ) - ? 4 2 ' / 4 ) - ? # ( 4 ) - ? # ( 4 ) - ? # ( 4 ) - ? # ( 4 ) - ? # ( 4 ) - ? # ( 4 ) - ? # ( 4 ) - ? # ( 4 ) - ? # ( 4 ) - ? # ( 4 ) - ? # ( 4 ) - ? # ( 4 ) - ? # ( 4 ) - ? 4 2 ' / 4 ) - ? # ( 4 ) - ? 4 2 ' / 4 ) - ? # ( 4 ) - ? 4 2 ' / 4 ) - ? # ( a i RM0033 analog-to-digital converter (adc) doc id 15403 rev 3 207/1317 10.3.1 adc on-off control the adc is powered on by setting the adon bit in the adc_cr2 register. when the adon bit is set for the first time, it wakes up the adc from the power-down mode. conversion starts when either the swstart or the jswstart bit is set. you can stop conversion and put the adc in power down mode by clearing the adon bit. in this mode the adc consumes al most no power (only a few a). 10.3.2 adc clock the adc features two clock schemes: clock for the analog circuitry: adcclk, common to all adcs this clock is generated from the apb2 clock divided by a programmable prescaler that allows the adc to work at f pclk2 /2, /4, /6 or /8. adcclk maximum value is 30 mhz when the apb2 clock is at 60 mhz. clock for the digital interface (used for registers read/write access) this clock is equal to the apb2 clock. the digital interf ace clock can be enabled/disabled individually for each adc through the rcc apb2 peripheral clock enable register (rcc_apb2enr). 10.3.3 channel selection there are 16 multiplexed channels. it is possible to organize the conversions in two groups: regular and injected. a group consists of a sequence of conversions that can be done on any channel and in any order. for instance, it is possible to implement the conversion sequence in the following order: adc_in3, adc_in8, adc_in2, adc_in2, adc_in0, adc_in2, adc_in2, adc_in15. a regular group is composed of up to 16 conversions. the regular channels and their order in the conversion sequence must be selected in the adc_sqrx registers. the total number of conversions in the regular group must be written in the l[3:0] bits in the adc_sqr1 register. an injected group is composed of up to 4 conversions. the injected channels and their order in the conversion sequence must be selected in the adc_jsqr register. table 32. adc pins name signal type remarks v ref+ input, analog reference positive the higher/positive reference voltage for the adc, 1.8 v v ref+ v dda v dda input, analog supply analog power supply equal to v dd and 2.4 v v dda v dd (3.6 v) for full speed 1.8 v v dda v dd (3.6 v) for reduced speed v ref? input, analog reference negative the lower/negative reference voltage for the adc, v ref? = v ssa v ssa input, analog supply ground ground for analog power supply equal to v ss adcx_in[15:0] analog input signals 16 analog input channels analog-to-digital converter (adc) RM0033 208/1317 doc id 15403 rev 3 the total number of conversions in the injected group must be written in the l[1:0] bits in the adc_jsqr register. if the adc_sqrx or adc_jsqr registers are modified during a conversion, the current conversion is reset and a new start pulse is sent to the adc to convert the newly chosen group. temperature sensor, v refint and v bat internal channels the temperature sensor is connected to channel adc1_in16 and the internal reference voltage v refint is connected to adc1_in17. these two internal channels can be selected and converted as injected or regular channels. the v bat channel is connected to channel adc1_in18. it can also be converted as an injected or regular channel. note: the temperature sensor, v refint and the v bat channel are available only on the master adc1 peripheral. 10.3.4 single conversion mode in single conversion mode the adc does one conversion. this mode is started with the cont bit at 0 by either: setting the swstart bit in the adc_cr2 register (for a regular channel only) setting the jswstart bit (for an injected channel) external trigger (for a regular or injected channel) once the conversion of the selected channel is complete: if a regular channel was converted: ? the converted data are stored into the 16-bit adc_dr register ? the eoc (end of conversion) flag is set ? an interrupt is generated if the eocie bit is set if an injected channel was converted: ? the converted data are stored into the 16-bit adc_jdr1 register ? the jeoc (end of conversion injected) flag is set ? an interrupt is generated if the jeocie bit is set then the adc stops. 10.3.5 continuous conversion mode in continuous conversion mode, the adc starts a new conversion as soon as it finishes one. this mode is started with the cont bit at 1 either by external trigger or by setting the swstrt bit in the adc_cr2 regist er (for regular channels only). after each conversion: if a regular group of channels was converted: ? the last converted data are stored into the 16-bit adc_dr register ? the eoc (end of conversion) flag is set ? an interrupt is generated if the eocie bit is set RM0033 analog-to-digital converter (adc) doc id 15403 rev 3 209/1317 note: injected channels cannot be converted continuously. the only exception is when an injected channel is configured to be converted automatically after regular channels in continuous mode (using jauto bit), refer to auto-injection section) . 10.3.6 timing diagram as shown in figure 29 , the adc needs a stabilization time of t stab before it starts converting accurately. after the start of the adc conversion and after 15 clock cycles, the eoc flag is set and the 16-bit adc data register contains the result of the conversion. figure 29. timing diagram 10.3.7 analog watchdog the awd analog watchdog status bit is set if the analog voltage converted by the adc is below a lower threshold or above a higher threshold. these thresholds are programmed in the 12 least significant bits of the adc_htr and adc_ltr 16-bit registers. an interrupt can be enabled by using the awdie bit in the adc_cr1 register. the threshold value is independent of the alignment selected by the align bit in the adc_cr2 register. the analog voltage is compared to the lower and higher thresholds before alignment. ta bl e 3 3 shows how the adc_cr1 register should be configured to enable the analog watchdog on one or more channels. figure 30. analog watchdog?s guarded area ! $ # ? # , + % / # . e x t ! $ # c o n v e r s i o n ! $ # c o n v e r s i o n # o n v e r s i o n t i m e t 3 4 ! " ! $ # 3 o f t w a r e c l e a r s t h e % / # b i t 3 % 4 ! $ / . ! $ # p o w e r o n t o t a l c o n v t i m e 3 t a r t s t c o n v e r s i o n 3 t a r t n e x t c o n v e r s i o n a i ! n a l o g v o l t a g e ( i g h e r t h r e s h o l d , o w e r t h r e s h o l d ' u a r d e d a r e a ( 4 2 , 4 2 a i analog-to-digital converter (adc) RM0033 210/1317 doc id 15403 rev 3 10.3.8 scan mode this mode is used to scan a group of analog channels. the scan mode is selected by setting the scan bit in the adc_cr1 register. once this bit has been set, the adc scans all the channel s selected in the adc_sqrx registers (for regular channels) or in the adc_jsqr register (for injected channels). a single conversion is performed for each channel of the group. after each end of conversion, the next channel in the group is converted automatically. if the cont bit is set, regular channel conversion does not stop at the last selected channel in the group but continues again from the first selected channel. if the dma bit is set, the direct memory access (dma) controller is used to transfer the data converted from the regular group of channels (stored in the adc_dr register) to sram after each regular channel conversion. the eoc bit is set in the adc_sr register: at the end of each regular group sequence if the eocs bit is cleared to 0 at the end of each regular channel conversion if the eocs bit is set to 1 the data converted from an injected channel are always stored into the adc_jdrx registers. 10.3.9 injected channel management triggered injection to use triggered injection, the jauto bit must be cleared in the adc_cr1 register. 1. start the conversion of a group of regular channels either by external trigger or by setting the swstart bit in the adc_cr2 register. 2. if an external injected trigger occurs or if the jswstart bit is set during the conversion of a regular group of channels, the current conversion is reset and the injected channel sequence switches to scan-once mode. 3. then, the regular conversion of the regular group of channels is resumed from the last interrupted regular conversion. if a regular event occurs during an injected conversion, the injected conversion is not table 33. analog watchdog channel selection channels guarded by the analog watchdog adc_cr1 register control bits (x = don?t care) awdsgl bit awden bit jawden bit none x 0 0 all injected channels 0 0 1 all regular channels 0 1 0 all regular and injected channels 0 1 1 single (1) injected channel 1. selected by the awdch[4:0] bits 101 single (1) regular channel 1 1 0 single (1) regular or injected channel 1 1 1 RM0033 analog-to-digital converter (adc) doc id 15403 rev 3 211/1317 interrupted but the regular sequence is executed at the end of the injected sequence. figure 31 shows the corresponding timing diagram. note: when using triggered injection, one must ensure that the interval between trigger events is longer than the injection sequence. for instance, if the sequence length is 30 adc clock cycles (that is two conversions with a sampling time of 3 clock periods), the minimum interval between triggers must be 31 adc clock cycles. auto-injection if the jauto bit is set, then the channels in the injected group are automatically converted after the regular group of channels. this can be used to convert a sequence of up to 20 conversions programmed in the adc_sqrx and adc_jsqr registers. in this mode, external trigger on injected channels must be disabled. if the cont bit is also set in addition to th e jauto bit, regular channel s followed by injected channels are continuously converted. note: it is not possible to use both the auto -injected and discontinuous modes simultaneously. figure 31. injected conversion latency 1. the maximum latency value can be found in the el ectrical characteristic s of the stm32f20x and stm32f21x datasheets. 10.3.10 discontinuous mode regular group this mode is enabled by setting the discen bit in the adc_cr1 register. it can be used to convert a short sequence of n conversions (n 8) that is part of the sequence of conversions selected in the adc_sqrx registers. the value of n is specified by writing to the discnum[2:0] bits in the adc_cr1 register. when an external trigger occurs, it starts the next n conversions selected in the adc_sqrx registers until all the conversions in the sequence are done. the total sequence length is defined by the l[3:0] bits in the adc_sqr1 register. ! $ # # , + ) n j e c t i o n e v e n t 2 e s e t ! $ # 3 / # m a x l a t e n c y a i analog-to-digital converter (adc) RM0033 212/1317 doc id 15403 rev 3 example: n = 3, channels to be converted = 0, 1, 2, 3, 6, 7, 9, 10 1st trigger: sequence converted 0, 1, 2 2nd trigger: sequence converted 3, 6, 7 3rd trigger: sequence converted 9, 10 and an eoc event generated 4th trigger: sequence converted 0, 1, 2 note: when a regular group is converted in discontinuous mode, no rollover occurs. when all subgroups are converted, the next trigger starts the conversion of the first subgroup. in the example above, the 4th trigger reconverts the channels 0, 1 and 2 in the 1st subgroup. injected group this mode is enabled by setting the jdiscen bit in the adc_cr1 register. it can be used to convert the sequence selected in the adc_jsqr register, channel by channel, after an external trigger event. when an external trigger occurs, it starts the next channel conversions selected in the adc_jsqr registers until all the conversions in the sequence are done. the total sequence length is defined by the jl[1:0] bits in the adc_jsqr register. example: n = 1, channels to be converted = 1, 2, 3 1st trigger: channel 1 converted 2nd trigger: channel 2 converted 3rd trigger: channel 3 converted and eoc and jeoc events generated 4th trigger: channel 1 note: 1 when all injected channels are converted, the next trigger starts the conversion of the first injected channel. in the example above, the 4th trigger reconverts the 1st injected channel 1. 2 it is not possible to use both the auto-i njected and discontinuous modes simultaneously. 3 discontinuous mode must not be set for regular and injected groups at the same time. discontinuous mode must be enabled only for the conversion of one group. 10.4 data alignment the align bit in the adc_cr2 register selects the alignment of the data stored after conversion. data can be right- or left-aligned as shown in figure 32 and figure 33 . the converted data value from the injected group of channels is decreased by the user- defined offset written in the adc_jofrx registers so the result can be a negative value. the sext bit represents t he extended sign value. for channels in a regular group, no offset is subtracted so only twelve bits are significant. RM0033 analog-to-digital converter (adc) doc id 15403 rev 3 213/1317 figure 32. right alignment of 12-bit data figure 33. left alignment of 12-bit data special case: when left-aligned, the data are aligned on a half-word basis except when the resolution is set to 6-bit. in that case, the data are aligned on a byte basis as shown in figure 34 . figure 34. left alignment of 6-bit data 10.5 channel-wise programmable sampling time the adc samples the input voltage for a number of adc_clk cycles that can be modified using the smp[2:0] bits in the adc_smpr1 and adc_smpr2 registers. each channel can be sampled with a different sampling time. the total conversion time is calculated as follows: t conv = sampling time + 12 cycles example: with adc_clk = 30 mhz and sampling time = 3 cycles: t conv = 3 + 12 = 15 cycles = 0.5 s $ $ $ $ $ $ $ $ $ $ $ $ 3 % 8 4 3 % 8 4 3 % 8 4 3 % 8 4 $ $ $ $ ) n j e c t e d g r o u p 2 e g u l a r g r o u p $ $ $ $ $ $ $ $ a i $ $ $ $ $ $ $ $ $ $ $ $ 3 % 8 4 ) n j e c t e d g r o u p 2 e g u l a r g r o u p a i $ $ $ $ $ $ $ $ $ $ $ $ $ $ 3 % 8 4 3 % 8 4 3 % 8 4 3 % 8 4 3 % 8 4 3 % 8 4 ) n j e c t e d g r o u p 2 e g u l a r g r o u p a i $ $ $ $ $ $ 3 % 8 4 3 % 8 4 $ $ $ $ 3 % 8 4 analog-to-digital converter (adc) RM0033 214/1317 doc id 15403 rev 3 10.6 conversion on external trigger and trigger polarity conversion can be triggered by an external event (e.g. timer capture, exti line). if the exten[1:0] control bits (for a regular conversion) or jexten[1:0] bits (for an injected conversion) are different from ?0b00?, then external events are able to trigger a conversion with the selected polarity. ta bl e 3 4 provides the correspondence between the exten[1:0] and jexten[1:0] values and the trigger polarity. note: the polarity of the external trigger can be changed on the fly. the extsel[3:0] and jextsel[3:0] control bits are used to select which out of 16 possible events can trigger conversion for the regular and injected groups. ta bl e 3 5 gives the possible external trigger for regular conversion. ta bl e 3 6 gives the possible external trigger for injected conversion. table 34. configuring the trigger polarity source exten[1:0] / jexten[1:0] trigger detection disabled 00 detection on the rising edge 01 detection on the falling edge 10 detection on both the rising and falling edges 11 table 35. external trigger for regular channels source type extsel[3:0] tim1_ch1 event internal signal from on-chip timers 0000 tim1_ch2 event 0001 tim1_ch3 event 0010 tim2_ch2 event 0011 tim2_ch3 event 0100 tim2_ch4 event 0101 tim2_trgo event 0110 tim3_ch1 event 0111 tim3_trgo event 1000 tim4_ch4 event 1001 tim5_ch1 event 1010 tim5_ch2 event 1011 tim5_ch3 event 1100 tim8_ch1 event 1101 tim8_trgo event 1110 exti line11 external pin 1111 RM0033 analog-to-digital converter (adc) doc id 15403 rev 3 215/1317 software source trigger events can be generated by setting swstart (for regular conversion) or jswstart (for injected conversion) in adc_cr2. a regular group conversion can be interrupted by an injected trigger. note: the trigger selection can be changed on the fly. however, when the selection changes, there is a time frame of 1 apb clock cycle during which the trigger detection is disabled. this is to avoid spurious detection during transitions. 10.7 fast conversion mode it is possible to perform faster conversion by reducing the adc resolution. the res bits are used to select the number of bits available in the data register. the minimum conversion time for each resolution is then as follows: 12 bits: 3 + 12 = 15 adcclk cycles 10 bits: 3 + 10 = 13 adcclk cycles 8 bits: 3 + 8 = 11 adcclk cycles 6 bits: 3 + 6 = 9 adcclk cycles table 36. external trigger for injected channels source connection type jextsel[3:0] tim1_ch4 event internal signal from on-chip timers 0000 tim1_trgo event 0001 tim2_ch1 event 0010 tim2_trgo event 0011 tim3_ch2 event 0100 tim3_ch4 event 0101 tim4_ch1 event 0110 tim4_ch2 event 0111 tim4_ch3 event 1000 tim4_trgo event 1001 tim5_ch4 event 1010 tim5_trgo event 1011 tim8_ch2 event 1100 tim8_ch3 event 1101 tim8_ch4 event 1110 exti line15 external pin 1111 analog-to-digital converter (adc) RM0033 216/1317 doc id 15403 rev 3 10.8 data management 10.8.1 using the dma since converted regular channel values are stored into a unique data register, it is useful to use dma for conversion of more than one regular channel. this avoids the loss of the data already stored in the adc_dr register. when the dma mode is enabled (dma bit set to 1 in the adc_cr2 register), after each conversion of a regular channel, a dma request is generated. this allows the transfer of the converted data from the adc_dr register to the destination location selected by the software. despite this, if data are lost (overrun), the ov r bit in the adc_sr register is set and an interrupt is generated (if the ovrie enable bit is set). dma transfers are then disabled and dma requests are no longer accepted. in this case, if a dma request is made, the regular conversion in progress is aborted and further regular triggers are ignored. it is then necessary to clear the ovr flag and the dmaen bit in the used dma stream, and to re- initialize both the dma and the adc to have the wanted converted channel data transferred to the right memory location. only then can the conversion be resumed and the data transfer, enabled again. injected channel conversions are not impacted by overrun errors. when ovr = 1 in dma mode, the dma requests are blocked after the last valid data have been transferred, which means that all the data transferred to the ram can be considered as valid. at the end of the last dma transfer (number of transfers configured in the dma controller?s dma_sxrtr register): no new dma request is issued to the dma controller if the dds bit is cleared to 0 in the adc_cr2 register (this avoids generating an overrun error). however the dma bit is not cleared by hardware. it must be written to 0, then to 1 to start a new transfer. requests can continue to be generated if the dds bit is set to 1. this allows configuring the dma in double-buffer circular mode. 10.8.2 managing a sequence of conve rsions without using the dma if the conversions are slow enough, the conversion sequence can be handled by the software. in this case the eocs bit must be set in the adc_cr2 register for the eoc status bit to be set at the end of each conversion, and not only at the end of the sequence. when eocs = 1, overrun detection is automatically enabled. thus, each time a conversion is complete, eoc is set and the adc_dr register can be read. the overrun management is the same as when the dma is used. 10.8.3 conversions without dm a and without overrun detection it may be useful to let the adc convert one or more channels without reading the data each time (if there is an analog watchdog for instance). for that, the dma must be disabled (dma = 0) and the eoc bit must be set at the end of a sequence only (eocs = 0). in this configuration, overrun detection is disabled. RM0033 analog-to-digital converter (adc) doc id 15403 rev 3 217/1317 10.9 multi adc mode in devices with two adcs or more, the dual (with two adcs) and triple (with three adcs) adc modes can be used (see figure 35 ). in multi adc mode, the start of conversion is triggered alternately or simultaneously by the adc1 master to the adc2 and adc3 slaves, depending on the mode selected by the multi[4:0] bits in the adc_ccr register. note: in multi adc mode, when configuring conversion trigger by an external event, the application must set trigger by the master only and disable trigger by slaves to prevent spurious triggers that would start unwanted slave conversions. the four possible modes below are implemented: injected simultaneous mode regular simultaneous mode interleaved mode alternate trigger mode it is also possible to use the previous modes combined in the following ways: injected simultaneous mode + regular simultaneous mode regular simultaneous mode + alternate trigger mode note: in multi adc mode, the converted data can be read on the multi-mode data register (adc_cdr). the status bits can be read in the multi-mode status register (adc_csr). analog-to-digital converter (adc) RM0033 218/1317 doc id 15403 rev 3 figure 35. multi adc block diagram (1) 1. although external triggers are pr esent on adc2 and adc3 they are not shown in this diagram. 2. in the dual adc mode, the ad c3 slave part is not present. 3. in triple adc mode, the adc common data register (adc_cdr) contains the adc1, adc2 and adc3?s regular converted data. all 32 register bits are used according to a selected storage order. in dual adc mode, the adc common data register (adc_cdr) contains both the adc1 and adc2?s regular converted data. all 32 register bits are used. ! $ # x ? ) . ! $ # x ? ) . ! $ # x ? ) . ' 0 ) / 0 o r t s ! d d r e s s d a t a b u s % 8 4 ) ? % 8 4 ) ? ) n j e c t e d d a t a r e g i s t e r s x b i t s 2 e g u l a r c h a n n e l s ) n j e c t e d c h a n n e l s ! $ # 3 l a v e b i t s ) n j e c t e d d a t a r e g i s t e r s x b i t s 2 e g u l a r c h a n n e l s ) n j e c t e d c h a n n e l s ! $ # - a s t e r $ u a l 4 r i p l e i n t e r n a l t r i g g e r s 3 t a r t t r i g g e r m u x r e g u l a r g r o u p i n j e c t e d g r o u p 3 t a r t t r i g g e r m u x c o n t r o l 4 e m p s e n s o r 6 2 % & ) . 4 2 e g u l a r d a t a r e g i s t e r b i t s 2 e g u l a r d a t a r e g i s t e r b i t s # o m m o n r e g u l a r d a t a r e g i s t e r b i t s 6 " ! 4 # o m m o n p a r t m o d e ! $ # 3 l a v e b i t s ) n j e c t e d d a t a r e g i s t e r s x b i t s 2 e g u l a r c h a n n e l s ) n j e c t e d c h a n n e l s 2 e g u l a r d a t a r e g i s t e r b i t s a i RM0033 analog-to-digital converter (adc) doc id 15403 rev 3 219/1317 dma requests in multi adc mode: in multi adc mode the dma may be configured to transfer converted data in three different modes. in all cases, the dma streams to use are those connected to the adc: ? dma mode 1: on each dma request (one data item is available), a half-word representing an adc-converted data item is transferred. in dual adc mode, adc1 data are transferr ed on the first request, adc2 data are transferred on the second request and so on. in triple adc mode, adc1 data are transferred on the first request, adc2 data are transferred on the second request and adc3 data are transferred on the third request; the sequence is repeated. so the dma first transfers adc1 data followed by adc2 data followed by adc3 data and so on. dma mode 1 is used in regular simultaneous triple mode. example: regular simultaneous triple mode: 3 consecutive dma requests are generated (one for each converted data item) 1st request: adc_cdr[31:0] = adc1_dr[15:0] 2nd request: adc_cdr[31:0] = adc2_dr[15:0] 3rd request: adc_cdr[31:0] = adc3_dr[15:0] 4th request: adc_cdr[31:0] = adc1_dr[15:0] ? dma mode 2 : on each dma request (two data items are available) two half-words representing two adc-converted data items are transferred as a word. in dual adc mode, both adc2 and adc1 data are transferred on the first request (adc2 data take the upper half-word and adc1 data take the lower half-word) and so on. in triple adc mode, three dma requests are generated. on the first request, both adc2 and adc1 data are transferred (adc2 data take the upper half-word and adc1 data take the lower half-word). on the second request, both adc1 and adc3 data are transferred (adc1 data take the upper half-word and adc3 data take the lower half-word).on the third request, both adc3 and adc2 data are transferred (adc3 data take the upper half-word and adc2 data take the lower half-word) and so on. dam mode 2 is used in interleaved mode and in regular simultaneous mode (for dual adc mode only). example: a) interleaved dual mode: a dma request is generated each time 2 data items are available: 1st request: adc_cdr[31:0] = adc2_dr[15:0] | adc1_dr[15:0] 2nd request: adc_cdr[31:0] = adc2_dr[15:0] | adc1_dr[15:0] b) interleaved triple mode: a dma request is generated each time 2 data items are available 1st request: adc_cdr[31:0] = adc2_dr[15:0] | adc1_dr[15:0] 2nd request: adc_cdr[31:0] = adc1_dr[15:0] | adc3_dr[15:0] 3rd request: adc_cdr[31:0] = a dc3_dr[15:0] | adc2_dr[15:0] 4th request: adc_cdr[31:0] = ad c2_dr[15:0] | adc1_dr[15:0] analog-to-digital converter (adc) RM0033 220/1317 doc id 15403 rev 3 ? dma mode 3 : this mode is similar to the dma mode 2. the only differences are that the on each dma request (two data items are available) two bytes representing two adc converted data items are transferred as a half-word. the data transfer order is similar to that of the dma mode 2. dma mode 3 is used in interleaved mode in 6-bit and 8-bit resolutions. example: a) interleaved dual mode: a dma request is generated each time 2 data items are available 1st request: adc_cdr[15:0] = adc2_dr[7:0] | adc1_dr[7:0] 2nd request: adc_cdr[15:0] = adc2_dr[7:0] | adc1_dr[7:0] b) interleaved triple mode: a dma request is generated each time 2 data items are available 1st request: adc_cdr[15:0] = adc2_dr[7:0] | adc1_dr7:0] 2nd request: adc_cdr[15:0] = adc1_dr[7:0] | adc3_dr[15:0] 3rd request: adc_cdr[15:0] = adc3_dr[7:0] | adc2_dr[7:0] 4th request: adc_cdr[15:0] = adc2_dr[7:0] | adc1_dr7:0] overrun detection: if an overrun is detected on one of the concerned adcs (adc1 and adc2 in dual and triple modes, adc3 in triple mode only), the dma requests are no longer issued to ensure that all the data transferred to the ram are valid. it may happen that the eoc bit corresponding to one adc remains set because the data register of this adc contains valid data. 10.9.1 injected simultaneous mode this mode converts an injected group of channels. the external trigger source comes from the injected group multiplexer of ad c1 (selected by the jextsel[3:0] bits in the adc1_cr2 register). a simultaneous trigger is provided to adc2 and adc3. note: do not convert the same channel on the two/three adcs (no overlapping sampling times for the two/three adcs when converting the same channel). in simultaneous mode, one must convert sequences with the same length or ensure that the interval between triggers is longer than the longer of the 2 sequences (dual adc mode) /3 sequences (triple adc mode). otherwise, the adc with the shortest sequence may restart while the adc with the longest sequence is completing the previous conversions. regular conversions can be performed on one or all adcs. in that case, they are independent of each other and are interrupted when an injected event occurs. they are resumed at the end of the injected conversion group. dual adc mode at the end of conversion event on adc1 or adc2: the converted data are stored into the adc_jdrx registers of each adc interface. a jeoc interrupt is generated (if enabled on one of the two adc interfaces) when the adc1/adc2?s injected channels have all been converted. RM0033 analog-to-digital converter (adc) doc id 15403 rev 3 221/1317 figure 36. injected simultaneous mode on 4 channels: dual adc mode triple adc mode at the end of conversion event on adc1, adc2 or adc3: the converted data are stored into the adc_jdrx registers of each adc interface. a jeoc interrupt is generated (if enabled on one of the three adc interfaces) when the adc1/adc2/adc3?s injected channels have all been converted. figure 37. injected simu ltaneous mode on 4 ch annels: triple adc mode 10.9.2 regular simultaneous mode this mode is performed on a regular group of channels. the external trigger source comes from the regular group multiplexer of adc1 (selected by the extsel[3:0] bits in the adc1_cr2 register). a simultaneous trigger is provided to adc2 and adc3. note: do not convert the same channel on the two/three adcs (no overlapping sampling times for the two/three adcs when converting the same channel). in regular simultaneous mode, one must convert sequences with the same length or ensure that the interval between triggers is longer th an the long conversion time of the 2 sequences (dual adc mode) /3 sequences (triple adc mode). otherwise, the adc with the shortest sequence may restart while the adc with the longest sequence is completing the previous conversions. injected conversions must be disabled. # ( # ( # ( # ( # ( # ( # ( # ( ! $ # ! $ # 4 r i g g e r % n d o f c o n v e r s i o n o n ! $ # a n d ! $ # # o n v e r s i o n 3 a m p l i n g # ( # ( a i # ( # ( # ( # ( # ( # ( # ( # ( ! $ # ! $ # 4 r i g g e r % n d o f c o n v e r s i o n o n ! $ # ! $ # a n d ! $ # # o n v e r s i o n 3 a m p l i n g # ( # ( a i # ( # ( # ( # ( ! $ # # ( analog-to-digital converter (adc) RM0033 222/1317 doc id 15403 rev 3 dual adc mode at the end of conversion event on adc1 or adc2: a 32-bit dma transfer request is generated (if dma[1:0] bits in the adc_ccr register are equal to 0b10). this request transfers the adc2 converted data stored in the upper half-word of the adc_cdr 32-bit register to the sram and then the adc1 converted data stored in the lower half-word of adc_ccr to the sram. an eoc interrupt is generated (if enabled on one of the two adc interfaces) when the adc1/adc2?s regular channels have all been converted. figure 38. regular simultaneous mode on 16 channels: dual adc mode triple adc mode at the end of conversion event on adc1, adc2 or adc3: three 32-bit dma transfer requests are generated (if dma[1:0] bits in the adc_ccr register are equal to 0b01). three transfers then take place from the adc_cdr 32-bit register to sram: first the adc1 converted data, then the adc2 converted data and finally the adc3 converted data. the process is repeated for each new three conversions. an eoc interrupt is generated (if enabled on one of the three adc interfaces) when the adc1/adc2/adc3?s regular channels are have all been converted. figure 39. regular simultaneous mode on 16 channels: triple adc mode 10.9.3 interleaved mode this mode can be started only on a regular group (usually one channel). the external trigger source co mes from the regular cha nnel multiplexer of adc1. # ( # ( # ( # ( # ( # ( # ( # ( ! $ # ! $ # 4 r i g g e r % n d o f c o n v e r s i o n o n ! $ # a n d ! $ # # o n v e r s i o n 3 a m p l i n g # ( # ( a i # ( # ( # ( # ( # ( # ( # ( # ( ! $ # ! $ # 4 r i g g e r % n d o f c o n v e r s i o n o n ! $ # ! $ # a n d ! $ # # o n v e r s i o n 3 a m p l i n g # ( # ( a i # ( # ( # ( # ( ! $ # # ( RM0033 analog-to-digital converter (adc) doc id 15403 rev 3 223/1317 dual adc mode after an external trigger occurs: adc1 starts immediately adc2 starts after a delay of several adc clock cycles the minimum delay which separates 2 conversions in interleaved mode is configured in the delay bits in the adc_ccr register. however, an adc cannot start a conversion if the complementary adc is still samplin g its input (only one adc can sample the inpu t signal at a given time). in this case, the delay becomes the sampling time + 2 adc clock cycles. for instance, if delay = 5 clock cycles and the sampling takes 15 cloc k cycles on both adcs, then 17 clock cycles will separate conversions on adc1 and adc2). if the cont bit is set on both adc1 and adc2, the selected regular channels of both adcs are continuously converted. after an eoc interrupt is generated by adc2 (if enabled through the eocie bit) a 32-bit dma transfer request is generated (if the dma[1:0] bits in adc_ccr are equal to 0b10). this request first transfers the adc2 converted data stored in the upper half-word of the adc_cdr 32-bit register into sram, then the adc1 converted data stored in the register?s lower half-word into sram. figure 40. interleaved mode on 1 channel in continuous conversion mode: dual adc mode triple adc mode after an external trigger occurs: adc1 starts immediately and adc2 starts after a delay of several adc clock cycles adc3 starts after a delay of several adc clock cycles referred to the adc2 conversion the minimum delay which separates 2 conversions in interleaved mode is configured in the delay bits in the adc_ccr register. however, an adc cannot start a conversion if the complementary adc is still samplin g its input (only one adc can sample the inpu t signal at a given time). in this case, the delay becomes the sampling time + 2 adc clock cycles. for instance, if delay = 5 clock cycles and the sampling takes 15 cloc k cycles on the three adcs, then 17 clock cycles will separate the conversions on adc1, adc2 and adc3). if the cont bit is set on adc1, adc2 and adc3, the selected regular channels of all adcs are continuously converted. in this mode a dma request is generated each time 2 data items are available, (if the dma[1:0] bits in the adc_ccr register are equal to 0b10). the request first transfers the first converted data stored in the lower half-w ord of the adc_cdr 32-bit register to sram, # ( # ( ! $ # ! $ # 4 r i g g e r % n d o f c o n v e r s i o n o n ! $ # # ( # ( ! $ # # , + c y c l e s % n d o f c o n v e r s i o n o n ! $ # # o n v e r s i o n 3 a m p l i n g a i analog-to-digital converter (adc) RM0033 224/1317 doc id 15403 rev 3 then it transfers the second converted data stored in adc_cdr?s upper half-word to sram. the sequence is the following: 1st request: adc_cdr[31:0] = adc2_dr[15:0] | adc1_dr[15:0] 2nd request: adc_cdr[31:0] = adc1_dr[15:0] | adc3_dr[15:0] 3rd request: adc_cdr[31:0] = ad c3_dr[15:0] | adc2_dr[15:0] 4th request: adc_cdr[31:0] = adc2_dr[15:0] | adc1_dr[15:0], ... figure 41. interleaved mode on 1 channel in continuous conversion mode: triple adc mode 10.9.4 alternate trigger mode this mode can be started only on an injected group. the source of external trigger comes from the injected gro up multiplexer of adc1. note: regular conversions can be enabled on one or all adcs. in this case the regular conversions are independent of each other. a regular conversion is interrupted when the adc has to perform an injected conversion. it is resumed when the injected conversion is finished. the time interval between 2 trigger events must be greater than or equal to 1 adc clock period. the minimum time interval between 2 trigger events that start conversions on the same adc is the same as in the single adc mode. dual adc mode when the 1st trigger occurs, all injected adc1 channels in the group are converted when the 2nd trigger occurs, all injected adc2 channels in the group are converted and so on a jeoc interrupt, if enabled, is generated after all injected adc1 channels in the group have been converted. a jeoc interrupt, if enabled, is generated after all injected adc2 channels in the group have been converted. if another external trigger occurs after all injected channels in the group have been converted then the alternate trigger process restarts by converting the injected adc1 channels in the group. ! $ # ! $ # 4 r i g g e r % n d o f c o n v e r s i o n o n ! $ # ! $ # # , + c y c l e s % n d o f c o n v e r s i o n o n ! $ # ! $ # % n d o f c o n v e r s i o n o n ! $ # $ - ! r e q u e s t e v e r y c o n v e r s i o n s # ( # o n v e r s i o n 3 a m p l i n g a i # ( # ( # ( # ( # ( # ( # ( # ( RM0033 analog-to-digital converter (adc) doc id 15403 rev 3 225/1317 figure 42. alternate trigger: injected group of each adc if the injected discontinuous mode is enabled for both adc1 and adc2: when the 1st trigger occurs, the first injected adc1 channel is converted. when the 2nd trigger occurs, the first injected adc2 channel are converted and so on a jeoc interrupt, if enabled, is generated after all injected adc1 channels in the group have been converted. a jeoc interrupt, if enabled, is generated after all injected adc2 channels in the group have been converted. if another external trigger occurs after all injected channels in the group have been converted then the alternate trigger process restarts. figure 43. alternate trigge r: 4 injected channels ( each adc) in discontinuous mode triple adc mode when the 1st trigger occurs, all injected adc1 channels in the group are converted. when the 2nd trigger occurs, all injected adc2 channels in the group are converted. when the 3rd trigger occurs, all injected adc3 channels in the group are converted. and so on a jeoc interrupt, if enabled, is generated after all injected adc1 channels in the group have been converted. a jeoc interrupt, if enabled, is generated after all injected adc2 channels in the group have been converted. a jeoc interrupt, if enabled, is generated after all injected adc3 channels in the group have been converted. ! $ # ! $ # s t t r i g g e r n d t r i g g e r r d t r i g g e r t h t r i g g e r n t h t r i g g e r n t h t r i g g e r % / # * % / # o n ! $ # % / # * % / # o n ! $ # % / # * % / # o n ! $ # % / # * % / # o n ! $ # # o n v e r s i o n 3 a m p l i n g a i ! $ # ! $ # s t t r i g g e r # o n v e r s i o n 3 a m p l i n g n d t r i g g e r r d t r i g g e r t h t r i g g e r t h t r i g g e r t h t r i g g e r t h t r i g g e r t h t r i g g e r * % / # o n ! $ # * % / # o n ! $ # a i analog-to-digital converter (adc) RM0033 226/1317 doc id 15403 rev 3 if another external trigger occurs after all injected channels in the group have been converted then the alternate trigger process restarts by converting the injected adc1 channels in the group. figure 44. alternate trigger: injected group of each adc 10.9.5 combined regular/injected simultaneous mode it is possible to interrupt the simultaneous conversion of a regular group to start the simultaneous conversion of an injected group. note: in combined regular/injected simultaneous mode, one must convert sequences with the same length or ensure that the interval between triggers is longer than the long conversion time of the 2 sequences (dual adc mode) /3 sequences (triple adc mode). otherwise, the adc with the shortest sequence may restart while the adc with the longest sequence is completing the previous conversions. 10.9.6 combined regular simult aneous + alternate trigger mode it is possible to interrupt the simultaneous conversion of a regular group to start the alternate trigger conversion of an injected group. figure 45 shows the behavior of an alternate trigger interrupting a simultaneous regular conversion. the injected alternate conversion is immediately started after the injected event. if regular conversion is already running, in order to ensure synchronization after the injected conversion, the regular conversion of all (master/slave) adcs is stopped and resumed synchronously at the end of the injected conversion. note: in combined regular simultaneous + alternate trigger mode, one must convert sequences with the same length or ensure that the interval between triggers is longer than the long conversion time of the 2 sequences (dual adc mode) /3 sequences (triple adc mode). otherwise, the adc with the shortest sequence may restart while the adc with the longest sequence is completing the previous conversions. ! $ # ! $ # s t t r i g g e r # o n v e r s i o n 3 a m p l i n g n d t r i g g e r t h t r i g g e r r d t r i g g e r n t h t r i g g e r n t h t r i g g e r % / # * % / # o n ! $ # % / # * % / # o n ! $ # % / # * % / # o n ! $ # % / # * % / # o n ! $ # t h t r i g g e r n t h t r i g g e r a i RM0033 analog-to-digital converter (adc) doc id 15403 rev 3 227/1317 figure 45. alternate + regular simultaneous if a trigger occurs during an injected conversion that has interrupted a regular conversion, it is ignored. figure 46 shows the behavior in this case (2nd trigger is ignored). figure 46. case of trigger occurring during injected conversion 10.10 temperature sensor the temperature sensor can be used to measure the ambient temperature (t a ) of the device. the temperature sensor is internally connect ed to the adc1_in16 in put channel which is used to convert the sensor?s output voltage to a digital value. the sampling time for the temperature sensor?s analog pin must be greater than 2.2 s. figure 47 shows the block diagram of the temperature sensor. when not in use, the sensor can be put in power down mode. note: the tsvrefe bit must be set to enable the conversion of both internal channels: adc1_in16 (temperature sensor) and adc1_in17 (v refint ). main features supported temperature range: ?40 to 125 c precision: 1.5 c ! $ # r e g # ( # ( # ( # ( # ( # ( # ( ! $ # i n j ! $ # r e g ! $ # i n j s t t r i g g e r n d t r i g g e r s y n c h r o n o t l o s t # ( # ( # ( # ( # ( # ( # ( # ( # ( a i ! $ # r e g # ( # ( # ( # ( # ( # ( # ( ! $ # i n j ! $ # r e g ! $ # i n j s t t r i g g e r n d t r i g g e r # ( # ( # ( # ( # ( # ( # ( # ( # ( a i # ( n d t r i g g e r r d t r i g g e r analog-to-digital converter (adc) RM0033 228/1317 doc id 15403 rev 3 figure 47. temperature sensor and v refint channel block diagram reading the temperature to use the sensor: 4. select the adc1_in16 input channel 5. select a sampling time greater than 2.2 s 6. set the tsvrefe bit in the adc_ccr register to wake up the temperature sensor from power down mode 7. start the adc conversion by setting the swstart bit (or by external trigger) 8. read the resulting v sense data in the adc data register 9. calculate the temperature using the following formula: temperature (in c) = {(v 25 ? v sense ) / avg_slope} + 25 where: ?v 25 = v sense value for 25 c ? avg_slope = average slope of the temperature vs. v sense curve (given in mv/c or v/c) refer to the datasheet?s electrical characteristics section for the actual values of v 25 and avg_slope. note: the sensor has a startup time after waking from power down mode before it can output v sense at the correct level. the adc also has a startup time after power-on, so to minimize the delay, the adon and tsvrefe bits should be set at the same time. 10.11 battery charge monitoring the vbate bit in the adc_ccr register is used to switch to the battery voltage. as the v bat voltage could be higher than v dda , to ensure the correct operation of the adc, the v bat pin is internally connected to a bridge divide r by 2. this bridge is automatically enabled when vbate is set, to connect v bat /2 to the adc1_in18 input channel. as a consequence, the converted digital value is half the v bat voltage. to prevent any unwanted consumption s e n s o r 4 e m p e r a t u r e 6 3 % . 3 % 4 3 6 2 % & % c o n t r o l b i t ! $ # ! d d r e s s d a t a b u s c o n v e r t e d d a t a 6 2 % & ) . 4 ! $ # ? ) . ! $ # ? ) . p o w e r b l o c k ) n t e r n a l a i RM0033 analog-to-digital converter (adc) doc id 15403 rev 3 229/1317 on the battery, it is recommended to enable the bridge divider only when needed, for adc conversion. 10.12 adc interrupts an interrupt can be produced on the end of conversion for regular and injected groups, when the analog watchdog status bit is set and when the overrun status bit is set. separate interrupt enable bits are available for flexibility. two other flags are present in the adc_sr register, but there is no interrupt associated with them: jstrt (start of conversion for channels of an injected group) strt (start of conversion for channels of a regular group) table 37. adc interrupts interrupt event event flag enable control bit end of conversion of a regular group eoc eocie end of conversion of an injected group jeoc jeocie analog watchdog status bit is set awd awdie overrun ovr ovrie analog-to-digital converter (adc) RM0033 230/1317 doc id 15403 rev 3 10.13 adc registers refer to section 1.1 on page 46 for a list of abbreviations used in register descriptions. 10.13.1 adc status register (adc_sr) address offset: 0x00 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 reserved ovr strt jstrt jeoc eoc awd rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 bits 31:6 reserved, must be kept cleared. bit 5 ovr: overrun this bit is set by hardware when data are lost (either in single mode or in dual/triple mode). it is cleared by software. overrun detection is enabled only when dma = 1 or eocs = 1. 0: no overrun occurred 1: overrun has occurred bit 4 strt: regular channel start flag this bit is set by hardware when regular channel conversion starts. it is cleared by software. 0: no regular channel conversion started 1: regular channel conversion has started bit 3 jstrt: injected channel start flag this bit is set by hardware when injected group conversion starts. it is cleared by software. 0: no injected group conversion started 1: injected group conversion has started bit 2 jeoc: injected channel end of conversion this bit is set by hardware at the end of the conversion of all injected channels in the group. it is cleared by software. 0: conversion is not complete 1: conversion complete bit 1 eoc: regular channel end of conversion this bit is set by hardware at the end of the conversion of a regular group of channels. it is cleared by software or by reading the adc_dr register. 0: conversion not complete (eocs=0), or sequence of conversions not complete (eocs=1) 1: conversion complete (eocs=0), or sequence of conversions complete (eocs=1) bit 0 awd: analog watchdog flag this bit is set by hardware when the converte d voltage crosses the values programmed in the adc_ltr and adc_htr registers. it is cleared by software. 0: no analog watchdog event occurred 1: analog watchdog event occurred RM0033 analog-to-digital converter (adc) doc id 15403 rev 3 231/1317 10.13.2 adc control r egister 1 (adc_cr1) address offset: 0x04 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved ovrie res awden jawden reserved rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 discnum[2:0] jdisce n disc en jauto awdsg l scan jeocie awdie eocie awdch[4:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:27 reserved, must be kept cleared. bit 26 ovrie: overrun interrupt enable this bit is set and cleared by software to enable/disable the overrun interrupt. 0: overrun interrupt disabled 1: overrun interrupt enabled. an interrupt is generated when the ovr bit is set. bits 25:24 res[1:0]: resolution these bits are written by software to select the resolution of the conversion. 00: 12-bit (15 adcclk cycles) 01: 10-bit (13 adcclk cycles) 10: 8-bit (11 adcclk cycles) 11: 6-bit (9 adcclk cycles) bit 23 awden: analog watchdog enable on regular channels this bit is set and cleared by software. 0: analog watchdog disabled on regular channels 1: analog watchdog enabled on regular channels bit 22 jawden: analog watchdog enable on injected channels this bit is set and cleared by software. 0: analog watchdog disabled on injected channels 1: analog watchdog enabled on injected channels bits 21:16 reserved, must be kept cleared. bits 15:13 discnum[2:0]: discontinuous mode channel count these bits are written by software to define the number of regular channels to be converted in discontinuous mode, after receiving an external trigger. 000: 1 channel 001: 2 channels ... 111: 8 channels bit 12 jdiscen: discontinuous mode on injected channels this bit is set and cleared by software to enable/disable discontinuous mode on the injected channels of a group. 0: discontinuous mode on injected channels disabled 1: discontinuous mode on injected channels enabled analog-to-digital converter (adc) RM0033 232/1317 doc id 15403 rev 3 bit 11 discen: discontinuous mode on regular channels this bit is set and cleared by software to enable/disable discontinuous mode on regular channels. 0: discontinuous mode on regular channels disabled 1: discontinuous mode on regular channels enabled bit 10 jauto: automatic injected group conversion this bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion. 0: automatic injected group conversion disabled 1: automatic injected group conversion enabled bit 9 awdsgl: enable the watchdog on a single channel in scan mode this bit is set and cleared by software to enable/disable the analog watchdog on the channel identified by the awdch[4:0] bits. 0: analog watchdog enabled on all channels 1: analog watchdog enabled on a single channel bit 8 scan: scan mode this bit is set and cleared by software to enable/disable the scan mode. in scan mode, the inputs selected through the adc_sqrx or adc_jsqrx registers are converted. 0: scan mode disabled 1: scan mode enabled note: an eoc interrupt is genera ted if the eocie bit is set: ? at the end of each regular group sequenc e if the eocs bit is cleared to 0 ? at the end of each regular channel conv ersion if the eocs bit is set to 1 note: a jeoc interrupt is generated only on the en d of conversion of the last channel if the jeocie bit is set. bit 7 jeocie: interrupt enable for injected channels this bit is set and cleared by software to enable/disable the end of conversion interrupt for injected channels. 0: jeoc interrupt disabled 1: jeoc interrupt enabled. an interrupt is generated when the jeoc bit is set. bit 6 awdie: analog watchdog interrupt enable this bit is set and cleared by software to enable/disable the analog watchdog interrupt. in scan mode if the watchdog thres holds are crossed, scan is aborted only if this bit is enabled. 0: analog watchdog interrupt disabled 1: analog watchdog interrupt enabled bit 5 eocie: interrupt enable for eoc this bit is set and cleared by software to enable/disable the end of conversion interrupt. 0: eoc interrupt disabled 1: eoc interrupt enabled. an interrupt is generated when the eoc bit is set. RM0033 analog-to-digital converter (adc) doc id 15403 rev 3 233/1317 10.13.3 adc control r egister 2 (adc_cr2) address offset: 0x08 reset value: 0x0000 0000 bits 4:0 awdch[4:0]: analog watchdog channel select bits these bits are set and cleared by software. they select the input channel to be guarded by the analog watchdog. note: 00000: adc analog input channel0 00001: adc analog input channel1 ... 01111: adc analog input channel15 10000: adc analog input channel16 10001: adc analog input channel17 10010: adc analog input channel18 other values reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserve d swst art exten extsel[3:0] reserve d jswst art jexten jextsel[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved align eocs dds dma reserved cont adon rw rw rw rw rw rw bit 31 reserved, must be kept cleared. bit 30 swstart: start conversion of regular channels this bit is set by software to start conversion and cleared by hardware as soon as the conversion starts. 0: reset state 1: starts conversion of regular channels note: this bit can be set only when adon = 1 otherwise no conversion is launched. bits 29:28 exten: external trigger enable for regular channels these bits are set and cleared by software to se lect the external trigger polarity and enable the trigger of a regular group. 00: trigger detection disabled 01: trigger detection on the rising edge 10: trigger detection on the falling edge 11: trigger detection on both the rising and falling edges analog-to-digital converter (adc) RM0033 234/1317 doc id 15403 rev 3 bits 27:24 extsel[3:0]: external event select for regular group these bits select the external event used to tr igger the start of conversion of a regular group: 0000: timer 1 cc1 event 0001: timer 1 cc2 event 0010: timer 1 cc3 event 0011: timer 2 cc2 event 0100: timer 2 cc3 event 0101: timer 2 cc4 event 0110: timer 2 trgo event 0111: timer 3 cc1 event 1000: timer 3 trgo event 1001: timer 4 cc4 event 1010: timer 5 cc1 event 1011: timer 5 cc2 event 1100: timer 5 cc3 event 1101: timer 8 cc1 event 1110: timer 8 trgo event 1111: exti line11 bit 23 reserved, must be kept cleared. bit 22 jswstart: start conversion of injected channels this bit is set by software and cleared by hardware as soon as the conversion starts. 0: reset state 1: starts conversion of injected channels note: this bit can be set only when adon = 1 otherwise no conversion is launched. bits 21:20 jexten: external trigger enable for injected channels these bits are set and cleared by software to se lect the external trigger polarity and enable the trigger of an injected group. 00: trigger detection disabled 01: trigger detection on the rising edge 10: trigger detection on the falling edge 11: trigger detection on both the rising and falling edges bits 19:16 jextsel[3:0]: external event select for injected group these bits select the external event used to trigger the start of conversion of an injected group. 0000: timer 1 cc4 event 0001: timer 1 trgo event 0010: timer 2 cc1 event 0011: timer 2 trgo event 0100: timer 3 cc2 event 0101: timer 3 cc4 event 0110: timer 4 cc1 event 0111: timer 4 cc2 event 1000: timer 4 cc3 event 1001: timer 4 trgo event 1010: timer 5 cc4 event 1011: timer 5 trgo event 1100: timer 8 cc2 event 1101: timer 8 cc3 event 1110: timer 8 cc4 event 1111: exti line15 bits 15:12 reserved, must be kept cleared. RM0033 analog-to-digital converter (adc) doc id 15403 rev 3 235/1317 bit 11 align: data alignment this bit is set and cleared by software. refer to figure 32 and figure 33 . 0: right alignment 1: left alignment bit 10 eocs: end of conversion selection this bit is set and cleared by software. 0: the eoc bit is set at the end of each sequence of regula r conversions. overrun detection is enabled only if dma=1. 1: the eoc bit is set at the end of each re gular conversion. overrun detection is enabled. bit 9 dds: dma disable selection (for single adc mode) this bit is set and cleared by software. 0: no new dma request is issued after the last tr ansfer (as configured in the dma controller) 1: dma requests are issued as long as data are converted and dma=1 bit 8 dma: direct memory access mode (for single adc mode) this bit is set and cleared by software. refer to the dma controller chapter for more details. 0: dma mode disabled 1: dma mode enabled bits 7:2 reserved, must be kept cleared. bit 1 cont: continuous conversion this bit is set and cleared by software. if it is set, conversion takes place continuously until it is cleared. 0: single conversion mode 1: continuous conversion mode bit 0 adon: a/d converter on / off this bit is set and cleared by software. note: 0: disable adc conversion and go to power down mode 1: enable adc analog-to-digital converter (adc) RM0033 236/1317 doc id 15403 rev 3 10.13.4 adc sample time register 1 (adc_smpr1) address offset: 0x0c reset value: 0x0000 0000 10.13.5 adc sample time register 2 (adc_smpr2) address offset: 0x10 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved smp18[2:0] smp17[2:0] smp16[2:0] smp15[2:1] rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smp15_0 smp14[2:0] smp13[2:0] smp12[2:0] smp11[2:0] smp10[2:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31: 27 reserved, must be kept cleared. bits 26:0 smpx[2:0]: channel x sampling time selection these bits are written by software to select the sampling time individually for each channel. during sampling cycles, the channel sele ction bits must remain unchanged. note: 000: 3 cycles 001: 15 cycles 010: 28 cycles 011: 56 cycles 100: 84 cycles 101: 112 cycles 110: 144 cycles 111: 480 cycles 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved smp9[2:0] smp8[2:0] smp7[2:0] smp6[2:0] smp5[2:1] rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 smp 5_0 smp4[2:0] smp3[2:0] smp2[2:0] smp1[2:0] smp0[2:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:30 reserved, must be kept cleared. bits 29:0 smpx[2:0]: channel x sampling time selection these bits are written by software to select the sampling time individually for each channel. during sample cycles, the channel selection bits must remain unchanged. note: 000: 3 cycles 001: 15 cycles 010: 28 cycles 011: 56 cycles 100: 84 cycles 101: 112 cycles 110: 144 cycles 111: 480 cycles RM0033 analog-to-digital converter (adc) doc id 15403 rev 3 237/1317 10.13.6 adc injected channel data offset register x (adc_jofrx)(x=1..4) address offset: 0x14-0x20 reset value: 0x0000 0000 10.13.7 adc watchdog higher thr eshold register (adc_htr) address offset: 0x24 reset value: 0x0000 0fff 10.13.8 adc watchdog lower thr eshold register (adc_ltr) address offset: 0x28 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 reserved joffsetx[11:0] rw rw rw rw rw rw rw rw rw rw rw rw bits 31:12 reserved, must be kept cleared. bits 11:0 joffsetx[11:0]: data offset for injected channel x these bits are written by software to define the offset to be subtracted from the raw converted data when converting injected channels. the conversion result can be read from in the adc_jdrx registers. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 reserved ht[11:0] rw rw rw rw rw rw rw rw rw rw rw rw bits 31:12 reserved, must be kept cleared. bits 11:0 ht[11:0]: analog watchdog higher threshold these bits are written by software to define the higher threshold for the analog watchdog. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 reserved lt[11:0] rw rw rw rw rw rw rw rw rw rw rw rw bits 31:12 reserved, must be kept cleared. bits 11:0 lt[11:0]: analog watchdog lower threshold these bits are written by software to define the lower threshold for the analog watchdog. analog-to-digital converter (adc) RM0033 238/1317 doc id 15403 rev 3 10.13.9 adc regular sequence register 1 (adc_sqr1) address offset: 0x2c reset value: 0x0000 0000 10.13.10 adc regular sequence register 2 (adc_sqr2) address offset: 0x30 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved l[3:0] sq16[4:1] rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sq16_0 sq15[4:0] sq14[4:0] sq13[4:0] rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:24 reserved, must be kept cleared. bits 23:20 l[3:0]: regular channel sequence length these bits are written by software to define the total number of conversions in the regular channel conversion sequence. 0000: 1 conversion 0001: 2 conversions ... 1111: 16 conversions bits 19:15 sq16[4:0]: 16th conversion in regular sequence these bits are written by software with the c hannel number (0..18) assigned as the 16th in the conversion sequence. bits 14:10 sq15[4:0]: 15th conversion in regular sequence bits 9:5 sq14[4:0]: 14th conversion in regular sequence bits 4:0 sq13[4:0]: 13th conversion in regular sequence 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sq12[4:0] sq11[4:0] sq10[4:1] rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sq10_0 sq9[4:0] sq8[4:0] sq7[4:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:30 reserved, must be kept cleared. bits 29:26 sq12[4:0]: 12th conversion in regular sequence these bits are written by software with the channel number (0..18 ) assigned as the 12th in the sequence to be converted. bits 24:20 sq11[4:0]: 11th conversion in regular sequence bits 19:15 sq10[4:0]: 10th conversion in regular sequence bits 14:10 sq9[4:0]: 9th conversion in regular sequence RM0033 analog-to-digital converter (adc) doc id 15403 rev 3 239/1317 10.13.11 adc regular sequence register 3 (adc_sqr3) address offset: 0x34 reset value: 0x0000 0000 10.13.12 adc injected se quence register (adc_jsqr) address offset: 0x38 reset value: 0x0000 0000 bits 9:5 sq8[4:0]: 8th conversion in regular sequence bits 4:0 sq7[4:0]: 7th conversion in regular sequence 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved sq6[4:0] sq5[4:0] sq4[4:1] rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 sq4_0 sq3[4:0] sq2[4:0] sq1[4:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:30 reserved, must be kept cleared. bits 29:25 sq6[4:0]: 6th conversion in regular sequence these bits are written by software with the cha nnel number (0..18) assigned as the 6th in the sequence to be converted. bits 24:20 sq5[4:0]: 5th conversion in regular sequence bits 19:15 sq4[4:0]: 4th conversion in regular sequence bits 14:10 sq3[4:0]: 3rd conversion in regular sequence bits 9:5 sq2[4:0]: 2nd conversion in regular sequence bits 4:0 sq1[4:0]: 1st conversion in regular sequence 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved jl[1:0] jsq4[4:1] rw rw rw rw rw rw 1514131211109876543210 jsq4[0] jsq3[4:0] jsq2[4:0] jsq1[4:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:22 reserved, must be kept cleared. bits 21:20 jl[1:0]: injected sequence length these bits are written by software to define th e total number of conversions in the injected channel conversion sequence. 00: 1 conversion 01: 2 conversions 10: 3 conversions 11: 4 conversions analog-to-digital converter (adc) RM0033 240/1317 doc id 15403 rev 3 note: when jl[1:0]=3 (4 injected conversions in the sequencer), the adc converts the channels in the following order: jsq1[4:0], jsq2[4:0], jsq3[4:0], and jsq4[4:0]. when jl=2 (3 injected conversions in the sequencer), the adc converts the channels in the following order: jsq2[4:0], jsq3[4:0], and jsq4[4:0]. when jl=1 (2 injected conversions in the sequencer), the adc converts the channels in starting from jsq3[4:0], and then jsq4[4:0]. when jl=0 (1 injected conversion in the sequencer), the adc converts only jsq4[4:0] channel. 10.13.13 adc injected data regi ster x (adc_jdrx) (x= 1..4) address offset: 0x3c - 0x48 reset value: 0x0000 0000 10.13.14 adc regular dat a register (adc_dr) address offset: 0x4c reset value: 0x0000 0000 bits 19:15 jsq4[4:0]: 4th conversion in injected sequence (when jl[1:0]=3, see note below) these bits are written by software with the cha nnel number (0..18) assigned as the 4th in the sequence to be converted. bits 14:10 jsq3[4:0]: 3rd conversion in injected sequence (when jl[1:0]=3, see note below) bits 9:5 jsq2[4:0]: 2nd conversion in injected sequence (when jl[1:0]=3, see note below) bits 4:0 jsq1[4:0]: 1st conversion in injected sequence (when jl[1:0]=3, see note below) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 jdata[15:0] rrrrrr r r r r rrrrrr bits 31:16 reserved, must be kept cleared. bits 15:0 jdata[15:0]: injected data these bits are read-only. they contain the conv ersion result from injected channel x. the data are left -or right-aligned as shown in figure 32 and figure 33 . 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 data[15:0] rrrrrr r r r r r r r r r r RM0033 analog-to-digital converter (adc) doc id 15403 rev 3 241/1317 bits 31:16 reserved. bits 15:0 data[15:0]: regular data these bits are read-only. they contain the co nversion result from the regular channels. the data are left- or right-aligned as shown in figure 32 and figure 33 . analog-to-digital converter (adc) RM0033 242/1317 doc id 15403 rev 3 10.13.15 adc common status register (adc_csr) address offset: 0x00 (this offset address is relative to adc1 base address + 0x300) reset value: 0x0000 0000 this register provides an image of the status bits of the different adcs. nevertheless it is read-only and does not allow to clear the different status bits. instead each status bit must be cleared by writing it to 0 in the corresponding adc_sr register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved ovr3 strt3 jstrt3 jeoc 3 eoc3 awd3 adc3 rrrrrr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ovr2 strt2 jstrt 2 jeoc2 eoc2 awd2 reserved ovr1 strt1 jstrt1 jeoc 1 eoc1 awd1 adc2 adc1 rrrrrr r r r r rr bits 31:22 reserved, must be kept cleared. bit 21 ovr3: overrun flag of adc3 this bit is a copy of the ovr bit in the adc3_sr register. bit 20 strt3: regular channel start flag of adc3 this bit is a copy of the strt bit in the adc3_sr register. bit 19 jstrt3: injected channel start flag of adc3 this bit is a copy of the jstrt bit in the adc3_sr register. bit 18 jeoc3: injected channel end of conversion of adc3 this bit is a copy of the jeoc bit in the adc3_sr register. bit 17 eoc3: end of conversion of adc3 this bit is a copy of the eoc bit in the adc3_sr register. bit 16 awd3: analog watchdog flag of adc3 this bit is a copy of the awd bit in the adc3_sr register. bits 15:14 reserved, must be kept cleared. bit 13 ovr2: overrun flag of adc2 this bit is a copy of the ovr bit in the adc2_sr register. bit 12 strt2: regular channel start flag of adc2 this bit is a copy of the strt bit in the adc2_sr register. bit 11 jstrt2: injected channel start flag of adc2 this bit is a copy of the jstrt bit in the adc2_sr register. bit 10 jeoc2: injected channel end of conversion of adc2 this bit is a copy of the jeoc bit in the adc2_sr register. bit 9 eoc2: end of conversion of adc2 this bit is a copy of the eoc bit in the adc2_sr register. bit 8 awd2: analog watchdog flag of adc2 this bit is a copy of the awd bit in the adc2_sr register. RM0033 analog-to-digital converter (adc) doc id 15403 rev 3 243/1317 10.13.16 adc common contro l register (adc_ccr) address offset: 0x04 (this offset address is relative to adc1 base address + 0x300) reset value: 0x0000 0000 bits 7:6 reserved, must be kept cleared. bit 5 ovr1: overrun flag of adc1 this bit is a copy of the ovr bit in the adc1_sr register. bit 4 strt1: regular channel start flag of adc1 this bit is a copy of the strt bit in the adc1_sr register. bit 3 jstrt1: injected channel start flag of adc1 this bit is a copy of the jstrt bit in the adc1_sr register. bit 2 jeoc1: injected channel end of conversion of adc1 this bit is a copy of the jeoc bit in the adc1_sr register. bit 1 eoc1: end of conversion of adc1 this bit is a copy of the eoc bit in the adc1_sr register. bit 0 awd1: analog watchdog flag of adc1 this bit is a copy of the awd bit in the adc1_sr register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved tsvrefe vbate reserved adcpre rw rw rw rw 15141312111098 7 654321 0 dma[1:0] dds res. delay[3:0] reserved multi[4:0] rw rw rw rw rw rw rw rw rw rw rw rw bits 31:24 reserved, must be kept cleared. bit 23 tsvrefe: temperature sensor and v refint enable this bit is set and cleared by software to enable/disable the temper ature sensor and the v refint channel. 0: temperature sensor and v refint channel disabled 1: temperature sensor and v refint channel enabled bit 22 vbate: v bat enable this bit is set and cleared by software to enable/disable the v bat channel. 0: v bat channel disabled 1: v bat channel enabled bits 21:18 reserved, must be kept cleared. bits 17:16 adcpre: adc prescaler set and cleared by software to select the frequency of the clock to the adc. the clock is common for all the adcs. note: 00: pclk2 divided by 2 01: pclk2 divided by 4 10: pclk2 divided by 6 11: pclk2 divided by 8 analog-to-digital converter (adc) RM0033 244/1317 doc id 15403 rev 3 bits 15:14 dma: direct memory access mode for multi adc mode this bit-field is set and cleared by software. refer to the dma controller section for more details. 00: dma mode disabled 01: dma mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3) 10: dma mode 2 enabled (2 / 3 half-wor ds by pairs - 2&1 then 1&3 then 3&2) 11: dma mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) bit 13 dds: dma disable selection (for multi-adc mode) this bit is set and cleared by software. 0: no new dma request is issued after the last transfer (as configured in the dma controller). dma bits are not cleared by hardware, however they must have been cleared and set to the wanted mode by software before new dma requests can be generated. 1: dma requests are issued as long as da ta are converted and dma = 01, 10 or 11. bit 12 reserved, must be kept cleared. bit 11:8 delay: delay between 2 sampling phases set and cleared by software. these bits are used in dual or triple interleaved modes. 0000: 5 * t adcclk 0001: 6 * t adcclk 0010: 7 * t adcclk ... 1111: 20 * t adcclk bits 7:5 reserved, must be kept cleared. bits 4:0 multi[4:0]: multi adc mode selection these bits are written by software to select the operating mode. ? all the adcs independent: 00000: independent mode ? 00001 to 01001: dual mode, adc1 and adc2 working together, adc3 is independent 00001: combined regular simultaneous + injected simultaneous mode 00010: combined regular simultaneous + alternate trigger mode 00011: reserved 00101: injected simultaneous mode only 00110: regular simultaneous mode only 00111: interleaved mode only 01001: alternate trigger mode only ? 10001 to 11001: triple mode: adc1, 2 and 3 working together 10001: combined regular simultaneous + injected simultaneous mode 10010: combined regular simultaneous + alternate trigger mode 10011: reserved 10101: injected simultaneous mode only 10110: regular simultaneous mode only 10111: interleaved mode only 11001: alternate trigger mode only all other combinations are reserved and must not be programmed note: in multi mode, a change of channel conf iguration generates an abort that can cause a loss of synchronization. it is recommended to disable the multi adc mode before any configuration change. RM0033 analog-to-digital converter (adc) doc id 15403 rev 3 245/1317 10.13.17 adc common regular data register for dual and triple modes (adc_cdr) address offset: 0x08 (this offset address is relative to adc1 base address + 0x300) reset value: 0x0000 0000 10.13.18 adc register map the following table summarizes the adc registers. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 data2[15:0] rrrrrr r r r r rrrrrr 1514131211109876543210 data1[15:0] rrrrrr r r r r rrrrrr bits 31:16 data2[15:0]: 2nd data item of a pair of regular conversions ? in dual mode, these bits contain the regular data of adc2. refer to dual adc mode . ? in triple mode, these bits contain alternat ively the regular data of adc2, adc1 and adc3. refer to triple adc mode . bits 15:0 data1[15:0] : 1st data item of a pair of regular conversions ? in dual mode, these bits contain the regular data of adc1. refer to dual adc mode ? in triple mode, these bits contain alternat ively the regular data of adc1, adc3 and adc2. refer to triple adc mode . table 38. adc global register map offset register 0x000 - 0x04c adc1 0x050 - 0x0fc reserved 0x100 - 0x14c adc2 0x118 - 0x1fc reserved 0x200 - 0x24c adc3 0x250 - 0x2fc reserved 0x300 - 0x308 common registers analog-to-digital converter (adc) RM0033 246/1317 doc id 15403 rev 3 table 39. adc register map and reset values for each adc offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 adc_sr reserved ovr strt jstrt jeoc eoc awd reset value 000000 0x04 adc_cr1 reserved ovrie res[1:0] awden jawden reserved disc num [2:0] jdiscen discen jauto awd sgl scan jeocie awdie eocie awdch[4:0] reset value 00000 0000000000000000 0x08 adc_cr2 re se rv ed swstart exten[1:0] extsel [3:0] re se rv ed jswstart jexten[1:0] jextsel [3:0] reserved align eocs dds dma reserved cont adon reset value 0000000 0000000 00 0 00 0x0c adc_smpr1 sample time bits smpx_x reset value 00000000000000000000000000000000 0x10 adc_smpr2 sample time bits smpx_x reset value 00000000000000000000000000000000 0x14 adc_jofr1 reserved joffset1[11:0] reset value 000000000000 0x18 adc_jofr2 reserved joffset2[11:0] reset value 000000000000 0x1c adc_jofr3 reserved joffset3[11:0] reset value 000000000000 0x20 adc_jofr4 reserved joffset4[11:0] reset value 000000000000 0x24 adc_htr reserved ht[11:0] reset value 111111111111 0x28 adc_ltr reserved lt[11:0] reset value 000000000000 0x2c adc_sqr1 reserved l[3:0] regular channel sequence sqx_x bits reset value 000000000000000000000000 0x30 adc_sqr2 reserved regular channel sequence sqx_x bits reset value 000000000000000000000000000000 0x34 adc_sqr3 reserved regular channel sequence sqx_x bits reset value 000000000000000000000000000000 0x38 adc_jsqr reserved jl[1:0] injected channel sequence jsqx_x bits reset value 0000000000000000000000 0x3c adc_jdr1 reserved jdata[15:0] reset value 0000000000000000 0x40 adc_jdr2 reserved jdata[15:0] reset value 0000000000000000 0x44 adc_jdr3 reserved jdata[15:0] reset value 0000000000000000 0x48 adc_jdr4 reserved jdata[15:0] reset value 0000000000000000 0x4c adc_dr reserved regular data[15:0] reset value 0000000000000000 RM0033 analog-to-digital converter (adc) doc id 15403 rev 3 247/1317 refer to table 1 on page 50 for the register boundary addresses. table 40. adc register map and reset values (common adc registers) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 adc_csr reserved ovr strt jstrt jeoc eoc awd reser ved ovr strt jstrt jeoc eoc awd reser ved ovr strt jstrt jeoc eoc awd reset value 000000 000000 000000 adc3 adc2 adc1 0x04 adc_ccr reserved tsvrefe vbate reserved adcpre[1:0] dma[1:0] dds re se rv ed delay [3:0] reserved multi [4:0] reset value 00 00000 0000 00000 0x08 adc_cdr regular data2[15:0] regular data1[15:0] reset value 00000000000000000000000000000000 digital-to-analog converter (dac) RM0033 248/1317 doc id 15403 rev 3 11 digital-to-analog converter (dac) 11.1 dac introduction the dac module is a 12-bit, voltage output digital-to-analog converter. the dac can be configured in 8- or 12-bit mode and may be used in conjunction with the dma controller. in 12-bit mode, the data could be left- or right-aligned. the dac has two output channels, each with its own converter. in dual dac channel mode, conversions could be done independently or simultaneously when both channels are grouped together for synchronous update operations. an input reference pin, v ref+ (shared with adc) is available for better resolution. 11.2 dac main features two dac converters: one output channel each left or right data alignment in 12-bit mode synchronized update capability noise-wave generation triangular-wave generation dual dac channel for independent or simultaneous conversions dma capability for each channel dma underrun error detection external triggers for conversion input voltage reference, v ref+ figure 48 shows the block diagram of a dac channel and ta bl e 4 1 gives the pin description. RM0033 digital-to-analog converter (dac) doc id 15403 rev 3 249/1317 figure 48. dac channel block diagram note: once the dac channelx is enabled, the corresponding gpio pin (pa4 or pa5) is automatically connected to the analog converter output (dac_outx). in order to avoid parasitic consumption, the pa4 or pa5 pin should first be configured to analog (ain). table 41. dac pins name signal type remarks v ref+ input, analog reference positive the higher/positive reference voltage for the dac, 1.8 v v ref+ v dda v dda input, analog supply analog power supply v ssa input, analog supply ground ground for analog power supply dac_outx analog output signal dac channelx analog output v dda v ssa v ref+ dac_ ou tx control logicx dhrx 12-bit 12-bit lfsrx trianglex dm a req ue stx tselx[2:0] bits tim4_t rgo tim5_t rgo tim6_t rgo tim7_t rgo tim2_t rgo tim8_t rgo exti_9 dmaenx tenx mampx[3:0] bits wavenx[1:0] bits swtrigx dorx digital-to-analog converterx 12-bit dac control register ai14708b trigger selectorx digital-to-analog converter (dac) RM0033 250/1317 doc id 15403 rev 3 11.3 dac functional description 11.3.1 dac channel enable each dac channel can be powered on by setting its corresponding enx bit in the dac_cr register. the dac channel is then enabled after a startup time t wakeup . note: the enx bit enables the analog dac channelx macrocell only. the dac channelx digital interface is enabled even if the enx bit is reset. 11.3.2 dac output buffer enable the dac integrates two output buffers that can be used to reduce the output impedance, and to drive external loads directly without having to add an external operational amplifier. each dac channel output buffer can be enabled and disabled using the corresponding boffx bit in the dac_cr register. 11.3.3 dac data format depending on the selected configuration mode, the data have to be written into the specified register as described below: single dac channelx, ther e are three possibilities: ? 8-bit right alignment: the software has to load data into the dac_dhr8rx [7:0] bits (stored into the dhrx[11:4] bits) ? 12-bit left alignment: the software has to load data into the dac_dhr12lx [15:4] bits (stored into the dhrx[11:0] bits) ? 12-bit right alignment: the software has to load data into the dac_dhr12rx [11:0] bits (stored into the dhrx[11:0] bits) depending on the loaded dac_dhryyyx register, the data written by the user is shifted and stored into the corresponding dhrx (data holding registerx, which are internal non- memory-mapped registers). the dhrx register is then loaded into the dorx register either automatically, by software trigger or by an external event trigger. figure 49. data registers in single dac channel mode 31 24 15 7 0 8-bit right aligned 12-bit left aligned 12-bit right aligned ai14710 RM0033 digital-to-analog converter (dac) doc id 15403 rev 3 251/1317 dual dac channels, ther e are three possibilities: ? 8-bit right alignment: data for dac cha nnel1 to be loaded into the dac_dhr8rd [7:0] bits (stored into the dhr1[11:4] bits) and data for dac channel2 to be loaded into the dac_dhr8rd [15:8] bits (stored into the dhr2[11:4] bits) ? 12-bit left alignment: data for dac cha nnel1 to be loaded in to the dac_dhr12ld [15:4] bits (stored into the dhr1[11:0] bits) and data for dac channel2 to be loaded into the dac_dhr12ld [31:20] bits (stored into the dhr2[11:0] bits) ? 12-bit right alignment: data for dac channel1 to be loaded into the dac_dhr12rd [11:0] bits (stored into the dhr1[11:0] bits) and data for dac channel2 to be loaded into the dac_dhr12ld [27:16] bits (stored into the dhr2[11:0] bits) depending on the loaded dac_dhryyyd register, the data written by the user is shifted and stored into dhr1 and dhr2 (data holding registers, which are internal non-memory- mapped registers). the dhr1 and dhr2 registers are then loaded into the dor1 and dor2 registers, respectively, either automatically, by software trigger or by an external event trigger. figure 50. data registers in dual dac channel mode 11.3.4 dac conversion the dac_dorx cannot be written directly and any data transfer to the dac channelx must be performed by loading the dac_dhrx regi ster (write to dac_dhr8rx, dac_dhr12lx, dac_dhr12rx, dac_dhr8rd, dac_dhr12ld or dac_dhr12ld). data stored in the dac_dhrx register are automatically transferred to the dac_dorx register after one apb1 clock cycle, if no hardw are trigger is selected (tenx bit in dac_cr register is reset). however, when a hardware trigger is selected (tenx bit in dac_cr register is set) and a trigger occurs, the tran sfer is performed three apb1 clock cycles later. when dac_dorx is loaded with the dac_d hrx contents, the analog output voltage becomes available after a time t settling that depends on the power supply voltage and the analog output load. figure 51. timing diagram for conversion with trigger disabled ten = 0 31 24 15 7 0 8-bit right aligned 12-bit left aligned 12-bit right aligned ai14709 apb1_clk 0x1ac 0x1ac t settling dhr dor output voltage available on dac_out pin ai14711b digital-to-analog converter (dac) RM0033 252/1317 doc id 15403 rev 3 11.3.5 dac output voltage digital inputs are converted to output voltages on a linear conversion between 0 and v ref+ . the analog output voltages on each dac channel pin are determined by the following equation: 11.3.6 dac trigger selection if the tenx control bit is set, conversion can t hen be triggered by an external event (timer counter, external interrupt line). the tselx[2:0] control bits determine which out of 8 possi- ble events will trigger conversion as shown in table 42 . each time a dac interface detects a rising edge on the selected timer trgo output, or on the selected external interrupt line 9, the last data stored into the dac_dhrx register are transferred into the dac_dorx register. t he dac_dorx register is updated three apb1 cycles after the trigger occurs. if the software trigger is selected, the conversion starts once the swtrig bit is set. swtrig is reset by hardware once the dac_dorx register has been loaded with the dac_dhrx register contents. note: 1 tselx[2:0] bit cannot be changed when the enx bit is set. 2 when software trigger is selected, the transfer from the dac_dhrx register to the dac_dorx register takes only one apb1 clock cycle. 11.3.7 dma request each dac channel has a dma capability. tw o dma channels are used to service dac channel dma requests. a dac dma request is generated when an external trigger (but not a software trigger) occurs while the dmaenx bit is set. the value of the dac_dhrx register is then transferred into the dac_dorx register. in dual mode, if both dmaenx bits are set, two dma requests are generated. if only one dma request is needed, you should set only the corresponding dmaenx bit. in this way, the application can manage both dac channels in dual mode by using one dma request and a unique dma channel. dacoutput v ref dor 4095 ------------- - = table 42. external triggers source type tsel[2:0] timer 6 trgo event internal signal from on-chip timers 000 timer 8 trgo event 001 timer 7 trgo event 010 timer 5 trgo event 011 timer 2 trgo event 100 timer 4 trgo event 101 exti line9 external pin 110 swtrig software control bit 111 RM0033 digital-to-analog converter (dac) doc id 15403 rev 3 253/1317 dma underrun the dac dma request is not queued so that if a second external trigger arrives before the acknowledgement for the first external trigger is received (first request), then no new request is issued and the dma channelx underrun flag dmaudrx in the dac_sr register is set, reporting the error condition. dma data transfers are then disabled and no further dma request is treated. the dac channelx continues to convert old data. the software should clear the dmaudrx flag by writing ?1?, clear the dmaen bit of the used dma stream and re-initialize both dma and dac channelx to restart the transfer correctly. the software should modify the dac trigger conversion frequency or lighten the dma workload to avoid a new dma underrun. finally, the dac conversion could be resumed by enabling both dma data transfer and conversion trigger. for each dac channlex, an interrupt is also generated if its corres ponding dmaudriex bit in the dac_cr register is enabled. 11.3.8 noise generation in order to generate a variable-amplitude pseudonoise, an lfsr (linear feedback shift register) is available. dac noise generation is selected by setting wavex[1:0] to ?01?. the preloaded value in lfsr is 0xaaa. this regist er is updated three apb1 clock cycles after each trigger event, following a specific calculation algorithm. figure 52. dac lfsr register calculation algorithm the lfsr value, that may be masked partially or totally by means of the mampx[3:0] bits in the dac_cr register, is added up to the dac_dhrx contents without overflow and this value is then stored into the dac_dorx register. if lfsr is 0x0000, a ?1 is inject ed into it (ant ilock-up mechanism). it is possible to reset lfsr wave generation by resetting the wavex[1:0] bits. 11 10 9 8 7 6 5 4 3 2 1 0 12 nor x 12 x 0 x x 4 x 6 xor ai14713b digital-to-analog converter (dac) RM0033 254/1317 doc id 15403 rev 3 figu re 53 . d a c con v e r s i on (sw trig g e r ena b le d) wit h lfsr wa ve g e ne rat i o n not e : t h e d a c tr ig ger m u st be ena b l e d f o r n o ise gen er a t i on b y set t i ng t he tenx b i t in t h e d a c_ cr re gi s t e r . 11.3.9 t r iangle-wa ve g eneration i t is po ssib le t o ad d a small- amp litu d e t r ian g u l ar w a v e f o r m on a dc or slo wly v a r y ing sign al. d a c t r iang le- w a v e gen er a t io n is sele ct e d b y se t t in g w a vex[1 : 0 ] t o ? 10? . t he am plit ude is con f ig ur ed th ro ugh th e m a m p x[ 3: 0] b i ts in th e d a c_cr r egist er . an int e r n a l tr iang le cou n t e r is inc r emented three apb 1 cloc k cycles after eac h tr igger e v ent. the v a lue of t h is count e r is th en a d d e d to th e d a c _ d hrx re gis te r w i th ou t o v er flo w an d th e su m is s to r e d int o the d a c_ do rx re gist er . th e t r iang le coun te r is in crem ent ed as lo ng a s it is less t h a n t he ma xim u m amp lit ude d e f i ne d b y th e mampx[ 3: 0] b i ts . on ce th e co nf igu r e d amp litu d e is re a c h ed, th e coun te r is d e cre m en t ed do wn t o 0, th en incr eme n t e d a gain a n d so on . i t is possib l e to r e set t r iang le w a v e gen er a t ion b y r e set t in g t he w a vex[ 1: 0] bit s . figu re 54 . d a c trian g le wa ve g e ne rat i on apb1_clk 0x00 0xaaa dhr dor ai14714 0xd55 swtrig - ! - 0 x ; = m a x a m p l i t u d e $ ! # ? $ ( 2 x b a s e v a l u e $ ! # ? $ ( 2 x b a s e v a l u e ) n c r e m e n t a t i o n a i c $ e c r e m e n t a t i o n RM0033 digital-to-analog converter (dac) doc id 15403 rev 3 255/1317 figure 55. dac conversion (sw trigger enabled) with triangle wave generation note: 1 the dac trigger must be enabled for noise generation by setting the tenx bit in the dac_cr register. 2 the mampx[3:0] bits must be configured before enabling the dac, otherwise they cannot be changed. 11.4 dual dac channel conversion to efficiently use the bus bandwidth in applications that require the two dac channels at the same time, three dual registers are implemented: dhr8rd, dhr12rd and dhr12ld. a unique register access is then required to drive both dac channels at the same time. eleven possible conversion modes are possible using the two dac channels and these dual registers. all the conversion modes can nevertheless be obtained using separate dhrx registers if needed. all modes are described in the paragraphs below. 11.4.1 independent trigger wi thout wave generation to configure the dac in this conversion mode, the following sequence is required: set the two dac channel trigger enable bits ten1 and ten2 configure different trigger sources by setting different values in the tsel1[2:0] and tsel2[2:0] bits load the dual dac channel data into the desired dhr register (dac_dhr12rd, dac_dhr12ld or dac_dhr8rd) when a dac channel1 trigger arrives, the dhr1 register is transf erred into dac_dor1 (three apb1 clock cycles later). when a dac channel2 trigger arrives, the dhr2 register is transf erred into dac_dor2 (three apb1 clock cycles later). apb1_clk 0xabe 0xabe dhr dor ai14714 0xabf swtrig 0xac0 digital-to-analog converter (dac) RM0033 256/1317 doc id 15403 rev 3 11.4.2 independent trigger with single lfsr generation to configure the dac in this conversion mode, the following sequence is required: set the two dac channel trigger enable bits ten1 and ten2 configure different trigger sources by setting different values in the tsel1[2:0] and tsel2[2:0] bits configure the two dac channel wavex[1:0] bits as ?01? and the same lfsr mask value in the mampx[3:0] bits load the dual dac channel data into th e desired dhr register (dhr12rd, dhr12ld or dhr8rd) when a dac channel1 trigger arrives, the lfsr1 counter, with the same mask, is added to the dhr1 register and the sum is transferred into dac_dor1 (three apb1 clock cycles later). then the lfsr1 counter is updated. when a dac channel2 trigger arrives, the lfsr2 counter, with the same mask, is added to the dhr2 register and the sum is transferred into dac_dor2 (three apb1 clock cycles later). then the lfsr2 counter is updated. 11.4.3 independent trigger with different lfsr generation to configure the dac in this conversion mode, the following sequence is required: set the two dac channel trigger enable bits ten1 and ten2 configure different trigger sources by setting different values in the tsel1[2:0] and tsel2[2:0] bits configure the two dac channel wavex[1:0] bits as ?01? and set different lfsr masks values in the mamp1[3:0] and mamp2[3:0] bits load the dual dac channel data into the desired dhr register (dac_dhr12rd, dac_dhr12ld or dac_dhr8rd) when a dac channel1 trigger arrives, the lfsr1 counter, with the mask configured by mamp1[3:0], is added to the dhr1 register and the sum is transferred into dac_dor1 (three apb1 clock cycles later). then the lfsr1 counter is updated. when a dac channel2 trigger arrives, the lfsr2 counter, with the mask configured by mamp2[3:0], is added to the dhr2 register and the sum is transferred into dac_dor2 (three apb1 clock cycles later). then the lfsr2 counter is updated. 11.4.4 independent trigger with single triangle generation to configure the dac in this conversion mode, the following sequence is required: set the two dac channel trigger enable bits ten1 and ten2 configure different trigger sources by setting different values in the tsel1[2:0] and tsel2[2:0] bits configure the two dac channel wavex[1:0] bits as ?1x? and the same maximum amplitude value in the mampx[3:0] bits load the dual dac channel data into the desired dhr register (dac_dhr12rd, dac_dhr12ld or dac_dhr8rd) when a dac channel1 trigger arrives, the dac channel1 triangle counter, with the same triangle amplitude, is added to the dhr1 register and the sum is transferred into RM0033 digital-to-analog converter (dac) doc id 15403 rev 3 257/1317 dac_dor1 (three apb1 clock cycles later). th e dac channel1 triangle counter is then updated. when a dac channel2 trigger arrives, the dac channel2 triangle counter, with the same triangle amplitude, is added to the dhr2 register and the sum is transferred into dac_dor2 (three apb1 clock cycles later). th e dac channel2 triangle counter is then updated. 11.4.5 independent trigger with different triangle generation to configure the dac in this conversion mode, the following sequence is required: set the two dac channel trigger enable bits ten1 and ten2 configure different trigger sources by setting different values in the tsel1[2:0] and tsel2[2:0] bits configure the two dac channel wavex[1:0] bits as ?1x? and set different maximum amplitude values in the mamp1[3:0] and mamp2[3:0] bits load the dual dac channel data into the desired dhr register (dac_dhr12rd, dac_dhr12ld or dac_dhr8rd) when a dac channel1 trigger arrives, the dac channel1 triangle counter, with a triangle amplitude configured by mamp1[3:0], is added to the dhr1 register and the sum is transferred into dac_dor1 (three apb1 cloc k cycles later). the dac channel1 triangle counter is then updated. when a dac channel2 trigger arrives, the dac channel2 triangle counter, with a triangle amplitude configured by mamp2[3:0], is added to the dhr2 register and the sum is transferred into dac_dor2 (three apb1 cloc k cycles later). the dac channel2 triangle counter is then updated. 11.4.6 simultaneous software start to configure the dac in this conversion mode, the following sequence is required: load the dual dac channel data to the desired dhr register (dac_dhr12rd, dac_dhr12ld or dac_dhr8rd) in this configuration, one apb1 clock cycle later, the dhr1 and dhr2 registers are transferred into dac_dor1 and dac_dor2, respectively. 11.4.7 simultaneous trigger without wave generation to configure the dac in this conversion mode, the following sequence is required: set the two dac channel trigger enable bits ten1 and ten2 configure the same trigger source for both dac channels by setting the same value in the tsel1[2:0] and tsel2[2:0] bits load the dual dac channel data to the desired dhr register (dac_dhr12rd, dac_dhr12ld or dac_dhr8rd) when a trigger arrives, the dhr1 and dhr2 registers are transferred into dac_dor1 and dac_dor2, respectively (after three apb1 clock cycles). digital-to-analog converter (dac) RM0033 258/1317 doc id 15403 rev 3 11.4.8 simultaneous trigger wi th single lf sr generation to configure the dac in this conversion mode, the following sequence is required: set the two dac channel trigger enable bits ten1 and ten2 configure the same trigger source for both dac channels by setting the same value in the tsel1[2:0] and tsel2[2:0] bits configure the two dac channel wavex[1:0] bits as ?01? and the same lfsr mask value in the mampx[3:0] bits load the dual dac channel data to the desired dhr register (dhr12rd, dhr12ld or dhr8rd) when a trigger arrives, the lfsr1 counter, with the same mask, is added to the dhr1 register and the sum is tran sferred into dac_dor1 (three apb1 clock cycles later). the lfsr1 counter is then updated. at the same time, the lfsr2 counter, with the same mask, is added to the dhr2 register and the sum is transferred in to dac_dor2 (three apb1 clock cycles later). the lfsr2 counter is then updated. 11.4.9 simultaneous trigger with different lf sr generation to configure the dac in this conversion mode, the following sequence is required: set the two dac channel trigger enable bits ten1 and ten2 configure the same trigger source for both dac channels by setting the same value in the tsel1[2:0] and tsel2[2:0] bits configure the two dac channel wavex[1:0] bits as ?01? and set different lfsr mask values using the mamp1[3:0] and mamp2[3:0] bits load the dual dac channel data into the desired dhr register (dac_dhr12rd, dac_dhr12ld or dac_dhr8rd) when a trigger arrives, the lfsr1 counter, with the mask configured by mamp1[3:0], is added to the dhr1 register and the sum is transferred into dac_dor1 (three apb1 clock cycles later). the lfsr1 counter is then updated. at the same time, the lfsr2 counter, with the mask configured by mamp2[3:0], is added to the dhr2 register and the sum is transferred into dac_dor2 (three apb1 clock cycles later). the lfsr2 counter is then updated. 11.4.10 simultaneous trigger with single triangle generation to configure the dac in this conversion mode, the following sequence is required: set the two dac channel trigger enable bits ten1 and ten2 configure the same trigger source for both dac channels by setting the same value in the tsel1[2:0] and tsel2[2:0] bits configure the two dac channel wavex[1:0] bits as ?1x? and the same maximum amplitude value using the mampx[3:0] bits load the dual dac channel data into the desired dhr register (dac_dhr12rd, dac_dhr12ld or dac_dhr8rd) when a trigger arrives, the dac channel1 triang le counter, with the same triangle amplitude, is added to the dhr1 register and the sum is transferred in to dac_dor1 (three apb1 clock cycles later). the dac channel1 triangle counter is then updated. at the same time, the dac channel2 triangle counter, with the same triangle amplitude, is RM0033 digital-to-analog converter (dac) doc id 15403 rev 3 259/1317 added to the dhr2 register and the sum is transferred into dac_dor2 (three apb1 clock cycles later). the dac channel2 triangle counter is then updated. 11.4.11 simultaneous trigger with different triang le generation to configure the dac in this conversion mode, the following sequence is required: set the two dac channel trigger enable bits ten1 and ten2 configure the same trigger source for both dac channels by setting the same value in the tsel1[2:0] and tsel2[2:0] bits configure the two dac channel wavex[1:0] bits as ?1x? and set different maximum amplitude values in the mamp1[3:0] and mamp2[3:0] bits load the dual dac channel data into the desired dhr register (dac_dhr12rd, dac_dhr12ld or dac_dhr8rd) when a trigger arrives, the dac channel1 triangle counter, with a triangle amplitude configured by mamp1[3:0], is added to the dhr1 register and the sum is transferred into dac_dor1 (three apb1 clock cycles later). then the dac cha nnel1 triangle counter is updated. at the same time, the dac channel2 triangle counter, with a triangle amplitude configured by mamp2[3:0], is added to the dhr2 register and the sum is transferred into dac_dor2 (three apb1 clock cycles later). then the dac channel2 triangle counter is updated. 11.5 dac registers refer to section 1.1 on page 46 for a list of abbreviations used in register descriptions. 11.5.1 dac control register (dac_cr) address offset: 0x00 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved dmau drie2 dma en2 mamp2[3:0] wave2[1:0] tsel2[2:0] ten2 boff2 en2 rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 reserved dmau drie1 dma en1 mamp1[3:0] wave1[1:0] tsel1[2:0] ten1 boff1 en1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:30 reserved. bits 29 dmaudrie2 : dac channel2 dma underrun interrupt enable this bit is set and cleared by software. 0: dac channel2 dma underrun interrupt disabled 1: dac channel2 dma underrun interrupt enabled bit 28 dmaen2 : dac channel2 dma enable this bit is set and cleared by software. 0: dac channel2 dma mode disabled 1: dac channel2 dma mode enabled digital-to-analog converter (dac) RM0033 260/1317 doc id 15403 rev 3 bit 27:24 mamp2[3:0] : dac channel2 mask/amplitude selector these bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. 0000: unmask bit0 of lfsr/ triangle amplitude equal to 1 0001: unmask bits[1:0] of lfsr/ triangle amplitude equal to 3 0010: unmask bits[2:0] of lfsr/ triangle amplitude equal to 7 0011: unmask bits[3:0] of lfsr/ triangle amplitude equal to 15 0100: unmask bits[4:0] of lfsr/ triangle amplitude equal to 31 0101: unmask bits[5:0] of lfsr/ triangle amplitude equal to 63 0110: unmask bits[6:0] of lfsr/ triangle amplitude equal to 127 0111: unmask bits[7:0] of lfsr/ triangle amplitude equal to 255 1000: unmask bits[8:0] of lfsr/ triangle amplitude equal to 511 1001: unmask bits[9:0] of lfsr/ triangle amplitude equal to 1023 1010: unmask bits[10:0] of lfsr/ triangle amplitude equal to 2047 1011: unmask bits[11:0] of lfsr / triangle amplitude equal to 4095 bit 23:22 wave2[1:0] : dac channel2 noise/triangle wave generation enable these bits are set/reset by software. 00: wave generation disabled 01: noise wave generation enabled 1x: triangle wave generation enabled note: only used if bit ten2 = 1 (dac channel2 trigger enabled) bits 21:19 tsel2[2:0] : dac channel2 trigger selection these bits select the external event used to trigger dac channel2 000: timer 6 trgo event 001: timer 8 trgo event 010: timer 7 trgo event 011: timer 5 trgo event 100: timer 2 trgo event 101: timer 4 trgo event 110: external line9 111: software trigger note: only used if bit ten2 = 1 (dac channel2 trigger enabled). bit 18 ten2 : dac channel2 trigger enable this bit is set and cleared by software to enable/disable dac channel2 trigger 0: dac channel2 trigger disabled and data written into the dac_dhrx register are transferred one apb1 clock cycle la ter to the dac_ dor2 register 1: dac channel2 trigger enabled and data from the dac_dhrx register are transferred three apb1 clock cycles later to the dac_dor2 register note: when software trigger is selected, the transfer from the dac_dhrx reg ister to the dac_dor2 register takes only one apb1 clock cycle. bit 17 boff2 : dac channel2 output buffer disable this bit is set and cleared by software to enable/disable dac channel2 output buffer. 0: dac channel2 output buffer enabled 1: dac channel2 output buffer disabled bit 16 en2 : dac channel2 enable this bit is set and cleared by software to enable/disable dac channel2. 0: dac channel2 disabled 1: dac channel2 enabled bits 15:14 reserved. RM0033 digital-to-analog converter (dac) doc id 15403 rev 3 261/1317 bit 13 dmaudrie1 : dac channel1 dma underrun interrupt enable this bit is set and cleared by software. 0: dac channel1 dma underrun interrupt disabled 1: dac channel1 dma underrun interrupt enabled bit 12 dmaen1 : dac channel1 dma enable this bit is set and cleared by software. 0: dac channel1 dma mode disabled 1: dac channel1 dma mode enabled bits 11:8 mamp1[3:0] : dac channel1 mask/amplitude selector these bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. 0000: unmask bit0 of lfsr/ triangle amplitude equal to 1 0001: unmask bits[1:0] of lfsr/ triangle amplitude equal to 3 0010: unmask bits[2:0] of lfsr/ triangle amplitude equal to 7 0011: unmask bits[3:0] of lfsr/ triangle amplitude equal to 15 0100: unmask bits[4:0] of lfsr/ triangle amplitude equal to 31 0101: unmask bits[5:0] of lfsr/ triangle amplitude equal to 63 0110: unmask bits[6:0] of lfsr/ triangle amplitude equal to 127 0111: unmask bits[7:0] of lfsr/ triangle amplitude equal to 255 1000: unmask bits[8:0] of lfsr/ triangle amplitude equal to 511 1001: unmask bits[9:0] of lfsr/ triangle amplitude equal to 1023 1010: unmask bits[10:0] of lfsr/ triangle amplitude equal to 2047 1011: unmask bits[11:0] of lfsr / triangle amplitude equal to 4095 bits 7:6 wave1[1:0] : dac channel1 noise/triangle wave generation enable these bits are set and cleared by software. 00: wave generation disabled 01: noise wave generation enabled 1x: triangle wave generation enabled note: only used if bit ten1 = 1 (dac channel1 trigger enabled). bits 5:3 tsel1[2:0] : dac channel1 trigger selection these bits select the external event used to trigger dac channel1. 000: timer 6 trgo event 001: timer 8 trgo event 010: timer 7 trgo event 011: timer 5 trgo event 100: timer 2 trgo event 101: timer 4 trgo event 110: external line9 111: software trigger note: only used if bit ten1 = 1 (dac channel1 trigger enabled). digital-to-analog converter (dac) RM0033 262/1317 doc id 15403 rev 3 11.5.2 dac software trigge r register (dac_swtrigr) address offset: 0x04 reset value: 0x0000 0000 bit 2 ten1 : dac channel1 trigger enable this bit is set and cleared by software to enable/disable dac channel1 trigger. 0: dac channel1 trigger disabled and data written into the dac_dhrx register are transferred one apb1 clock cycle la ter to the dac_ dor1 register 1: dac channel1 trigger enabled and data from the dac_dhrx register are transferred three apb1 clock cycles later to the dac_dor1 register note: when software trigger is selected, the tr ansfer from the dac_dhrx register to the dac_dor1 register takes only one apb1 clock cycle. bit 1 boff1 : dac channel1 output buffer disable this bit is set and cleared by software to enable/disable dac channel1 output buffer. 0: dac channel1 output buffer enabled 1: dac channel1 output buffer disabled bit 0 en1 : dac channel1 enable this bit is set and cleared by software to enable/disable dac channel1. 0: dac channel1 disabled 1: dac channel1 enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved swtrig2 swtrig1 ww bits 31:2 reserved. bit 1 swtrig2 : dac channel2 software trigger this bit is set and cleared by software to enable/disable the software trigger. 0: software trigger disabled 1: software trigger enabled note: this bit is cleared by hardware (one apb1 clock cycle later) once the dac_dhr2 register value has been loaded into the dac_dor2 register. bit 0 swtrig1 : dac channel1 software trigger this bit is set and cleared by software to enable/disable the software trigger. 0: software trigger disabled 1: software trigger enabled note: this bit is cleared by hardware (one apb1 clock cycle later) once the dac_dhr1 register value has been loaded into the dac_dor1 register. RM0033 digital-to-analog converter (dac) doc id 15403 rev 3 263/1317 11.5.3 dac channel1 12-bit right-al igned data holding register (dac_dhr12r1) address offset: 0x08 reset value: 0x0000 0000 11.5.4 dac channel1 12-bit left aligned data holding register (dac_dhr12l1) address offset: 0x0c reset value: 0x0000 0000 11.5.5 dac channel1 8-bit right aligned data hol ding register (dac_dhr8r1) address offset: 0x10 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved dacc1dhr[11:0] rw rw rw rw rw rw rw rw rw rw rw rw bits 31:12 reserved. bit 11:0 dacc1dhr[11:0] : dac channel1 12-bit right-aligned data these bits are written by software whic h specifies 12-bit data for dac channel1. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dacc1dhr[11:0] reserved rw rw rw rw rw rw rw rw rw rw rw rw bits 31:16 reserved. bit 15:4 dacc1dhr[11:0] : dac channel1 12-bit left-aligned data these bits are written by software which specifies 12-bit data for dac channel1. bits 3:0 reserved. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved dacc1dhr[7:0] rw rw rw rw rw rw rw rw bits 31:8 reserved. bits 7:0 dacc1dhr[7:0] : dac channel1 8-bit right-aligned data these bits are written by software which specifies 8-bit data for dac channel1. digital-to-analog converter (dac) RM0033 264/1317 doc id 15403 rev 3 11.5.6 dac channel2 12-bit right al igned data holding register (dac_dhr12r2) address offset: 0x14 reset value: 0x0000 0000 11.5.7 dac channel2 12-bit left aligned data holding register (dac_dhr12l2) address offset: 0x18 reset value: 0x0000 0000 11.5.8 dac channel2 8-bit right- aligned data hol ding register (dac_dhr8r2) address offset: 0x1c reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved dacc2dhr[11:0] rw rw rw rw rw rw rw rw rw rw rw rw bits 31:12 reserved. bits 11:0 dacc2dhr[11:0] : dac channel2 12-bit right-aligned data these bits are written by software whic h specifies 12-bit data for dac channel2. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dacc2dhr[11:0] reserved rw rw rw rw rw rw rw rw rw rw rw rw bits 31:16 reserved. bits 15:4 dacc2dhr[11:0] : dac channel2 12-bit left-aligned data these bits are written by software which specify 12-bit data for dac channel2. bits 3:0 reserved. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved dacc2dhr[7:0] rw rw rw rw rw rw rw rw bits 31:8 reserved. bits 7:0 dacc2dhr[7:0] : dac channel2 8-bit right-aligned data these bits are written by software which specifies 8-bit data for dac channel2. RM0033 digital-to-analog converter (dac) doc id 15403 rev 3 265/1317 11.5.9 dual dac 12-bit righ t-aligned data holding register (dac_dhr12rd) address offset: 0x20 reset value: 0x0000 0000 11.5.10 dual dac 12-bit le ft aligned data holding register (dac_dhr12ld) address offset: 0x24 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved dacc2dhr[11:0] rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved dacc1dhr[11:0] rw rw rw rw rw rw rw rw rw rw rw rw bits 31:28 reserved. bits 27:16 dacc2dhr[11:0] : dac channel2 12-bit right-aligned data these bits are written by software whic h specifies 12-bit data for dac channel2. bits 15:12 reserved. bits 11:0 dacc1dhr[11:0] : dac channel1 12-bit right-aligned data these bits are written by software whic h specifies 12-bit data for dac channel1. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 dacc2dhr[11:0] reserved rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dacc1dhr[11:0] reserved rw rw rw rw rw rw rw rw rw rw rw rw bits 31:20 dacc2dhr[11:0] : dac channel2 12-bit left-aligned data these bits are written by software whic h specifies 12-bit data for dac channel2. bits 19:16 reserved. bits 15:4 dacc1dhr[11:0] : dac channel1 12-bit left-aligned data these bits are written by software whic h specifies 12-bit data for dac channel1. bits 3:0 reserved. digital-to-analog converter (dac) RM0033 266/1317 doc id 15403 rev 3 11.5.11 dual dac 8-bit right aligned data ho lding register (dac_dhr8rd) address offset: 0x28 reset value: 0x0000 0000 11.5.12 dac channel1 data out put register (dac_dor1) address offset: 0x2c reset value: 0x0000 0000 11.5.13 dac channel2 data out put register (dac_dor2) address offset: 0x30 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dacc2dhr[7:0] dacc1dhr[7:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:16 reserved. bits 15:8 dacc2dhr[7:0] : dac channel2 8-bit right-aligned data these bits are written by software which specifies 8-bit data for dac channel2. bits 7:0 dacc1dhr[7:0] : dac channel1 8-bit right-aligned data these bits are written by software which specifies 8-bit data for dac channel1. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved dacc1dor[11:0] rrrrrrrrrrrr bits 31:12 reserved. bit 11:0 dacc1dor[11:0] : dac channel1 data output these bits are read-only, they co ntain data output for dac channel1. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved dacc2dor[11:0] rrrrrrrrrrrr bits 31:12 reserved. bit 11:0 dacc2dor[11:0] : dac channel2 data output these bits are read-only, they contain data output for dac channel2. RM0033 digital-to-analog converter (dac) doc id 15403 rev 3 267/1317 11.5.14 dac status register (dac_sr) address offset: 0x34 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved dmaudr2 reserved rc_w1 1514 13 1211109876543210 reserved dmaudr1 reserved rc_w1 bits 31:30 reserved. bit 29 dmaudr2 : dac channel2 dma underrun flag this bit is set by hardware and cleared by software (by writing it to 1). 0: no dma underrun error condition occurred for dac channel2 1: dma underrun error condition occurred for dac channel2 (the currently selected trigger is driving dac channel2 conversion at a frequency higher than the dma service capability rate) bits 28:14 reserved. bit 13 dmaudr1 : dac channel1 dma underrun flag this bit is set by hardware and cleared by software (by writing it to 1). 0: no dma underrun error condition occurred for dac channel1 1: dma underrun error condition occurred for dac channel1 (the currently selected trigger is driving dac channel1 conversion at a frequency higher than the dma service capability rate) bits 12:0 reserved. digital-to-analog converter (dac) RM0033 268/1317 doc id 15403 rev 3 11.5.15 dac register map ta bl e 4 3 summarizes the dac registers. refer to table 1 on page 50 for the register boundary addresses. table 43. dac register map address offset register name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 dac_cr reserved dmaudrie2 dmaen2 mamp2[3:0] wave 2[2:0] tsel2[2:0] ten2 boff2 en2 reserved dmaudrie1 dmaen1 mamp1[3:0] wave 1[2:0] tsel1[2:0] ten1 boff1 en1 0x04 dac_swt rigr reserved swtrig2 swtrig1 0x08 dac_dhr1 2r1 reserved dacc1dhr[11:0] 0x0c dac_dhr1 2l1 reserved dacc1dhr[11:0] reserved 0x10 dac_dhr8 r1 reserved dacc1dhr[7:0] 0x14 dac_dhr1 2r2 reserved dacc2dhr[11:0] 0x18 dac_dhr1 2l2 reserved dacc2dhr[11:0] reserved 0x1c dac_dhr8 r2 reserved dacc2dhr[7:0] 0x20 dac_dhr1 2rd reserved dacc2dhr[11:0] reserved dacc1dhr[11:0] 0x24 dac_dhr1 2ld dacc2dhr[11:0] reserved dacc1dhr[11:0] reserved 0x28 dac_dhr8 rd reserved dacc2dhr[7:0] dacc1dhr[7:0] 0x2c dac_dor1 reserved dacc1dor[11:0] 0x30 dac_dor2 reserved dacc2dor[11:0] 0x34 dac_sr reserved dmaudr2 reserved dmaudr1 reserved RM0033 digital camera interface (dcmi) doc id 15403 rev 3 269/1317 12 digital camera interface (dcmi) 12.1 dcmi introduction the digital camera is a synchronous parallel interface able to receive a high-speed data flow from an external 8-, 10-, 12- or 14-bit cmos camera module. it supports different data formats: ycbcr4:2:2/rgb565 progressive video and compressed data (jpeg). this interface is for use with black & white cameras, x24 and x5 cameras, and it is assumed that all pre-processing like resizing is performed in the camera module. 12.2 dcmi main features 8-, 10-, 12- or 14-bit parallel interface embedded/external line and frame synchronization continuous or snapshot mode crop feature supports the following data formats: ? 8/10/12/14- bit progressive video: either monochrome or raw bayer ? ycbcr 4:2:2 progressive video ? rgb 565 progressive video ? compressed data: jpeg 12.3 dcmi pins ta bl e 4 4 shows the dcmi pins. 12.4 dcmi clocks the digital camera interface uses two clock domains pixclk and hclk. the signals generated with pixclk are sampled on the rising edge of hclk once they are stable. an enable signal is generated in the hclk domain, to indicate that data coming from the camera are stable and can be sampled. the maximum pixclk period must be higher than 2.5 hclk periods. table 44. dcmi pins name signal type d[0:13] data inputs hsync horizontal synchronization input vsync vertical synchronization input pixclx pixel clock input digital camera interface (dcmi) RM0033 270/1317 doc id 15403 rev 3 12.5 dcmi functional overview the digital camera interface is a synchronous parallel interface that can receive high-speed (up to 54 mbytes/s) data flows. it consists of up to 14 data lines (d13-d0) and a pixel clock line (pixclk). the pixel clock has a programmable polarity, so that data can be captured on either the rising or the falling edge of the pixel clock. the data are packed into a 32-bit data register (dcmi_dr) and then transferred through a general-purpose dma channel. the image buffer is managed by the dma, not by the camera interface. the data received from the camera can be organized in lines/frames (raw yub/rgb/bayer modes) or can be a sequence of jpeg images. to enable jpeg image reception, the jpeg bit (bit 3 of dcmi_cr register) must be set. the data flow is synchronized either by hardware using the optional hsync (horizontal synchronization) and vsync (vertical synchronizat ion) signals or by synchronization codes embedded in the data flow. figure 56 shows the dcmi block diagram. figure 56. dcmi block diagram figure 57. top-level block diagram dma interface control/status register ahb interface fifo/ data formatter data extraction synchronizer dcmi_pixclk dcmi_d[0:13], dcmi_hsync, dcmi_vsync ai15604 $ # - ) ) n t e r r u p t c o n t r o l l e r $ # - ) ? ) 4 % x t e r n a l i n t e r f a c e $ # - ) ? $ ; = $ # - ) ? 0 ) 8 # , + $ # - ) ? ( 3 9 . # $ # - ) ? 6 3 9 . # $ - ! ? 2 % 1 ( # , + a i b RM0033 digital camera interface (dcmi) d o c id 154 03 re v 3 271 /13 1 7 12.5.1 dma interface the dma interf ac e is activ e when the captur e bit in the dcmi_cr register is s e t. a d m a r e q uest is ge ner at ed ea ch tim e th e ca mer a int e r f a c e rece iv e s a com p let e 3 2 -b it d a t a b l o c k in its regis t er . 12.5.2 dcmi ph ysical interface th e int e r f ace is comp osed o f 1 1 / 13/ 15 / 17 inp u t s . only th e sla v e m ode is supp or t e d . th e came r a int e r f ace ca n capt ur e 8- bit , 1 0 - b it , 1 2 -b it o r 14 -b it da ta d e p end ing o n th e edm[ 1: 0] bit s in t h e dcmi _ cr r e g i st er . if less t h a n 14 b i ts ar e used, t he un u s e d inp u t p i ns m u st be con nect ed t o g r o u n d . the data are synchronous w i th pixc lk and ch ange on the r i sing/f a lling edge of the pixe l cloc k de pen ding on t he p o lar i t y . th e hsync sig nal in dicat e s t h e st ar t / end o f a lin e . the vsyn c signal indicates the star t/end of a fr ame fi gu re 58 . dcmi s i g nal wa ve f orms 1. th e capt ure edge of dcmi_pixclk is the fall ing edge , the active state of dc mi_hsync and dcmi_ v sync is 1. 1. dcmi_ hsync and d c mi_vsync can change states at the same time. t a b l e 45 . dcmi s i g nal s si gnal name sig n al descrip t io n 8 bits 10 bi ts 12 bi ts 14 bi ts d[0..7] d[0..9] d[0..11] d[0..13] data pixclk p i x e l cloc k hsync hor iz on ta l synch roniza tion / data v a l id vsync v er tic a l sy nchronization $ # - ) ? 0 ) 8 # , + $ # - ) ? $ 2 ; = $ # - ) ? ( 3 9 . # $ # - ) ? 6 3 9 . # a i b digital camera interface (dcmi) RM0033 272/1317 doc id 15403 rev 3 8-bit data when edm[1:0] in dcmi_cr are programmed to ?00? the interface captures 8 lsb?s at its input (d[0:7]) and stores them as 8-bit data. the d[13:8] inputs are ignored. in this case, to capture a 32-bit word, the camera interface takes four pixel clock cycles. the first captured data byte is placed in the lsb position in the 32-bit word and the 4 th captured data byte is placed in the msb position in the 32-bit word. ta bl e 4 6 gives an example of the positioning of captured data bytes in two 32-bit words. 10-bit data when edm[1:0] in dcmi_cr are programmed to ?01?, the camera interface captures 10-bit data at its input d[0..9] and stores them as the 10 least significant bits of a 16-bit word. the remaining most significant bits in the dcmi_dr register (bits 11 to 15) are cleared to zero. so, in this case, a 32-bit data word is made up every two pixel clock cycles. the first captured data are placed in the lsb position in the 32-bit word and the 2 nd captured data are placed in the msb position in the 32-bit word as shown in ta b l e 4 7 . 12-bit data when edm[1:0] in dcmi_cr are programmed to ?10?, the camera interface captures the 12-bit data at its input d[0..11] and stores them as the 12 least significant bits of a 16-bit word. the remaining most significant bits are cleared to zero. so, in this case a 32-bit data word is made up every two pixel clock cycles. the first captured data are placed in the lsb position in the 32-bit word and the 2 nd captured data are placed in the msb position in the 32-bit word as shown in ta b l e 4 8 . 14-bit data when edm[1:0] in dcmi_cr are programmed to ?11?, the camera interface captures the 14-bit data at its input d[0..13] and stores them as the 14 least significant bits of a 16-bit table 46. positioning of captured data bytes in 32-bit words (8-bit width) byte address 31:24 23:16 15:8 7:0 0d n+3 [7:0] d n+2 [7:0] d n+1 [7:0] d n [7:0] 4d n+7 [7:0] d n+6 [7:0] d n+5 [7:0] d n+4 [7:0] table 47. positioning of captured data bytes in 32-bit words (10-bit width) byte address 31:26 25:16 15:10 9:0 00d n+1 [9:0] 0 d n [9:0] 40d n+3 [9:0] 0 d n+2 [9:0] table 48. positioning of captured data bytes in 32-bit words (12-bit width) byte address 31:28 27:16 15:12 11:0 00d n+1 [11:0] 0 d n [11:0] 40d n+3 [11:0] 0 d n+2 [11:0] RM0033 digital camera interface (dcmi) doc id 15403 rev 3 273/1317 word. the remaining most significant bits are cleared to zero. so, in this case a 32-bit data word is made up every two pixel clock cycles. the first captured data are placed in the lsb position in the 32-bit word and the 2 nd captured data are placed in the msb position in the 32-bit word as shown in ta b l e 4 9 . 12.5.3 synchronization the digital camera interface supports embedded or hardware (hsync & vsync) synchronization. when embedded synchronization is used, it is up to the digital camera module to make sure that the 0x00 and 0xff values are used only for synchronization (not in data). embedded synchronization codes are supported only for the 8-bit parallel data interface width (that is, in the dcmi_cr register, the edm[1:0] bits should be cleared to ?00?). for compressed data, the dcmi supports only the hardware synchronization mode. in this case, vsync is used as a start/end of the im age, and hsync is used as a data valid signal. figure 59 shows the corresponding timing diagram. figure 59. timing diagram table 49. positioning of captured data bytes in 32-bit words (14-bit width) byte address 31:30 29:16 15:14 13:0 00d n+1 [13:0] 0 d n [13:0] 40d n+3 [13:0] 0 d n+2 [13:0] p a dding d a t a a t the end of the jpeg s tre a m jpeg p a cket s ize progr a mm ab le end of jpeg s tre a m beginning of jpeg s tre a m jpeg d a t a h s ync v s ync p a cket di s p a tching depend s on the im a ge content. thi s re su lt s in a v a ri ab le b l a nking d u r a tion. jpeg p a cket d a t a a i15944 digital camera interface (dcmi) RM0033 274/1317 doc id 15403 rev 3 hardware synchronization mode in hardware synchronisation mode, the two synchronization signals (hsync/vsync) are used. depending on the camera module/mode, data may be transmitted during horizontal/vertical synchronisation periods. the hsync/vsync signa ls act like blanking signals since all the data received during hsync/vsyn c active periods are ignored. in order to correctly transfer images into the dma/ram buffer, data transfer is synchronized with the vsync signal. when the hardware synchronisation mode is selected, and capture is enabled (capture bit set in dcmi_cr), data transfer is synchronized with the deactivation of the vsync si gnal (next start of frame). transfer can then be continuous, with successive frames transferred by dma to successive buffers or the same/circular buffer. to allow the dma management of successive frames, a vsif (vertical synchronization interrupt flag) is activated at the end of each frame. embedded data synchronization mode in this synchronisation mode, the data flow is synchronised using 32-bit codes embedded in the data flow. these codes use the 0x00/0xff values that are not used in data anymore. there are 4 types of codes, all with a 0xff0000xy format. the embedded synchronization codes are supported only in 8-bit parallel data width capture (in the dcmi_cr register, the edm[1:0] bits should be programmed to ?00?). for other data widths, this mode generates unpredictable results and must not be used. note: camera modules can have 8 such codes (in interleaved mode). for this reason, the interleaved mode is not supported by the camera interface (otherwise, every other half- frame would be discarded). mode 2 four embedded codes signal the following events ?frame start (fs) ? frame end (fe) ?line start (ls) ? line end (le) the xy values in the 0xff0000xy format of the four codes are programmable (see section 12.8.7: dcmi embedded synchronization code register (dcmi_escr) ). a 0xff value programmed as a ?frame end? means that all the unused codes are interpreted as valid frame end codes. in this mode, once the camera interface has been enabled, the frame capture starts after the first occurrence of the frame end (fe) code followed by a frame start (fs) code. mode 1 an alternative coding is the camera mode 1. this mode is itu656 compatible. the codes signal another set of events: ? sav (active line) - line start ? eav (active line) - line end ? sav (blanking) - end of line during interframe blanking period ? eav (blanking) - end of line during interframe blanking period RM0033 digital camera interface (dcmi) doc id 15403 rev 3 275/1317 this mode can be supported by programming the following codes: fs 0xff fe 0xff ls sav (active) le eav (active) an embedded unmask code is also implemented for frame/line start and frame/line end codes. using it, it is possible to compare only the selected unmasked bits with the programmed code. you can therefore select a bit to compare in the embedded code and detect a frame/line start or frame/line end. this means that there can be different codes for the frame/line start and frame/line end with the unmasked bit position remaining the same. example fs = 0xa5 unmask code for fs = 0x10 in this case the frame start code is embedded in the bit 4 of the frame start code. 12.5.4 capture modes this interface supports two types of capture: snapshot (single frame) and continuous grab. snapshot mode (single frame) in this mode, a single frame is captured (cm = ?1? in the dcmi_cr register). after the capture bit is set in dcmi_cr, the interface waits for the detection of a start of frame before sampling the data. the camera interface is automatically disabled (capture bit cleared in dcmi_cr) after receiving the first complete frame. an interrupt is generated (it_frame) if it is enabled. in case of an overrun, the frame is lost and the capture bit is cleared. figure 60. frame capture waveforms in snapshot mode 1. here, the active state of dcmi_hsync and dcmi_vsync is 1. 2. dcmi_hsync and dcmi_vsync can change states at the same time. dcmi_hsync dcmi_vsync frame 1 captured frame 2 not captured ai15832 digital camera interface (dcmi) RM0033 276/1317 doc id 15403 rev 3 continuous grab mode in this mode (cm bit = ?0? in dcmi_cr), once the capture bi t has been set in dcmi_cr, the grabbing process starts on the next vsync or embedded frame start depending on the mode. the process continues until the capture bit is cleared in dcmi_cr. once the capture bit has been cleared, the grabbing process continues until the end of the current frame. figure 61. frame capture waveforms in continuous grab mode 1. here, the active state of dcmi_hsync and dcmi_vsync is 1. 2. dcmi_hsync and dcmi_vsync can change states at the same time. in continuous grab mode, you can configure th e fcrc bits in dcmi_cr to grab all pictures, every second picture or one out of four pictures to decrease the frame capture rate. note: in the hardware synchroniz ation mode (ess = ?0? in dcmi_c r), the it_vsync interrupt is generated (if enabled) even when capture = ?0? in dcmi_cr so, to reduce the frame capture rate even further, the it_vsync interrupt can be used to count the number of frames between 2 captures in conjunction with the snapshot mode. this is not allowed by embedded data synchronization mode. 12.5.5 crop feature with the crop feature, the camera interface can select a rectangular window from the received image. the start (upper left corner) coordinates and size (horizontal dimension in number of pixel clocks and vertical dimension in number of lines) are specified using two 32- bit registers (dcmi_cwstrt and dcmi_cwsize). the size of the window is specified in number of pixel clocks (horizontal dimension) and in number of lines (vertical dimension). figure 62. coordinates and size of the window after cropping dcmi_hsync dcmi_vsync frame 1 captured frame 2 captured ai15833 capcnt bit in dcmi_csize hoffcnt bit in dcmi_cstrt ai15834 vst bit in dcmi_cstrt vline bit in dcmi_csize RM0033 digital camera interface (dcmi) doc id 15403 rev 3 277/1317 these registers specify the coordinates of the starting point of the capture window as a line number (in the frame, starting from 0) and a number of pixel clocks (on the line, starting from 0), and the size of the window as a line number and a number of pixel clocks. the capcnt value can only be a multiple of 4 (two least significant bits are forced to 0) to allow the correct transfer of data through the dma. if the vsync signal goes active before the number of lines is specified in the dcmi_cwsize register, then the capture stops and an it_frame interrupt is generated when enabled. figure 63. data capture waveforms 1. here, the active state of dcmi_hsync and dcmi_vsync is 1. 2. dcmi_hsync and dcmi_vsync can change states at the same time. 12.5.6 jpeg format to allow jpeg image reception, it is necessary to set the jpeg bit in the dcmi_cr register. jpeg images are not stored as lines and fram es, so the vsync signal is used to start the capture while hsync serves as a data enable signal. the number of bytes in a line may not be a multiple of 4, you should therefore be careful when handling this case since a dma request is generated each time a complete 32-bit word has been constructed from the captured data. when an end of frame is detected and the 32-bit word to be transferred has not been completely received, the remaining data are padded with ?0s? and a dma request is generated. the crop feature and embedded synchronization codes cannot be used in the jpeg format. 12.5.7 fifo a four-word fifo is implemented to manage data rate transfers on the ahb. the dcmi features a simple fifo controller with a read pointer incremented each time the camera interface reads from the ahb, and a write pointer incremented each time the camera interface writes to the fifo. there is no overrun protection to prevent the data from being overwritten if the ahb interface does not sustain the data transfer rate. in case of overrun or errors in the synchronization signals, the fifo is reset and the dcmi interface waits for a new start of frame. dcmi_hsync dcmi_vsync ai15833 capcnt hoffcnt data not captured in this phase data captured in this phase digital camera interface (dcmi) RM0033 278/1317 doc id 15403 rev 3 12.6 data format description 12.6.1 data formats three types of data are supported: 8-bit progressive video: either monochrome or raw bayer format ycbcr 4:2:2 progressive video rgb565 progressive video. a pixel coded in 16 bits (5 bits for blue, 5 bits for red, 6 bits for green) takes two clock cycles to be transferred. compressed data: jpeg for b&w, ycbcr or rgb data, the maximum input size is 2048 2048 pixels. no limit in jpeg compressed mode. for monochrome, rgb & ycbcr, the frame buffer is stored in raster mode. 32-bit words are used. only the little endian format is supported. figure 64. pixel raster scan order 12.6.2 monochrome format characteristics: raster format 8 bits per pixel ta bl e 5 0 shows how the data are stored. 12.6.3 rgb format characteristics: raster format rgb interleaved: one buffer: r, g & b interleaved: brgbrgbrg, etc. optimized for display output 0 i x e l r a s t e r s c a n o r d e r i n c r e a s i n g a d d r e s s e s 7 o r d 7 o r d 7 o r d 0 i x e l r o w 0 i x e l r o w n n a i table 50. data storage in monochrome progressive video format byte address 31:24 23:16 15:8 7:0 0 n + 3 n + 2 n + 1 n 4 n + 7 n + 6 n + 5 n + 4 RM0033 digital camera interface (dcmi) doc id 15403 rev 3 279/1317 the rgb planar format is compatible with standard os frame buffer display formats. only 16 bpp (bits per pixel): rgb565 (2 pixels per 32-bit word) is supported. the 24 bpp (palletized format) and grayscale formats are not supported. pixels are stored in a raster scan order, that is from top to bottom for pixel rows, and from left to right within a pixel row. pixel components are r (red), g (green) and b (blue). all components have the same spatial resolution (4:4:4 format). a frame is stored in a single part, with the components interleaved on a pixel basis. ta bl e 5 1 shows how the data are stored. 12.6.4 ycbcr format characteristics: raster format ycbcr 4:2:2 interleaved: one buffer: y, cb & cr interleaved: cbycrycbycr, etc. pixel components are y (luminance or ?luma?), cb and cr (chrominance or ?chroma? blue and red). each component is encoded in 8 bits. luma and chroma are stored together (interleaved) as shown in ta bl e 5 2 . 12.7 dcmi interrupts five interrupts are generated. all interrupts are maskable by software. the global interrupt (it_dcmi) is the or of all the individual interrupts. ta b l e 5 3 gives the list of all interrupts. table 51. data storage in rgb progressive video format byte address 31:27 26:21 20:16 15:11 10:5 4:0 0 red n + 1 green n + 1 blue n + 1 red n green n blue n 4 red n + 4 green n + 3 blue n + 3 red n + 2 green n + 2 blue n + 2 table 52. data storage in ycbcr progressive video format byte address 31:24 23:16 15:8 7:0 0y n + 1cr n y ncb n 4 y n + 3 cr n + 2 y n + 2 cb n + 2 table 53. dcmi interrupts interrupt name interrupt event it_line indicates the end of line it_frame indicates the end of frame capture it_ovr indicates the overrun of data reception it_vsync indicates the synchronization frame it_err indicates the detection of an error in the embedded synchronization frame detection it_dcmi logic or of the previous interrupts digital camera interface (dcmi) RM0033 280/1317 doc id 15403 rev 3 12.8 dcmi register description all dcmi registers have to be accessed as 32-bit words, otherwise a bus error occurs. 12.8.1 dcmi control regi ster 1 (dcmi_cr) address offset: 0x00 reset value: 0x0000 313029282726252423222120191817161514131211109876543210 reserved enable reserved edm fcrc vspol hspol pckpol ess jpeg crop cm capture rw rw rw rw rw rw rw rw rw rw rw rw rw bit 31:15 reserved, forced by hardware to 0. bit 14 enable: dcmi enable 0: dcmi disabled 1: dcmi enabled note: the dcmi configuration registers should be programmed correctly before enabling this bit bit 13: 12 reserved, forced by hardware to 0. 11:10 edm[1:0]: extended data mode 00: interface captures 8-bit data on every pixel clock 01: interface captures 10-bit data on every pixel clock 10: interface captures 12-bit data on every pixel clock 11: interface captures 14-bit data on every pixel clock 9:8 fcrc[1:0]: frame capture rate control these bits define the frequency of frame captur e. they are meaningful only in continuous grab mode. they are ignored in snapshot mode. 00: all frames are captured 01: every alternate frame captured (50% bandwidth reduction) 10: one frame in 4 frames captured (75% bandwidth reduction) 11: reserved bit 7 vspol: vertical synchronization polarity this bit indicates the level on the vsync pin when the data are not valid on the parallel interface. 0: vsync active low 1: vsync active high bit 6 hspol: horizontal synchronization polarity this bit indicates the level on the hsync pin when the data are not valid on the parallel interface. 0: hsync active low 1: hsync active high bit 5 pckpol: pixel clock polarity this bit configures the capture edge of the pixel clock 0: falling edge active. 1: rising edge active. RM0033 digital camera interface (dcmi) doc id 15403 rev 3 281/1317 bit 4 ess: embedded synchronization select 0: hardware synchronization data capture (frame/line start/st op) is synchronized with the hsync/vsync signals. 1: embedded synchronization data capture is synchronized with synchronization codes embedded in the data flow. note: valid only for 8-bit parallel data. hspol/vspol are ignored when the ess bit is set. this bit is disabled in jpeg mode. bit 3 jpeg: jpeg format 0: uncompressed video format 1: this bit is used for jpeg data transfers. th e hsync signal is used as data enable. the crop and embedded synchronization features (ess bit) cannot be used in this mode. bits 2 crop: crop feature 0: the full image is captured. in this case the total number of bytes in an image frame should be a multiple of 4 1: only the data inside the window specified by the crop register will be captured. if the size of the crop window exceeds the picture size, then only the picture size is captured. bit 1 cm: capture mode 0: continuous grab mode - the received data ar e transferred into the destination memory through the dma. the buffer location and mode (linear or circular buffer) is controlled through the system dma. 1: snapshot mode (single frame) - once activate d, the interface waits for the start of frame and then transfers a single frame through the dm a. at the end of the frame, the capture bit is automatically reset. bit 0 capture: capture enable 0: capture disabled. 1: capture enabled. the camera interface waits for the first start of frame, then a dma request is generated to transfer the received data into the destination memory. in snapshot mode, the capture bit is automa tically cleared at the end of the 1st frame received. in continuous grab mode, if the software clears this bit while a capture is ongoing, the bit will be effectively cleared after the frame end. note: the dma controller and all dcmi configuration registers should be programmed correctly before enabling this bit. digital camera interface (dcmi) RM0033 282/1317 doc id 15403 rev 3 12.8.2 dcmi status register (dcmi_sr) address offset: 0x04 reset value: 0x0000 313029282726252423222120191817161514131211109876543210 reserved fne vsync hsync rrr bit 31:3 reserved, forced by hardware to 0. bit 2 fne: fifo not empty this bit gives the status of the fifo 1: fifo contains valid data 0: fifo empty bit 1 vsync this bit gives the state of the vsync pin with the correct programmed polarity. when embedded synchronization codes are used, the meaning of this bit is the following: 0: active frame 1: synchronization between frames in case of embedded synchronization, this bit is meaningful only if the capture bit in dcmi_cr is set. bit 0 hsync this bit gives the state of the hsync pin with the correct programmed polarity. when embedded synchronization codes are used, the meaning of this bit is the following: 0: active line 1: synchronization between lines in case of embedded synchronization, this bit is meaningful only if the capture bit in dcmi_cr is set. RM0033 digital camera interface (dcmi) doc id 15403 rev 3 283/1317 12.8.3 dcmi raw interrupt st atus register (dcmi_ris) address offset: 0x08 reset value: 0x0000 dcmi_ris gives the raw interrupt status and is accessible in read only. when read, this register returns the status of the corresponding interrupt before masking with the dcmi_ier register value. 313029282726252423222120191817161514131211109876543210 reserved line_ris vsync_ris err_ris ovr_ris frame_ris rrrrr bit 31:5 reserved, forced by hardware to 0. bit 4 line_ris: line raw interrupt status this bit gets set when the hsync signal changes from the inactive state to the active state. it goes high even if the line is not valid. in the case of embedded synchronization, this bit is set only if the capture bit in dcmi_cr is set. it is cleared by writing a ?1? to the line_isc bit in dcmi_icr. bit 3 vsync_ris: vsync raw interrupt status this bit is set when the vsync signal changes from the inactive state to the active state. in the case of embedded synchronization, this bit is set only if the capture bit is set in dcmi_cr. it is cleared by writing a ?1? to the vsync_isc bit in dcmi_icr. bit 2 err_ris: synchronization error raw interrupt status 0: no synchronization error detected 1: embedded synchronization characters are not received in the correct order. this bit is valid only in the embedded synchronization mode. it is cleared by writing a ?1? to the err_isc bit in dcmi_icr. note: this bit is available only in embedded synchronization mode. bit 1 ovr_ris: overrun raw interrupt status 0: no data buffer overrun occurred 1: a data buffer overrun occurred and the data fifo is corrupted. this bit is cleared by writing a ?1? to the ovr_isc bit in dcmi_icr. bit 0 frame_ris: capture complete raw interrupt status 0: no new capture 1: a frame has been captured. this bit is set when a frame or window has been captured. in case of a cropped window, this bit is set at the end of line of the last line in the crop. it is set even if the captured frame is em pty (e.g. window cropped outside the frame). this bit is cleared by writing a ?1? to the frame_isc bit in dcmi_icr. digital camera interface (dcmi) RM0033 284/1317 doc id 15403 rev 3 12.8.4 dcmi interrupt enab le register (dcmi_ier) address offset: 0x0c reset value: 0x0000 the dcmi_ier register is used to enable interrupts. when one of the dcmi_ier bits is set, the corresponding interrupt is enabled. this register is accessible in both read and write. 313029282726252423222120191817161514131211109876543210 reserved line_ie vsync_ie err_ie ovr_ie frame_ie rw rw rw rw rw bit 31:5 reserved, forced by hardware to 0. bit 4 line_ie: line interrupt enable 0: no interrupt generation when the line is received 1: an interrupt is generated when a line has been completely received bit 3 vsync_ie: vsync interrupt enable 0: no interrupt generation 1: an interrupt is generated on each vsync transit ion from the inactive to the active state the active state of the vsync si gnal is defined by the vspol bit. bit 2 err_ie: synchronization error interrupt enable 0: no interrupt generation 1: an interrupt is generated if the embedded synchronization codes are not received in the correct order. note: this bit is available only in embedded synchronization mode. bit 1 ovr_ie: overrun interrupt enable 0: no interrupt generation 1: an interrupt is generated if the dma was not ab le to transfer the last data before new data (32-bit) are received. bit 0 frame_ie: capture complete interrupt enable 0: no interrupt generation 1: an interrupt is generated at the end of each received frame/crop window (in crop mode). RM0033 digital camera interface (dcmi) doc id 15403 rev 3 285/1317 12.8.5 dcmi masked interrupt st atus register (dcmi_mis) this dcmi_mis register is a read-only register. when read, it returns the current masked status value (depending on the value in dcmi_ier) of the corresponding interrupt. a bit in this register is set if the corresponding enable bit in dcmi_ier is set and the corresponding bit in dcmi_ris is set. address offset: 0x10 reset value: 0x0000 313029282726252423222120191817161514131211109876543210 reserved line_mis vsync_mis err_mis ovr_mis frame_mis rrrrr bit 31:5 reserved, forced by hardware to 0. bit 4 line_mis: line masked interrupt status this bit gives the status of the masked line interrupt 0: no interrupt generation when the line is received 1: an interrupt is generated when a line has been completely received and the line_ie bit is set in dcmi_ier. bit 3 vsync_mis: vsync masked interrupt status this bit gives the status of the masked vsync interrupt 0: no interrupt is generated on vsync transitions 1: an interrupt is generated on each vsync tr ansition from the inactive to the active state and the vsync_ie bit is set in dcmi_ier. the active state of the vsync si gnal is defined by the vspol bit. bit 2 err_mis: synchronization error masked interrupt status this bit gives the status of the masked synchronization error interrupt 0: no interrupt is generated on a synchronization error 1: an interrupt is generated if the embedded synchronization codes are not received in the correct order and the err_ie bit in dcmi_ier is set. note: this bit is available only in embedded synchronization mode. bit 1 ovr_mis: overrun masked interrupt status this bit gives the status of the masked overflow interrupt 0: no interrupt is generated on overrun 1: an interrupt is generated if the dma was not able to transfer the last data before new data (32-bit) are received and the ovr_ie bit is set in dcmi_ier. bit 0 frame_mis: capture complete masked interrupt status this bit gives the status of the masked capture complete interrupt 0: no interrupt is generated after a complete capture 1: an interrupt is generated at the end of each received frame/crop window (in crop mode) and the frame_ie bit is set in dcmi_ier. digital camera interface (dcmi) RM0033 286/1317 doc id 15403 rev 3 12.8.6 dcmi interrupt clear register (dcmi_icr) address offset: 0x14 reset value: 0x0000 the dcmi_icr register is write-only. writing a ?1? into a bit of this register clears the corresponding bit in the dcmi_ris and dcmi_mis registers. writing a ?0? has no effect. 12.8.7 dcmi embedded synchroniza tion code register (dcmi_escr) address offset: 0x18 reset value: 0x0000 313029282726252423222120191817161514131211109876543210 reserved line_isc vsync_isc err_isc ovr_isc frame_isc wwwww bit 15:5 reserved, forced by hardware to 0. bit 4 line_isc: line interrupt status clear writing a ?1? into this bit clears line_ris in the dcmi_ris register bit 3 vsync_isc: vertical synch interrupt status clear writing a ?1? into this bit clears the vsync_ris bit in dcmi_ris bit 2 err_isc: synchronization error interrupt status clear writing a ?1? into this bit clears the err_ris bit in dcmi_ris note: this bit is available only in embedded synchronization mode. bit 1 ovr_isc: overrun interrupt status clear writing a ?1? into this bit clears the ovr_ris bit in dcmi_ris bits 0 frame_isc: capture complete interrupt status clear writing a ?1? into this bit clears the frame_ris bit in dcmi_ris 313029282726252423222120191817161514131211109876543210 fec lec lsc fsc rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bit 31:24 fec: frame end delimiter code this byte specifies the code of the frame end delimiter. the code consists of 4 bytes in the form of 0xff, 0x00, 0x00, fec. if fec is programmed to 0xff, all the unused codes (0xff0000xy) are interpreted as frame end delimiters. bit 23:16 lec: line end delimiter code this byte specifies the code of the line end delim iter. the code consists of 4 bytes in the form of 0xff, 0x00, 0x00, lec. RM0033 digital camera interface (dcmi) doc id 15403 rev 3 287/1317 12.8.8 dcmi embedded synchroniza tion unmask register (dcmi_esur) address offset: 0x1c reset value: 0x0000 bit 15:8 lsc: line start delimiter code this byte specifies the code of the line start de limiter. the code consists of 4 bytes in the form of 0xff, 0x00, 0x00, lsc. bit 7:0 fsc: frame start delimiter code this byte specifies the code of the frame star t delimiter. the code consists of 4 bytes in the form of 0xff, 0x00, 0x00, fsc. if fsc is programmed to 0xff, no frame start delimiter is detected. but, the 1 st occurrence of lsc after an fec code will be interpreted as a start of frame delimiter. 313029282726252423222120191817161514131211109876543210 feu leu lsu fsu rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bit 31:24 feu: frame end delimiter unmask this byte specifies the mask to be applied to the code of the frame end delimiter. 0: the corresponding bit in the fec byte in dcmi_escr is masked while comparing the frame end delimiter with the received data. 1: the corresponding bit in the fec byte in dcmi_escr is compared while comparing the frame end delimiter with the received data bit 23:16 leu: line end delimiter unmask this byte specifies the mask to be applie d to the code of the line end delimiter. 0: the corresponding bit in the lec byte in dcmi_escr is masked while comparing the line end delimiter with the received data 1: the corresponding bit in the lec byte in dcmi_escr is compared while comparing the line end delimiter with the received data bit 15:8 lsu: line start delimiter unmask this byte specifies the mask to be applied to the code of the line start delimiter. 0: the corresponding bit in the lsc byte in dcmi_escr is masked while comparing the line start delimiter with the received data 1: the corresponding bit in the lsc byte in dcmi_escr is compared while comparing the line start delimiter with the received data bit 7:0 fsu: frame start delimiter unmask this byte specifies the mask to be applied to the code of the frame start delimiter. 0: the corresponding bit in the fsc byte in dcmi_escr is masked while comparing the frame start delimiter with the received data 1: the corresponding bit in the fsc byte in dcmi_escr is compared while comparing the frame start delimiter with the received data digital camera interface (dcmi) RM0033 288/1317 doc id 15403 rev 3 12.8.9 dcmi crop window start (dcmi_cwstrt) address offset: 0x20 reset value: 0x0000 12.8.10 dcmi crop window size (dcmi_cwsize) address offset: 0x24 reset value: 0x0000 313029282726252423222120191817161514131211109876543210 reserved vst[12:0 reserv ed hoffcnt[13:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:29 reserved bit 28:16 vst[12:0]: vertical start line count the image capture starts with this line number. previous line data are ignored. 0x0000 => line 1 0x0001 => line 2 0x0002 => line 3 .... bits 15:14 reserved. bit 13:0 hoffcnt[13:0]: horizontal offset count this value gives the number of pixel clocks to count before starting a capture. 313029282726252423222120191817161514131211109876543210 reserved vline13:0] reserved capcnt[13:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:30 reserved. bit 29:16 vline[13:0]: vertical line count this value gives the number of lines to be captured from the starting point. 0x0000 => 1 line 0x0001 => 2 lines 0x0002 => 3 lines .... bits 15:14 reserved. bit 13:0 capcnt[13:0]: capture count this value gives the number of pixel clocks to be captured from the starting point on the same line. it value should corresponds to word-aligned data for different widths of parallel interfaces. 0x0000 => 1 pixel 0x0001 => 2 pixels 0x0002 => 3 pixels .... RM0033 digital camera interface (dcmi) doc id 15403 rev 3 289/1317 12.8.11 dcmi data register (dcmi_dr) address offset: 0x28 reset value: 0x0000 the digital camera interface packages all the received data in 32-bit format before requesting a dma transfer. a 4-word deep fifo is available to leave enough time for dma transfers and avoid dma overrun conditions. 12.8.12 dcmi register map ta bl e 5 4 summarizes the dcmi registers. 313029282726252423222120191817161514131211109876543210 byte3 byte2 byte1 byte0 rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr bits 31:24 data byte 3 bit 23:16 data byte 2 bits 15:8 data byte 1 bit 7:0 data byte 0 table 54. dcmi register map and reset values offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 dcmi_cr reserved enable reserved edm fcrc vspol hspol pckpol ess jpeg crop cm capture reset value 0 000000000000 0x04 dcmi_sr reserved fne vsync hsync reset value 000 0x08 dcmi_ris reserved line_ris vsync_ris err_ris ovr_ris frame_ris reset value 00000 0x0c dcmi_ier reserved line_ie vsync_ie err_ie ovr_ie frame_ie reset value 00000 0x10 dcmi_mis reserved line_mis vsync_mis err_mis ovr_mis frame_mis reset value 00000 0x14 dcmi_icr reserved line_isc vsync_isc err_isc ovr_isc frame_isc reset value 00000 digital camera interface (dcmi) RM0033 290/1317 doc id 15403 rev 3 refer to table 1 on page 50 for the register boundary addresses. 0x18 dcmi_escr fec lec lsc fsc reset value 00000000000000000000000000000000 0x1c dcmi_esur feu leu lsu fsu reset value 00000000000000000000000000000000 0x20 dcmi_cwstrt reserved vst[12:0 reserved hoffcnt[13:0] reset value 0000000000000 00000000000000 0x24 dcmi_cwsize reserved vline13:0] reserved capcnt[13:0] reset value 00000000000000 00000000000000 0x28 dcmi_dr byte3 byte2 byte1 byte0 reset value 00000000000000000000000000000000 table 54. dcmi register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 291/1317 13 advanced-control timers (tim1&tim8) 13.1 tim1&tim8 introduction the advanced-control timers (tim1&tim8) consist of a 16-bit auto-reload counter driven by a programmable prescaler. it may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, pwm, complementary pwm with dead-time insertion). pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the rcc clock controller prescalers. the advanced-control (tim1&tim8) and gener al-purpose (timx) timers are completely independent, and do not share any resources. they can be synchronized together as described in section 13.3.20 . 13.2 tim1&tim8 main features tim1&tim8 timer features include: 16-bit up, down, up/down auto-reload counter. 16-bit programmable prescaler allowing dividing (also ?on the fly?) the counter clock frequency either by any factor between 1 and 65535. up to 4 independent channels for: ? input capture ? output compare ? pwm generation (edge and center-aligned mode) ? one-pulse mode output complementary outputs with programmable dead-time synchronization circuit to control the timer with external signals and to interconnect several timers together. repetition counter to update the timer registers only after a given number of cycles of the counter. break input to put the timer?s output signals in reset state or in a known state. interrupt/dma generation on the following events: ? update: counter overflow/underflow, counter initialization (by software or internal/external trigger) ? trigger event (counter start, stop, initialization or count by internal/external trigger) ? input capture ? output compare ? break input supports incremental (quadrature) encoder and hall-sensor circuitry for positioning purposes trigger input for external clock or cycle-by-cycle cu rrent management advanced-control timers (tim1&tim8) RM0033 292/1317 doc id 15403 rev 3 figure 65. advanced-control timer block diagram prescaler autoreload register counter capture/compare 1 register capture/compare 2 register u u u cc1i cc2i etr trigger controller +/- stop, clear or up/down ti1fp1 ti2fp2 itr0 itr1 itr2 trgi controller encoder interface capture/compare 3 register u cc3i output control dtg dtg registers trgo oc1ref oc2ref oc3ref rep register u repetition counter ui reset, enable, up/down, count capture/compare 4 register u cc4i oc4ref ck_psc ti4 prescaler prescaler ic4ps ic3ps ic1 ic2 prescaler prescaler input filter & edge detector ic2ps ic1ps ti1fp1 output control dtg output control dtg output control reg event notes: preload registers transferred to active registers on u event according to control bit interrupt & dma output input filter polarity selection & edge detector & prescaler etrp tgi trc trc ic3 ic4 itr etrf trc ti1f_ed input filter & edge detector input filter & edge detector input filter & edge detector cc1i cc2i cc3i cc4i ti1fp2 ti2fp1 ti2fp2 ti3fp3 trc trc ti3fp4 ti4fp3 ti4fp4 bi ti3 ti1 ti2 xor timx_ch1 timx_ch2 timx_ch3 timx_ch4 brk timx_bkin oc1 oc2 oc3 timx_ch1 timx_ch2 timx_ch3 timx_ch3n oc3n timx_ch2n oc2n timx_ch1n oc1n oc4 timx_ch4 timx_etr to other timers mode slave psc cnt internal clock (ck_int) ck_cnt etrf clock failure event from clock controller polarity selection css (clock security system ck_tim18 from rcc to dac/adc itr3 RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 293/1317 13.3 tim1&tim8 functional description 13.3.1 time-base unit the main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. the counter can count up, down or both up and down. the counter clock can be divided by a prescaler. the counter, the auto-reload register and the prescaler register can be written or read by software. this is true even when the counter is running. the time-base unit includes: counter register (timx_cnt) prescaler register (timx_psc) auto-reload register (timx_arr) repetition counter register (timx_rcr) the auto-reload register is preloaded. writing to or reading from the auto-reload register accesses the preload register. the content of the preload register are transferred into the shadow register permanently or at each update event (uev), depending on the auto-reload preload enable bit (arpe) in timx_cr1 register. the update event is sent when the counter reaches the overflow (or underflow when downcounting) and if the udis bit equals 0 in the timx_cr1 register. it can also be generated by software. the generation of the update event is described in detailed for each configuration. the counter is clocked by the prescaler output ck_cnt, which is enabled only when the counter enable bit (cen) in timx_cr1 register is set (refer also to the slave mode controller description to get more details on counter enabling). note that the counter starts counting 1 clock cycle after setting the cen bit in the timx_cr1 register. prescaler description the prescaler can divide the counter clock frequency by any factor between 1 and 65536. it is based on a 16-bit counter controlled through a 16-bit register (in the timx_psc register). it can be changed on the fly as this control register is buffered. the new prescaler ratio is taken into account at the next update event. figure 67 and figure 68 give some examples of the counter behavior when the prescaler ratio is changed on the fly: advanced-control timers (tim1&tim8) RM0033 294/1317 doc id 15403 rev 3 figure 66. counter timing diagram with prescaler division change from 1 to 2 figure 67. counter timing diagram with prescaler division change from 1 to 4 13.3.2 counter modes upcounting mode in upcounting mode, the counter counts from 0 to the auto-reload value (content of the timx_arr register), then restarts from 0 and generates a counter overflow event. if the repetition counter is used, the update event (uev) is generated after upcounting is repeated for the number of times programmed in the repetition counter register (timx_rcr). else the update event is generated at each counter overflow. setting the ug bit in the timx_egr register (by software or by using the slave mode controller) also generates an update event. the uev event can be disabled by software by setting the udis bit in the timx_cr1 register. this is to avoid updating the shadow registers while writing new values in the ck_psc 00 cen timer clock = ck_cnt counter register update event (uev) 0 f9 fa fb fc f7 prescaler control register 01 write a new value in timx_psc 01 02 03 prescaler buffer 01 prescaler counter 0 1 0 1 0 1 0 1 f8 ck_psc 00 cen timer clock = ck_cnt counter register update event (uev) 0 f9 fa fb fc f7 prescaler control register 03 write a new value in timx_psc prescaler buffer 03 prescaler counter 0 1 2 3 0 1 2 3 f8 01 RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 295/1317 preload registers. then no update event occurs until the udis bit has been written to 0. however, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). in addition, if the urs bit (update request selection) in timx_cr1 register is set, setting the ug bit generates an update event uev but without setting the uif flag (thus no interrupt or dma request is sent). this is to avoid generating both update and capture interrupts when clearing the counter on the capture event. when an update event occurs, all the registers are updated and the update flag (uif bit in timx_sr register) is set (depending on the urs bit): the repetition counter is reloaded with the content of timx_rcr register, the auto-reload shadow register is updated with the preload value (timx_arr), the buffer of the prescaler is reloaded with the preload value (content of the timx_psc register). the following figures show some examples of the counter behavior for different clock frequencies when timx_arr=0x36. figure 68. counter timing diagram, internal clock divided by 1 figure 69. counter timing diagram, internal clock divided by 2 ck_psc 00 cnt_en timer clock = ck_cnt counter register update interrupt flag (uif) counter overflow update event (uev) 01 02 03 04 05 06 07 32 33 34 35 36 31 ck_psc 0035 0000 0001 0002 0003 cnt_en timer clock = ck_cnt counter register update interrupt flag (uif) 0034 0036 counter overflow update event (uev) advanced-control timers (tim1&tim8) RM0033 296/1317 doc id 15403 rev 3 figure 70. counter timing diagram, internal clock divided by 4 figure 71. counter timing diagram, internal clock divided by n figure 72. counter timing diagram, u pdate event when arpe=0 (timx_arr not preloaded) ck_psc 0000 0001 cnt_en timer clock = ck_cnt counter register update interrupt flag (uif) 0035 0036 counter overflow update event (uev) timer clock = ck_cnt counter register 00 1f 20 update interrupt flag (uif) counter overflow update event (uev) ck_psc ck_psc 00 cen timer clock = ck_cnt counter register update interrupt flag (uif) counter overflow update event (uev) 01 02 03 04 05 06 07 32 33 34 35 36 31 auto-reload register ff 36 write a new value in timx_arr RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 297/1317 figure 73. counter timing diagra m, update event when arpe=1 (timx_arr preloaded) downcounting mode in downcounting mode, the counter counts from the auto-reload value (content of the timx_arr register) down to 0, then restarts from the auto-reload value and generates a counter underflow event. if the repetition counter is used, the update event (uev) is generated after downcounting is repeated for the number of times programmed in the repetition counter register (timx_rcr). else the update event is generated at each counter underflow. setting the ug bit in the timx_egr register (by software or by using the slave mode controller) also generates an update event. the uev update event can be disabled by software by setting the udis bit in timx_cr1 register. this is to avoid updating the shadow registers while writing new values in the preload registers. then no update event occurs until udis bit has been written to 0. however, the counter restarts from the current auto-reload value, whereas the counter of the prescaler restarts from 0 (but the prescale rate doesn?t change). in addition, if the urs bit (update request selection) in timx_cr1 register is set, setting the ug bit generates an update event uev but without setting the uif flag (thus no interrupt or dma request is sent). this is to avoid generating both update and capture interrupts when clearing the counter on the capture event. when an update event occurs, all the registers are updated and the update flag (uif bit in timx_sr register) is set (depending on the urs bit): the repetition counter is reloaded with the content of timx_rcr register the buffer of the prescaler is reloaded with the preload value (content of the timx_psc register) the auto-reload active register is updated with the preload value (content of the timx_arr register). note that the auto-reload is updated before the counter is reloaded, so that the next period is the expected one ck_psc 00 cen timer clock = ck_cnt counter register update interrupt flag (uif) counter overflow update event (uev) 01 02 03 04 05 06 07 f1 f2 f3 f4 f5 f0 auto-reload preload register f5 36 auto-reload shadow register f5 36 write a new value in timx_arr advanced-control timers (tim1&tim8) RM0033 298/1317 doc id 15403 rev 3 the following figures show some examples of the counter behavior for different clock frequencies when timx_arr=0x36. figure 74. counter timing diagram, internal clock divided by 1 figure 75. counter timing diagram, internal clock divided by 2 figure 76. counter timing diagram, internal clock divided by 4 ck_psc 36 cnt_en timer clock = ck_cnt counter register update interrupt flag (uif) counter underflow (cnt_udf) update event (uev) 35 34 33 32 31 30 2f 04 03 02 01 00 05 ck_psc 0001 0036 0035 0034 0033 cnt_en timer clock = ck_cnt counter register update interrupt flag (uif) 0002 0000 counter underflow update event (uev) ck_psc 0036 0035 cnt_en timer clock = ck_cnt counter register update interrupt flag (uif) 0001 0000 counter underflow update event (uev) RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 299/1317 figure 77. counter timing diagram, internal clock divided by n figure 78. counter timing diagram, update event when repetition counter is not used center-aligned mode (up/down counting) in center-aligned mode, the counter counts from 0 to the auto-reload value (content of the timx_arr register) ? 1, generates a counter overflow event, then counts from the auto- reload value down to 1 and generates a counter underflow event. then it restarts counting from 0. center-aligned mode is active when the cms bits in timx_cr1 register are not equal to '00'. the output compare interrupt flag of channels configured in output is set when: the counter counts down (center aligned mode 1, cms = "01"), the counter counts up (center aligned mode 2, cms = "10") the counter counts up and down (center aligned mode 3, cms = "11"). in this mode, the dir direction bit in the timx_cr1 register cannot be written. it is updated by hardware and gives the current direction of the counter. the update event can be generated at each counter overflow and at each counter underflow or by setting the ug bit in the timx_egr register (by software or by using the slave mode controller) also generates an update event. in this case, the counter restarts counting from 0, as well as the counter of the prescaler. timer clock = ck_cnt counter register 36 20 1f update interrupt flag (uif) counter underflow update event (uev) ck_psc 00 ck_psc 36 cen timer clock = ck_cnt counter register update interrupt flag (uif) counter underflow update event (uev) 35 34 33 32 31 30 2f 04 03 02 01 00 05 auto-reload register ff 36 write a new value in timx_arr advanced-control timers (tim1&tim8) RM0033 300/1317 doc id 15403 rev 3 the uev update event can be disabled by software by setting the udis bit in the timx_cr1 register. this is to avoid updating the shadow registers while writing new values in the preload registers. then no update event occurs until udis bit has been written to 0. however, the counter continues counting up and down, based on the current auto-reload value. in addition, if the urs bit (update request selection) in timx_cr1 register is set, setting the ug bit generates an uev update event but without setting the uif flag (thus no interrupt or dma request is sent). this is to avoid generating both update and capture interrupts when clearing the counter on the capture event. when an update event occurs, all the registers are updated and the update flag (uif bit in timx_sr register) is set (depending on the urs bit): the repetition counter is reloaded with the content of timx_rcr register the buffer of the prescaler is reloaded with the preload value (content of the timx_psc register) the auto-reload active register is updated with the preload value (content of the timx_arr register). note that if the update source is a counter overflow, the auto- reload is updated before the counter is reloaded, so that the next period is the expected one (the counter is loaded with the new value). the following figures show some examples of the counter behavior for different clock frequencies. figure 79. counter timing diagram, intern al clock divided by 1, timx_arr = 0x6 1. here, center-aligned mode 1 is used (for more details refer to section 13.4: tim1&tim8 registers on page 331 ). ck_psc 02 cnt_en timer clock = ck_cnt counter register update interrupt flag (uif) counter underflow update event (uev) 03 04 05 06 05 04 03 03 02 01 00 01 04 counter overflow RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 301/1317 figure 80. counter timing diagram, internal clock divided by 2 figure 81. counter timing diagram, inte rnal clock divided by 4, timx_arr=0x36 1. center-aligned mode 2 or 3 is used with an uif on overflow. figure 82. counter timing diagram, internal clock divided by n ck_psc 0002 0000 0001 0002 0003 cnt_en timer clock = ck_cnt counter register update interrupt flag (uif) 0003 0001 counter underflow update event (uev) ck_psc 0036 0035 cnt_en timer clock = ck_cnt counter register update interrupt flag (uif) 0034 0035 counter overflow update event (uev) timer clock = ck_cnt counter register 00 20 1f update interrupt flag (uif) counter underflow update event (uev) ck_psc 01 advanced-control timers (tim1&tim8) RM0033 302/1317 doc id 15403 rev 3 figure 83. counter timing diagram, update event with arpe=1 (counter underflow) figure 84. counter timing diagram, update event with arpe=1 (counter overflow) 13.3.3 repetition counter section 13.3.1: time-base unit describes how the update event (uev) is generated with respect to the counter overflows/underflows. it is actually generated only when the repetition counter has reached zero. this can be useful when generating pwm signals. this means that data are transferred from the preload registers to the shadow registers (timx_arr auto-reload register, timx_psc prescaler register, but also timx_ccrx capture/compare registers in compare mode) every n counter overflows or underflows, where n is the value in the timx _rcr repetition counter register. ck_psc 00 cen timer clock = ck_cnt counter register update interrupt flag (uif) counter underflow update event (uev) 01 02 03 04 05 06 07 05 04 03 02 01 06 auto-reload preload register fd 36 write a new value in timx_arr auto-reload active register fd 36 ck_psc 36 cen timer clock = ck_cnt counter register update interrupt flag (uif) counter overflow update event (uev) 35 34 33 32 31 30 2f f8 f9 fa fb fc f7 auto-reload preload register fd 36 write a new value in timx_arr auto-reload active register fd 36 RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 303/1317 the repetition counter is decremented: at each counter overflow in upcounting mode, at each counter underflow in downcounting mode, at each counter overflow and at each counter underflow in center-aligned mode. although this limits the maximum number of repetition to 128 pwm cycles, it makes it possible to update the duty cycle twice per pwm period. when refreshing compare registers only once per pwm period in center-aligned mode, maximum resolution is 2xt ck , due to the symmetry of the pattern. the repetition counter is an auto-reload type; the repetition rate is maintained as defined by the timx_rcr register value (refer to figure 85 ). when the update event is generated by software (by setting the ug bit in timx_egr register) or by hardware through the slave mode controller, it occurs immediately whatever the value of the repetition counter is and the repetition counter is reloaded with the content of the timx_rcr register. figure 85. update rate examples depending on mode and timx_rcr register settings center-aligned mode edge-aligned mode uev update event : preload registers transferred to active registers and update interrupt generated counter timx_rcr = 0 timx_rcr = 1 timx_rcr = 2 timx_rcr = 3 update event if the repetition counter underflow occurs when the counter is equal to to the auto-reload value. uev timx_rcr = 3 and re-synchronization (by sw) (by sw) timx_cnt (by sw) upcounting downcounting uev uev uev uev advanced-control timers (tim1&tim8) RM0033 304/1317 doc id 15403 rev 3 13.3.4 clock selection the counter clock can be provided by the following clock sources: internal clock (ck_int) external clock mode1: external input pin external clock mode2: external trigger input etr internal trigger inputs (itrx): using one timer as prescaler for another timer, for example, you can configure timer 1 to act as a prescaler for timer 2. refer to using one timer as prescaler for another for more details. internal clock source (ck_int) if the slave mode controller is disabled (sms=000), then the cen, dir (in the timx_cr1 register) and ug bits (in the timx_egr register) are actual control bits and can be changed only by software (except ug which remains cl eared automatically). as soon as the cen bit is written to 1, the prescaler is clocked by the internal clock ck_int. figure 86 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler. figure 86. control circuit in normal mode, internal clock divided by 1 external clock source mode 1 this mode is selected when sms=111 in the timx_smcr register. the counter can count at each rising or falling edge on a selected input. figure 87. ti2 external clock connection example internal clock 00 counter clock = ck_cnt = ck_psc counter register 01 02 03 04 05 06 07 32 33 34 35 36 31 cen=cnt_en ug cnt_init ck_int encoder mode external clock mode 1 external clock mode 2 internal clock mode etrf trgi ti1f ti2f or or or (internal clock) ck_psc ece timx_smcr sms[2:0] itrx ti1_ed ti1fp1 ti2fp2 etrf timx_smcr ts[2:0] ti2 0 1 timx_ccer cc2p filter icf[3:0] timx_ccmr1 edge detector ti2f_rising ti2f_falling 110 0xx 100 101 111 RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 305/1317 for example, to configure the upcounter to count in response to a rising edge on the ti2 input, use the following procedure: 1. configure channel 2 to detect rising edges on the ti2 input by writing cc2s = ?01? in the timx_ccmr1 register. 2. configure the input filter duration by writing the ic2f[3:0] bits in the timx_ccmr1 register (if no filter is needed, keep ic2f=0000). 3. select rising edge polarity by writ ing cc2p=0 and cc2np=0 in the timx_ccer register. 4. configure the timer in external clock mode 1 by writing sms=111 in the timx_smcr register. 5. select ti2 as the trigger input source by writing ts=110 in the timx_smcr register. 6. enable the counter by writing cen=1 in the timx_cr1 register. note: the capture prescaler is not used for triggering, so you don?t need to configure it. when a rising edge occurs on ti2, the counter counts once and the tif flag is set. the delay between the rising edge on ti2 and the actual clock of the counter is due to the resynchronization circuit on ti2 input. figure 88. control circuit in external clock mode 1 counter clock = ck_cnt = ck_psc counter register 35 36 34 ti2 cnt_en tif write tif=0 advanced-control timers (tim1&tim8) RM0033 306/1317 doc id 15403 rev 3 external clock source mode 2 this mode is selected by writing ece=1 in the timx_smcr register. the counter can count at each rising or falling edge on the external trigger input etr. the figure 89 gives an overview of the external trigger input block. figure 89. external trigger input block for example, to configure the upcounter to count each 2 rising edges on etr, use the following procedure: 1. as no filter is needed in this example, write etf[3:0]=0000 in the timx_smcr register. 2. set the prescaler by writing etps[1:0]=01 in the timx_smcr register 3. select rising edge detection on the etr pin by writing etp=0 in the timx_smcr register 4. enable external clock mode 2 by writing ece=1 in the timx_smcr register. 5. enable the counter by writing cen=1 in the timx_cr1 register. the counter counts once each 2 etr rising edges. the delay between the rising edge on etr and the actual clock of the counter is due to the resynchronization circuit on the etrp signal. figure 90. control circuit in external clock mode 2 etr 0 1 timx_smcr etp divider /1, /2, /4, /8 etps[1:0] etrp filter etf[3:0] downcounter f dts timx_smcr timx_smcr etr pin ck_int encoder mode external clock mode 1 external clock mode 2 internal clock mode etrf trgi ti1f ti2f or or or (internal clock) ck_psc ece timx_smcr sms[2:0] counter clock = ck_cnt = ck_psc counter register 35 36 34 etr cnt_en f ck_int etrp etrf RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 307/1317 13.3.5 capture/compare channels each capture/compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control). figure 91 to figure 94 give an overview of one capture/compare channel. the input stage samples the corresponding tix input to generate a filtered signal tixf. then, an edge detector with polarity selection generates a signal (tixfpx) which can be used as trigger input by the slave mode controller or as the capture command. it is prescaled before the capture register (icxps). figure 91. capture/compare channel (example: channel 1 input stage) the output stage generates an intermediate waveform which is then used for reference: ocxref (active high). the polarity acts at the end of the chain. figure 92. capture/compare channel 1 main circuit ti1 0 1 timx_ccer cc1p/cc1np divider /1, /2, /4, /8 icps[1:0] ti1f_ed filter icf[3:0] downcounter timx_ccmr1 edge detector ti1f_rising ti1f_falling to the slave mode controller ti1fp1 11 01 timx_ccmr1 cc1s[1:0] ic1 ti2fp1 trc (from channel 2) (from slave mode controller) 10 f dts timx_ccer cc1e ic1ps ti1f 0 1 ti2f_rising ti2f_falling (from channel 2) cc1e capture/compare shadow register comparator capture/compare preload register counter ic1ps cc1s[0] cc1s[1] capture input mode s r read ccr1h read ccr1l read_in_progress capture_transfer cc1s[0] cc1s[1] s r write ccr1h write ccr1l write_in_progress output mode uev oc1pe (from time compare_transfer apb bus 8 8 high low (if 16-bit) mcu-peripheral interface tim1_ccmr1 oc1pe base unit) cnt>ccr1 cnt=ccr1 tim1_egr cc1g advanced-control timers (tim1&tim8) RM0033 308/1317 doc id 15403 rev 3 figure 93. output stage of capture/compare channel (channel 1 to 3) figure 94. output stage of capture/compare channel (channel 4) the capture/compare block is made of one preload register and one shadow register. write and read always access the preload register. in capture mode, captures are actually done in the shadow register, which is copied into the preload register. in compare mode, the content of the preload register is copied into the shadow register which is compared to the counter. 13.3.6 input capture mode in input capture mode, the capture/compare registers (timx_ccrx) are used to latch the value of the counter after a transition detected by the corresponding icx signal. when a capture occurs, the corresponding ccxif flag (timx_sr register) is set and an interrupt or a dma request can be sent if they are enabled. if a capture occurs while the ccxif flag was already high, then the over-capture flag ccx of (timx_sr register) is set. ccxif can be cleared by software by writing it to ?0? or by reading the captured data stored in the timx_ccrx register. ccxof is clea red when you write it to ?0?. output mode cnt>ccr1 cnt=ccr1 controller tim1_ccmr1 oc1m[2:0] oc1ref oc1ce dead-time generator oc1_dt oc1n_dt dtg[7:0] tim1_bdtr ?0? ?0? cc1e tim1_ccer cc1ne 0 1 cc1p tim1_ccer 0 1 cc1np tim1_ccer output enable circuit oc1 output enable circuit oc1n cc1e tim1_ccer cc1ne ossi tim1_bdtr moe ossr 0x 10 11 11 10 x0 etr output mode cnt > ccr4 cnt = ccr4 controller tim1_ccmr2 oc2m[2:0] oc4 ref 0 1 cc4p tim1_ccer output enable circuit oc4 cc4e tim1_ccer ossi tim1_bdtr moe to the master mode controller tim1_cr2 ois4 etr RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 309/1317 the following example shows how to capture the counter value in timx_ccr1 when ti1 input rises. to do this, use the following procedure: select the active input: timx_ccr1 must be linked to the ti1 input, so write the cc1s bits to 01 in the timx_ccmr1 register. as soon as cc1s becomes different from 00, the channel is configured in input and the timx_ccr1 register becomes read-only. program the input filter duration you need with respect to the signal you connect to the timer (when the input is one of the tix (icxf bits in the timx_ccmrx register). let?s imagine that, when toggling, the input signal is not stable during at must 5 internal clock cycles. we must program a filter duration longer than these 5 clock cycles. we can validate a transition on ti1 when 8 consecutive samples with the new level have been detected (sampled at f dts frequency). then write ic1f bits to 0011 in the timx_ccmr1 register. select the edge of the active transition on the ti1 channel by writing cc1p and cc1np bits to 0 in the timx_ccer regi ster (rising edge in this case). program the input prescaler. in our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write ic1ps bits to ?00? in the timx_ccmr1 register). enable capture from the counter into the capture register by setting the cc1e bit in the timx_ccer register. if needed, enable the related interrupt request by setting the cc1ie bit in the timx_dier register, and/or the dma request by setting the cc1de bit in the timx_dier register. when an input capture occurs: the timx_ccr1 register gets the value of the counter on the active transition. cc1if flag is set (interrupt flag). cc1of is also set if at least two consecutive captures occurred whereas the flag was not cleared. an interrupt is generated depending on the cc1ie bit. a dma request is generated depending on the cc1de bit. in order to handle the overcapture, it is recommended to read the data before the overcapture flag. this is to avoid missing an overcapture which could happen after reading the flag and before reading the data. note: ic interrupt and/or dma requests can be generated by software by setting the corresponding ccxg bit in the timx_egr register. 13.3.7 pwm input mode this mode is a particular case of input c apture mode. the procedure is the same except: two icx signals are mapped on the same tix input. these 2 icx signals are active on edges with opposite polarity. one of the two tixfp signals is selected as trigger input and the slave mode controller is configured in reset mode. advanced-control timers (tim1&tim8) RM0033 310/1317 doc id 15403 rev 3 for example, you can measure the period (in timx_ccr1 register) and the duty cycle (in timx_ccr2 register) of the pwm applied on ti1 using the following procedure (depending on ck_int frequency and prescaler value): select the active input for timx_ccr1: write the cc1s bits to 01 in the timx_ccmr1 register (ti1 selected). select the active polarity for ti1fp1 (used both for capture in timx_ccr1 and counter clear): write the cc1p and cc1np bits to ?0? (active on rising edge). select the active input for timx_ccr2: write the cc2s bits to 10 in the timx_ccmr1 register (ti1 selected). select the active polarity for ti1fp2 (used for capture in timx_ ccr2): write the cc2p and cc2np bits to ?1? (active on falling edge). select the valid trigger input: write the ts bits to 101 in the timx_smcr register (ti1fp1 selected). configure the slave mode controller in reset mode: write the sms bits to 100 in the timx_smcr register. enable the captures: write the cc1e and cc2e bits to ?1? in the timx_ccer register. figure 95. pwm input mode timing 13.3.8 forced output mode in output mode (ccxs bits = 00 in the timx_ccmrx register), each output compare signal (ocxref and then ocx/ocxn) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. to force an output compare signal (ocxref/ocx) to its active level, you just need to write 101 in the ocxm bits in the corresponding ti mx_ccmrx register. thus ocxref is forced high (ocxref is always active high) and ocx get opposite value to ccxp polarity bit. for example: ccxp=0 (ocx active high) => ocx is forced to high level. the ocxref signal can be forced low by writing the ocxm bits to 100 in the timx_ccmrx register. ti1 timx_cnt 0000 0001 0002 0003 0004 0000 0004 timx_ccr1 timx_ccr2 0004 0002 ic1 capture ic2 capture reset counter ic2 capture pulse width ic1 capture period measurement measurement ai15413 RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 311/1317 anyway, the comparison between the timx_ccrx shadow register and the counter is still performed and allows the flag to be set. interrupt and dma requests can be sent accordingly. this is described in the output compare mode section below. 13.3.9 output compare mode this function is used to control an output waveform or indicating when a period of time has elapsed. when a match is found between the capture/compare register and the counter, the output compare function: assigns the corresponding output pin to a programmable value defined by the output compare mode (ocxm bits in the timx_ccmrx register) and the output polarity (ccxp bit in the timx_ccer register). the output pin can keep its level (ocxm=000), be set active (ocxm=001), be set inactive (ocx m=010) or can toggle (ocxm=011) on match. sets a flag in the interrupt status register (ccxif bit in the timx_sr register). generates an interrupt if the corresponding interrupt mask is set (ccxie bit in the timx_dier register). sends a dma request if the corresponding enable bit is set (ccxde bit in the timx_dier register, ccds bit in the timx_cr2 register for the dma request selection). the timx_ccrx registers can be programmed with or without preload registers using the ocxpe bit in the timx_ccmrx register. in output compare mode, the update event uev has no effect on ocxref and ocx output. the timing resolution is one count of the counter. output compare mode can also be used to output a single pulse (in one pulse mode). procedure: 1. select the counter clock (internal, external, prescaler). 2. write the desired data in the timx_arr and timx_ccrx registers. 3. set the ccxie bit if an interrupt request is to be generated. 4. select the output mode. for example: ? write ocxm = 011 to toggle oc x output pin when cnt matches ccrx ? write ocxpe = 0 to disable preload register ? write ccxp = 0 to select active high polarity ? write ccxe = 1 to enable the output 5. enable the counter by setting the cen bit in the timx_cr1 register. the timx_ccrx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (ocxpe=?0?, else timx_ccrx shadow register is updated only at the next update event uev). an example is given in figure 96 . advanced-control timers (tim1&tim8) RM0033 312/1317 doc id 15403 rev 3 figure 96. output compare mode, toggle on oc1. 13.3.10 pwm mode pulse width modulation mode allows you to generate a signal with a frequency determined by the value of the timx_arr register and a duty cycle determined by the value of the timx_ccrx register. the pwm mode can be selected independently on each channel (one pwm per ocx output) by writing ?110? (pwm mode 1) or ?111? (pwm mode 2) in the ocxm bits in the timx_ccmrx register. you must enable the corresponding preload register by setting the ocxpe bit in the timx_ccmrx register, and even tually the auto-reload preload register (in upcounting or center-aligned modes) by setting the arpe bit in the timx_cr1 register. as the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, you have to initialize all the registers by setting the ug bit in the timx_egr register. ocx polarity is software programmable using the ccxp bit in the timx_ccer register. it can be programmed as active high or active low. ocx output is enabled by a combination of the ccxe, ccxne, moe, ossi and ossr bi ts (timx_ccer and timx_bdtr registers). refer to the timx_ccer register description for more details. in pwm mode (1 or 2), timx_cnt and timx_ccrx are always compared to determine whether timx_ccrx timx_cnt or timx_cnt timx_ccrx (depending on the direction of the counter). the timer is able to generate pwm in edge-aligned mode or center-aligned mode depending on the cms bits in the timx_cr1 register. oc1ref=oc1 tim1_cnt b200 b201 0039 tim1_ccr1 003a write b201h in the cc1r register match detected on ccr1 interrupt generated if enabled 003b b201 003a RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 313/1317 pwm edge-aligned mode upcounting configuration upcounting is active when the dir bit in th e timx_cr1 register is low. refer to the upcounting mode on page 294 . in the following example, we consider pwm mode 1. the reference pwm signal ocxref is high as long as timx_cnt < timx_ccrx else it becomes low. if the compare value in timx_ccrx is greater than the auto-reload value (in timx_arr) then ocxref is held at ?1?. if the compar e value is 0 then ocxref is held at ?0?. figure 97 shows some edge-aligned pwm waveforms in an example where timx_arr=8. figure 97. edge-aligned pwm waveforms (arr=8) downcounting configuration downcounting is active when dir bit in ti mx_cr1 register is high. refer to the downcounting mode on page 297 in pwm mode 1, the reference signal ocxref is low as long as timx_cnt > timx_ccrx else it becomes high. if the compare value in timx_ccrx is greater than the auto-reload value in timx_arr, then ocxref is held at ?1?. 0% pwm is not possible in this mode. pwm center-aligned mode center-aligned mode is active when the cms bits in timx_cr1 register are different from ?00? (all the remaining configurations having the same effect on the ocxref/ocx signals). the compare flag is set when the counter counts up, when it counts down or both when it counts up and down depending on the cms bits configuration. the direction bit (dir) in the timx_cr1 register is updated by hardware and must not be changed by software. refer to the center-aligned mode (up/down counting) on page 299 . figure 98 shows some center-aligned pwm waveforms in an example where: timx_arr=8, pwm mode is the pwm mode 1, the flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for cms=01 in timx_cr1 register. counter register ?1? 0 1234567801 ?0? ocxref ccxif ocxref ccxif ocxref ccxif ocxref ccxif ccrx=4 ccrx=8 ccrx>8 ccrx=0 advanced-control timers (tim1&tim8) RM0033 314/1317 doc id 15403 rev 3 figure 98. cente r-aligned pwm waveforms (arr=8) hints on using center-aligned mode: when starting in center-aligned mode, the current up-down configuration is used. it means that the counter counts up or down depending on the value written in the dir bit in the timx_cr1 register. moreover, the dir and cms bits must not be changed at the same time by the software. writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results. in particular: ? the direction is not updated if you write a value in the counter that is greater than the auto-reload value (timx_cnt>timx_arr). for example, if the counter was counting up, it continues to count up. ? the direction is updated if you write 0 or write the timx_arr value in the counter but no update event uev is generated. the safest way to use center-aligned mode is to generate an update by software (setting the ug bit in the timx_egr register) just before starting the counter and not to write the counter while it is running. # # x ) & # o u n t e r r e g i s t e r # # 2 x / # x 2 % & # - 3 # - 3 # - 3 # # x ) & # # 2 x / # x 2 % & # - 3 o r # # x ) & # # 2 x / # x 2 % & # - 3 # - 3 # - 3 g g # # x ) & # # 2 x / # x 2 % & # - 3 # - 3 # - 3 g g # # x ) & # # 2 x / # x 2 % & # - 3 # - 3 # - 3 g g a i b RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 315/1317 13.3.11 complementary out puts and dead-time insertion the advanced-control timers (tim1&tim8) can output two complementary signals and manage the switching-off and the switching-on instants of the outputs. this time is generally known as dead-time and you have to adjust it depending on the devices you have connected to the outputs and their characteristics (intrinsic delays of level- shifters, delays due to power switches...) you can select the polarity of the outputs (main output ocx or complementary ocxn) independently for each output. this is done by writing to the ccxp and ccxnp bits in the timx_ccer register. the complementary signals ocx and ocxn are activated by a combination of several control bits: the ccxe and ccxne bits in the timx_ccer register and the moe, oisx, oisxn, ossi and ossr bits in the timx_bdtr and timx_cr2 registers. refer to ta bl e 5 7 : output control bits for complementary ocx and ocxn channels with break feature on page 348 for more details. in particular, the dead -time is activated when switching to the idle state (moe falling down to 0). dead-time insertion is enabled by setting both ccxe and ccxne bits, and the moe bit if the break circuit is present. there is one 10-bit dead-time generator for each channel. from a reference waveform ocxref, it generates 2 outputs ocx and ocxn. if ocx and ocxn are active high: the ocx output signal is the same as the re ference signal except for the rising edge, which is delayed relative to the reference rising edge. the ocxn output signal is the opposite of the reference signal except for the rising edge, which is delayed relative to the reference falling edge. if the delay is greater than the width of the active output (ocx or ocxn) then the corresponding pulse is not generated. the following figures show the relationships between the output signals of the dead-time generator and the reference signal ocxref. (we suppose ccxp=0, ccxnp=0, moe=1, ccxe=1 and ccxne=1 in these examples) figure 99. complementary output with dead-time insertion. figure 100. dead-time waveforms with delay greater than the negative pulse. delay delay ocxref ocx ocxn delay ocxref ocx ocxn advanced-control timers (tim1&tim8) RM0033 316/1317 doc id 15403 rev 3 figure 101. dead-time waveforms with delay greater than the positive pulse. the dead-time delay is the same for each of the channels and is programmable with the dtg bits in the timx_bdtr register. refer to section 13.4.18: tim1&tim8 break and dead- time register (timx_bdtr) on page 352 for delay calculation. re-directing ocxref to ocx or ocxn in output mode (forced, output compare or pwm), ocxref can be re-directed to the ocx output or to ocxn output by configuring the ccxe and ccxne bits in the timx_ccer register. this allows you to send a specific waveform (such as pwm or static active level) on one output while the complementary remains at its inactive level. other alternat ive possibilities are to have both outputs at inactive level or both outputs active and complementary with dead-time. note: when only ocxn is enabled (ccxe=0, ccxne=1), it is not complemented and becomes active as soon as ocxref is high. for example, if ccxnp=0 then ocxn=ocxref. on the other hand, when both ocx and ocxn are enabled (ccxe=ccxne=1) ocx becomes active when ocxref is high whereas ocxn is complemented and becomes active when ocxref is low. 13.3.12 using the break function when using the break function, the output enable signals and inactive levels are modified according to additional control bits (moe, ossi and ossr bits in the timx_bdtr register, oisx and oisxn bits in the timx_cr2 register). in any case, the ocx and ocxn outputs cannot be set both to active level at a given time. refer to table 57: output control bits for complementary ocx and ocxn channels with break feature on page 348 for more details. the break source can be either the break input pin or a clock failure event, generated by the clock security system (css), from the reset clock controller. for further information on the clock security system, refer to section 5.2.7: clock security system (css) . when exiting from reset, the break circuit is disabled and the moe bit is low. you can enable the break function by setting the bke bit in the timx_bdtr register. the break input polarity can be selected by configuring the bkp bit in the same register. bke and bkp can be modified at the same time. when the bke and bkp bits are written, a delay of 1 apb clock cycle is applied before the writing is effective. consequently, it is necessary to wait 1 apb clock period to correctly read ba ck the bit after the write operation. because moe falling edge can be asynchronous, a resynchronization circuit has been inserted between the actual signal (acting on the outputs) and the synchronous control bit (accessed in the timx_bdtr register). it results in some delays between the asynchronous and the synchronous signals. in particular, if you write moe to 1 whereas it was low, you delay ocxref ocx ocxn RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 317/1317 must insert a delay (dummy instruction) before reading it correctly. this is because you write the asynchronous signal and read the synchronous signal. when a break occurs (selected level on the break input): the moe bit is cleared asynchronously, putting the outputs in inactive state, idle state or in reset state (selected by the ossi bit). this feature functions even if the mcu oscillator is off. each output channel is driven with the level programmed in the oisx bit in the timx_cr2 register as soon as moe=0. if ossi=0 then the timer releases the enable output else the enable output remains high. when complementary outputs are used: ? the outputs are first put in reset state inactive state (depending on the polarity). this is done asynchronously so that it works even if no clock is provided to the timer. ? if the timer clock is still present, then th e dead-time ge nerator is re activated in order to drive the outputs with the level programmed in the oisx and oisxn bits after a dead-time. even in this case, ocx and ocxn cannot be driven to their active level together. note that becaus e of the resynchronization on moe, the dead-time duration is a bit longer than usual (around 2 ck_tim clock cycles). ? if ossi=0 then the timer releases the enable outputs else the enable outputs remain or become high as soon as on e of the ccxe or ccxne bits is high. the break status flag (bif bit in the timx_sr register) is set. an interrupt can be generated if the bie bit in the timx_dier register is set. a dma request can be sent if the bde bit in the timx_dier register is set. if the aoe bit in the timx_bdtr register is set, the moe bit is automatically set again at the next update event uev. this can be used to perform a regulation, for instance. else, moe remains low until you write it to ?1? again. in this case, it can be used for security and you can connect the break input to an alarm from power drivers, thermal sensors or any security components. note: the break inputs is acting on level. thus, the moe cannot be set while the break input is active (neither automatically nor by software). in the meantime, the status flag bif cannot be cleared. the break can be generated by the brk input which has a programmable polarity and an enable bit bke in the timx_bdtr register. in addition to the break input and the output management, a write protection has been implemented inside the break circuit to safeguard the application. it allows you to freeze the configuration of several parameters (dead-time duration, ocx/ocxn polarities and state when disabled, ocxm configurations, break enable and polarity). you can choose from 3 levels of protection selected by the lock bits in the timx_bdtr register. refer to section 13.4.18: tim1&tim8 break and dead-time register (timx_bdtr) on page 352 . the lock bits can be written only once after an mcu reset. the figure 102 shows an example of behavior of the outputs in response to a break. advanced-control timers (tim1&tim8) RM0033 318/1317 doc id 15403 rev 3 figure 102. output behavior in response to a break. delay ocxref break (moe ocx (ocxn not implemented, ccxp=0, oisx=1) ocx (ocxn not implemented, ccxp=0, oisx=0) ocx (ocxn not implemented, ccxp=1, oisx=1) ocx (ocxn not implemented, ccxp=1, oisx=0) ocx ocxn (ccxe=1, ccxp=0, oisx=0, ccxne=1, ccxnp=0, oisxn=1) delay delay delay ocx ocxn (ccxe=1, ccxp=0, oisx=1, ccxne=1, ccxnp=1, oisxn=1) delay delay delay ocx ocxn (ccxe=1, ccxp=0, oisx=0, ccxne=0, ccxnp=0, oisxn=1) ) delay ocx ocxn (ccxe=1, ccxp=0, oisx=1, ccxne=0, ccxnp=0, oisxn=0) ocx ocxn (ccxe=1, ccxp=0, ccxne=0, ccxnp=0, oisx=oisxn=0 or oisx=oisxn=1) RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 319/1317 13.3.13 clearing the ocxref signal on an external event the ocxref signal for a given channel can be driven low by applying a high level to the etrf input (ocxce enable bit of the corresponding timx_ccmrx register set to ?1?). the ocxref signal remains low until the next update event, uev, occurs. this function can only be used in output compare and pwm modes, and does not work in forced mode. for example, the ocxref signal) can be connected to the output of a comparator to be used for current handling. in this case, the etr must be configured as follow: 1. the external trigger prescaler should be kept off: bits etps[1:0] of the timx_smcr register set to ?00?. 2. the external clock mode 2 must be disabled: bit ece of the timx_smcr register set to ?0?. 3. the external trigger polarity (etp) and the external trigger filter (etf) can be configured according to the user needs. figure 103 shows the behavior of the ocxref signal when the etrf input becomes high, for both values of the enable bit ocxce. in this example, the timer timx is programmed in pwm mode. figure 103. clearing timx ocxref note: in case of a pwm with a 100% duty cycle (if ccrx>arr), then ocxref is enabled again at the next counter overflow. ocxref counter (cnt) ocxref etrf (ocxce=?0?) (ocxce=?1?) ocref_clr becomes high ocref_clr still high (ccrx) advanced-control timers (tim1&tim8) RM0033 320/1317 doc id 15403 rev 3 13.3.14 6-step pwm generation when complementary outputs are used on a channel, preload bits are available on the ocxm, ccxe and ccxne bits. the preload bits are transferred to the shadow bits at the com commutation event. thus you can program in advance the configuration for the next step and change the configuration of all the channels at the same time. com can be generated by software by setting the com bit in the timx_egr register or by hardware (on trgi rising edge). a flag is set when the com event occurs (comif bit in the timx_sr register), which can generate an interrupt (if the comie bit is set in the timx_dier register) or a dma request (if the comde bit is set in the timx_dier register). the figure 104 describes the behavior of the ocx and ocxn outputs when a com event occurs, in 3 different examples of programmed configurations. figure 104. 6-step genera tion, com example (ossr=1) (ccrx) ocx ocxn write com to 1 counter (cnt) ocxref com event ccxe=1 ccxne=0 ocxm=100 ocx ocxn ccxe=0 ccxne=1 ocxm=101 ocx ocxn ccxe=1 ccxne=0 ocxm=100 example 1 example 2 example 3 write ocxm to 100 ccxe=1 ccxne=0 ocxm=100 (forced inactive) ccxe=1 ccxne=0 ocxm=100 (forced inactive) write ccxne to 1 and ocxm to 101 write ccxne to 0 and ocxm to 100 ccxe=1 ccxne=0 ocxm=100 (forced inactive) ai14910 RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 321/1317 13.3.15 one-pulse mode one-pulse mode (opm) is a particular case of the previous modes. it allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. starting the counter can be controlled through the slave mode controller. generating the waveform can be done in output compare mode or pwm mode. you select one-pulse mode by setting the opm bit in the timx_cr1 register. this makes the counter stop automatically at the next update event uev. a pulse can be correctly generated only if the compare value is different from the counter initial value. before starting (when the timer is waiting for the trigger), the configuration must be: in upcounting: cnt < ccrx arr (in particular, 0 < ccrx) in downcounting: cnt > ccrx figure 105. example of one pulse mode. for example you may want to generate a positive pulse on oc1 with a length of t pulse and after a delay of t delay as soon as a positive edge is detected on the ti2 input pin. let?s use ti2fp2 as trigger 1: map ti2fp2 to ti2 by writing cc2s =?01? in the timx_ccmr1 register. ti2fp2 must detect a rising edge, write cc2p=?0? and cc2np=?0? in the timx_ccer register. configure ti2fp2 as trigger for the slave m ode controller (trgi) by writing ts=?110? in the timx_smcr register. ti2fp2 is used to start the counter by writing sms to ?110? in the timx_smcr register (trigger mode). ti2 oc1ref counter t 0 tim1_arr tim1_ccr1 oc1 t delay t pulse advanced-control timers (tim1&tim8) RM0033 322/1317 doc id 15403 rev 3 the opm waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). the t delay is defined by the value writte n in the timx_ccr1 register. the t pulse is defined by the difference between the auto-reload value and the compare value (timx_arr - timx_ccr1). let?s say you want to build a waveform with a transition from ?0? to ?1? when a compare match occurs and a transition from ?1? to ?0? when the counter reaches the auto-reload value. to do this you enable pwm mode 2 by writing oc1m=111 in the timx_ccmr1 register. you can optionally enable the preload registers by writing oc1pe=?1? in the timx_ccmr1 register and arpe in the timx_cr1 register. in this case you have to write the compare value in the timx_ccr1 register, the auto-reload value in the timx_arr register, generate an update by setting the ug bit and wait for external trigger event on ti2. cc1p is written to ?0? in this example. in our example, the dir and cms bits in the timx_cr1 register should be low. you only want 1 pulse (single mode), so you write '1 in the opm bit in the timx_cr1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0). when opm bit in the timx_cr1 register is set to '0', so the repetitive mode is selected. particular case: ocx fast enable: in one-pulse mode, the edge detection on tix input set the cen bit which enables the counter. then the comparison between the counter and the compare value makes the output toggle. but several clock cycles are needed for these operations and it limits the minimum delay t delay min we can get. if you want to output a waveform with the minimum delay, you can set the ocxfe bit in the timx_ccmrx register. then ocxref (and ocx) are forced in response to the stimulus, without taking in account the comparison. its new level is the same as if a compare match had occurred. ocxfe acts only if the channel is configured in pwm1 or pwm2 mode. 13.3.16 encoder interface mode to select encoder interface mode write sms=?001? in the timx_smcr register if the counter is counting on ti2 edges only, sms=?010? if it is counting on ti1 edges only and sms=?011? if it is counting on both ti1 and ti2 edges. select the ti1 and ti2 polarity by programming the cc1p and cc2p bits in the timx_ccer register. when needed, you can program the input filter as well. cc1np and cc2np must be kept low. the two inputs ti1 and ti2 are used to interface to an incremental encoder. refer to ta bl e 5 5 . the counter is clocked by each valid transition on ti1fp1 or ti2fp2 (ti1 and ti2 after input filter and polarity selection, ti1fp1=ti1 if not filtered and not inverted, ti2fp2=ti2 if not filtered and not inverted) assuming that it is enabled (cen bit in timx_cr1 register written to ?1?). the sequence of transitions of the two inputs is evaluated and generates count pulses as well as the dire ction signal. depending on the sequence the counter counts up or down, the dir bit in the timx_cr1 register is modified by hardware accordingly. the dir bit is calculated at each transition on any input (ti1 or ti2), whatever the counter is counting on ti1 only, ti2 only or both ti1 and ti2. encoder interface mode acts simply as an ex ternal clock with direction selection. this means that the counter just counts continuously between 0 and the auto-reload value in the timx_arr register (0 to arr or arr down to 0 depending on the direction). so you must RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 323/1317 configure timx_arr before starting. in the same way, the capture, compare, prescaler, repetition counter, trigger output features continue to work as normal. encoder mode and external clock mode 2 are not compatible and must not be selected together. in this mode, the counter is modified automatically following the speed and the direction of the incremental encoder and its content, therefore, always represents the encoder?s position. the count direction correspond to the rotation direction of the connected sensor. the table summarizes the possible combinations, assuming ti1 and ti2 don?t switch at the same time. an external incremental encoder can be connected directly to the mcu without external interface logic. however, comparators are normally be used to convert the encoder?s differential outputs to digital signals. this greatly increases noise immunity. the third encoder output which indicate the mechanical zero position, may be connected to an external interrupt input and trigger a counter reset. the figure 106 gives an example of counter operation, showing count signal generation and direction control. it also shows how input jitter is compensated where both edges are selected. this might occur if the sensor is positioned near to one of the switching points. for this example we assume that the configuration is the following: cc1s=?01? (timx_ccmr1 register, ti1fp1 mapped on ti1). cc2s=?01? (timx_ccmr2 register, ti1fp2 mapped on ti2). cc1p=?0? and cc1np=?0? (timx_ccer register, ti1fp1 non-inverted, ti1fp1=ti1). cc2p=?0? and cc2np=?0? (timx_ccer register, ti1fp2 non-inverted, ti1fp2= ti2). sms=?011? (timx_smcr register, both inputs are active on both rising and falling edges). cen=?1? (timx_cr1 register, counter enabled). table 55. counting direction versus encoder signals active edge level on opposite signal (ti1fp1 for ti2, ti2fp2 for ti1) ti1fp1 signal ti2fp2 signal rising falling rising falling counting on ti1 only high down up no count no count low up down no count no count counting on ti2 only high no count no count up down low no count no count down up counting on ti1 and ti2 high down up up down low up down down up advanced-control timers (tim1&tim8) RM0033 324/1317 doc id 15403 rev 3 figure 106. example of counter operation in encoder interface mode. figure 107 gives an example of counter behavior when ti1fp1 polarity is inverted (same configuration as above except cc1p=?1?). figure 107. example of encoder interface mode with ti1fp1 polarity inverted. the timer, when configured in encoder interface mode provides information on the sensor?s current position. you can obtain dynamic information (speed, acceleration, deceleration) by measuring the period between two encoder events using a second timer configured in capture mode. the output of the encoder which indicates the mechanical zero can be used for this purpose. depending on the time between two events, the counter can also be read at regular times. you can do this by latching the counter value into a third input capture register if available (then the capture signal must be periodic and can be generated by another timer). when available, it is also possible to read its value through a dma request generated by a real-time clock. ti1 forward forward backward jitter jitter up down up ti2 counter ti1 forward forward backward jitter jitter up down ti2 counter down RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 325/1317 13.3.17 timer input xor function the ti1s bit in the timx_cr2 register, allows the input filter of channel 1 to be connected to the output of a xor gate, combining the three input pins timx_ch1, timx_ch2 and timx_ch3. the xor output can be used with all the timer input functions such as trigger or input capture. an example of this feature used to interface hall sensors is given in section 13.3.18 below. 13.3.18 interfacing with hall sensors this is done using the advanced-control timers (tim1 or tim8) to generate pwm signals to drive the motor and another timer timx (tim2, tim3, tim4 or tim5) referred to as ?interfacing timer? in figure 108 . the ?interfacing timer? captures the 3 timer input pins (cc1, cc2, cc3) connected through a xor to the ti1 input channel (selected by setting the ti1s bit in the timx_cr2 register). the slave mode controller is configured in reset mode; the slave input is ti1f_ed. thus, each time one of the 3 inputs toggles, the counter restarts counting from 0. this creates a time base triggered by any change on the hall inputs. on the ?interfacing timer?, capture/compare channel 1 is configured in capture mode, capture signal is trc (see figure 91: capture/compare channel (example: channel 1 input stage) on page 307 ). the captured value, which corresponds to the time elapsed between 2 changes on the inputs, gives information about motor speed. the ?interfacing timer? can be used in output mode to generate a pulse which changes the configuration of the channels of the advanced-control timer (tim1 or tim8) (by triggering a com event). the tim1 timer is used to generate pwm signals to drive the motor. to do this, the interfacing timer channel must be programmed so that a positive pulse is generated after a programmed delay (in output compare or pwm mode). this pulse is sent to the advanced- control timer (tim1 or tim8) through the trgo output. example: you want to change the pwm configuration of your advanced-control timer tim1 after a programmed delay each time a change occurs on the hall inputs connected to one of the timx timers. configure 3 timer inputs ored to the ti1 input channel by writing the ti1s bit in the timx_cr2 register to ?1?, program the time base: write the timx_arr to the max value (the counter must be cleared by the ti1 change. set the prescaler to get a maximum counter period longer than the time between 2 changes on the sensors, program the channel 1 in capture mode (trc selected): write the cc1s bits in the timx_ccmr1 register to ?01?. you can also program the digital filter if needed, program the channel 2 in pwm 2 mode with the desired delay: write the oc2m bits to ?111? and the cc2s bits to ?00? in the timx_ccmr1 register, select oc2ref as trigger output on trgo: write the mms bits in the timx_cr2 register to ?101?, in the advanced-control timer tim1, the right itr input must be selected as trigger input, the timer is programmed to generate pwm signals, the capture/compare control signals are preloaded (ccpc=1 in the timx_cr2 register) and the com event is controlled by the trigger input (ccus=1 in the timx_cr2 register). the pwm control bits (ccxe, ocxm) are advanced-control timers (tim1&tim8) RM0033 326/1317 doc id 15403 rev 3 written after a com event for the next step (this can be done in an interrupt subroutine generated by the rising edge of oc2ref). the figure 108 describes this example. figure 108. example of hall sensor interface co u nter (cnt) trgo=oc2ref (ccr2) oc1 oc1n com write ccxe, ccxne tih1 tih2 tih 3 ccr1 oc2 oc2n oc 3 oc 3 n c7a 3 c7a 8 c794 c7a5 c7ab c796 a nd ocxm for next s tep interf a cing timer a dv a nced-control timer s (tim1&tim 8 ) a i17 33 5 RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 327/1317 13.3.19 timx and external trigger synchronization the timx timer can be synchronized with an external trigger in several modes: reset mode, gated mode and trigger mode. slave mode: reset mode the counter and its prescaler can be reinitialized in response to an event on a trigger input. moreover, if the urs bit from the timx_cr1 register is low, an update event uev is generated. then all the preloaded registers (timx_arr, timx_ccrx) are updated. in the following example, the upcounter is cleared in response to a rising edge on ti1 input: configure the channel 1 to detect rising edges on ti1. configure the input filter duration (in this example, we don?t need any filter, so we keep ic1f=0000). the capture prescaler is not used for triggering, so you don?t need to configure it. the cc1s bits select the input capture source only, cc1s = 01 in the timx_ccmr1 register. write cc1p=0 and cc1np=?0? in timx_ccer register to validate the polarity (and detect rising edges only). configure the timer in reset mode by writ ing sms=100 in timx_smcr register. select ti1 as the input source by writi ng ts=101 in timx_smcr register. start the counter by writing cen=1 in the timx_cr1 register. the counter starts counting on the internal clock, then behaves normally until ti1 rising edge. when ti1 rises, the counter is cleared and restarts from 0. in the meantime, the trigger flag is set (tif bit in the timx_sr register) and an interrupt request, or a dma request can be sent if enabled (depending on the tie and tde bits in timx_dier register). the following figure shows this behavior when the auto-reload register timx_arr=0x36. the delay between the rising edge on ti1 and the actual reset of the counter is due to the resynchronization circuit on ti1 input. figure 109. control circuit in reset mode 00 counter clock = ck_cnt = ck_psc counter register 01 02 03 00 01 02 03 32 33 34 35 36 ug ti1 31 30 tif advanced-control timers (tim1&tim8) RM0033 328/1317 doc id 15403 rev 3 slave mode: gated mode the counter can be enabled depending on the level of a selected input. in the following example, the upcounter counts only when ti1 input is low: configure the channel 1 to detect low levels on ti1. configure the input filter duration (in this example, we don?t need any filter, so we keep ic1f=0000). the capture prescaler is not used for triggering, so you don?t need to configure it. the cc1s bits select the input capture source only, cc1s=01 in timx_ccmr1 register. write cc1p=1 and cc1np=?0? in timx_ccer register to validate the polarity (and detect low level only). configure the timer in gated mode by writing sms=101 in timx_smcr register. select ti1 as the input source by writi ng ts=101 in timx_smcr register. enable the counter by writing cen=1 in the timx_cr1 register (in gated mode, the counter doesn?t start if cen=0, what ever is the trigger input level). the counter starts counting on the internal clock as long as ti1 is low and stops as soon as ti1 becomes high. the tif flag in the timx_sr register is set both when the counter starts or stops. the delay between the rising edge on ti1 and the actual stop of the counter is due to the resynchronization circuit on ti1 input. figure 110. control circuit in gated mode counter clock = ck_cnt = ck_psc counter register 35 36 37 38 32 33 34 ti1 31 30 cnt_en tif write tif=0 RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 329/1317 slave mode: trigger mode the counter can start in response to an event on a selected input. in the following example, the upcounter starts in response to a rising edge on ti2 input: configure the channel 2 to detect rising edges on ti2. configure the input filter duration (in this example, we don?t need any filter, so we keep ic2f=0000). the capture prescaler is not used for triggering, so you don?t need to configure it. the cc2s bits are configured to select the input capture source only, cc2s=01 in timx_ccmr1 register. write cc2p=1 and cc2np=0 in timx_ccer register to validate the polarity (and detect low level only). configure the timer in trigger mode by writ ing sms=110 in timx_smcr register. select ti2 as the input source by writi ng ts=110 in timx_smcr register. when a rising edge occurs on ti2, the counter starts counting on the internal clock and the tif flag is set. the delay between the rising edge on ti2 and the actual start of the counter is due to the resynchronization circuit on ti2 input. figure 111. control circuit in trigger mode slave mode: external clock mode 2 + trigger mode the external clock mode 2 can be used in addition to another slave mode (except external clock mode 1 and encoder mode). in this case, the etr signal is used as external clock input, and another input can be selected as trigger input (in reset mode, gated mode or trigger mode). it is recommended not to select etr as trgi through the ts bits of timx_smcr register. in the following example, the upcounter is incremented at each rising edge of the etr signal as soon as a rising edge of ti1 occurs: 1. configure the external trigger input circui t by programming the timx_smcr register as follows: ? etf = 0000: no filter ? etps=00: prescaler disabled ? etp=0: detection of rising edges on etr and ece=1 to enable the external clock mode 2. counter clock = ck_cnt = ck_psc counter register 35 36 37 38 34 ti2 cnt_en tif advanced-control timers (tim1&tim8) RM0033 330/1317 doc id 15403 rev 3 2. configure the channel 1 as follows, to detect rising edges on ti: ? ic1f=0000: no filter. ? the capture prescaler is not used for triggering and does not need to be configured. ? cc1s=01in timx_ccmr1 register to select only the input capture source ? cc1p=0 and cc1np=?0? in timx_ccer regi ster to validate the polarity (and detect rising edge only). 3. configure the timer in trigger mode by wr iting sms=110 in timx_smcr register. select ti1 as the input source by writi ng ts=101 in timx_smcr register. a rising edge on ti1 enables the counter and sets the tif flag. the counter then counts on etr rising edges. the delay between the rising edge of the etr signal and the actual reset of the counter is due to the resynchronization circuit on etrp input. figure 112. control circuit in external clock mode 2 + trigger mode 13.3.20 timer synchronization the tim timers are linked together internally for timer synchronization or chaining. refer to section 14.3.15: timer synchronization on page 388 for details. 13.3.21 debug mode when the microcontroller enters debug mode (cortex-m3 core halted), the timx counter either continues to work normally or stops, depending on dbg_timx_stop configuration bit in dbg module. for more details, refer to section 32.16.2: debug support for timers, watchdog, bxcan and i 2 c . counter clock = ck_cnt = ck_psc counter register 35 36 34 etr cen/cnt_en tif ti1 RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 331/1317 13.4 tim1&tim8 registers refer to section 1.1 on page 46 for a list of abbreviations used in register descriptions. 13.4.1 tim1&tim8 control register 1 (timx_cr1) address offset: 0x00 reset value: 0x0000 1514131211109876543210 reserved ckd[1:0] arpe cms[1:0] dir opm urs udis cen rw rw rw rw rw rw rw rw rw rw bits 15:10 reserved, always read as 0 bits 9:8 ckd[1:0] : clock division this bit-field indicates the division ratio between the timer clock (ck_int) frequency and the dead-time and sampling clock (t dts )used by the dead-time generators and the digital filters (etr, tix), 00: t dts =t ck_int 01: t dts =2*t ck_int 10: t dts =4*t ck_int 11: reserved, do not program this value bit 7 arpe : auto-reload preload enable 0: timx_arr register is not buffered 1: timx_arr register is buffered bits 6:5 cms[1:0] : center-aligned mode selection 00: edge-aligned mode. the counter counts up or down depending on the direction bit (dir). 01: center-aligned mode 1. the counter counts up and down alternatively. output compare interrupt flags of channels configured in output (ccxs=00 in timx_ccmrx register) are set only when the counter is counting down. 10: center-aligned mode 2. the counter counts up and down alternatively. output compare interrupt flags of channels configured in output (ccxs=00 in timx_ccmrx register) are set only when the counter is counting up. 11: center-aligned mode 3. the counter counts up and down alternatively. output compare interrupt flags of channels configured in output (ccxs=00 in timx_ccmrx register) are set both when the counter is counting up or down. note: it is not allowed to switch from edge-a ligned mode to center-aligned mode as long as the counter is enabled (cen=1) bit 4 dir : direction 0: counter used as upcounter 1: counter used as downcounter note: this bit is read only when the timer is configured in center-aligned mode or encoder mode. bit 3 opm : one pulse mode 0: counter is not stopped at update event 1: counter stops counting at the next update event (clearing the bit cen) advanced-control timers (tim1&tim8) RM0033 332/1317 doc id 15403 rev 3 13.4.2 tim1&tim8 control register 2 (timx_cr2) address offset: 0x04 reset value: 0x0000 bit 2 urs : update request source this bit is set and cleared by softw are to select the uev event sources. 0: any of the following events generate an update interrupt or dma request if enabled. these events can be: ? counter overflow/underflow ? setting the ug bit ? update generation through the slave mode controller 1: only counter overflow/underflow genera tes an update interrupt or dma request if enabled. bit 1 udis : update disable this bit is set and cleared by software to enable/disable uev event generation. 0: uev enabled. the update (uev) event is generated by one of the following events: ? counter overflow/underflow ? setting the ug bit ? update generation through the slave mode controller buffered registers are then loaded with their preload values. 1: uev disabled. the update event is not g enerated, shadow registers keep their value (arr, psc, ccrx). however the counter and the pr escaler are reinitialized if the ug bit is set or if a hardware reset is received from the slave mode controller. bit 0 cen : counter enable 0: counter disabled 1: counter enabled note: external clock, gated mode and encoder mode can work only if the cen bit has been previously set by software. however trigger mode can set the cen bit automatically by hardware. 1514131211109876543210 res. ois4 ois3n ois3 ois2n ois2 ois1n ois1 ti1s mms[2:0] ccds ccus res. ccpc rw rw rw rw rw rw rw rw rw rw rw rw rw rw bit 15 reserved, always read as 0 bit 14 ois4 : output idle stat e 4 (oc4 output) refer to ois1 bit bit 13 ois3n : output idle state 3 (oc3n output) refer to ois1n bit bit 12 ois3 : output idle stat e 3 (oc3 output) refer to ois1 bit bit 11 ois2n : output idle state 2 (oc2n output) refer to ois1n bit bit 10 ois2 : output idle stat e 2 (oc2 output) refer to ois1 bit RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 333/1317 bit 9 ois1n : output idle state 1 (oc1n output) 0: oc1n=0 after a dead-time when moe=0 1: oc1n=1 after a dead-time when moe=0 note: this bit can not be modified as long as lock level 1, 2 or 3 has been programmed (lock bits in timx_bdtr register). bit 8 ois1 : output idle stat e 1 (oc1 output) 0: oc1=0 (after a dead-time if oc1n is implemented) when moe=0 1: oc1=1 (after a dead-time if oc1n is implemented) when moe=0 note: this bit can not be modified as long as lock level 1, 2 or 3 has been programmed (lock bits in timx_bdtr register). bit 7 ti1s : ti1 selection 0: the timx_ch1 pin is connected to ti1 input 1: the timx_ch1, ch2 and ch3 pins are conn ected to the ti1 input (xor combination) bits 6:4 mms[1:0] : master mode selection these bits allow to select the information to be sent in master mode to slave timers for synchronization (trgo). the combination is as follows: 000: reset - the ug bit from the timx_egr register is used as trigger output (trgo). if the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on trgo is delayed compared to the actual reset. 001: enable - the counter enable signal cnt_en is used as trigger output (trgo). it is useful to start several timers at the same time or to control a window in which a slave timer is enable. the counter enable signal is generat ed by a logic or between cen control bit and the trigger input when configured in gated mode. when the counter enable signal is controlled by the trigger input, there is a dela y on trgo, except if the master/slave mode is selected (see the msm bit descr iption in timx_smcr register). 010: update - the update event is selected as tr igger output (trgo). for instance a master timer can then be used as a prescaler for a slave timer. 011: compare pulse - the trigger output send a positive pulse when the cc1if flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (trgo). 100: compare - oc1ref signal is used as trigger output (trgo) 101: compare - oc2ref signal is used as trigger output (trgo) 110: compare - oc3ref signal is used as trigger output (trgo) 111: compare - oc4ref signal is used as trigger output (trgo) bit 3 ccds : capture/compare dma selection 0: ccx dma request sent when ccx event occurs 1: ccx dma requests sent when update event occurs bit 2 ccus : capture/compare cont rol update selection 0: when capture/compare control bits are pr eloaded (ccpc=1), they are updated by setting the comg bit only 1: when capture/compare control bits are pr eloaded (ccpc=1), they are updated by setting the comg bit or when an rising edge occurs on trgi note: this bit acts only on channels that have a complementary output. bit 1 reserved, always read as 0 bit 0 ccpc : capture/compare preloaded control 0: ccxe, ccxne and ocxm bits are not preloaded 1: ccxe, ccxne and ocxm bits are preloaded, after having been written, they are updated only when a commutation event (com) occurs (comg bit set or rising edge detected on trgi, depending on the ccus bit). note: this bit acts only on channels that have a complementary output. advanced-control timers (tim1&tim8) RM0033 334/1317 doc id 15403 rev 3 13.4.3 tim1&tim8 slave mode control register (timx_smcr) address offset: 0x08 reset value: 0x0000 1514131211109876543210 etp ece etps[1:0] etf[3:0] msm ts[2:0] res. sms[2:0] rw rw rw rw rw rw rw rw rw rw rw rw res. rw rw rw bit 15 etp : external trigger polarity this bit selects wh ether etr or etr is used for trigger operations 0: etr is non-inverted, active at high level or rising edge. 1: etr is inverted, active at low level or falling edge. bit 14 ece : external clock enable this bit enables external clock mode 2. 0: external clock mode 2 disabled 1: external clock mode 2 enabled. the counter is clocked by any active edge on the etrf signal. note: 1: setting the ece bit has the same effect as selecting external clock mode 1 with trgi connected to etrf (sms=111 and ts=111). 2: it is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. nevertheless, trgi must not be connected to etrf in this case (ts bits must not be 111). 3: if external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is etrf. bits 13:12 etps[1:0] : external trigger prescaler external trigger signal etrp frequency must be at most 1/4 of timxclk frequency. a prescaler can be enabled to reduce etrp frequenc y. it is useful when inputting fast external clocks. 00: prescaler off 01: etrp frequency divided by 2 10: etrp frequency divided by 4 11: etrp frequency divided by 8 RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 335/1317 bits 11:8 etf[3:0] : external trigger filter this bit-field then defines the frequency used to sample etrp signal and the length of the digital filter applied to etrp. the digital filter is made of an event counter in which n events are needed to validate a tr ansition on the output: 0000: no filter, sampling is done at f dts 0001: f sampling =f ck_int , n=2 0010: f sampling =f ck_int , n=4 0011: f sampling =f ck_int , n=8 0100: f sampling =f dts /2, n=6 0101: f sampling =f dts /2, n=8 0110: f sampling =f dts /4, n=6 0111: f sampling =f dts /4, n=8 1000: f sampling =f dts /8, n=6 1001: f sampling =f dts /8, n=8 1010: f sampling =f dts /16, n=5 1011: f sampling =f dts /16, n=6 1100: f sampling =f dts /16, n=8 1101: f sampling =f dts /32, n=5 1110: f sampling =f dts /32, n=6 1111: f sampling =f dts /32, n=8 bit 7 msm: master/slave mode 0: no action 1: the effect of an event on the trigger input (trgi) is delayed to allow a perfect synchronization between the current timer and its sl aves (through trgo). it is useful if we want to synchronize several timers on a single external event. bits 6:4 ts[2:0]: trigger selection this bit-field selects the trigger input to be used to synch ronize the counter. 000: internal trigger 0 (itr0) 001: internal trigger 1 (itr1) 010: internal trigger 2 (itr2) 011: internal trigger 3 (itr3) 100: ti1 edge detector (ti1f_ed) 101: filtered timer input 1 (ti1fp1) 110: filtered timer input 2 (ti2fp2) 111: external trigger input (etrf) see table 56: timx internal trigger connection on page 336 for more details on itrx meaning for each timer. note: these bits must be changed only when they are not used (e.g. when sms=000) to avoid wrong edge detections at the transition. bit 3 reserved, always read as 0. advanced-control timers (tim1&tim8) RM0033 336/1317 doc id 15403 rev 3 13.4.4 tim1&tim8 dma/ interrupt enable r egister (timx_dier) address offset: 0x0c reset value: 0x0000 bits 2:0 sms: slave mode selection when external signals are selected the active edge of the trigger signal (trgi) is linked to the polarity selected on the external input (s ee input control register and control register description. 000: slave mode disabled - if cen = ?1? then the pr escaler is clocked directly by the internal clock. 001: encoder mode 1 - counter counts up/down on ti2fp2 edge depending on ti1fp1 level. 010: encoder mode 2 - counter counts up/down on ti1fp1 edge depending on ti2fp2 level. 011: encoder mode 3 - counter counts up/down on both ti1fp1 and ti2fp2 edges depending on the level of the other input. 100: reset mode - rising edge of the selected tr igger input (trgi) reinitializes the counter and generates an update of the registers. 101: gated mode - the counter clock is enabled when the trigger input (trgi) is high. the counter stops (but is not reset) as soon as the trigger becomes low. both start and stop of the counter are controlled. 110: trigger mode - the counter starts at a ri sing edge of the trigger trgi (but it is not reset). only the start of the counter is controlled. 111: external clock mode 1 - rising edges of the selected trigger (trgi) clock the counter. note: the gated mode must not be used if ti1f_ed is selected as the trigger input (ts=?100?). indeed, ti1f_ed outputs 1 pulse for each transition on ti1f, whereas the gated mode checks the level of the trigger signal. table 56. timx internal trigger connection slave tim itr0 (ts = 000) itr1 (ts = 001) itr2 (ts = 010) itr3 (ts = 011) tim1 tim5 tim2 tim3 tim4 tim8 tim1 tim2 tim4 tim5 1514131211109876543210 res. tde comde cc4de cc3de cc2de cc1de ude bie tie comie cc4ie cc3ie cc2ie cc1ie uie rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bit 15 reserved, always read as 0. bit 14 tde : trigger dma request enable 0: trigger dma request disabled 1: trigger dma request enabled bit 13 comde : com dma request enable 0: com dma request disabled 1: com dma request enabled bit 12 cc4de : capture/compare 4 dma request enable 0: cc4 dma request disabled 1: cc4 dma request enabled RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 337/1317 bit 11 cc3de : capture/compare 3 dma request enable 0: cc3 dma request disabled 1: cc3 dma request enabled bit 10 cc2de : capture/compare 2 dma request enable 0: cc2 dma request disabled 1: cc2 dma request enabled bit 9 cc1de : capture/compare 1 dma request enable 0: cc1 dma request disabled 1: cc1 dma request enabled bit 8 ude : update dma request enable 0: update dma request disabled 1: update dma request enabled bit 7 bie : break interrupt enable 0: break interrupt disabled 1: break interrupt enabled bit 6 tie : trigger interrupt enable 0: trigger interrupt disabled 1: trigger interrupt enabled bit 5 comie : com interrupt enable 0: com interrupt disabled 1: com interrupt enabled bit 4 cc4ie : capture/compare 4 interrupt enable 0: cc4 interrupt disabled 1: cc4 interrupt enabled bit 3 cc3ie : capture/compare 3 interrupt enable 0: cc3 interrupt disabled 1: cc3 interrupt enabled bit 2 cc2ie : capture/compare 2 interrupt enable 0: cc2 interrupt disabled 1: cc2 interrupt enabled bit 1 cc1ie : capture/compare 1 interrupt enable 0: cc1 interrupt disabled 1: cc1 interrupt enabled bit 0 uie : update interrupt enable 0: update interrupt disabled 1: update interrupt enabled advanced-control timers (tim1&tim8) RM0033 338/1317 doc id 15403 rev 3 13.4.5 tim1&tim8 stat us register (timx_sr) address offset: 0x10 reset value: 0x0000 1514131211109876543210 reserved cc4of cc3of cc2of cc1of res. bif tif c omif cc4if cc3if cc2if cc1if uif rc_w0 rc_w0 rc_w0 rc_w0 res. rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 bits 15:13 reserved, always read as 0. bit 12 cc4of : capture/compare 4 overcapture flag refer to cc1of description bit 11 cc3of : capture/compare 3 overcapture flag refer to cc1of description bit 10 cc2of : capture/compare 2 overcapture flag refer to cc1of description bit 9 cc1of : capture/compare 1 overcapture flag this flag is set by hardware only when the corresponding channel is configured in input capture mode. it is cleared by software by writing it to ?0?. 0: no overcapture has been detected. 1: the counter value has been captured in timx_ccr1 register while cc1if flag was already set bit 8 reserved, always read as 0. bit 7 bif : break interrupt flag this flag is set by hardware as soon as the break input goes active. it can be cleared by software if the break input is not active. 0: no break event occurred. 1: an active level has been detected on the break input. bit 6 tif : trigger interrupt flag this flag is set by hardware on trigger even t (active edge detected on trgi input when the slave mode controller is enabled in all modes but gated mode. it is set when the counter starts or stops when gated mode is selected. it is cleared by software. 0: no trigger event occurred. 1: trigger interrupt pending. bit 5 comif : com interrupt flag this flag is set by hardware on com event (when capture/compare control bits - ccxe, ccxne, ocxm - have been updated). it is cleared by software. 0: no com event occurred. 1: com interrupt pending. bit 4 cc4if : capture/compare 4 interrupt flag refer to cc1if description bit 3 cc3if : capture/compare 3 interrupt flag refer to cc1if description RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 339/1317 13.4.6 tim1&tim8 event gene ration register (timx_egr) address offset: 0x14 reset value: 0x0000 bit 2 cc2if : capture/compare 2 interrupt flag refer to cc1if description bit 1 cc1if : capture/compare 1 interrupt flag if channel cc1 is configured as output: this flag is set by hardware when the coun ter matches the compare value, with some exception in center-aligned mode (refer to the cms bits in the timx_cr1 register description). it is cleared by software. 0: no match. 1: the content of the counter timx_cnt matches the conten t of the timx_ccr1 register. when the contents of timx_ccr1 are greater than the contents of timx_arr, the cc1if bit goes high on the counter overflow (in upcounting and up/down-counting modes) or underflow (in downcounting mode) if channel cc1 is configured as input: this bit is set by hardware on a capture. it is cleared by software or by reading the timx_ccr1 register. 0: no input capture occurred 1: the counter value has been captured in timx_ccr1 register (an edge has been detected on ic1 which matches the selected polarity) bit 0 uif : update interrupt flag this bit is set by hardware on an update event. it is cleared by software. 0: no update occurred. 1: update interrupt pending. this bit is se t by hardware when the registers are updated: ?at overflow or underflow regarding the repet ition counter value (update if repetition counter = 0) and if the udis=0 in the timx_cr1 register. ?when cnt is reinitialized by software using the ug bit in timx_egr register, if urs=0 and udis=0 in the timx_cr1 register. ?when cnt is reinitialized by a trigger event (refer to section 13.4.3: tim1&tim8 slave mode control register (timx_smcr) ), if urs=0 and udis=0 in the timx_cr1 register. 1514131211109876543210 reserved bg tg comg cc4g cc3g cc2g cc1g ug wwwwwwww bits 15:8 reserved, always read as 0. bit 7 bg : break generation this bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: no action 1: a break event is generated. moe bit is clea red and bif flag is set. related interrupt or dma transfer can occur if enabled. advanced-control timers (tim1&tim8) RM0033 340/1317 doc id 15403 rev 3 bit 6 tg : trigger generation this bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: no action 1: the tif flag is set in timx_sr register. re lated interrupt or dma transfer can occur if enabled. bit 5 comg : capture/compare cont rol update generation this bit can be set by software, it is automatically cleared by hardware 0: no action 1: when ccpc bit is set, it allows to update ccxe, ccxne and ocxm bits note: this bit acts only on channels having a complementary output. bit 4 cc4g : capture/compare 4 generation refer to cc1g description bit 3 cc3g : capture/compare 3 generation refer to cc1g description bit 2 cc2g : capture/compare 2 generation refer to cc1g description bit 1 cc1g : capture/compare 1 generation this bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: no action 1: a capture/compare event is generated on channel 1: if channel cc1 is configured as output: cc1if flag is set, corresponding interrupt or dma request is sent if enabled. if channel cc1 is configured as input: the current value of the counter is captured in timx_ccr1 regi ster. the cc1if flag is set, the corresponding interrupt or dma request is sent if enabled. the cc1of flag is set if the cc1if flag was already high. bit 0 ug : update generation this bit can be set by software, it is automatically cleared by hardware. 0: no action 1: reinitialize the counter and generates an up date of the registers. note that the prescaler counter is cleared too (anyway the prescaler rati o is not affected). the counter is cleared if the center-aligned mode is selected or if dir= 0 (upcounting), else it takes the auto-reload value (timx_arr) if dir=1 (downcounting). RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 341/1317 13.4.7 tim1&tim8 capt ure/compare mode regist er 1 (timx_ccmr1) address offset: 0x18 reset value: 0x0000 the channels can be used in input (capture mode) or in output (compare mode). the direction of a channel is defined by configuring the corresponding ccxs bits. all the other bits of this register have a different function in input and in output mode. for a given bit, ocxx describes its function when the channel is configured in output, icxx describes its function when the channel is configured in input. so you must take care that the same bit can have a different meaning for the input stage and for the output stage. output compare mode: 1514131211109876543210 oc2 ce oc2m[2:0] oc2 pe oc2 fe cc2s[1:0] oc1 ce oc1m[2:0] oc1 pe oc1 fe cc1s[1:0] ic2f[3:0] ic2psc[1:0] ic1f[3:0] ic1psc[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bit 15 oc2ce: output compare 2 clear enable bits 14:12 oc2m[2:0] : output compare 2 mode bit 11 oc2pe : output compare 2 preload enable bit 10 oc2fe : output compare 2 fast enable bits 9:8 cc2s[1:0] : capture/compare 2 selection this bit-field defines the direction of the chan nel (input/output) as well as the used input. 00: cc2 channel is configured as output 01: cc2 channel is configured as input, ic2 is mapped on ti2 10: cc2 channel is configured as input, ic2 is mapped on ti1 11: cc2 channel is configured as input, ic2 is mapped on trc. this mode is working only if an internal trigger input is selected through the ts bit (timx_smcr register) note: cc2s bits are writable only when the c hannel is off (cc2e = ?0? in timx_ccer). bit 7 oc1ce: output compare 1 clear enable oc1ce: output compare 1 clear enable 0: oc1ref is not affected by the etrf input 1: oc1ref is cleared as soon as a high level is detected on etrf input advanced-control timers (tim1&tim8) RM0033 342/1317 doc id 15403 rev 3 bits 6:4 oc1m : output compare 1 mode these bits define the behavior of the output reference sign al oc1ref from which oc1 and oc1n are derived. oc1ref is active high whereas oc1 and oc1n active level depends on cc1p and cc1np bits. 000: frozen - the comparison between the output compare register timx_ccr1 and the counter timx_cnt has no effect on the outputs.(this mode is used to generate a timing base). 001: set channel 1 to active level on match. oc1ref signal is forced high when the counter timx_cnt matches the capture/co mpare register 1 (timx_ccr1). 010: set channel 1 to inactive level on matc h. oc1ref signal is forced low when the counter timx_cnt matches the captur e/compare register 1 (timx_ccr1). 011: toggle - oc1ref toggles when timx_cnt=timx_ccr1. 100: force inactive level - oc1ref is forced low. 101: force active level - oc1ref is forced high. 110: pwm mode 1 - in upcounting, channel 1 is active as long as timx_cnt RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 343/1317 input capture mode bits 1:0 cc1s : capture/compare 1 selection this bit-field defines the direction of the chan nel (input/output) as well as the used input. 00: cc1 channel is configured as output 01: cc1 channel is configured as input, ic1 is mapped on ti1 10: cc1 channel is configured as input, ic1 is mapped on ti2 11: cc1 channel is configured as input, ic1 is mapped on trc. this mode is working only if an internal trigger input is selected through ts bit (timx_smcr register) note: cc1s bits are writable only when the c hannel is off (cc1e = ?0? in timx_ccer). bits 15:12 ic2f : input capture 2 filter bits 11:10 ic2psc[1:0] : input capture 2 prescaler bits 9:8 cc2s : capture/compare 2 selection this bit-field defines the direction of the chann el (input/output) as well as the used input. 00: cc2 channel is configured as output 01: cc2 channel is configured as input, ic2 is mapped on ti2 10: cc2 channel is configured as input, ic2 is mapped on ti1 11: cc2 channel is configured as input, ic2 is ma pped on trc. this mode is working only if an internal trigger input is selected through ts bit (timx_smcr register) note: cc2s bits are writable only when the channel is off (cc2e = ?0? in timx_ccer). bits 7:4 ic1f[3:0] : input capture 1 filter this bit-field defines the frequency used to sample ti 1 input and the length of the digital filter applied to ti1. the digital filter is ma de of an event counter in which n events are needed to validate a transition on the output: 0000: no filter, sampling is done at f dts 0001: f sampling =f ck_int , n=2 0010: f sampling =f ck_int , n=4 0011: f sampling =f ck_int , n=8 0100: f sampling =f dts /2, n=6 0101: f sampling =f dts /2, n=8 0110: f sampling =f dts /4, n=6 0111: f sampling =f dts /4, n=8 1000: f sampling =f dts /8, n=6 1001: f sampling =f dts /8, n=8 1010: f sampling =f dts /16, n=5 1011: f sampling =f dts /16, n=6 1100: f sampling =f dts /16, n=8 1101: f sampling =f dts /32, n=5 1110: f sampling =f dts /32, n=6 1111: f sampling =f dts /32, n=8 bits 3:2 ic1psc : input capture 1 prescaler this bit-field defines the ratio of the prescaler acting on cc1 input (ic1). the prescaler is reset as soon as cc1e=?0? (timx_ccer register). 00: no prescaler, capture is done each ti me an edge is detected on the capture input 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events advanced-control timers (tim1&tim8) RM0033 344/1317 doc id 15403 rev 3 13.4.8 tim1&tim8 capt ure/compare mode regist er 2 (timx_ccmr2) address offset: 0x1c reset value: 0x0000 refer to the above ccmr1 register description. output compare mode bits 1:0 cc1s : capture/compare 1 selection this bit-field defines the direction of the chann el (input/output) as well as the used input. 00: cc1 channel is configured as output 01: cc1 channel is configured as input, ic1 is mapped on ti1 10: cc1 channel is configured as input, ic1 is mapped on ti2 11: cc1 channel is configured as input, ic1 is ma pped on trc. this mode is working only if an internal trigger input is selected through ts bit (timx_smcr register) note: cc1s bits are writable only when the channel is off (cc1e = ?0? in timx_ccer). 1514131211109876543210 oc4 ce oc4m[2:0] oc4 pe oc4 fe cc4s[1:0] oc3 ce. oc3m[2:0] oc3 pe oc3 fe cc3s[1:0] ic4f[3:0] ic4psc[1:0] ic3f[3:0] ic3psc[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bit 15 oc4ce: output compare 4 clear enable bits 14:12 oc4m : output compare 4 mode bit 11 oc4pe : output compare 4 preload enable bit 10 oc4fe : output compare 4 fast enable bits 9:8 cc4s : capture/compare 4 selection this bit-field defines the direction of the ch annel (input/output) as well as the used input. 00: cc4 channel is configured as output 01: cc4 channel is configured as input, ic4 is mapped on ti4 10: cc4 channel is configured as input, ic4 is mapped on ti3 11: cc4 channel is configured as input, ic4 is mapped on trc. this mode is working only if an internal trigger input is selected through ts bit (timx_smcr register) note: cc4s bits are writable only when the channel is off (cc4e = ?0? in timx_ccer). bit 7 oc3ce: output compare 3 clear enable bits 6:4 oc3m : output compare 3 mode bit 3 oc3pe : output compare 3 preload enable bit 2 oc3fe : output compare 3 fast enable bits 1:0 cc3s : capture/compare 3 selection this bit-field defines the direction of the ch annel (input/output) as well as the used input. 00: cc3 channel is configured as output 01: cc3 channel is configured as input, ic3 is mapped on ti3 10: cc3 channel is configured as input, ic3 is mapped on ti4 11: cc3 channel is configured as input, ic3 is mapped on trc. this mode is working only if an internal trigger input is selected through ts bit (timx_smcr register) note: cc3s bits are writable only when the channel is off (cc3e = ?0? in timx_ccer). RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 345/1317 input capture mode 13.4.9 tim1&tim8 capt ure/compare enable re gister (timx_ccer) address offset: 0x20 reset value: 0x0000 bits 15:12 ic4f : input capture 4 filter bits 11:10 ic4psc : input capture 4 prescaler bits 9:8 cc4s : capture/compare 4 selection this bit-field defines the direction of the cha nnel (input/output) as well as the used input. 00: cc4 channel is configured as output 01: cc4 channel is configured as input, ic4 is mapped on ti4 10: cc4 channel is configured as input, ic4 is mapped on ti3 11: cc4 channel is configured as input, ic4 is mapped on trc. this mode is working only if an internal trigger input is sele cted through ts bit (timx_smcr register) note: cc4s bits are writable only when the channel is off (cc4e = ?0? in timx_ccer). bits 7:4 ic3f : input capture 3 filter bits 3:2 ic3psc : input capture 3 prescaler bits 1:0 cc3s : capture/compare 3 selection this bit-field defines the direction of the cha nnel (input/output) as well as the used input. 00: cc3 channel is configured as output 01: cc3 channel is configured as input, ic3 is mapped on ti3 10: cc3 channel is configured as input, ic3 is mapped on ti4 11: cc3 channel is configured as input, ic3 is mapped on trc. this mode is working only if an internal trigger input is sele cted through ts bit (timx_smcr register) note: cc3s bits are writable only when the channel is off (cc3e = ?0? in timx_ccer). 1514131211109876543210 reserved cc4p cc4e cc3np cc3ne cc3p cc3e cc2np cc2ne cc2p cc2e cc1np cc1ne cc1p cc1e rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 15:14 reserved, always read as 0. bit 13 cc4p : capture/compare 4 output polarity refer to cc1p description bit 12 cc4e : capture/compare 4 output enable refer to cc1e description bit 11 cc3np : capture/compare 3 comp lementary output polarity refer to cc1np description bit 10 cc3ne : capture/compare 3 complementary output enable refer to cc1ne description bit 9 cc3p : capture/compare 3 output polarity refer to cc1p description bit 8 cc3e : capture/compare 3 output enable refer to cc1e description advanced-control timers (tim1&tim8) RM0033 346/1317 doc id 15403 rev 3 bit 7 cc2np : capture/compare 2 comp lementary output polarity refer to cc1np description bit 6 cc2ne : capture/compare 2 complementary output enable refer to cc1ne description bit 5 cc2p : capture/compare 2 output polarity refer to cc1p description bit 4 cc2e : capture/compare 2 output enable refer to cc1e description bit 3 cc1np : capture/compare 1 comp lementary output polarity cc1 channel configured as output: 0: oc1n active high. 1: oc1n active low. cc1 channel conf igured as input: this bit is used in conjunction with cc1p to define the polarity of ti1fp1 and ti2fp1. refer to cc1p description. note: this bit is not writable as soon as lock level 2 or 3 has been programmed (lock bits in timx_bdtr register) and cc1s=?00 ? (channel configured as output). note: on channels having a complementary output, this bit is preloaded. if the ccpc bit is set in the timx_cr2 register then the cc1np active bit takes the new value from the preloaded bit only when a commutation event is generated. bit 2 cc1ne : capture/compare 1 complementary output enable 0: off - oc1n is not active. oc1n level is then function of moe, ossi, ossr, ois1, ois1n and cc1e bits. 1: on - oc1n signal is output on the corres ponding output pin depending on moe, ossi, ossr, ois1, ois1n and cc1e bits. note: on channels having a complementary output, this bit is preloaded. if the ccpc bit is set in the timx_cr2 register then the cc1ne active bit takes the new value from the preloaded bit only when a commutation event is generated. RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 347/1317 bit 1 cc1p : capture/compare 1 output polarity cc1 channel configured as output: 0: oc1 active high 1: oc1 active low cc1 channel conf igured as input: cc1np/cc1p bits select the active polarity of ti1fp1 and ti2fp1 for trigger or capture operations. 00: non-inverted/rising edge the circuit is sensitive to tixfp1 rising edge (c apture or trigger operations in reset, external clock or trigger mode), tixfp1 is not inverted (trigger operation in gated mode or encoder mode). 01: inverted/falling edge the circuit is sensitive to tixfp1 falling edge (c apture or trigger operations in reset, external clock or trigger mode), tixfp1 is inverted (trigger operation in gated mode or encoder mode). 10: reserved, do not use this configuration. 11: non-inverted/both edges the circuit is sensitive to both tixfp1 risi ng and falling edges (capture or trigger operations in reset, external clock or trigger mode), tixf p1 is not inverted (trigger operation in gated mode). this configuration must not be used in encoder mode. note: this bit is not writable as soon as lock level 2 or 3 has been programmed (lock bits in timx_bdtr register). note: on channels having a complementary output, this bit is preloaded. if the ccpc bit is set in the timx_cr2 register then the cc1p active bit takes the new value from the preloaded bit only when a commutation event is generated. bit 0 cc1e : capture/compare 1 output enable cc1 channel configured as output: 0: off - oc1 is not active. oc1 level is then function of moe, ossi, ossr, ois1, ois1n and cc1ne bits. 1: on - oc1 signal is output on the corr esponding output pin depending on moe, ossi, ossr, ois1, ois1n and cc1ne bits. cc1 channel conf igured as input: this bit determines if a capture of the counte r value can actually be done into the input capture/compare register 1 (timx_ccr1) or not. 0: capture disabled. 1: capture enabled. note: on channels having a complementary output, this bit is preloaded. if the ccpc bit is set in the timx_cr2 register then the cc1e active bit takes the new value from the preloaded bit only when a commutation event is generated. advanced-control timers (tim1&tim8) RM0033 348/1317 doc id 15403 rev 3 table 57. output control bits for complementary ocx and ocxn channels with break feature control bits output states (1) moe bit ossi bit ossr bit ccxe bit ccxne bit ocx output state ocxn output state 1x 00 0 output disabled (not driven by the timer) ocx=0, ocx_en=0 output disabled (not driven by the timer) ocxn=0, ocxn_en=0 00 1 output disabled (not driven by the timer) ocx=0, ocx_en=0 ocxref + polarity ocxn=ocxref xor ccxnp, ocxn_en=1 01 0 ocxref + polarity ocx=ocxref xor ccxp, ocx_en=1 output disabled (not driven by the timer) ocxn=0, ocxn_en=0 01 1 ocref + polarity + dead- time ocx_en=1 complementary to ocref (not ocref) + polarity + dead-time ocxn_en=1 10 0 output disabled (not driven by the timer) ocx=ccxp, ocx_en=0 output disabled (not driven by the timer) ocxn=ccxnp, ocxn_en=0 10 1 off-state (output enabled with inactive state) ocx=ccxp, ocx_en=1 ocxref + polarity ocxn=ocxref xor ccxnp, ocxn_en=1 11 0 ocxref + polarity ocx=ocxref xor ccxp, ocx_en=1 off-state (output enabled with inactive state) ocxn=ccxnp, ocxn_en=1 11 1 ocref + polarity + dead- time ocx_en=1 complementary to ocref (not ocref) + polarity + dead-time ocxn_en=1 0 0 x 00 output disabled (not driven by the timer) ocx=ccxp, ocx_en=0 output disabled (not driven by the timer) ocxn=ccxnp, ocxn_en=0 0 0 1 output disabled (not driven by the timer) asynchronously: ocx=ccxp, ocx_en=0, ocxn=ccxnp, ocxn_en=0 then if the clock is present: ocx=oisx and ocxn=oisxn after a dead-time, assuming that oisx and oisxn do not correspond to ocx and ocxn both in active state. 010 011 100 output disabled (not driven by the timer) ocx=ccxp, ocx_en=0 output disabled (not driven by the timer) ocxn=ccxnp, ocxn_en=0 1 0 1 off-state (output enabled with inactive state) asynchronously: ocx=ccxp, ocx_en=1, ocxn=ccxnp, ocxn_en=1 then if the clock is present: ocx=oisx and ocxn=oisxn after a dead-time, assuming that oisx and oisxn do not correspond to ocx and ocxn both in active state 110 111 RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 349/1317 note: the state of the external i/o pins connected to the complementary ocx and ocxn channels depends on the ocx and ocxn channel state and the gpio registers. 13.4.10 tim1&tim8 counter (timx_cnt) address offset: 0x24 reset value: 0x0000 13.4.11 tim1&tim8 pr escaler (timx_psc) address offset: 0x28 reset value: 0x0000 13.4.12 tim1&tim8 auto-r eload register (timx_arr) address offset: 0x2c reset value: 0x0000 1. when both outputs of a channel are not used (ccx e = ccxne = 0), the oisx, oisxn, ccxp and ccxnp bits must be kept cleared. 1514131211109876543210 cnt[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 15:0 cnt[15:0] : counter value 1514131211109876543210 psc[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 15:0 psc[15:0] : prescaler value the counter clock frequency (ck_cnt) is equal to f ck_psc / (psc[15:0] + 1). psc contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through ug bit of timx_egr register or through trigger controller when configured in ?reset mode?). 1514131211109876543210 arr[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 15:0 arr[15:0] : prescaler value arr is the value to be loaded in the actual auto-reload register. refer to the section 13.3.1: time-base unit on page 293 for more details about arr update and behavior. the counter is blocked while the auto-reload value is null. advanced-control timers (tim1&tim8) RM0033 350/1317 doc id 15403 rev 3 13.4.13 tim1&tim8 repetition counter r egister (timx_rcr) address offset: 0x30 reset value: 0x0000 13.4.14 tim1&tim8 capture/compare register 1 (timx_ccr1) address offset: 0x34 reset value: 0x0000 1514131211109876543210 reserved rep[7:0] rw rw rw rw rw rw rw rw bits 15:8 reserved, always read as 0. bits 7:0 rep[7:0] : repetition counter value these bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) w hen preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable. each time the rep_cnt related downcounter reaches zero, an update event is generated and it restarts counting from rep value. as rep_ cnt is reloaded with rep value only at the repetition update event u_rc, any write to the ti mx_rcr register is not taken in account until the next repetition update event. it means in pwm mode (rep+1) corresponds to: ? the number of pwm periods in edge-aligned mode ? the number of half pwm period in center-aligned mode. 1514131211109876543210 ccr1[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 15:0 ccr1[15:0] : capture/compare 1 value if channel cc1 is configured as output : ccr1 is the value to be loaded in the actual capture/compare 1 register (preload value). it is loaded permanently if the pr eload feature is not selected in the timx_ccmr1 register (bit oc1pe). else the preload value is copied in t he active capture/compare 1 register when an update event occurs. the active capture/compare register contains the value to be compared to the counter timx_cnt and signaled on oc1 output. if channel cc1 is configured as input : ccr1 is the counter value transferred by the last input capture 1 event (ic1). RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 351/1317 13.4.15 tim1&tim8 capture/compare register 2 (timx_ccr2) address offset: 0x38 reset value: 0x0000 13.4.16 tim1&tim8 capture/compare register 3 (timx_ccr3) address offset: 0x3c reset value: 0x0000 1514131211109876543210 ccr2[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 15:0 ccr2[15:0] : capture/compare 2 value if channel cc2 is configured as output : ccr2 is the value to be loaded in the actual capture/compare 2 register (preload value). it is loaded permanently if the preload feature is not selected in the timx_ccmr2 register (bit oc2pe). else the preload value is copied in t he active capture/compare 2 register when an update event occurs. the active capture/compare register contains the value to be compared to the counter timx_cnt and signalled on oc2 output. if channel cc2 is configured as input : ccr2 is the counter value transferred by the last input capture 2 event (ic2). 1514131211109876543210 ccr3[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 15:0 ccr3[15:0] : capture/compare value if channel cc3 is configured as output : ccr3 is the value to be loaded in the actual capture/compare 3 register (preload value). it is loaded permanently if the preload feature is not selected in the timx _ccmr3 register (bit oc3pe). else the preload value is copied in th e active capture/compare 3 register when an update event occurs. the active capture/compare r egister contains the value to be compared to the counter timx_cnt and signalled on oc3 output. if channel cc3 is configured as input : ccr3 is the counter value transferred by the last input capture 3 event (ic3). advanced-control timers (tim1&tim8) RM0033 352/1317 doc id 15403 rev 3 13.4.17 tim1&tim8 capture/compare register 4 (timx_ccr4) address offset: 0x40 reset value: 0x0000 13.4.18 tim1&tim8 br eak and dead-time r egister (timx_bdtr) address offset: 0x44 reset value: 0x0000 note: as the bits aoe, bkp, bke, ossi, ossr and dtg[7:0] can be write-locked depending on the lock configuration, it can be necessary to configure all of them during the first write access to the timx_bdtr register. 1514131211109876543210 ccr4[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 15:0 ccr4[15:0] : capture/compare value if channel cc4 is configured as output : ccr4 is the value to be loaded in the actual capture/compare 4 register (preload value). it is loaded permanently if the preload feature is not selected in the timx_ccmr4 register (bit oc4pe). else the preload value is copied in the active capture/compare 4 register when an update event occurs. the active capture/compare register contains the value to be compared to the counter timx_cnt and signalled on oc4 output. if channel cc4 is configured as input : ccr4 is the counter value transferred by the last input capture 4 event (ic4). 1514131211109876543210 moe aoe bkp bke ossr ossi lock[1:0] dtg[7:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bit 15 moe : main output enable this bit is cleared asynchronously by hardware as soon as the break input is active. it is set by software or automatically depending on the aoe bit. it is acting only on the channels which are configured in output. 0: oc and ocn outputs are disabled or forced to idle state. 1: oc and ocn outputs are enabled if their respec tive enable bits are set (ccxe, ccxne in timx_ccer register). see oc/ocn enable descripti on for more details ( section 13.4.9: tim1&tim8 capture/compare enable register (timx_ccer) on page 345 ). bit 14 aoe : automatic output enable 0: moe can be set only by software 1: moe can be set by software or automatically at the next update event (if the break input is not be active) note: this bit can not be modified as long as lock level 1 has been programmed (lock bits in timx_bdtr register). RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 353/1317 bit 13 bkp : break polarity 0: break input brk is active low 1: break input brk is active high note: this bit can not be modified as long as lock level 1 has been programmed (lock bits in timx_bdtr register). note: any write operation to this bit takes a del ay of 1 apb clock cycle to become effective. bit 12 bke : break enable 0: break inputs (brk and ccs clock failure event) disabled 1; break inputs (brk and ccs clock failure event) enabled note: this bit cannot be modified when lock level 1 has been programmed (lock bits in timx_bdtr register). note: any write operation to this bit takes a del ay of 1 apb clock cycle to become effective. bit 11 ossr : off-state selection for run mode this bit is used when moe=1 on channels having a complementary output which are configured as outputs. ossr is not implemen ted if no complementary output is implemented in the timer. see oc/ocn enable descripti on for more details ( section 13.4.9: tim1&tim8 capture/compare enable register (timx_ccer) on page 345 ). 0: when inactive, oc/ocn outputs are di sabled (oc/ocn enable output signal=0). 1: when inactive, oc/ocn outputs are enabled with their inactive level as soon as ccxe=1 or ccxne=1. then, oc/ocn enable output signal=1 note: this bit can not be modified as soon as the lock level 2 has been programmed (lock bits in timx_bdtr register). bit 10 ossi : off-state selection for idle mode this bit is used when moe=0 on channels configured as outputs. see oc/ocn enable descripti on for more details ( section 13.4.9: tim1&tim8 capture/compare enable register (timx_ccer) on page 345 ). 0: when inactive, oc/ocn outputs are di sabled (oc/ocn enable output signal=0). 1: when inactive, oc/ocn outputs are forced firs t with their idle level as soon as ccxe=1 or ccxne=1. oc/ocn enable output signal=1) note: this bit can not be modified as soon as the lock level 2 has been programmed (lock bits in timx_bdtr register). bits 9:8 lock[1:0] : lock configuration these bits offer a write protection against software errors. 00: lock off - no bit is write protected. 01: lock level 1 = dtg bits in timx_bdtr re gister, oisx and oisxn bits in timx_cr2 register and bke/bkp/aoe bits in timx_b dtr register can no longer be written. 10: lock level 2 = lock level 1 + cc polari ty bits (ccxp/ccxnp bits in timx_ccer register, as long as the related channel is co nfigured in output through the ccxs bits) as well as ossr and ossi bits can no longer be written. 11: lock level 3 = lock level 2 + cc co ntrol bits (ocxm and ocxpe bits in timx_ccmrx registers, as long as the related channel is configured in output through the ccxs bits) can no longer be written. note: the lock bits can be written only once after the reset. once the timx_bdtr register has been written, their content is frozen until the next reset. advanced-control timers (tim1&tim8) RM0033 354/1317 doc id 15403 rev 3 13.4.19 tim1&tim8 dma contr ol register (timx_dcr) address offset: 0x48 reset value: 0x0000 bits 7:0 dtg[7:0] : dead-time generator setup this bit-field defines the duration of the dead-time inserted between the complementary outputs. dt correspond to this duration. dtg[7:5]=0xx => dt=dtg[7:0]x t dtg with t dtg =t dts . dtg[7:5]=10x => dt=(64+dtg[5:0])xt dtg with t dtg =2xt dts . dtg[7:5]=110 => dt=(32+dtg[4:0])xt dtg with t dtg =8xt dts . dtg[7:5]=111 => dt=(32+dtg[4:0])xt dtg with t dtg =16xt dts . example if t dts =125ns (8mhz), dead-time possible values are: 0 to 15875 ns by 125 ns steps, 16 us to 31750 ns by 250 ns steps, 32 us to 63us by 1 us steps, 64 us to 126 us by 2 us steps note: this bit-field can not be modified as lo ng as lock level 1, 2 or 3 has been programmed (lock bits in timx_bdtr register). 1514131211109876543210 reserved dbl[4:0] reserved dba[4:0] rw rw rw rw rw rw rw rw rw rw bits 15:13 reserved, always read as 0 bits 12:8 dbl[4:0] : dma burst length this 5-bit vector defines the number of dma transfers (the timer recognizes a burst transfer when a read or a write access is done t the timx_dmar address) 00000: 1 transfer 00001: 2 transfers 00010: 3 transfers ... 10001: 18 transfers bits 7:5 reserved, always read as 0 bits 4:0 dba[4:0] : dma base address this 5-bits vector defines the base-address for dma transfers (when read/write access are done through the timx_dmar address). dba is defined as an offset starting from the address of the timx_cr1 register. example: 00000: timx_cr1, 00001: timx_cr2, 00010: timx_smcr, ... example: let us consider the following transfer: dbl = 7 transfers and dba = timx_cr1. in this case the transfer is done to/from 7 re gisters starting from the timx_cr1 address. RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 355/1317 13.4.20 tim1&tim8 dma address for full transfer (timx_dmar) address offset: 0x4c reset value: 0x0000 example of how to use the dma burst feature in this example the timer dma burst feature is used to update the contents of the ccrx registers (x = 2, 3, 4) with the dma transferring half words into the ccrx registers. this is done in the following steps: 1. configure the corresponding dma channel as follows: ? dma channel peripheral address is the dmar register address ? dma channel memory address is the address of the buffer in the ram containing the data to be transferred by dma into ccrx registers. ? number of data to transfer = 3 (see note below). ? circular mode disabled. 2. configure the dcr register by configuring the dba and dbl bit fields as follows: dbl = 3 transfers, dba = 0xe. 3. enable the timx update dma request (set the ude bit in the dier register). 4. enable timx 5. enable the dma channel note: this example is for the ca se where every ccrx register to be updated once. if every ccrx register is to be updated twice for example, the number of data to transfer should be 6. let's take the example of a buffer in the ram containing data1, data2, data3, data4, data5 and data6. the data is transferred to the ccrx registers as follows: on the first update dma request, data1 is transferred to ccr2, data2 is transferred to ccr3, data3 is transferred to ccr4 and on the second update dma request, data4 is transferred to ccr2, data5 is transferred to ccr3 and data6 is transferred to ccr4. 1514131211109876543210 dmab[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 15:0 dmab[15:0] : dma register for burst accesses a read or write operation to the dmar register accesses the register located at the address (timx_cr1 address) + (dba + dma index) x 4 where timx_cr1 address is the address of the control register 1, dba is the dma base address configured in timx_dcr register, dma i ndex is automatically controlled by the dma transfer, and ranges from 0 to dbl (dbl configured in timx_dcr). advanced-control timers (tim1&tim8) RM0033 356/1317 doc id 15403 rev 3 13.4.21 tim1&tim 8 register map tim1&tim8 registers are mapped as 16-bit addressable registers as described in the table below: table 58. tim1&tim8 register map and reset values offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 timx_cr1 reserved ckd [1:0] arpe cms [1:0] dir opm urs udis cen reset value 0000000000 0x04 timx_cr2 reserved ois4 ois3n ois3 ois2n ois2 ois1n ois1 ti1s mms[2:0] ccds ccus reserved ccpc reset value 0000000000000 0 0x08 timx_smcr reserved etp ece etps [1:0] etf[3:0] msm ts[2:0] reserved sms[2:0] reset value 000000000000 000 0x0c timx_dier reserved tde comde cc4de cc3de cc2de cc1de ude bie tie comie cc4ie cc3ie cc2ie cc1ie uie reset value 000000000000000 0x10 timx_sr reserved cc4of cc3of cc2of cc1of reserved bif tif comif cc4if cc3if cc2if cc1if uif reset value 0000 00000000 0x14 timx_egr reserved bg tg com cc4g cc3g cc2g cc1g ug reset value 00000000 0x18 timx_ccmr1 output compare mode reserved oc2ce oc2m [2:0] oc2pe oc2fe cc2s [1:0] oc1ce oc1m [2:0] oc1pe oc1fe cc1s [1:0] reset value 0000000000000000 timx_ccmr1 input capture mode reserved ic2f[3:0] ic2 psc [1:0] cc2s [1:0] ic1f[3:0] ic1 psc [1:0] cc1s [1:0] reset value 0000000000000000 0x1c timx_ccmr2 output compare mode reserved o24ce oc4m [2:0] oc4pe oc4fe cc4s [1:0] oc3ce oc3m [2:0] oc3pe oc3fe cc3s [1:0] reset value 0000000000000000 timx_ccmr2 input capture mode reserved ic4f[3:0] ic4 psc [1:0] cc4s [1:0] ic3f[3:0] ic3 psc [1:0] cc3s [1:0] reset value 0000000000000000 0x20 timx_ccer reserved cc4p cc4e cc3np cc3ne cc3p cc3e cc2np cc2ne cc2p cc2e cc1np cc1ne cc1p cc1e reset value 00000000000000 0x24 timx_cnt reserved cnt[15:0] reset value 0000000000000000 0x28 timx_psc reserved psc[15:0] reset value 0000000000000000 0x2c timx_arr reserved arr[15:0] reset value 0000000000000000 0x30 timx_rcr reserved rep[7:0] reset value 00000000 RM0033 advanced-control timers (tim1&tim8) doc id 15403 rev 3 357/1317 refer to table 1 on page 50 for the register boundary addresses. 0x34 timx_ccr1 reserved ccr1[15:0] reset value 0000000000000000 0x38 timx_ccr2 reserved ccr2[15:0] reset value 0000000000000000 0x3c timx_ccr3 reserved ccr3[15:0] reset value 0000000000000000 0x40 timx_ccr4 reserved ccr4[15:0] reset value 0000000000000000 0x44 timx_bdtr reserved moe aoe bkp bke ossr ossi lock [1:0] dt[7:0] reset value 0000000000000000 0x48 timx_dcr reserved dbl[4:0] reserved dba[4:0] reset value 00000 00000 0x4c timx_dmar reserved dmab[15:0] reset value 0000000000000000 table 58. tim1&tim8 register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 general-purpose timers (tim2 to tim5) RM0033 358/1317 doc id 15403 rev 3 14 general-purpose timer s (tim2 to tim5) 14.1 tim2 to tim5 intr oduction th e ge ner al- pur po se t i me rs co nsist of a 16 -bit or 3 2 - b it a u t o - r e l oa d co unt e r dr iv en b y a p r o g r a mm ab le pr escaler . th e y ma y be u s ed f o r a v a r i et y of pu r p oses , in cludin g me asur ing th e pulse le ngt hs of inpu t signals ( inp ut ca pt ur e ) o r ge ner at ing ou t put w a v ef or m s ( o u t p u t comp ar e an d pwm ). pulse len g t h s an d w a v e f o r m per io ds can be mod u la te d f r om a f e w m i cr osecon ds t o se v e r a l mil lise c o nds using t h e tim e r p r escale r an d th e rcc clo c k con t r o lle r pr escaler s . th e t i mer s a r e comp let e ly ind epe nde nt , a nd do not sh ar e an y r e sou r ces . th e y ca n be synchr oniz ed t o g e t her as d e scr ibed in se ctio n 14. 3. 1 5 . 14.2 tim2 to tim5 main f eatures g ene r a l- pu r p ose ti mx t i me r f eat ur es includ e: 16 -b it (t im 3 and tim 4 ) o r 32 -b it (t im 2 and tim 5 ) u p , d o wn , up /d o w n aut o- re loa d coun te r . 16 -b it pr og r a mma b le pre sca ler u s e d to divide ( a lso ?o n th e f l y? ) t h e cou n t e r cloc k f r eq ue ncy b y a n y f a cto r be tw ee n 1 and 655 35. up to 4 inde pen de nt cha n n e ls f o r : ? i n put ca pt ur e ? o ut pu t comp ar e ? p wm ge ne r a t i on ( e dg e- a nd cent e r - a lign e d mo de s) ? o ne -p ulse mod e ou tp ut syn chro n izat ion cir c u i t t o cont r o l th e t i mer wit h e xt e r nal signa ls a nd t o int e r conn ect se v e r a l t i mers . i n t e r r upt / d m a g ene r a t i on on t he f o llo wing e v ent s: ? u p dat e: coun te r o v er flo w / und er flo w , co unt er init ializat ion ( b y sof t w a r e or int e r n al/ e xt er n a l t r igge r) ? t r i gg er e v e n t (cou nt er st ar t , sto p , in itia lizat ion or co un t b y int e r n a l /e xt e r na l t r igg e r ) ? i n put ca pt ur e ? o ut pu t comp ar e sup por t s in cr em ent al ( qua dr a t u r e ) en co der and hall- sensor cir cuit r y f o r po sit i on ing pu r p oses t r igger input f o r e x ter n al cloc k or cycle-b y-cycle c u rrent management RM0033 general-purpose timers (tim2 to tim5) doc id 15403 rev 3 359/1317 figu re 113. general-p u rpo se time r b l oc k dia g ram (tim2 to tim5) 14.3 tim2 to tim5 functional description 14.3.1 time-base unit th e ma in b l o c k o f t he pr og r a mma b l e tim e r is a 16- bit / 32- bit coun te r with it s rela t ed au to - r e lo ad r egist er . t he coun t e r can cou n t up b u t a l so do wn or b o t h up a nd do wn. the co unt er cloc k ca n be d i vided b y a pre s ca ler . th e coun te r , t h e a u t o - r elo a d r e g i st er and t h e pr esca ler r e g i st er ca n be wr it te n or r e a d b y sof t w ar e . th is is tr u e e v en wh en t he cou n t e r is r unn ing . t h e tim e -b as e un it inclu d e s : counter regis t er (timx_cnt) pre s cal e r reg i st er (ti m x_psc): a u t o - r e l oa d re gist er ( t i m x_arr) autoreload register capture/compare 1 register capture/compare 2 register u u u cc1i cc2i trigger controller stop, clear or up/down ti 1fp1 ti 2fp2 itr0 itr1 itr2 itr3 tr g i encoder interface capture/compare 3 register u cc3i output control oc1 trgo oc 1 r e f oc2 r e f oc3ref u ui reset, enable, up/down, count, capture/compare 4 register u cc4i oc4ref prescaler p r escaler ic4ps ic 3 p s ic1 ic2 prescaler prescaler i npu t fi lter & edge d etect or ic 2 p s ic 1 p s ti 1f p1 oc 2 oc 3 oc 4 re g event no t es : p r el oa d r e gi s t er s t r a ns f e r re d to active registers on u event according to control bit i n terrupt & dma output tgi tr c tr c ic3 ic 4 it r trc ti 1f_e d i npu t fi lt er & edge detect or i npu t fi lt er & edge de tect or i npu t fi lter & edge detect or cc1i cc2i cc3i cc4 i ti 1f p2 ti 2f p1 ti2fp2 ti3fp3 trc tr c ti3fp4 ti 4f p3 ti4fp4 ti4 ti 3 ti 1 ti2 xor timx _ch1 timx _ch2 timx_ch3 timx_ch4 timx_ch1 timx_ch2 timx _ch3 timx _ch4 t o oth e r t i m e rs timx clk fr o m rcc prescal e r counter +/- ck_p s c ps c cnt ck_cnt contr o ll er mode sl a v e int e rnal clock (ck_int) etr input filter polarity selection & edge detector & prescaler etr p etrf timx _ e tr etrf to dac / a d c output contr o l output contr o l output contr o l general-purpose timers (tim2 to tim5) RM0033 360/1317 doc id 15403 rev 3 th e au to -r elo ad r egist er is pr eloa de d. wr it ing t o or re adin g fr om t h e a u t o - r e l oa d reg i ste r a c cesses th e pr eloa d re gist er . th e cont en t o f t he pr elo a d r e g i st er are tr a n sf err e d in t o th e sha d o w r egist er p e r m ane nt ly or a t ea ch u pda te e v ent ( u ev) , d epe ndin g on t he au to -r eloa d pr elo a d en a b le bit ( a rpe) in t i m x _ cr1 r e g i st er . t h e up da te e v e n t is se nt wh en t h e c o u n t er r e a c h e s t h e o v e r f l o w ( o r u nde rf lo w whe n do wncou n t i ng ) an d if t h e udis bit equ als 0 in t he ti mx_cr1 r egist er . i t can also be g ene r a t e d b y so ft w a re . t he ge ne r a t i on o f t h e u pda te e v e n t is de scr i b ed in d e t a il f o r ea ch co nf igu r at ion . th e coun te r is clo c k ed b y t h e p r e s cale r ou t put ck_ c nt , wh ich is en ab led o n ly wh en t h e cou n t e r en ab le bit ( c en) in tim x _ c r1 r egist er is set ( r e f e r also t o th e sla v e mod e con t r o lle r d e scr i p t ion t o ge t mo re d e t a ils o n coun te r en ab ling ) . no te th at th e a c tu al co un te r en ab le sign a l cn t_ en is s e t 1 clo c k cy cle a fte r cen. presca ler descripti on th e pr esca ler can d i vid e th e co un te r clo c k f r e que ncy b y a n y f a ct or bet w e en 1 an d 655 36 . it is base d on a 16 -b it cou n t e r con t r o lle d t h ro ug h a 16 -bit / 3 2 - bi t re gist er ( i n th e ti mx_psc r e g i st er ). it ca n be chan ge d o n th e fly as t h is co nt ro l r e g i st er is b u f f e r e d . th e ne w pr escale r r a t i o is t a k e n int o accoun t at t he ne xt up dat e e v e n t . fig u r e 11 4 a nd f i gur e 11 5 g i v e som e e x a m ple s of t he co unt er be ha vior when t he p r e s ca ler r a t i o is chan ge d on t h e f l y: fi gu re 11 4. coun te r t i min g d i a g ram wi th p r es cal er di v i s i on c h ang e fr om 1 to 2 ck_p sc 00 cn t_ en timer clock = ck _cnt count er re giste r update event (uev) 0 f 9 fa fb fc f7 prescaler control register 01 write a new value in timx_psc 01 02 03 prescaler buffer 01 prescaler counter 0 1 0 1 0 1 0 1 f8 RM0033 general-purpose timers (tim2 to tim5) doc id 15403 rev 3 361/1317 fi gu re 11 5. coun te r t i min g d i a g ram wi th p r es cal er di v i s i on c h ang e fr om 1 to 4 14.3.2 counter modes up c o un ti n g m o de i n up co un tin g mod e , t he cou n t e r cou n t s f r o m 0 t o th e au to -r eloa d v a lu e (con te nt o f t h e ti mx_arr reg i ste r ) , t hen rest ar t s f r o m 0 an d gen er a t e s a cou n t e r o v e r f l o w e v e n t . an upd a t e e v en t can b e ge ner at ed at ea ch cou n t e r o v e r f l o w o r b y set t in g t he ug bit in th e ti mx_eg r r egist er ( b y sof t w ar e or b y using t h e sla v e mod e co nt ro ller ) . th e uev e v e n t ca n be di sa b l e d b y sof t w a re b y se tt in g th e udi s b i t in t i m x _ c r1 r egist er . th is is to a v oid u p d a t i ng t h e sha d o w r e g i st e r s wh ile wr it in g ne w v a lu es in th e pr eloa d r e g i st er s . t hen n o up dat e e v e n t occu rs unt il t he udis bit has bee n wr itt e n to 0 . ho w e v e r , t h e cou n t e r rest ar t s f r o m 0, a s w e ll as th e co un te r of th e pr esca ler ( b ut t h e pre sca le r a t e d oes no t chan ge ). i n a ddit i on , if th e urs bit (up d a t e r e q uest se lectio n) in t i m x _ c r1 r e g i st er is set , set t i ng t h e ug bit ge ner at es a n up dat e e v e n t uev b u t wit hou t set t i ng t h e ui f fla g (th u s n o int e r r up t or dm a r e qu es t is se nt ). t h is is t o a v o i d ge ne r a t i ng b o th up d a t e an d cap t u r e in te rr u p t s whe n clear in g th e coun te r on th e ca pt ur e e v en t . whe n an u pda te e v en t occur s , a ll t h e r e g i ste r s are u p d a t ed a nd t he up da te f l ag (ui f b i t in t i m x_ s r r e g i st er ) is se t ( d ep en d i ng o n th e urs bit) : the b u f f er of t h e p r escale r is rel oad ed wi th t he pr eloa d v a lue (co n t ent o f th e ti mx_ psc re gist er ) the aut o- re loa d sh ad o w re gist er is upd at ed wit h th e pr elo ad v a lu e (ti m x_arr) th e f o llo wing f i gu res sho w som e e xamp l es of t h e co unt er beh a vio r f o r dif f er ent cloc k fr eq ue n cie s wh e n ti mx _ar r =0 x3 6. ck_psc 00 cnt _ e n t imer clock = ck _cnt coun ter re giste r upda te even t (uev ) 0 f9 fa fb fc f7 prescaler control re giste r 03 wr ite a new value in timx_psc pr esca ler buf fe r 03 p r escaler count e r 0 1 2 3 0 1 2 3 f8 01 general-purpose timers (tim2 to tim5) RM0033 362/1317 doc id 15403 rev 3 figu re 116. coun ter timin g d i a g ra m, i n t e r n al c l oc k di vi ded b y 1 figu re 117. coun ter timin g d i a g ra m, i n t e r n al c l oc k di vi ded b y 2 figure 118. counter timing diagra m, internal clock divided by 4 ck_int 00 cnt _ e n t imer clock = ck _cnt coun ter re giste r updat e int e rr upt f l ag (ui f ) coun te r overf l ow upda te even t (uev ) 01 02 03 04 05 06 07 32 33 34 35 3 6 31 ck_int 00 35 00 00 0001 0002 0003 cnt_ e n t i mer clock = ck _cnt coun ter re giste r updat e int e rr upt f l ag ( u i f ) 0034 0036 cou n te r overf l ow upda te even t (uev ) 00 00 0 001 cnt_e n timer clock = ck _cnt coun ter re giste r updat e int e rr upt f l ag (ui f ) 00 35 0 036 counte r overf l ow upda te even t (uev ) ck_int RM0033 general-purpose timers (tim2 to tim5) doc id 15403 rev 3 363/1317 figu re 119. coun ter timin g d i a g ra m, i n t e r n al c l oc k di vi ded b y n figu re 120. coun ter timin g d i a g ram, up d a t e e vent whe n arpe=0 (ti m x _ arr not pr e l o a de d ) timer clock = ck_cnt counter register 00 1f 20 update interrupt flag (uif) cou n te r overf l ow upda te even t (uev ) ck _ i n t 00 cnt _ e n t imer clock = ck _cnt coun ter re giste r updat e int e rr upt f l ag (ui f ) coun te r overf l ow upda te even t (uev ) 01 02 03 04 05 06 07 32 33 34 35 3 6 31 a uto-reload register ff 36 writ e a new value in timx_arr ck_int general-purpose timers (tim2 to tim5) RM0033 364/1317 doc id 15403 rev 3 figu re 121. coun ter timin g d i a g ram, upd a t e e vent whe n arpe=1 (ti m x _ arr pr e l o a de d ) do wn counting mode i n do wncou n t i ng m ode , th e co un te r coun ts f r om t h e aut o- re loa d v a lue ( c ont en t o f t he ti mx_arr reg i ste r ) d o wn t o 0 , t hen r e st ar t s f r o m th e au to -r eloa d v a lu e and g e n e r a te s a co un te r un de r f lo w e v e n t . an upd a t e e v en t can b e ge ner at e at e a ch coun t e r u nde rf lo w o r b y set t in g t he ug bit in th e ti mx_eg r r egist er ( b y sof t w ar e or b y using t h e sla v e mod e co nt ro ller ) th e uev up da te e v ent ca n be d i sab l ed b y sof t w ar e b y set t in g t he udi s bit in ti mx_ c r1 r e g i st er . this is t o a v o i d up dat ing t h e sh ado w re giste r s while wr iti ng ne w v a lues in t he p r e l oad r e g i st er s . the n no up da te e v ent occurs un til udi s bit has bee n wr itt e n to 0 . ho w e v e r , t h e cou n t e r r e st ar ts f r om t h e cur r ent aut o- r e loa d v a lue , wh er eas th e coun te r of th e p r e s cale r re sta r t s fr om 0 ( b u t t h e p r e s cale r a t e do esn?t ch ang e) . i n ad dit i on, if th e urs bit ( upd at e re que st se lect ion) in ti mx_cr1 re giste r is set , set t i ng th e ug bit ge ner at es a n up dat e e v e n t uev b u t wit hou t set t i ng t h e ui f fla g (t hu s no int e r r upt or dma re que st is sen t ). t h is is t o a v o i d gen er a t in g bo th u p d a t e and ca pt ur e int e r r upt s wh en cle a r i n g th e co un te r o n th e ca pt ur e e v en t. whe n an u pda te e v en t occur s , a ll t h e r e g i ste r s are u p d a t ed a nd t he up da te f l ag (ui f b i t in t i m x _ s r r e g i st er ) is se t ( d ep en d i ng o n th e urs bit) : the b u f f er of t h e p r escale r is rel oad ed wi th t he pr eloa d v a lue (co n t ent o f th e ti mx_ psc re gist er ). the aut o- re loa d activ e r e g i st e r is u pda te d with t h e p r e l oa d v a lue ( cont en t o f t he ti mx_arr r egist er ). no te th at t h e aut o- re loa d is up da te d bef o r e t h e cou n t e r is re loa ded , so t hat th e ne xt per i od is t h e e xpect e d o n e . th e f o llo wing f i gu res sho w som e e xamp l es of t h e co unt er beh a vio r f o r dif f er ent cloc k fr eq ue n cie s wh e n ti mx _ar r =0 x3 6. 00 cnt _ e n t imer clock = ck _cnt coun ter re giste r updat e int e rr upt f l ag (ui f ) coun te r overf l ow upda te even t (uev ) 01 02 03 04 05 06 07 f1 f2 f3 f4 f5 f0 aut o-reload preload register f5 36 aut o-reload shadow register f5 36 writ e a new value in timx_arr ck_p sc RM0033 general-purpose timers (tim2 to tim5) doc id 15403 rev 3 365/1317 figu re 122. coun ter timin g d i a g ra m, i n t e r n al c l oc k di vi ded b y 1 figu re 123. coun ter timin g d i a g ra m, i n t e r n al c l oc k di vi ded b y 2 figu re 124. coun ter timin g d i a g ra m, i n t e r n al c l oc k di vi ded b y 4 ck_int 36 cnt _ e n t imer clock = ck _cnt coun ter re giste r updat e int e rr upt f l ag (ui f ) count er und erf l ow ( c n t _ udf ) upda te even t (uev ) 35 34 33 32 31 30 2f 04 03 02 01 00 05 ck_int 00 01 00 36 0035 0034 0033 cnt_ e n t i mer clock = ck _cnt coun ter re giste r updat e int e rr upt f l ag (ui f ) 0002 0000 co unt er und erf l ow upda te even t (uev ) 00 36 0 035 cnt_e n t imer clock = ck _cnt coun ter re giste r updat e int e rr upt f l ag (ui f ) 0001 0000 counter underf l ow upda te even t (uev ) ck_int general-purpose timers (tim2 to tim5) RM0033 366/1317 doc id 15403 rev 3 figu re 125. coun ter timin g d i a g ra m, i n t e r n al c l oc k di vi ded b y n figu re 12 6. coun te r t i min g d i a g ram, upd a t e e vent whe n repe tit i on c ount er is not u sed cente r -alig ned mode (up/do wn counti ng) i n cent e r - a lign e d mo de , t h e co unt e r co un ts fr om 0 t o t h e a u t o - r elo a d v a lue ( c o n t ent of th e ti mx_arr reg i ste r ) ? 1 , g ene r a t e s a coun te r o v er flo w e v en t, th en cou n t s f r o m th e au to - r e lo ad v a lu e do wn to 1 and g e n e r a te s a cou n t e r u nde rf lo w e v ent . t hen it re st ar t s co unt ing fr om 0 . cen t e r - a lig ned m ode is act i v e wh en t h e cms bit s in tim x _ c r1 r e g i st er ar e not equ al t o '0 0'. the o u t p u t comp ar e int e r r up t f l ag of chan nels conf igu r e d in ou tp ut is set whe n : th e cou n t e r cou n t s d o wn ( c ent er align e d m ode 1 , cms = "01 " ), t h e co unt e r co un ts up ( c e n t e r a ligne d mod e 2, cm s = "10") t h e co unt er co unt s up an d do wn (ce n t e r a ligne d mod e 3, cms = "11"). i n th is mod e , th e d i re ct ion b i t (dir fr om ti mx_cr1 r egist er ) ca nno t be wr itt e n . it is u p d a t ed b y h a r d w a re a nd giv e s t h e cur r e n t dire ctio n of t h e co unt e r . th e u pda te e v en t can be g e n e r a te d at ea ch co un te r o v er f l o w an d a t e a ch coun t e r u n d e rf lo w o r b y set t in g t he ug bit in th e ti mx_egr re gist er ( b y so f t w a re o r b y u s in g th e sla v e mo de con t r o lle r) a l so gen er a t e s a n upd at e e v e n t . i n th is case , t h e co unt er re st ar t s cou n t i ng f r o m 0, as well as the counter of the prescaler. timer clock = ck_cnt counter register 36 20 1f update interrupt flag (uif) count er un derf l ow upda te even t (uev ) ck _ i n t 00 36 cnt _ e n t imer clock = ck _cnt coun ter re giste r updat e int e rr upt f l ag (ui f ) counter un derf l ow upda te even t (uev ) 35 34 33 32 31 30 2f 04 0 3 0 2 01 00 05 a uto-reload register ff 36 write a new value in timx_arr ck_ i nt RM0033 general-purpose timers (tim2 to tim5) doc id 15403 rev 3 367/1317 th e uev up da te e v ent ca n be d i sab l ed b y sof t w ar e b y set t in g t he udi s bit in ti mx_ c r1 r e g i st er . this is t o a v o i d up dat ing t h e sh ado w re giste r s while wr iti ng ne w v a lues in t he p r e l oad r e g i st er s . the n no up da te e v ent occurs un til t he udis bit has be en wr it te n to 0 . ho w e v e r , t h e cou n t e r con t in ues co un tin g up a nd do wn, ba se d on t h e cur r e n t aut o- r e loa d va l u e . i n ad dit i on, if th e urs bit ( upd at e re que st se lect ion) in ti mx_cr1 re giste r is set , set t i ng th e ug bit ge ner at es a n up dat e e v e n t uev b u t wit hou t set t i ng t h e ui f fla g (t hu s no int e r r upt or dma re que st is sen t ). t h is is t o a v o i d gen er a t in g bo th u p d a t e and ca pt ur e int e r r upt when cle a r i n g th e co un te r o n th e ca pt ur e e v en t. whe n an u pda te e v en t occur s , a ll t h e r e g i ste r s are u p d a t ed a nd t he up da te f l ag (ui f b i t in t i m x_ s r r e g i st er ) is se t ( d ep en d i ng o n th e urs bit) : the b u f f er of t h e p r escale r is rel oad ed wi th t he pr eloa d v a lue (co n t ent o f th e ti mx_ psc re gist er ). the aut o- re loa d activ e r e g i st e r is u pda te d with t h e p r e l oa d v a lue ( cont en t o f t he ti mx_arr r egist er ). no te th at if th e up dat e sou r ce is a co unt er o v e r f l o w , t he au t o - re loa d is upd at ed bef or e t h e co un te r is re loa ded , so t h a t t h e ne xt pe r i od is t h e e xpe ct ed on e (t he cou n t e r is loa ded wit h t h e n e w v a lue ) . th e f o llo wing f i gu res sho w som e e xamp l es of t h e co unt er beh a vio r f o r dif f er ent cloc k fr eq ue n cie s . figu re 127. coun ter timin g d i a g ram, in t e r n al c l oc k di vi ded b y 1, ti mx_ a rr=0x6 1. here , ce nte r-ali gned mod e 1 is used (f o r mo re det ails ref e r t o sect ion 14. 4. 1: ti mx cont rol re giste r 1 (ti m x_cr1) on pag e 394 ). ck_int 02 cnt_en t i mer clock = ck _cnt coun ter re giste r updat e int e rr upt f l ag (ui f ) counter underflow update even t (uev ) 03 04 0 5 06 05 0 4 03 03 02 01 00 01 04 counter overflow general-purpose timers (tim2 to tim5) RM0033 368/1317 doc id 15403 rev 3 figu re 128. coun ter timin g d i a g ra m, i n t e r n al c l oc k di vi ded b y 2 figu re 129. coun ter timin g d i a g ram, inte r n al c l oc k di vi ded b y 4, ti mx_ a rr=0x3 6 1. cent er- a lign ed mode 2 or 3 is u s e d wit h an ui f on o v erf l o w . figure 130. counter timing diagra m, internal clock divided by n 00 02 0000 0001 0002 0003 cnt _ e n timer clock = ck _cnt coun ter re giste r updat e int e rr upt f l ag (ui f ) 0 003 0001 co unt er und erf l ow update event (uev) ck_int ck_int 0036 0035 cnt _ e n t imer clock = ck _cnt coun ter re giste r updat e int e rr upt f l ag (ui f ) 00 34 0035 count er overf l ow ( c nt _ovf ) upda te even t (uev ) timer clock = ck_cnt counter register 00 20 1f update interrupt flag (uif) co unt er und erf l ow upda te even t (uev ) ck _ i n t 01 RM0033 general-purpose timers (tim2 to tim5) doc id 15403 rev 3 369/1317 figu re 13 1. coun te r t i min g d i a g ram, upd a t e e vent with arpe=1 ( c ou nte r unde rflo w) figu re 13 2. coun te r t i min g d i a g ram, upd a t e e vent with arpe=1 ( c ou nte r o v erf l o w ) 00 cnt _ e n t imer clock = ck _cnt coun ter re giste r updat e int e rr upt f l ag (ui f ) co unt er und erf l ow upda te even t (uev ) 01 02 03 04 05 06 07 0 5 04 03 02 0 1 06 auto-reload preload register fd 36 write a new value in timx_arr auto-reload active register fd 36 ck _int 36 cnt _ e n t imer clock = ck _cnt coun ter re giste r updat e int e rr upt f l ag (ui f ) counte r overf l ow upda te even t (uev ) 35 34 33 32 31 30 2f f8 f9 fa fb fc f7 aut o -reload preload register fd 36 writ e a new va lue in timx_arr auto -rel oad active register fd 36 ck_ i nt general-purpose timers (tim2 to tim5) RM0033 370/1317 doc id 15403 rev 3 14.3.3 cloc k selection th e coun te r cloc k ca n be p r o v ided b y th e f o llo wing cloc k so ur ce s: in te r n a l clo c k (ck_ in t) ext e r n a l clo c k mo de1 : e x t e r nal inp u t pin ( t i x ) ext e r n a l clo c k mo de2 : e x t e r nal t r igg e r in put (etr) i n t e r n al t r igge r inp u t s ( i t r x) : using one t i me r as pr esca ler f o r ano t her time r , f o r e x am ple , y o u ca n conf igu r e t i mer 1 to a c t as a pr esca ler f o r time r 2. re f e r t o : us ing on e tim e r a s pr escale r f o r an ot he r on p age 389 f o r m o re d e t a ils . inte rn al c l oc k sou r ce (ck_int) if th e sla v e m o de co n t ro lle r is d i sab l ed ( s m s =0 00 in th e tim x _ s m cr r e gist er ), th en t h e cen, dir (in the timx _cr 1 regi st er ) a nd ug bit s ( i n t he ti mx_eg r r egist er ) ar e act ual con t r o l bit s and can b e chan ge d only b y sof t w a r e (e xcep t ug which re main s clea re d a u t o ma tical l y) . as soo n as t h e cen b i t is wr it te n to 1 , t he pr escale r is cloc k e d b y t h e i n t e r n al cloc k ck _i nt . fig u r e 13 3 sh o w s th e be ha vio r of t he cont r o l cir c uit and t h e u p cou n t e r in n o r m al mo de , without prescaler . figu re 13 3. cont r o l ci r c uit in norma l mod e , in ter n al c l oc k divide d b y 1 exte rna l c l oc k sour ce mode 1 this mode is s e lected when sms= 11 1 in th e ti mx _sm c r r e g i ste r . th e co unt e r ca n coun t at eac h r i s i ng or f a lling edge on a s e lected input. ck_int 00 c o u n te r c l o c k = ck _cnt = ck_ps c counter r e gi ster 01 02 0 3 04 05 06 07 32 33 34 35 36 31 ce n=c n t_e n ug cnt_init RM0033 general-purpose timers (tim2 to tim5) doc id 15403 rev 3 371/1317 figu re 13 4. t i 2 e x ter n al c l oc k co nnec t ion e x a m ple f o r e xa m ple , t o con f ig ur e th e up co unt e r to co unt in re sp on se t o a r i sing e d g e on t h e ti 2 in put , u se th e f o llo wi ng pr oced ur e: f o r e xa m ple , t o con f ig ur e th e up co unt e r to co unt in re sp on se t o a r i sing e d g e on t h e ti 2 in put , u se th e f o llo wi ng pr oced ur e: 1 . conf igu r e ch ann el 2 t o d e t e ct r i sin g ed ges on th e ti 2 inp u t b y wr iti ng cc2s= ?0 1 in t h e timx_ccmr1 register . 2. co n f ig ur e the in p u t filte r du r a tion b y w r it ing t h e ic 2f[3 :0 ] bit s in th e tim x_ ccm r1 re gist er ( i f n o filt er is ne ed ed, k eep ic2f =0 000 ). not e : t h e capt ur e pr escale r is n o t u s e d f o r t r igg e r i ng , so y o u d o n ? t ne ed t o conf ig ure it. 3 . sele ct r i sin g ed ge po lar i t y b y wr it ing cc2p=0 and cc 2n p=0 in the timx_ccer re gist er . 4 . conf igu r e t h e tim e r in e x t e r n a l cloc k mod e 1 b y wr iti ng sms=111 in th e ti mx_smcr re gist er . 5 . sele ct ti 2 as t h e inpu t sou r ce b y wr itin g ts=11 0 in th e ti mx_smcr r e g i st er . 6 . ena b le t h e co unt er b y wr i t in g cen=1 in t he ti mx_cr1 re gist er . whe n a r i sing ed ge o c cu rs o n ti 2, th e co un te r coun ts on ce a nd t h e t i f f l ag is se t. th e de la y b e t w e en t h e r i sing edg e on ti 2 a nd t he a c t u a l cloc k of th e coun te r is d u e t o t he re syn ch ro n i za tion c i rcu i t on ti2 in pu t. figu re 13 5. cont r o l c i r c uit in e x t e rna l c l oc k mode 1 ck_int encod er mode e x t e r n al cl oc k mode 1 e x t e r n al cl oc k mode 2 internal clock mode etrf trgi ti1f ti2f or or or (in t e r nal cloc k) ck_psc ece timx_smcr sms[2:0] itrx ti1f_ed ti1fp1 ti2fp2 etrf timx_smcr ts[2:0] ti2 0 1 timx_ccer cc2p filter icf[3:0] timx_ccmr1 ed ge detector ti2f _r is ing ti2f_falling 110 001 100 101 111 counter clock = ck_cnt = ck_psc count er regi st er 35 36 34 ti2 cnt_en tif write tif=0 general-purpose timers (tim2 to tim5) RM0033 372/1317 doc id 15403 rev 3 exte rna l c l oc k sour ce mode 2 th is mo de is se lect ed b y wr it ing ece=1 in th e ti mx_smcr r egist er . th e coun te r can cou n t a t e a ch r i si ng or f a lling e dge o n th e e x t e r n al t r igge r inp u t et r. th e fig u re 136 giv e s an o v e r v i e w of th e e x te r n al tr ig ge r inp u t b l o c k. figu re 13 6. ex ter n al trig g e r in put b l oc k f o r e x a m ple , t o con f ig ur e th e up co unt e r to co unt ea ch 2 r i sin g edg es on etr, u s e t h e f o llo win g pr oc ed ur e : 1 . as no filt er is n eed ed in t h is e x a m ple , wr it e etf[ 3 : 0 ] =00 0 0 in t h e ti mx_smcr r egist er . 2 . set th e pr esca ler b y wr it ing et ps[ 1 : 0 ] = 01 in t h e tim x _ s mcr r egist er 3. se lec t r i s i ng e d g e d e te ct ion o n th e et r p i n b y wr itin g etp = 0 in th e ti mx _sm c r re gist er 4 . ena b le e x t e r n a l cloc k mo de 2 b y wr it ing ece=1 in t h e ti mx_ s mcr r egist er . 5 . ena b le t h e co unt er b y wr i t in g cen=1 in t he ti mx_cr1 re gist er . th e coun te r cou n t s on ce each 2 etr r i sin g ed ges . th e de la y bet w e en t h e r i sin g ed ge on et r a nd t he a c t u a l clo c k of t he cou n t e r is du e to t h e r e synchr onizat i o n cir c uit o n th e etrp sign al. figure 137. control circuit in external clock mode 2 etr 0 1 timx_smcr etp d i vider /1, /2, /4, /8 etps[1:0] etrp filter etf[3:0] downcounter ck_i nt ti mx _ s mcr t i mx_smcr etr pin ck_int encod er mode e x t e r nal cloc k mode 1 e x t e r nal cloc k mode 2 internal clock mode etrf trgi ti1f ti2f or or or (i nte r nal cloc k) ck_psc ece timx_smcr sms[2:0] c o unt er cl ock = c k _cnt = ck_p sc co unt er regi st er 35 36 34 etr cnt_en ck_int et r p etrf RM0033 general-purpose timers (tim2 to tim5) doc id 15403 rev 3 373/1317 14.3.4 capture/compare c h annels eac h ca pt ur e/ com p ar e ch an n e l is b u ilt ar ou n d a c a p tu r e /c o m p ar e re gis ter ( i nc lud i ng a sh ad o w r e g i st er ), a in p u t sta g e f o r ca pt ur e ( with d i git a l f ilter , m u ltip le x i ng an d pr e sca ler ) a n d an o u t pu t sta g e ( wit h c o m p ar a t o r an d ou tp ut co n t ro l). th e f o llo wing f i gu re g i v e s a n o v e r vie w o f on e capt ur e/ comp ar e ch ann el. th e inp u t st ag e sa mple s t h e cor r e spon ding tix inp u t t o g ene r a t e a f ilt ere d signa l t i xf . th en , an e d g e det ect o r wit h po lar i t y sele ct io n gen er a t e s a sign al (t ixfpx) which can be u s e d as tr ig ger inpu t b y t h e sla v e mod e cont r o ller or a s t he cap t u r e com m an d. i t is pr es ca led b e f o r e th e ca ptu r e r e gist er ( i cx ps). fi gu re 13 8. cap t ur e/ compa r e c h a nne l (e x a mpl e : c h ann e l 1 i n p u t st a g e ) th e ou tp ut st ag e gen er a t es a n int e r m ed iat e w a v e f o r m which is th en u s e d f o r re f e re nce: o c xref (act iv e hig h ) . th e pola r ity act s at t he en d of th e ch ain . fi gu re 13 9. cap t ur e/ compa r e c h a nne l 1 mai n ci r c ui t ti1 timx_ccer c c1p/cc1np divider / 1 , / 2 , /4 , /8 icps[1:0] ti1f _ed filter icf [ 3:0] downc ounter timx _c cmr1 edge de t e ct or ti1f_rising ti1f _f alling to the sl ave mode controller ti1fp1 11 01 tim x _ccmr1 cc1s [ 1: 0] ic1 ti2 f p1 tr c (fr om channel 2) (fr o m slav e mode c o n t ro l l e r) 10 f dts timx _ cce r cc1e ic1ps ti1f ti2f_rising ti2f _fal li ng (fr om channel 2) cc1e capture/comp are sha d o w reg i ster comparator capt ure/compare preload reg i st er counter ic1ps cc1s[0] cc1s[1] capt ure input mod e s r read ccr1h read ccr1l read_in_prog r ess capt ure _ transfer cc1s[0] cc1s[1] s r write ccr1h wr i t e ccr1l wr i t e_ in_p rog r ess output mode uev oc1 p e (from time co mpare _ tr ansf e r apb bus 8 8 high low (if 16-bi t) mcu-per iphe r a l inter f ace t i mx_ccmr1 oc1pe base unit) cn t>ccr1 cnt=ccr1 timx _ e g r cc1g general-purpose timers (tim2 to tim5) RM0033 374/1317 doc id 15403 rev 3 figu re 14 0. outp ut st a g e of c a pt ure/c o mpare c h ann e l ( c ha nnel 1) th e ca pt ur e/ comp are b l oc k is ma de of o ne pr elo ad re gist er an d one sha d o w r egi st er . wr it e a nd r ead a l w a ys acce ss t he pr elo ad r egist er . i n ca pt ur e m ode , cap t u r e s a r e act u a lly don e in t he sh ad o w r e g i st e r , which is co pie d in to t he pr elo a d re gis t e r . in co m p a r e m o de , th e co nt en t of th e pr elo a d re gis ter is co pie d in to th e sh ad o w r e gist er which is co mpa r e d to t h e co unt er . 14.3.5 input capture mode i n i npu t cap t u r e m ode , th e ca pt ur e/ comp ar e re gist ers (t im x_ ccrx) ar e used t o lat ch t he v a l ue of th e coun te r af t e r a t r a n siti on de te cte d b y th e cor r esp ond ing i c x signa l. whe n a cap t u r e o c cu rs , th e corr espo nd ing ccxi f f l ag ( t i m x_sr r e g i st er ) is se t an d an in te rr u p t o r a dm a r e q u e s t can b e sen t if t h e y are en ab led. i f a capt ur e o c cu rs while t h e ccxi f f l ag w a s a l re ady high , t h e n th e o v er -cap tu re f l ag ccx of (t im x_ sr re gis t er ) is se t . ccx if c a n b e clea re d b y sof t w a re b y wr it ing it t o 0 or b y r e a d in g th e ca pt ur ed d a t a sto r ed in th e timx_ccrx register . ccxof is cl eared w h en y o u wr ite it to 0. th e f o llo wing e xa m ple sho w s h o w t o capt ur e t he cou n t e r v a lu e in ti mx_ccr1 wh en ti 1 inp u t r i se s . t o d o th is , u se th e f o llo win g pr oc ed ur e : se lec t the ac tiv e in pu t: tim x_ ccr 1 m u s t be link e d t o t he ti 1 inpu t, so wr it e th e cc1s b i ts to 01 in t h e tim x_ ccm r 1 r e gist er . as so on a s cc1 s b e c o m e s d i ff e r en t f r o m 00 , t he cha nne l is co nf igu r e d in inp u t a nd t h e t i mx_ c cr1 re giste r be come s re ad -o nly . pro g r a m th e in pu t f ilt er du r a t i on y o u ne ed with re sp ect t o t h e si gna l y o u conn ect to t he t i mer ( w hen th e inpu t is one o f t h e t i x (i cxf b i ts in t he ti mx_ccmrx r egist er ). let ? s ima g ine th at , wh en t o gglin g, t he in put sign al is no t st ab le d u r i ng at m u st 5 in te r n a l cloc k cycles . w e m u st p r og r a m a f ilt er d u r a t i o n long er t h a n t hese 5 cloc k cycles . w e ca n v a lid at e a tr ansit ion o n ti 1 wh en 8 con secut iv e sa mple s wit h th e ne w le v e l ha v e bee n o u tp u t mode cnt > ccr1 cnt = ccr1 contro ller timx_ccmr1 oc1m[2:0] oc1ref 0 1 cc1p timx_ccer o u tp u t en ab le circ u it oc1 cc1e timx_ccer to t h e m as ter mode controlle r etrf 0 1 ocref_clr ocref_clr_int occ s timx_ s mcr a i171 8 7 RM0033 general-purpose timers (tim2 to tim5) doc id 15403 rev 3 375/1317 de te ct e d (samp l ed a t f dt s f r eq ue ncy) . t hen wr it e i c 1 f bit s t o 00 11 in t h e timx_ccmr1 register . sele ct th e ed ge of th e act i v e tr ansit ion o n th e ti 1 ch an nel b y wr it ing t h e cc1p and cc1 n p bit s to 0 0 in t he ti mx_ccer re gist er ( r ising ed ge in t h is case) . pro g r a m t h e in pu t pr escaler . in o u r e x a m ple , w e wish th e capt ur e t o be p e r f o r me d at ea ch v a lid tr ansit ion , so th e pr escaler is disa b l e d (wr i t e ic1 p s bit s to 0 0 in t he timx_ccmr1 register). ena b le capt ur e fr om th e co unt er in to t he ca pt ur e r e g i st er b y set t in g t h e cc1 e bit in t he timx_cce r register . i f ne ede d, ena b l e th e re lat ed in te rr u p t r e q uest b y se tt ing th e cc1i e bit in th e ti mx_di e r re gist er , a nd/ or th e dm a r e q uest b y se tt ing t h e cc1de bit in th e ti mx_di e r re gist er . whe n an in put capt ur e occur s : the tim x _ c cr1 r egist er g e t s t h e v a lue of t he coun t e r on th e acti v e t r a n sit i on. cc 1i f f l ag is s e t ( i n t er r u pt f l ag ). cc1 o f is als o se t if at lea st t w o co n sec ut iv e c a p t u r e s occur r e d wh er eas th e f l ag w a s no t clea re d. an int e r r up t is g e n e r a te d dep en ding o n t he cc1 i e b i t. a dma r equ est is gen er a t e d de pen ding on t he cc1de b i t. i n or de r t o han dle t h e o v e r cap t u r e , it is r e comm end ed t o r ead t h e dat a be f o re t h e o v er capt ur e f l ag . thi s is t o a v oid missing a n o v e r cap t ure wh ich co uld ha pp en af t e r r e a d ing t h e f l ag and b e f o r e re adin g t he da t a . not e : i c in te rr u p t and /o r dma r e q u e s t s can b e ge ner at ed b y sof t w ar e b y set t i ng t he co rr es po nd in g ccxg b i t in t h e t i m x_ e g r r e g i st er . 14.3.6 pwm input mode th is mo de is a pa r t icula r case of i npu t c apt u r e mo de . t he pr oced ur e is t h e sam e e xcept : t w o icx sign als ar e map ped o n t he same t i x inp u t . the se 2 icx sig nals ar e act i v e on ed ge s with o p p o site p o la r i ty . on e of t h e t w o ti xfp sign als is se lecte d as t r igg e r in put and t h e sla v e m ode con t r o lle r is configured in reset mode . general-purpose timers (tim2 to tim5) RM0033 376/1317 doc id 15403 rev 3 f o r e x a m ple , y o u can me asur e th e pe r i od ( i n ti mx_ccr1 r e g i st er ) an d t he du t y cycle ( i n timx_ccr2 register) of the pwm applied on ti1 using the f o llo wing procedure (depending o n ck_ i nt f r e que ncy a nd pr escale r v a lue ) : se lec t t h e a c tiv e in p u t f o r ti mx _c cr1 : w r ite th e cc1 s b i ts to 0 1 in th e ti mx _cc m r1 re gist er ( t i 1 se lect ed) . se lec t th e a c tiv e po la r i ty f o r t i 1 f p1 ( u s e d bo th f o r ca pt ur e in t i m x _cc r 1 a n d co u n te r clear): wr ite the cc1p to ?0? and the c c 1n p bit to ?0 ? (act iv e on r i sing e d g e ) . se lec t t h e a c tiv e in p u t f o r ti mx _c cr2 : w r ite th e cc2 s b i ts to 1 0 in th e ti mx _cc m r1 re gist er ( t i 1 se lect ed) . selec t the ac tiv e polar ity f o r ti1fp2 (us e d f o r capture in timx_ ccr2): w r ite the c c 2p bit to ?1? and the c c 2np bit to ?0?(ac tiv e on f a lling edge). selec t the v a lid tr igger input: wr ite the ts b i ts to 10 1 in th e tim x _s mc r r e g i st er (ti 1 fp1 selected). conf igu r e t h e sla v e mo de con t r o lle r in re se t mo de : wr ite th e sms b i ts t o 100 in th e ti mx_smcr r e g i st er . ena b le t h e ca pt ur es: wr ite th e cc1 e a nd cc2 e b i ts t o ?1 in th e ti mx_ccer re gist er . figu re 14 1. pwm input mo de timing 14.3.7 for ced output mode i n ou tp ut mod e (ccxs bit s = 00 in t h e tim x _ c cmrx reg i ste r ) , ea ch out pu t com par e signa l (o cxr e f an d th e n ocx ) c a n b e f o rc ed to a c t i v e or in ac tiv e le v e l d i r e ct ly b y s o ft w a r e , in dep en den tly of an y com par ison bet w e en t h e o u t p u t comp ar e re giste r an d th e coun te r . t o f o rce an o u t p u t comp ar e signa l ( o cxre f / o c x) t o it s a c t i v e le v e l, y o u just n eed t o wr it e 10 1 in t h e o c xm b i ts in t he cor r esp ond ing ti mx_ ccm rx re gis t e r . t h us o cxr ef is f o r c e d hig h (ocxr e f is alw a y s activ e h i gh ) an d ocx g e t o ppo site v a lue t o ccxp pola r ity bit . e . g .: ccx p=0 (o cx ac tiv e h i gh ) => ocx is f o rce d to h i gh le v e l. ocxref signal can be forced low by writing the ocxm bits to 100 in the timx_ccmrx register. ti 1 timx_cnt 0000 0001 0002 0003 0004 0000 0004 tim x _c cr1 tim x _c cr2 000 4 0 002 i c 1 capture ic2 capture reset counter ic2 capture pulse width i c1 capture period measurement measurement ai15413 RM0033 general-purpose timers (tim2 to tim5) doc id 15403 rev 3 377/1317 an yw a y , the compar ison betw e en the timx_c crx shado w regis t er and the c o unter is still p e r f o r me d and a llo ws t he f l ag t o be se t. in te rr u p t a n d dma re que sts ca n be sen t a c cor d in gly . this is d e scr i bed in t h e out p u t com par e mo de sectio n. 14.3.8 output compare mode th is f u n c t i o n is used to con t r o l an out pu t w a v e f o r m or in dicat i ng whe n a pe r i od o f t i me ha s e l apsed . whe n a ma tch is f o u n d b e t w e en t he cap t u r e / com par e re gist er a nd t h e cou n t e r , t h e out pu t com par e f unct i on : assig n s t h e co rr espo ndin g ou tp ut p i n t o a pr og r a mmab l e v a lu e de fin e d b y t h e o u t p u t comp ar e mo de ( o cxm bit s in t h e tim x _ c cmrx re gist er) an d t h e out pu t pola r ity ( c cxp bit in th e ti mx_ccer re gist er ). t he ou t put pin can k e ep it s le v e l (o cxm=0 00) , b e se t act i v e ( o cxm=001 ), be set in activ e (o cx m=0 10) or can t ogg le ( o cxm=011 ) on mat ch. set s a f l ag i n th e int e r r up t sta t u s r egist er ( c cxi f bit in th e ti mx_sr r e g i st er ). ge ner at es a n int e r r up t if t h e co rr espo ndin g int e r r up t ma sk is set (ccxie bit in th e ti mx_di e r re gist er) . sen d s a dma re qu est if t h e co rr espo ndin g en ab le bit is set ( c cxde b i t in t h e ti mx_di e r re gist er , ccds bit in t he ti mx_cr2 re giste r f o r t h e dma r equ est selection). th e ti mx_ccrx re giste r s ca n be p r o g r a mm ed wit h or wit hou t p r e l oad r e g i st er s u s i ng t he oc xpe b i t in th e ti mx _cc m rx r e g i st er . i n ou tp ut co mpa r e m ode , th e upd at e e v e n t uev has no e f f e ct o n ocxre f an d ocx o u t put . th e t i ming r e solu tio n is o ne cou n t o f t he cou n t e r . o u t p u t comp ar e mod e ca n also be u sed t o o u t put a single p u lse ( i n one - p u lse mo de) . pr oced ure : 1 . sele ct th e coun te r cloc k ( i nt er na l, e xt e r nal, pr esca ler ) . 2 . wr ite t h e desir ed da t a in th e ti mx_arr an d ti mx_ccrx re giste r s . 3 . set th e ccxi e a nd/ or ccxde bit s if an in te rr u p t and /o r a dma req u e s t is t o be ge ner at ed. 4 . sele ct th e ou tp ut m ode . f o r e xamp l e , y o u m u st wr it e o c xm=01 1 , ocxpe=0, ccxp=0 an d ccxe=1 t o to gg le ocx ou tp ut p i n wh en cnt ma tche s ccrx, ccrx pre l oa d is not used , o c x is en ab led a n d a c t i v e hig h . 5 . ena b le t h e co unt er b y se t t in g th e cen bit in th e ti mx_cr1 re giste r . th e ti mx_ccrx re giste r can b e upd at ed a t an y tim e b y sof t w a re to con t r o l t h e o u t put w a v e f o r m , p r o vide d t hat th e pr eloa d re gist er is not en ab led ( o cxpe=0, else ti mx_ccrx sha d o w r e g i st er is up da te d on ly at th e ne xt upd at e e v e n t uev). an e xamp l e is g i v en in fig u r e 14 2 . general-purpose timers (tim2 to tim5) RM0033 378/1317 doc id 15403 rev 3 figu re 14 2. outp ut co mpare mo de , to g g le on oc1. 14.3.9 pwm mode pu lse widt h mo du lat i on mo de a llo ws y ou t o ge ner at e a signa l wit h a f r e que ncy d e t e r m ined b y the v a lue of the timx_arr regis t er and a duty cycle deter mined b y the v a lue of t h e timx_ccrx register . th e pwm m ode ca n be sele ct ed i nde pen de nt ly on e a ch cha nne l ( o n e pwm p e r o c x ou tp u t ) b y wr itin g 11 0 (pw m mo d e 1) o r ?1 1 1 (pwm m o de 2 ) in th e ocx m bit s in t h e ti mx_ccmrx r e g i st er . y o u m u st ena b l e th e co rr espo ndi ng pr elo ad r egist er b y se tt ing t h e o c xpe bit in t h e tim x _ c cmrx re giste r , an d e v en tu ally th e au to -r eloa d pr elo ad r egist er ( i n u p coun t i ng or ce nt er -a ligne d mod e s) b y set t i ng t h e arpe b i t in t h e t i m x _ c r1 r egi st er . as th e pr eloa d re gist ers ar e tr ansf e r r e d to t h e sh ado w re giste r s on ly when an up da te e v ent o c cur s , bef or e sta r tin g th e coun te r , y o u ha v e to in itia liz e a ll t h e r e g i st e r s b y se tt ing t h e ug b i t in t h e ti mx_eg r r egist er . o c x po lar i t y is so ft w a re p r og r a mm ab le using t h e ccxp b i t in t he ti mx_ccer r egist er . it can b e pr og r a mme d as a c tiv e h i gh or activ e lo w . o c x ou tp ut is en ab led b y t h e ccxe b i t in t h e t i m x _ c cer r e g i st er . re f e r t o t he ti mx_ccerx re giste r de scr i p t io n f o r mo re d e t a ils . in pwm m o de ( 1 or 2 ) , t i m x _ cnt a n d t i mx _cc r x ar e alw a ys com p ar e d t o de te r m in e wh et he r ti mx _c crx timx_cnt o r timx_cnt t i m x _ c c r x ( d ep en d i ng o n th e dir e c t ion of th e co un te r) . ho we v e r , to co m p ly with the ocref_clr functionality (ocr ef can be clea re d b y an e x te r n a l e v e n t t h ro ug h t h e etr sig nal unt il t h e ne xt pwm pe r i od ), t he ocref sign al is a s ser t ed o n ly: when t h e re su lt of th e comp ar ison cha nge s , o r when t h e out pu t com par e mo de (o cxm b i ts in ti mx_ccmrx re gist er ) s wit ches fr om t he ? f r o z e n? con f igur a t ion ( no comp ar ison , ocxm=?00 0) t o on e of th e pwm mo de s (o cxm=?1 10 or ?111 ). this f o rce s th e pwm b y so ftw a r e wh ile th e tim e r is r u n n i ng . th e t i mer is ab le t o ge ner at e pwm in e dge -a lign ed mo de or ce nt er -a ligne d mo de d epe nd ing on t h e cm s b i ts in th e ti mx_cr1 re giste r . oc1ref= o c1 ti mx_cnt b200 b201 0039 timx_ccr1 003a wr ite b201 h in th e cc1r reg i ste r match detected on ccr1 interrupt generated if enabled 003b b201 003a RM0033 general-purpose timers (tim2 to tim5) doc id 15403 rev 3 379/1317 pwm edg e -aligned mode up co un tin g co nfig u r atio n upcounting is activ e when the dir bit in th e tim x _ c r1 re gist er is lo w . re f e r t o t he s e ct ion : upcou n t i ng m ode o n pa ge 36 1 . i n t he f o llo wing e x a m ple , w e consid er pwm mo d e 1. t he re f e re nce pwm sig nal ocxref is h i gh as lon g as t i m x _ c nt general-purpose timers (tim2 to tim5) RM0033 380/1317 doc id 15403 rev 3 figure 144. center -align ed pwm wa vef o rms (arr= 8) hint s o n using ce nt er -alig ne d mod e : when st ar t i ng in cen t er- a lig ne d mod e , t he cur r e n t u p - d o w n co nf igu r at ion is used . i t me ans th at t h e cou n t e r cou n t s up o r do wn dep end ing o n t h e v a lue wr itt e n in t h e di r bit in th e tim x _ c r1 r egist er . mo re o v e r , th e di r an d cms bit s m u st no t be chan ge d a t t he s a me t i me b y t h e so ft w a re . wr itin g t o th e co un te r while r u nnin g in cent er -a lign ed mo de is not re co mme nde d as it can lea d t o une xpect ed r e sult s . i n p a r t i c u l ar : ? t he d i re ct ion is no t up dat e d if y o u wr it e a v a lu e in t he cou n t e r t h a t is g r ea te r t h a n th e aut o - r e loa d v a lue (ti m x_cnt>ti m x_arr) . f o r e x am ple , if th e coun te r w a s co unt ing up , it cont in u e s t o cou n t u p . ? t he dir e ct ion is upd at ed if y o u wr it e 0 or wr it e t h e ti mx_arr v a lu e in t h e coun te r b u t no up dat e ev en t uev is gen er a t e d . the safest way to use center-aligned mode is to generate an update by software (setting the ug bit in the timx_egr register) just before starting the counter and not to write the counter while it is running. # # x ) & # o u n t e r r e g i s t e r # # 2 x / # x 2 % & # - 3 # - 3 # - 3 # # x ) & # # 2 x / # x 2 % & # - 3 o r # # x ) & # # 2 x / # x 2 % & # - 3 # - 3 # - 3 g g # # x ) & # # 2 x / # x 2 % & # - 3 # - 3 # - 3 g g # # x ) & # # 2 x / # x 2 % & # - 3 # - 3 # - 3 g g a i b RM0033 general-purpose timers (tim2 to tim5) doc id 15403 rev 3 381/1317 14.3.10 one-pulse mode o ne- pu lse m ode (opm ) is a p a r t icu l ar case o f t he p r e vio us m ode s . i t a llo ws th e coun te r t o b e st ar t e d in resp onse t o a stim u l us a n d t o ge ne r a t e a pu lse wit h a pr og r a mma b le leng t h a f t e r a pr og r a mmab le d e la y . st ar t i ng t h e cou n t e r ca n be con t r o lle d th ro ugh t h e sla v e mo de con t r o lle r . ge ner at ing t h e w a v e f o r m can b e d one in ou tp ut co mpa r e mod e or pwm mod e . y o u sele ct on e- pulse m ode b y set t in g t h e o p m bit in t he ti mx_cr1 r egist er . th is mak e s th e cou n t e r sto p a u t o ma t i ca lly a t t he n e xt up da te e v ent uev . a pu lse can be cor r e c t l y g ene r a t e d only if t h e com par e v a lu e is di ff er en t f r o m t h e co unt e r in itia l v a lue . bef o r e st ar t i ng ( w hen th e t i me r is w a it in g f o r t h e t r igge r) , th e conf ig ur a t io n m u st be : in upcounting: cnt general-purpose timers (tim2 to tim5) RM0033 382/1317 doc id 15403 rev 3 th e opm w a v e f o r m is de f i ned b y wr it ing t h e co mpa r e r e g i st er s ( t aking int o a c cou n t th e cloc k fr eq ue ncy an d t he coun t e r p r escale r) . the t dela y is defined b y the v a lue wr itte n in the timx_ccr1 register . the t pulse is de fin e d b y t h e dif f er ence be tw een t he aut o- r e loa d v a l ue a n d t he co mpa r e v a lue (timx_arr - timx _cc r 1). le t? s sa y y ou w a nt t o b u ild a w a v e f o r m with a tr a n sit i on f r o m ?0 to ?1 wh en a com par e ma tch occur s an d a t r an sit i on fr om ?1 t o ?0 when th e co un te r re ache s t he a u t o -r elo a d v a lu e . t o do th is y o u ena b l e pwm mo de 2 b y wr it ing o c 1 m =111 in th e ti mx_ccm r1 re gist er . y o u can op ti ona lly en ab le t he p r elo a d r e g i st er s b y wr it ing o c 1pe=1 in th e ti mx_ccmr1 re giste r an d arpe in t he ti mx_cr1 re gist er . i n t h is ca se y o u ha v e t o wr ite the c o mpare v a lue in the timx_ccr1 register , the auto-reload v a lue in the ti mx_arr r egist er , g e n e r a te a n up dat e b y set t i ng t h e ug bit an d w a it f o r e x t e r nal tr ig g e r e v en t on ti2 . c c 1 p is wr itt e n to ?0 in th is e x am p l e . i n ou r e x am ple , t h e di r a nd cms bit s in t h e t i m x _ c r1 r egist er sh ould b e lo w . y o u on ly w a nt 1 pulse ( s i ngle m ode ), so y o u wr ite ' 1 in th e opm b i t in t he ti mx_cr1 r e g i st er to st op t h e cou n t e r a t t h e n e xt u pda te e v ent (whe n t he cou n t e r r o lls o v e r f r o m t h e a u t o - r e l oad v a lue ba c k t o 0) . whe n opm b i t in t he ti mx_cr1 re gist er is se t t o '0' , so th e re pe titiv e mo d e is se le cte d . p a r t icula r c ase: ocx fast e n ab le: i n on e- pulse mo de , th e edg e de te ct ion on ti x in put set t h e cen bit which e nab les t he cou nt er . t hen t h e co mpa r iso n be tw een th e co un te r an d th e comp are v a lue ma k es th e o u t put t ogg le . but se v e r a l cloc k cycles ar e nee de d f o r t hese o per a t ions an d it limit s t h e minimum delay t dela y min we ca n ge t. i f y o u w a n t t o ou tp ut a w a v e f o r m wit h th e minim u m dela y , y ou can set th e ocxfe b i t in t h e tim x_ ccm rx re gis t e r . th en o c xr ef (a n d oc x) is f o r ced in r e s p o n se to th e stimulu s , wit hou t t a king in acco unt t he comp ar ison . i t s ne w le v e l is t h e sam e as if a comp are mat ch h ad occur r e d . o c xf e act s o n ly if t he chan ne l is co nf igu r e d in pwm 1 or pwm2 mo de . 14.3.11 clearing the ocxref signal on an e x ternal e vent 1. th e e xt e r n al t r igg e r p r e sc a le r sh ou ld be k e pt o ff: b i ts e t ps [1: 0 ] in th e tim x_ s mc r re gist er a r e clea re d to 0 0 . 2. t h e e xt e r n al c l oc k m o d e 2 m u s t b e d i sab l ed : bit ece in the t i m 1 _s mc r r e g i ste r is clear ed t o 0 . 3 . the e xte r n a l tr ig ger pola r it y (et p ) and th e e xte r n al tr ig ge r filt e r (etf ) can be conf igu r e d accor d ing t o t h e a pplica t io n? s ne eds . fig u r e 14 6 sh o w s th e be ha vio r of t he ocxref sign al when t h e etrf in pu t be co mes hig h , f o r bot h v a lu es o f t h e o c xce ena b l e b i t . i n th is e x a m ple , th e tim e r ti mx is p r og r a mm ed in pwm mode . RM0033 general-purpose timers (tim2 to tim5) doc id 15403 rev 3 383/1317 fi gu re 14 6. cl ear in g tim x ocxref 1. in case of a pwm with a 100% duty cycle (if c crx> a r r ), ocxref is enabled again at the next counter overflow. 14.3.12 encoder interface mode t o se lect en co de r i n t e r f a c e mod e wr ite sms=?001 in t he ti mx_sm c r re gist er if t he cou n t e r is co un tin g on t i 2 e dge s o n ly , sms=010 if it is coun tin g on t i 1 edg es o n ly and sm s=0 11 if it is cou n t i ng on bot h ti 1 an d ti 2 ed ges . se lect th e ti 1 an d ti 2 pol ar it y b y p r o g r a mm ing th e cc1p a nd cc2 p bit s in t h e ti mx_ccer r e g i st er . cc1np and cc2np m u st be k ept cle a r ed. when n e e ded , y o u ca n pr og r a m th e in put fil t e r as w e ll. th e t w o inp u t s t i 1 a nd ti 2 ar e use d to in te rf ace t o an in crem ent a l e n code r . ref e r t o ta b l e 5 9 . the co unt er is cloc k e d b y ea ch v a lid tr ansit ion o n ti 1fp1 or ti 2fp2 ( t i 1 and ti2 a f t e r inpu t f ilt er a nd po lar i t y sele ct io n, t i 1 f p1=ti 1 if n o t f ilt er ed a nd no t in v e r t ed, ti 2 f p2=ti 2 if no t f ilt er ed an d no t in v e r t ed) assu ming t h a t it is en ab led ( c en bit in ti mx_cr1 r egist er wr it te n t o ?1) . th e se qu ence of tr ansit ion s of th e t w o in put s is e v alu a t e d a nd gen er a t e s count pulses a s w e ll as t h e dir e ct ion sig n a l . de pen din g o n t h e sequ en ce t he co un te r co un ts up o r do w n , th e dir b i t in th e tim x_ cr1 r e g i ste r is m o dif i ed b y h a r d w a re a c cor d in gly . the di r b i t is ca lcu l at ed a t ea ch tr a n sit i on o n an y in put (ti1 o r ti 2) , wha t e v er t h e cou n t e r is coun tin g on t i 1 o n ly , ti 2 on ly or bot h ti 1 a nd ti 2. enc o d e r in te rf ac e mo d e act s s i mp ly as an e x ter n al c l oc k with direction selection. this me an s t hat th e co un te r just cou n t s con t in u ously bet w e en 0 an d t he au to -r elo ad v a lu e in th e ti mx_arr reg i ste r (0 t o arr o r arr do wn t o 0 dep en ding o n t he dir e ct ion ) . so y o u m u st con f ig ur e ti mx_arr be f o re st ar t i ng . i n th e same w a y , th e ca pt ur e , comp ar e , pr escaler , t r igg e r o u t p u t f eat ur es co nt in ue t o w o r k a s n o r m al. i n t h is m ode , th e coun te r is m odif i e d aut om at ica lly f o llo wing t h e sp eed and t h e dire ctio n of t h e in cr em ent al e n code r an d it s cont en t , t her ef or e , a l w a ys r e p r ese n t s t he e n code r? s po sit i on . t h e co un t dir e c t ion c o r r e sp o n d to th e ro ta tio n dir e ctio n of th e co nn e cte d se ns or . th e t a b l e su mma r i z e s th e po ssib le comb inat ion s , a ssu ming t i 1 a nd ti 2 d on?t s wit ch at t h e sa me t i me . ocxref counter (cnt) ocx r ef etrf (o cxce=0) ( o cxce=1) ocr e f _ cl r be c o me s hi g h ocref_c l r still high (ccrx) general-purpose timers (tim2 to tim5) RM0033 384/1317 doc id 15403 rev 3 an e x t e r nal in cr eme n t a l en co de r can be co nne ct ed dire ctly to t h e mcu with out e x t e r n al in te rf ace log i c. ho w e v e r , comp ar a t o r s are n o r m ally be use d to co n v er t th e en co der ? s d i ff er en tia l o u t p u t s to digit a l sign als . this g r e a t l y incr ease s no ise imm unit y . the th ird e n code r ou t put wh ich indicat e t h e m e chan ical z e r o po sit i on , ma y b e co nne cte d to a n e x t e r n a l in te rr u p t in pu t an d tr i gge r a coun te r r e set . fig u r e 14 7 giv e s an e x a m ple o f cou n t e r o per at ion, sho wing coun t sign al ge ner at ion an d d i re ct ion co nt rol . i t also sho w s h o w inp u t jit t e r is comp ensat e d wh er e bot h e dge s ar e sele ct e d . thi s migh t occu r if th e sen sor is po sit i on ed ne ar t o o ne of t h e s w it ching p o int s . f o r t h is e xamp l e w e a s su me t hat th e conf igu r at ion i s t he f o llo wing : cc1 s = 01 ( t i m x_ccmr1 re giste r , ti 1f p1 map ped o n ti 1) cc2 s = 01 ( t i m x_ccmr2 re giste r , ti 2f p2 map ped o n ti 2) cc1 p =0 , cc1np = ?0? (timx_ ccer r e g i st er , ti 1fp1 no nin v er t e d , ti 1fp1 =t i1 ) cc2 p =0 , cc2np = ?0? (timx_ ccer r e g i st er , ti 2fp2 no nin v er t e d , ti 2fp2 =t i2 ) sms= 011 (timx_smcr register , both inputs are ac tiv e on both r i sing and f a lling ed ges) cen= 1 (ti m x_cr1 r egist er , cou n t e r i s en ab led ) figu re 14 7. ex ample of c ount er op era t ion in e n co der int e rf ace m o de t a b l e 59 . c oun ting dire ction v e r s us e n co der sign als active edg e le v e l o n op po si te si gn al (t i1 fp1 f o r ti2, ti2fp2 f o r ti1) ti1fp1 signal ti2 f p2 signal rising f a lli ng rising f a lli ng cou n ting on ti1 only h i gh do wn up no coun t n o co unt lo w u p d o w n n o coun t n o co unt cou n ting on ti2 only h igh no coun t no co unt up do wn lo w n o coun t n o co unt do wn up cou n ting on ti1 an d ti2 h igh do wn up up do wn l ow u p d ow n d ow n u p ti1 fo r w a rd f or w a r d bac k w ar d jitte r jitte r up do wn up ti2 co unt er RM0033 general-purpose timers (tim2 to tim5) doc id 15403 rev 3 385/1317 fig u r e 14 8 giv e s an e x a m ple o f cou n t e r b eha vior wh en ti 1fp1 p o la r i ty is in v e r t ed ( s a m e con f ig ur a t io n as abo v e e x cep t cc1p=1) . fi gu re 14 8. ex ampl e of e n cod e r i n te rf ace mod e wi th t i 1 f p1 pol ari t y in v e r t e d th e t i mer , when co nf igu r e d in enco der in t e rf a c e mod e pr o v id es inf o r m at ion on t h e se nsor ? s cur r e n t posit ion. y o u ca n obt a i n dynam ic in f o r m a t io n (spe ed, acceler a t i on, de ce ler a tio n ) b y me asur in g t he pe r i od b e t w ee n t w o en code r e v e n t s using a se co nd t i me r conf igu r e d in cap t u r e m ode . the o u t p u t of th e en co der wh ich indicat e s t he me ch an ica l z e ro ca n be u s e d f o r th is pu r p ose . dep end ing o n th e tim e be tw een t w o e v en ts , t he coun t e r can a l so b e re ad a t r egu lar t i me s . y o u can do t h is b y lat chin g th e coun te r v a lu e int o a t h ir d inpu t cap t u r e r e g i st er if a v ailab l e ( t h en t h e cap t u r e sig nal m u st b e pe r i odic an d ca n be g ene r a t e d b y a not he r t i mer ) . when a v aila b l e , it is also po ssib le to rea d it s v a lu e th ro ugh a dm a r equ est g ene r a t e d b y a re al- t ime cloc k. 14.3.13 timer input xor function th e ti 1s bit in th e ti m 1 _ c r2 r egist er , a llo ws t he inp u t filt er of cha n n e l 1 to b e conn ecte d t o t h e o u t p u t of a xor gat e , com b inin g th e t h r ee inp u t pins ti mx_ch1 t o ti mx_ch3. th e xor out pu t can b e used wit h all t he t i mer inpu t f u n c t i on s such as t r igge r or inpu t ca pt ur e . an e xa m ple of th is f eat u r e used t o int e r f ace ha ll sen s o r s is giv e n in se ct ion 13. 3. 18 o n pag e 32 5 . 14.3.14 timer s and e x ternal trig g e r sync hr onization t h e t i m x tim e rs ca n be sy nc hr on iz ed w i th an e xt e r n a l t r igg e r in se v e r a l mo d e s: re se t mo de , g a t e d m ode a n d t r igge r mo de . sla v e mode: res e t mode th e cou n t e r an d it s pr escaler can be re init ializ e d in re sp on se t o an e v e n t on a t r ig ger inp u t . mo re o v er , if th e urs bit f r om t he ti mx_cr1 re gist er is lo w , an up da te e v ent uev is g ene r a t e d . th en a ll t h e p r e l oa ded r e g i st er s ( ti m x_arr, ti mx_ccrx) a r e u pda te d. i n t he f o llo wing e x a m ple , th e up co unt e r is clea re d in re sp onse t o a r i sing e dge on ti 1 inp u t : conf igu r e th e cha nne l 1 t o d e t e ct r i sin g e dge s o n ti 1 . con f ig ur e t h e inpu t filt er du r a t i on (in th is e xam ple , w e do n?t n e e d an y f ilt er , so w e k eep i c 1f=0 000 ). the cap t u r e ti1 f o r w ar d f orw a r d bac kw ard jitter jitte r up do w n ti2 co unte r do wn general-purpose timers (tim2 to tim5) RM0033 386/1317 doc id 15403 rev 3 pr escaler is no t u s e d f o r t r igge r i ng , so y o u d on?t ne ed t o conf igu r e it . t he cc1s bit s select t h e inpu t cap t u r e sou r ce on ly , cc1s = 0 1 in t he ti mx_ccmr1 re gist er . wr it e cc 1p= 0 an d cc1 np= 0 in t i mx _cc e r r e gist er to v a lid at e the p o l ar it y ( a n d de te ct r i sing e dge s on ly). configure the timer in reset mode b y wr it ing sms= 100 in timx _smc r register . select ti1 as the input source b y wr iti n g t s =1 01 in t i m x _ s m cr re gis t er . st ar t th e co un te r b y wr itin g cen= 1 in t h e t i m x _ c r 1 r e gist er . th e coun te r sta r ts co un tin g on t h e in te r n al clo c k, t hen b e h a v e s no r m a lly u n t il t i 1 r i sing e dge . wh en ti 1 r i ses , t he cou n t e r is cle a r ed an d re sta r t s fr om 0. i n th e mea n t i me , t h e tr ig ge r fla g is se t (tif b i t in t h e tim x _ s r re gis t e r ) a n d a n int e r r up t r e qu es t, or a dm a r e q uest can be sent if e nab led (de p e ndin g on t h e t i e an d tde b i ts in ti mx_di e r re gist er) . th e f o llo wing f i gu re sho w s t h is be ha vio r when t h e aut o- r e loa d re giste r ti mx_arr=0 x 3 6 . th e de la y b e t w e en t h e r i sing edg e on ti 1 a nd t he a c t u a l r e set of th e co un te r is d ue t o th e re syn ch ro n i za tion c i rcu i t on ti1 in pu t. figu re 14 9. cont r o l c i r c uit in res e t mo de sla v e mode: gated mode th e coun te r can b e ena b l ed de pe ndin g on t h e le v e l of a se lecte d inp u t . i n t he f o llo wing e x a m ple , th e up co unt e r co un ts only when t i 1 in pu t is lo w: conf igu r e t h e ch ann el 1 t o de te ct lo w le v e ls on ti1 . con f ig ur e th e inp u t f ilt er d u r a tio n (in th is e x am ple , w e do n?t n e e d an y f ilt er , so w e k eep i c 1f=0 000 ). the cap t u r e pr escaler is no t u s e d f o r t r igge r i ng , so y o u d on?t ne ed t o conf igu r e it . t he cc1s bit s se le ct the in p u t ca pt ur e so ur ce o n ly , c c 1 s =0 1 in t i mx _cc m r 1 re gis te r . w r ite cc 1p= 1 an d cc 1np = 0 in t i m x _ ccer r e g i ste r to v a lid at e th e po lar i t y ( a nd d e t ec t lo w le v e l only). conf igu r e th e t i mer in g a t ed m ode b y wr iti ng sms=10 1 in t i m x _ s m c r r egist er . select ti1 as the input source b y wr iti n g t s =1 01 in t i m x_ s m cr re gis t er . ena b le t h e co unt er b y wr i t in g cen=1 in t he ti mx_cr1 re gist er ( i n gat e d mod e , t he coun te r do esn?t st ar t if cen=0 , what e v er is the tr igger input le v e l). t h e co un te r sta r ts co un tin g on th e int e r n al c l oc k as lon g as ti 1 is lo w an d sto p s as so on a s ti1 b e co m e s h i gh . the tif fla g in th e tim x_ s r r e g i st er is se t bo th w h e n th e co un te r sta r t s or st op s . th e de la y b e t w e en t h e r i sing edg e on ti 1 a nd t he a c t u a l st op o f t he cou n t e r is due to t h e re syn ch ro n i za tion c i rcu i t on ti1 in pu t. 00 co u n ter c l o c k = ck _cnt = ck_p sc cou n te r regist er 01 02 0 3 00 01 0 2 03 32 33 34 35 36 ug ti 1 31 30 tif RM0033 general-purpose timers (tim2 to tim5) doc id 15403 rev 3 387/1317 figu re 15 0. cont r o l c i r c uit in gat e d mod e 1. th e conf iguratio n ?ccxp=ccxnp=1? (detection of both rising and falli ng edges) d oes n o t have any effect in gated mode becau se ga ted mode acts on a level and no t on an edge . sla v e mode: t r ig g e r mo de th e coun te r can st ar t in r e spo n se t o an e v e n t o n a select ed in put . i n t he f o llo wing e x a m ple , th e up co unt e r st a r t s in resp onse t o a r i sing e dge o n ti 2 inp u t : conf igu r e th e cha nne l 2 t o d e t e ct r i sin g e dge s o n ti 2 . con f ig ur e t h e inpu t filt er du r a t i on (in th is e xam ple , w e do n?t n e e d an y f ilt er , so w e k eep i c 2f=0 000 ). the cap t u r e pr escaler is no t u s e d f o r t r igge r i ng , so y o u d on?t ne ed t o conf igu r e it . cc2s bit s a r e select ing t h e in pu t capt ur e sou r ce on ly , cc2s=01 in t i m x _ c cmr1 r egist er . wr it e cc 2p= 1 an d cc 2np = 0 in t i m x_ ccer r e g i ste r to v a lid at e th e po lar i t y ( a nd d e t ec t lo w le v e l only). configure the timer in tr igger mode b y wr it ing sms=110 in timx_smcr regis t er . select ti2 as the input source b y wr iti n g t s =1 10 in t i m x_ s m cr re gis t er . whe n a r i sing ed ge o c cu rs o n ti 2, th e co un te r sta r t s co unt in g on t he in te r n a l clo c k an d t he tif flag is se t. th e de la y b e t w e en t h e r i sing edg e on ti 2 a nd t he a c t u a l st ar t o f t h e cou n t e r is du e to t h e re syn ch ro n i za tion c i rcu i t on ti2 in pu t. figu re 15 1. cont r o l c i r c uit in tr ig g e r mode sla v e mode: exte rn al cloc k mode 2 + trig g e r mode th e e xt e r n al cloc k m ode 2 ca n be u s e d in ad dit i on t o an ot he r sla v e mo de ( e xce p t e xte r n al cloc k mod e 1 an d en co der mod e ). i n th is case , t h e etr signa l is used a s e x t e r nal cloc k in put , a n d a not h e r in put ca n be sele ct e d as t r ig ger in pu t whe n ope r a t i ng in rese t mo de , co u n ter c l o c k = ck _cnt = ck_p sc counter register 35 36 3 7 38 32 33 34 ti 1 31 30 cnt_en tif write tif=0 counter clock = ck _cnt = ck_p sc cou n te r regist er 35 36 3 7 38 34 ti2 cnt_en tif general-purpose timers (tim2 to tim5) RM0033 388/1317 doc id 15403 rev 3 g a t ed mo de o r tr igge r mo de . i t is re co mme nde d not t o se lect etr as trg i t h r o u gh t he ts b i ts of t i m x _ s mcr r egist er . i n th e f o llo win g e x a m ple , t h e u p coun te r is incre m en t ed at ea ch r i sing e dge of t h e etr sig nal a s soon as a r i sin g edg e of ti 1 occu rs: 1 . conf igu r e t h e e x te r n a l tr ig ger inpu t circu i t b y pr og r a mmin g t he ti mx_smcr re giste r as f o llo ws : ? e t f = 00 00: no f ilt er ? e tps = 00 : pr es ca ler d i sa b l ed ? e t p =0 : d e t e ct ion o f r i sing edg es on et r a n d ece=1 t o en ab le t h e e x te r n al cloc k mod e 2. 2 . conf igu r e t h e ch ann el 1 as f o llo ws , t o de te ct r i sing ed ges on t i : ? i c1f= 0000: no filter . ? t he cap t u r e p r e s cale r is n o t used f o r t r ig ger in g an d doe s n o t n eed to b e co nf igur ed . ? c c1 s=0 1 in t i m x_ ccm r 1 r e gist er to s e le ct on ly th e in p u t ca pt ur e so ur ce ? c c1 p=0 an d cc 1np = 0 in t i mx _c cer r e gist er to v a lid ate t h e p o la r i ty (a nd d e t ec t r i sin g ed ge on ly) . 3. co n f ig ur e th e tim e r in tr ig g e r m o de b y wr iting sms=110 in timx_smcr regis t er . select ti1 as the input source b y wr iti n g t s =1 01 in t i m x_ s m cr re gis t er . a r i sing ed ge o n ti 1 ena b l es t h e co unt er and se ts th e ti f fla g . t he cou n t e r t h e n co un ts on etr r i sing ed ge s . th e de la y b e t w e en t h e r i sing edg e of t h e etr sign al and th e actu al re set o f t h e cou n t e r is du e to th e r e sy nc hr on iza t io n circ uit o n e t r p in pu t. figu re 15 2. cont r o l ci r c uit in e x t e rna l c l oc k mode 2 + t r ig g e r mode 14.3.15 timer sync hr onization th e ti mx t i me rs ar e link e d to get he r int e r n a lly f o r t i me r syn c h r o n izat ion o r chain i ng . whe n o ne tim e r is co nf igu r ed in mast er mo de , it can r e set , sta r t, st o p or cloc k th e coun te r of a not he r tim e r con f ig ur ed in sla v e mod e . f i gu re 1 5 3 : ma st er /sla v e t i m e r e xam p l e pr es en ts a n o v er vie w o f th e tr ig g e r se lec t io n an d th e ma st er m o d e se lec tio n b l oc k s . counter clock = ck_cnt = ck_p sc cou n t e r regist er 35 36 34 etr cen/cnt_en tif ti1 RM0033 general-purpose timers (tim2 to tim5) doc id 15403 rev 3 389/1317 using one time r as presca ler f o r a nother fi gu re 15 3. m ast er/ s l a ve t i me r e x ampl e f o r e xa m ple , y o u can con f ig ur e timer 1 to act as a pr escaler f o r time r 2. re f e r t o fig u r e 15 3 . t o d o th is: conf igu r e t i mer 1 in mast er m ode so t h a t it o u t p u t s a pe r i odic tr ig ge r signa l o n ea ch up dat e e v e n t uev . i f y o u wr ite m m s=0 1 0 in t h e tim 1_cr2 re gist er , a r i sin g edg e is ou tp ut o n trgo 1 ea ch t i me a n up dat e e v e nt is ge ner at ed. t o con nect t h e trgo1 o u t p u t of time r 1 t o time r 2, timer 2 m u st be co nf igur ed in sla v e m ode u s in g i t r1 as in te r n al tr ig ge r . y o u se lect t h is th ro ugh t h e t s b i ts in t he ti m2_ s mcr r egist er ( w r i tin g ts=000 ). the n y o u pu t t h e sla v e mo de con t rolle r in e xte r n a l clo c k m ode 1 ( w r i t e sms=11 1 in t h e ti m2_ s mcr r egist er ). this ca uses timer 2 to b e cloc k e d b y th e r i sing ed ge o f t he pe r i odic time r 1 t r igg e r sign al (which cor r e s p o n d to t h e t i me r 1 cou n t e r o v er f l o w ) . fina lly bo th tim e rs m u st be e n a b le d b y se ttin g th eir re sp e ctiv e c e n b i ts (tim x_ cr 1 re gist er ). not e : i f o c x is sele ct e d on tim e r 1 a s t r igge r ou t put (mm s=1 x x) , it s r i sing e dge is used t o cloc k th e co un te r o f tim e r 2 . using one time r to enab le another timer i n t h is e xamp l e , w e con t r o l t h e e nab le o f time r 2 wit h th e out p u t com par e 1 of time r 1. ref e r to fig u r e 153 f o r co nne ct io ns . time r 2 co un ts on t he d i vid e d int e r nal cloc k o n ly when o c 1 r ef o f tim e r 1 is high . bot h cou n t e r cloc k f r eq ue ncies a r e d i vided b y 3 b y th e pr es ca ler co m p a r e d to c k _i nt (f ck_cnt = f ck_int /3 ). conf igu r e t i mer 1 mast er mo de t o sen d its out p ut com par e 1 ref e r e n c e ( o c1ref) signa l a s t r igg e r o u t p u t (m ms=100 in t h e ti m1_ c r2 r egist er ). conf igu r e t h e timer 1 oc1ref w a v e f o r m ( t i m 1_ ccmr1 r e g i st er ). conf igu r e t i mer 2 to g e t t h e inpu t t r igg e r f r o m time r 1 (t s=0 00 in t h e t i m 2_smcr re gist er ). conf igu r e t i mer 2 in gat e d mod e (sms=10 1 in ti m2_ s mcr r egist er ). enab le timer 2 b y w r iting ?1 in the ce n bit (tim2_cr1 register). star t timer 1 b y wr iting ?1 in t h e cen bit ( t i m 1_ cr1 r e g i st er ) . not e : t h e coun te r 2 cloc k is no t synchr oniz ed wit h co unt e r 1, t h is mo de on ly a f f e ct s t h e t i mer 2 co un te r en ab le sig n a l . trgo1 uev itr1 prescaler cou n ter sms ts mms tim1 ti m2 mast er mode cont rol sl a v e mode control ck_psc p r escale r count er cl ock input selection tr ig ge r general-purpose timers (tim2 to tim5) RM0033 390/1317 doc id 15403 rev 3 fi gu re 15 4. g a t i n g t i mer 2 wi t h o c 1ref o f ti mer 1 i n t he e x a m ple in f i gur e 15 4 , th e time r 2 coun te r an d pr esca ler a r e n o t init ializ e d be f o re be in g sta r te d. so th e y st ar t co un tin g fr om t h e i r cu rr en t v a lu e . i t is p o s s ib le to s t ar t fr o m a g i v en v a lu e b y re se tt in g bot h t i mer s b e f o r e sta r t i n g time r 1. y ou can t h e n wr ite a n y v a lu e y o u w a n t in t h e t i me r coun te rs . th e tim e rs can e a s i ly b e re se t b y so ft w a r e u s in g th e ug b i t in th e ti mx _eg r re gis t e r s . in th e ne xt e x a m p l e , w e sy nc hr on iz e tim e r 1 an d t i m e r 2. t i me r 1 is t h e m a ste r an d sta r ts f r o m 0. timer 2 is t h e sla v e and st ar t s f r o m 0xe7. t he pr escale r r a t i o is th e sa me f o r b o t h t i me rs . tim e r 2 sto p s whe n tim e r 1 is disab l ed b y wr iting ?0 to the cen bit in the tim1_c r1 re gis t e r : conf igu r e t i mer 1 mast er mo de t o sen d its out p ut com par e 1 ref e r e n c e ( o c1ref) signa l a s t r igg e r o u t p u t (m ms=100 in t h e ti m1_ c r2 r egist er ). conf igu r e t h e timer 1 oc1ref w a v e f o r m ( t i m 1_ ccmr1 r e g i st er ). conf igu r e t i mer 2 to g e t t h e inpu t t r igg e r f r o m time r 1 (t s=0 00 in t h e t i m 2_smcr re gist er ). conf igu r e t i mer 2 in gat e d mod e (sms=10 1 in ti m2_ s mcr r egist er ). reset timer 1 b y w r i t ing ?1 in ug b i t (tim 1 _ eg r r e gist er ). reset timer 2 b y w r i t ing ?1 in ug b i t (tim 2 _ eg r r e gist er ). initializ e timer 2 to 0x e7 b y wr iting ?0 x e 7? in t h e t i me r 2 co un te r (t im 2_ cn tl ) . enab le timer 2 b y w r iting ?1 in the ce n bit (tim2_cr1 register). star t timer 1 b y wr iting ?1 in t h e cen bit ( t i m 1_ cr1 r e g i st er ) . stop timer 1 b y wr iting ?0 in the cen bit (tim1_c r 1 regis t er). tim e r 2 - ti f writ e tif=0 fc f d fe ff 00 304 5 3047 3048 ck_int ti mer1- o c1ref ti mer1- cnt timer2-cnt 01 3046 RM0033 general-purpose timers (tim2 to tim5) doc id 15403 rev 3 391/1317 figu re 155. gatin g timer 2 with en ab le of timer 1 using one time r to star t a nother time r in th is e xa m ple , we se t t h e e n a b le o f tim e r 2 wit h th e up da te e v e n t o f tim e r 1 . r e f e r to fig u r e 15 3 f o r conn ect i ons . time r 2 sta r ts coun tin g f r om it s cu rr ent v a lue ( w hich can be no n z e r o) on th e d i vid e d in te r n a l clo c k as so on a s th e up da te e v en t is ge ne r a ted b y tim e r 1 . whe n time r 2 re ceiv es th e tr i gge r signa l it s cen bit is au to mat i cally se t an d th e coun te r counts until w e wr ite ?0 to the cen bit in th e ti m2 _ cr1 r e g i ste r . bo th co un te r clo c k f r e q u encies ar e divide d b y 3 b y t h e p r e s cale r comp ar ed t o ck_ i nt ( f ck_cnt = f ck_int /3 ). co n f ig ur e tim e r 1 m a ste r m o d e to se nd it s u p d a t e ev e n t (u ev) as tr ig ge r ou tp ut (m ms=010 in t h e tim 1_cr2 r egist er ). conf igu r e t h e timer 1 per iod ( t im 1_arr r e g i st e r s). conf igu r e t i mer 2 to g e t t h e inpu t t r igg e r f r o m time r 1 (t s=0 00 in t h e t i m 2_smcr re gist er ). configure timer 2 in tr igger mode (sm s =11 0 in ti m2 _smcr r e g i st er ). star t timer 1 b y wr iting ?1 in t h e cen bit ( t i m 1_ cr1 r e g i st er ) . figu re 15 6. t rig g e rin g timer 2 wit h upda te of timer 1 ti m e r 2 - t i f writ e tif=0 7 5 00 01 ck_int timer1- c en= c nt_en ti mer1- cnt ti mer2- cnt 02 ti mer1- cnt _i nit ab 00 e7 e8 e 9 timer2-cnt_init timer2 write cnt ti mer 2-tif writ e tif=0 fd fe ff 00 01 4 5 47 48 ck_int timer1-u ev ti mer 1 - cnt ti mer 2 - cnt 02 46 ti mer2- c en=cnt_en general-purpose timers (tim2 to tim5) RM0033 392/1317 doc id 15403 rev 3 as in th e pr e v iou s e x am ple , y o u ca n init ializ e bo th cou n t e r s b e f o re st ar t i ng cou n t i ng . fig u r e 15 7 sh o w s th e be ha vio r wit h th e sa me con f ig ur a t io n as in figu re 1 5 6 b u t in t r igg e r mo de in st ea d of gat e d mod e (sms=11 0 in t he ti m2 _smcr r egist er ). figu re 157. t r ig g e rin g timer 2 with e n ab le of timer 1 using one time r as presca ler f o r a nother time r f o r e x a m ple , y o u can con f ig ur e timer 1 to act as a pr escaler f o r time r 2. re f e r t o fig u r e 15 3 f o r conn ect i ons . t o d o th is: co n f ig ur e tim e r 1 m a ste r m o d e to se nd it s u p d a t e ev e n t (u ev) as tr ig ge r ou tp ut (m ms=010 in t h e ti m1 _cr2 r e g i st e r ) . t hen it out pu ts a per io dic sig nal on e a ch co un te r ov e r f l ow . conf igu r e t h e timer 1 per iod ( t im 1_arr r e g i st e r s). conf igu r e t i mer 2 to g e t t h e inpu t t r igg e r f r o m time r 1 (t s=0 00 in t h e t i m 2_smcr re gist er ). conf igu r e t i mer 2 in e x te r n al clo c k mo de 1 ( s ms=111 in tim 2_sm c r re giste r ) . star t timer 2 b y wr iting ?1 in t h e cen bit ( t i m 2_ cr1 r e g i st er ) . star t timer 1 b y wr iting ?1 in t h e cen bit ( t i m 1_ cr1 r e g i st er ) . star ti ng 2 time r s s y nc hr onousl y in re sponse to an e x te rna l trig g e r in this example, we set the enable of timer 1 when its ti1 input rises, and the enable of timer 2 with the enable of timer 1. refer to figure 153 for connections. to ensure the ti mer 2-tif write tif=0 75 00 01 ck_i nt ti mer1- c en= cnt_en timer1-c nt timer2-c nt 02 timer1- cnt_ini t cd 0 0 e7 e8 ea timer2-cnt_init timer2 write cnt e9 RM0033 general-purpose timers (tim2 to tim5) doc id 15403 rev 3 393/1317 cou n t e r s ar e a lign ed, t i mer 1 m u st be conf ig ure d in m a ste r / s la v e mo de (sla v e wit h resp ect t o ti 1, mast er wit h re sp ect t o time r 2) : conf igu r e t i mer 1 mast er mo de t o sen d its enab le a s t r igge r ou tp ut (mm s=0 01 in t h e t im 1 _cr 2 re gis te r ) . conf igu r e t i mer 1 sla v e mo de t o ge t t he inp u t tr ig ge r fr om ti 1 ( t s=100 in th e ti m1_ s mcr r egist er ). conf igu r e t i mer 1 in tr ig ge r mod e (sm s =11 0 in t he ti m1 _smcr r e g i st er ). conf igu r e th e time r 1 in mast er /sla v e mo de b y wr it ing msm=1 ( t im 1_sm c r re gist er) . conf igu r e t i mer 2 to g e t t h e inpu t t r igg e r f r o m time r 1 (t s=0 00 in t h e t i m 2_smcr re gist er ). conf igu r e t i mer 2 in tr ig ge r mod e (sm s =11 0 in t he ti m2 _smcr r e g i st er ). whe n a r i sin g ed ge o ccu rs on ti 1 (t imer 1) , b o t h cou n t e r s st ar t s cou n t i ng synchr on ou sly on th e int e r n a l c l oc k an d b o th ti f fla g s ar e se t. not e : i n t h is e xamp l e bot h t i me rs a r e in it ializ e d bef or e sta r tin g (b y se tt ing t h eir r e spe c t i v e ug b i ts) . bot h coun t e rs sta r t s fr om 0, b u t y o u can ea sily inser t an of f set b e t w e en t hem b y wr it ing a n y of th e co un te r re gist ers (t im x_ cnt) . y o u can see t h a t t h e ma ste r / sla v e mo de in se r t a de la y bet w e en cnt_en and ck_psc on t i mer 1. fi gu re 15 8. t r i g g e rin g ti mer 1 an d 2 wi th t i me r 1 ti 1 in put 14.3.16 deb u g mode whe n t he micro cont r o ller ent er s d e b u g mo de ( c or te x-m3 cor e - h a lt ed ), t h e ti mx cou n t e r e i th er con t in ues to w o r k nor mally or st op s , d epe ndin g on dbg_ ti mx_st o p co nf igu r at ion bit in dbgmcu module . f o r more details , ref e r to se ctio n 3 2 . 1 6 . 2 : de b u g su pp or t f o r t i me rs , w a t chdo g, bxcan and i 2 c . 00 01 ck_int timer1-cen=cnt_en timer1- cnt timer 1-ti 1 timer 1- ck_psc 02 03 04 05 06 07 08 09 ti mer1- t i f 00 01 ti mer 2 - c en= cnt_en timer2- cnt timer 2- ck_psc 02 03 04 05 06 07 08 09 timer2- t i f general-purpose timers (tim2 to tim5) RM0033 394/1317 doc id 15403 rev 3 14.4 tim2 to tim5 register s ref e r to se ct ion 1 . 1 on p age 4 6 f o r a list o f ab b r e v ia t i ons used in r e g i st er descr ipt i on s . th e pe r i phe r a l r egist er s can b e accesse d b y ha lf- w o r d s ( 16- bit ) o r w o rds (3 2- bit ) . 14.4.1 timx contr o l register 1 (timx_cr1) ad dre s s of f s e t : 0x00 re se t v a lu e: 0x 00 0 0 1 5 1 4 1 3 1 2 1 1 1 0 987 654321 0 reser v ed c k d[1 : 0] arp e cms d ir opm urs u d is c e n rw rw rw rw rw r w rw rw rw rw bits 1 5 :10 r eser v ed, alw a ys re ad as 0 bits 9:8 ckd : cloc k division thi s bi t-fiel d indi ca te s the di vision rati o betw een the timer cl oc k (ck_ int) frequ ency and sa mp lin g cl oc k u s ed b y the d i gi tal filters (etr, tix), 00 : t dt s = t ck_ i n t 01 : t dt s = 2 t ck_ i n t 10 : t dt s = 4 t ck_ i n t 11 : r e se r v ed bit 7 arpe : a u to -reloa d prelo ad ena b l e 0 : timx_arr regi ste r is not b u ff ere d 1: ti mx_ a r r re g i st er is b u ff er ed bits 6:5 cms : cen t e r -a lign ed mode sele ctio n 0 0 : ed ge-al igne d mo de . the coun te r cou n ts up o r do wn depe ndi ng on the dire ctio n bit (dir). 0 1 : ce nter-ali gned mod e 1. the coun te r cou n ts up a nd do wn a l te r n ativ ely . ou tpu t compa r e i n terr up t flag s of channels con f i gured in outp ut (ccxs=00 in timx_c cmrx register) are se t on l y w h en th e cou n t e r i s cou n t i n g do w n . 1 0 : ce nter-ali gned mod e 2. the coun te r cou n ts up a nd do wn a l te r n ativ ely . ou tpu t compa r e i n terr up t flag s of channels con f i gured in outp ut (ccxs=00 in timx_c cmrx register) are se t on l y w h en th e cou n t e r i s cou n t i n g up . 1 1 : ce nter-ali gned mod e 3. the coun te r cou n ts up a nd do wn a l te r n ativ ely . ou tpu t compa r e i n terr up t flag s of channels con f i gured in outp ut (ccxs=00 in timx_c cmrx register) are se t b o th when the cou n ter i s cou n ting up o r do w n . note: i t is not all o w e d to s w itch from edge -alig ned mod e to cen t er-a lign ed mode as lon g as the cou n te r i s en ab le d (cen=1 ) bit 4 dir : di r ec ti on 0 : cou n ter used as upcou nter 1 : cou n ter used as do wn co unter note: t his bit is re ad onl y wh en th e ti me r is c onfig ured in ce nter-alig ned mod e or en co der mode . bit 3 opm : one-p u lse mode 0 : cou n ter is n o t stopp ed at u pda te e v en t 1 : cou n ter stop s cou n ting at th e n e xt upd ate e v e n t (cle ar in g the b i t cen) RM0033 general-purpose timers (tim2 to tim5) doc id 15403 rev 3 395/1317 bit 2 urs : up date requ est sou r ce thi s bi t is set an d cleare d b y so ftw a re to se lect the uev e v ent sources . 0 : an y of the f o l l o win g e v ents g enerate an upd ate interr up t or dma req uest i f en ab le d. thes e e v en ts ca n b e : ? c ounter o v erflo w /un derflo w ? s et ting the ug bit ? u pdate ge nerati on throug h the sl a v e mode con t roll er 1 : only counter o v erflo w /un derflo w gen er a t e s an u pda te in te rr upt or d m a requ est if ena b l ed . bit 1 udis : u p da te di sa b l e thi s bi t is set an d cleare d b y so ftw a re to e nab le/disab le uev e v e n t g ene r a tion . 0 : uev ena b l ed . th e upda te (uev) e v ent i s g enerated b y one o f th e f o ll o wing e v e n ts: ? c ounter o v erflo w /un derflo w ? s et ting the ug bit ? u pdate ge nerati on throug h the sl a v e mode con t roll er bu ff e r ed regi sters are then lo aded w i th the i r p r eloa d v a lu es . 1 : uev disab l ed . th e upda te e v en t is not gene r a ted , shad o w re gisters k e ep their v a l ue (arr , psc , ccrx). ho w e v e r th e counter and the pr e sca ler are rein itiali z e d i f the ug bi t is se t or if a h a rdw a re reset is re ce iv ed from th e sl a v e mode con t ro ller . bit 0 cen : co unter ena b l e 0: co un te r d i sa b l e d 1 : cou n ter enab led note: e xter nal cloc k, gated mode a nd enco der mo de can w o r k only if the c e n b i t ha s b een pre vio usly se t b y softw a re . ho w e v e r tr ig ger mode can set th e c e n b i t au to ma ti cally b y hardw a re . cen is cl eared au to ma ti cally in on e-pul se mode , wh en an up date e v ent occurs . general-purpose timers (tim2 to tim5) RM0033 396/1317 doc id 15403 rev 3 14.4.2 timx contr o l register 2 (timx_cr2) ad dre s s of f s e t : 0x04 re se t v a lu e: 0x 00 0 0 1 5 1 4 1 3 1 2 1 1 1 0 987 654321 0 reser v ed t i 1s mms[2:0] ccds reser v e d rw rw rw r w rw bits 15 :8 re se r v e d , al w a ys read as 0. bit 7 ti 1s : ti1 sele ctio n 0: the timx_ch 1 pin is conn ecte d to ti1 i nput 1: the timx_ch1 , ch2 an d ch3 pin s are con nec ted to the ti1 in put (xor co mbina t i on)see also section 1 3.3.18: interf a c i ng with hal l se nsors on pag e 325 bits 6:4 mms : master mode s e lection th ese bits a llo w to select th e i n f o r m ation to be sen t in master mod e to sla v e ti me rs f o r synchron i zation (trgo). th e combina t i on is as f o llo w s : 000 : rese t - the ug bit from the timx_ e gr register i s used as tr i gger output (trgo). if the reset is ge nerated b y the tr i gge r i npu t (sla v e m ode controll er configu r ed i n reset mode ) the n th e signa l on trgo is de la y ed compared to the actual reset. 001 : enab le - th e coun te r en ab l e si gna l, cnt_en, is u s ed as tr i gger ou tpu t (tr g o). it is useful to star t se v e r a l timers at the same time o r to con t rol a win do w in w h ich a sl a v e timer is ena b l e d . the cou n te r ena b le sig nal is ge ner a t e d b y a l ogic or b e tw ee n cen co ntrol bit and th e tr i gge r in put when con f i gured in g a ted mode . wh en th e c ounter enab le sign al is co ntro lled b y the tr igge r in put, there is a del a y on trgo , e x ce pt i f th e ma ste r /sla v e mo de is selected (see the msm bi t de sc r i ption in timx_smcr regi ster). 010 : up da te - the upda te e v ent is se lected a s tr i gge r output (trgo). f o r instance a master ti mer ca n the n be used as a prescal e r f o r a sl a v e timer . 011 : compa r e pulse - the tr igg e r o u tput se nd a positiv e p u lse whe n the cc 1if fl ag is to be set (e v e n if it w a s a l read y high ), as soo n as a ca pt ur e o r a co mp a r e mat c h oc curr ed . ( tr g o ) 100 : compa r e - oc1ref si gna l i s u s e d as tr i gger ou tpu t (tr g o) 101 : compa r e - oc2ref si gna l i s u s e d as tr i gger ou tpu t (tr g o) 110 : compa r e - oc3ref si gna l i s u s e d as tr i gger ou tpu t (tr g o) 111 : compa r e - oc4ref si gna l i s u s e d as tr i gger ou tpu t (tr g o) bit 3 ccd s : capture / compa r e dma sele cti o n 0: c c x dma reque st sent when cc x e v en t occurs 1: c c x dma reque sts sent when u pdate e v en t occurs bits 2 : 0 r e s e r v e d, al w a ys read as 0 RM0033 general-purpose timers (tim2 to tim5) doc id 15403 rev 3 397/1317 14.4.3 timx sla ve mode contr ol register (timx_smcr) ad dre s s of f s e t : 0x08 re se t v a lu e: 0x 00 0 0 1 5 1 4 1 3 1 2 1 1 1 0 987 654321 0 et p e ce et p s [1 :0 ] e t f [ 3 : 0 ] m s m ts [2 :0] res . sms [ 2: 0] rw rw rw rw r w r w rw rw rw rw rw r w rw rw rw bit 15 etp : exte r n a l tr i gge r po lar i ty this bit selects whether etr or etr is used f o r tr igg e r o perations 0: etr is n oni n v er ted, activ e at h i gh le v e l or r i sing ed ge 1: etr is i n v e r t ed , activ e at lo w le v e l or f a l ling e dge bit 14 ece : exter nal clo c k en ab l e th is b i t e nab l e s exter nal cl oc k mod e 2. 0 : exte r n a l cl oc k mo de 2 di sa b l e d 1: exter nal clo c k mod e 2 e nab led. the co unter is cl oc k ed b y an y acti v e edg e on th e etrf sign al. 1: settin g th e ec e bi t ha s the same eff e ct a s sele cting e xte r n a l cloc k mo de 1 with trgi conn ecte d to etrf (sms=11 1 a nd ts= 111 ). 2: it i s p o ssib l e to sim u ltaneo usly use e xter nal cl oc k mode 2 with the f o llo wi ng sla v e mode s: reset mo de , ga te d mo de and tr ig ger mode . ne v e r t h e le ss , trgi m u st not b e conne cte d to etrf in th is ca se (ts bits must no t be 11 1). 3: if e xter nal clo c k mod e 1 a nd e xte r n a l cloc k mo de 2 are ena b l e d a t the same ti me , th e e xter n a l cl oc k i npu t is etrf . bi ts 13:12 etp s : exter n a l tr i gger prescal e r exte r n al tr i gge r sig nal etr p frequ ency m u st b e at most 1 / 4 o f ck_int frequ ency . a prescal e r can be enab led to redu ce etr p fre quen cy . it is u s e f u l wh en i nputting f a st e xte r n al cloc ks . 00: prescaler off 01: etrp fre que ncy d i vide d b y 2 10: etrp fre que ncy d i vide d b y 4 11: etrp fre que ncy d i vide d b y 8 bits 11: 8 etf[3:0] : ex ter n al tr igger filter th is b it-fie ld then de fi nes th e freq uency used to sample etrp si gnal a nd the len g th o f the dig i tal filter a ppl ied to etrp . t he di gital filter is ma de of a n e v e n t co unter in which n e v en ts are ne eded to v a l i date a tr an si ti on on the outpu t: 000 0: no fil t er , sampl i ng is do ne at f dt s 000 1: f sampl i n g =f ck_ i n t , n= 2 001 0: f sampl i n g =f ck_ i n t , n= 4 001 1: f sampl i n g =f ck_ i n t , n= 8 010 0: f sampl i n g =f dt s /2, n=6 010 1: f sampl i n g =f dt s /2, n=8 011 0: f sampl i n g =f dt s /4, n=6 011 1: f sampl i n g =f dt s /4, n=8 100 0: f sampl i n g =f dt s /8, n=6 100 1: f sampl i n g =f dt s /8, n=8 101 0: f sampl i n g =f dt s /16, n = 5 101 1: f sampl i n g =f dt s /16, n = 6 110 0: f sampl i n g =f dt s /16, n = 8 110 1: f sampl i n g =f dt s /32, n = 5 111 0: f sampl i n g =f dt s /32, n = 6 111 1: f sampl i n g =f dt s /32, n = 8 general-purpose timers (tim2 to tim5) RM0033 398/1317 doc id 15403 rev 3 bit 7 msm: master/sl a v e mode 0: n o acti on 1 : th e e f f e c t o f an e v en t on t h e tr i g g e r inp u t (trgi) is d e la y ed to allo w a pe rf ect synchron i zation be tw ee n the cu rre n t timer and its sla v e s (throug h trgo). it i s use f u l if w e w ant to synchro niz e se v e r a l timers on a sing le e xte r n a l e v ent. bits 6:4 ts: t r igg e r se lection th is b it-fie ld sele cts th e tr i gger in put to be use d to synchro niz e th e co unter . 000 : inter nal t r igge r 0 (itr0 ) . 001 : inter nal t r igge r 1 (itr1 ) . 010 : inter nal t r igge r 2 (itr2 ) . 011 : inter nal t r igge r 3 (itr3 ) . 100 : ti1 edg e detecto r (ti1 f_ed) 101 : filtered timer inp u t 1 (ti1 fp1) 110 : filtered timer inp u t 2 (ti2 fp2) 111 : exte r n al t r igge r in put (etrf) see t a b l e 6 0: timx inter nal tr ig ger conne ctio n on pa ge 398 f o r m o r e details on it rx mean ing f o r ea ch timer . no te : t he se bits must be cha nge d o n ly whe n the y a r e n o t u s e d (e .g. whe n sms= 000) to a v oi d wrong ed ge detection s a t th e transitio n. bit 3 r e s e r v e d, al w a ys read a s 0. bits 2:0 sms: sla v e mode sel e cti o n wh en e x ter n a l si gna ls a r e se lected the activ e ed ge of the tr igg e r si gna l (trgi) is link e d to the pol ar ity se lected on the e xte r n al inp u t (see inpu t con t rol reg i ster a nd con t rol re gister descr i p tion. 000: sla v e mo de disa b led - if c e n = ? 1 th en the prescale r is cloc k e d d irectly b y the in te r n al cloc k. 001 : encod e r mo de 1 - co unter counts up/do wn o n ti2fp2 e dge de pen ding o n ti1fp1 le v e l . 010 : encod e r mo de 2 - co unter counts up/do wn o n ti1fp1 e dge de pen ding o n ti2fp2 le v e l . 011 : encod e r mo de 3 - co unter counts up/do wn o n both ti1fp1 a nd ti2fp2 edg es dep end ing on the le v e l of the other in put. 100 : rese t mode - risin g edge o f the selected tr ig ger inpu t (tr g i) rei n itial i z e s the co unter and g ener a tes an upd ate of the regi ster s . 101: gate d mo de - the cou n ter cl oc k i s en ab l ed when the tr ig ger inpu t (trgi) i s hi gh. the coun te r stops (b ut i s n o t rese t) as so on as th e tr i gger be co mes l o w . both sta r t and stop of the counter are con t rol l ed. 110 : t r igg e r mod e - the coun te r star ts at a r i si ng e dge of th e tr i gger tr gi (b ut it is n o t reset). only th e star t of the coun te r is controll ed. 111 : exte r n al clo c k mode 1 - risin g edge s of th e selected tr igg e r (trgi) cloc k th e co unter . no te : t he gated mod e m u st not be u sed if ti1f_ed is sele cte d as th e tr igge r inpu t (ts=1 00). in deed , ti1f_ed outpu ts 1 pulse f o r ea ch tr ansition o n ti1f , wh ereas the gated mode ch ec ks the le v e l of the tr igge r si gnal. t a b l e 60 . t imx int e r n al tri g g e r conn ect i o n sla ve tim i tr 0 (ts = 000) itr1 (ts = 001 ) i tr2 (ts = 0 10) itr3 (ts = 011 ) tim2 ti m1 ti m8 t i m3 ti m4 tim3 ti m1 ti m2 t i m5 ti m4 RM0033 general-purpose timers (tim2 to tim5) doc id 15403 rev 3 399/1317 ti m4 ti m1 ti m2 t i m3 ti m8 ti m5 ti m2 ti m3 t i m4 ti m8 t a b l e 60 . t imx int e r n al tri g g e r conn ect i o n sla ve tim i tr 0 (ts = 000) itr1 (ts = 001 ) i tr2 (ts = 0 10) itr3 (ts = 011 ) general-purpose timers (tim2 to tim5) RM0033 400/1317 doc id 15403 rev 3 14.4.4 timx dma/interrupt enab le register (timx_dier) ad dre s s of f s e t : 0x0c re se t v a lu e: 0x 00 0 0 1 5 1 4 1 3 1 2 1 1 1 0 987 654321 0 res . tde res cc4de cc3de cc2de c c 1 d e ude re s . tie re s cc4 ie cc 3 i e cc2ie cc1ie uie rw rw r w r w rw rw rw r w rw rw rw rw bit 1 5 re ser v e d , al w a ys read a s 0. bit 14 tde : t r ig ger dma req uest e nab l e 0: t r i gge r dma re que st disab l ed . 1: t r i gge r dma re que st ena b l ed . bi t 13 r e se r v ed , a l w a ys re a d as 0 bit 12 cc 4 d e : c apture/compa r e 4 d m a requ est en ab le 0: cc4 dma re que st disab l ed . 1: cc4 dma re que st ena b l ed . bit 11 cc 3 d e : c apture/compa r e 3 dm a requ est en ab le 0: cc3 dma re que st disab l ed . 1: cc3 dma re que st ena b l ed . bit 10 cc 2 d e : c apture/compa r e 2 dm a requ est en ab le 0: cc2 dma re que st disab l ed . 1: cc2 dma re que st ena b l ed . bit 9 cc 1 d e : c apture/compa r e 1 dm a requ est en ab le 0: cc1 dma re que st disab l ed . 1: cc1 dma re que st ena b l ed . bit 8 ud e : upd a te dma requ est e nab l e 0: upda te dma requ est di sa b l e d . 1: upda te dma requ est en ab le d. bit 7 r e ser v e d, al w a ys read a s 0. bit 6 tie : t r i gge r in te rr upt e nab le 0: t r i gge r in te rr upt d i sab l ed. 1: t r i gge r inte rr upt e nab led. bit 5 r e ser v e d, al w a ys read a s 0. bit 4 cc 4 i e : cap t u r e / co mpare 4 interr u p t e nab l e 0: cc4 in terr u p t d i sab l ed. 1: cc4 in terr u p t e nab l ed. bit 3 cc 3 i e : cap t u r e / co mpare 3 interr u p t e nab l e 0: cc3 in terr u p t d i sab l ed 1: cc3 in terr u p t e nab l e d RM0033 general-purpose timers (tim2 to tim5) doc id 15403 rev 3 401/1317 14.4.5 timx status register (timx_sr) ad dre s s of f s e t : 0x10 re se t v a lu e: 0x 00 0 0 bit 2 cc 2 i e : cap t u r e / co mpare 2 interr u p t e nab l e 0: cc2 in terr u p t d i sab l ed 1: cc2 in terr u p t e nab l e d bit 1 cc 1 i e : cap t u r e / co mpare 1 interr u p t e nab l e 0: cc1 in terr u p t d i sab l ed 1: cc1 in terr u p t e nab l e d bit 0 uie : u pdate in terr upt e nab le 0: upda te i n terr upt disab l ed 1: upda te i n terr upt ena b l ed 1 5 1 4 1 3 1 2 1 1 1 0 987 654321 0 reser v e d cc4of cc3of cc2of c c 1 o f reser v e d ti f re s cc4if cc3if c c 2 i f cc1if uif rc_w0 r c_w0 r c _ w 0 r c _ w0 rc_w0 r c _ w 0 r c _ w 0 r c_w0 rc_w0 r c_w0 bi t 15:13 reser v ed , alw a ys re ad as 0. bi t 12 cc4 of : cap t u r e/c o mpare 4 o v e r ca pture fl ag ref e r to cc1of descr iption bi t 11 cc3 of : cap t u r e/c o mpare 3 o v e r ca pture fl ag ref e r to cc1of descr iption bi t 10 cc2 of : c a pt ure / com p a r e 2 o v e r ca pt ur e fl ag ref e r to cc1of descr iption bit 9 cc1 of : cap t u r e/c o mpare 1 o v e r ca pture fl ag th is fla g is se t b y hardw a r e o n ly when the corre sp ond ing cha nnel i s con f ig ured in i nput capture mode . it is cl eared b y softw a r e b y w r iting it to ?0 . 0: n o o v ercapture ha s be en de tected 1: the cou n ter v a lue h a s b een cap t u r e d in timx_ccr1 re gister w h ile cc 1if fl ag w a s alre ady set bits 8 : 7 r eser v e d , alw a ys re ad as 0. bit 6 ti f : t r igg e r i n terr upt fl ag th is fla g is se t b y hardw a r e o n tr i gger e v en t (activ e edg e detected on trgi inpu t whe n th e sla v e mod e controlle r is en ab le d in all mod e s b u t g a ted mode . it i s set when the cou n ter sta r ts or stop s wh en gated mod e is selected. it is cleared b y softw a r e . 0: n o tr ig ger e v ent occurred 1: t r ig ger interr up t pe ndin g bit 5 r eser v e d , alw a ys re ad as 0 bit 4 cc4 if : ca ptu r e/compare 4 in te rr upt fla g ref e r to cc1if descr iption bit 3 cc3 if : ca ptu r e/compare 3 in te rr upt fla g ref e r to cc1if descr iption bit 2 cc2if : capture/compare 2 interrupt flag refer to cc1if description general-purpose timers (tim2 to tim5) RM0033 402/1317 doc id 15403 rev 3 bit 1 cc1 if : ca ptu r e/co mpare 1 interr u p t flag i f c h an nel cc1 is con fig ured as o u tp ut: this fla g is se t b y hardw a r e w hen the coun te r matches th e compare v al ue , w i th so me e x ce ption in cen t e r -a lig ned mode (ref e r to the cms b i ts in the timx_cr1 re gister descr i p ti on). it i s cle a red b y softw a re . 0: n o ma tch 1: the con t e n t of th e co unter timx_cnt matche s the conten t of the timx_c cr1 regi ster . wh en the contents of timx_cc r 1 are g r e a ter t han th e conten ts o f ti mx_ a rr, th e cc1 if bi t goes hig h on th e cou n te r o v erflo w (i n up co unting and up/do w n -coun ting mod e s) or un derflo w (in do wn countin g mo de) i f c h an nel cc1 is conf ig ured as in pu t: th is b i t i s set b y h a rdw a re on a cap t u r e . it is cl eared b y softw are or b y re adin g th e timx_ccr1 re gister . 0: n o inpu t capture occurre d 1: the counter v a lu e h a s be en captured in timx_ccr1 reg i ste r (an e dge has bee n d e tecte d on ic1 which matches the sele cted p o lar i ty) bit 0 uif : upda te i n te rr upt fl ag this bi t is set b y ha rd w a re on an up date e v ent. it is clea red b y softw a re . 0 : no up date occurred . 1 : upd a te interr up t pe ndin g . this bit is se t b y hardw a r e w hen the regi ste r s are up dated: at o v erflo w or unde rflo w (f o r tim2 to tim5 ) a nd if u d is=0 in the timx_cr1 reg i ste r . when cn t is re ini t ia liz ed b y softw a re u sing the ug b i t in timx_egr register , if u r s=0 a nd udis=0 in the timx_c r1 re gister . wh en cnt is rein itiali z e d b y a tr ig ger e v en t (ref e r to th e synchro con t ro l regi ster d e scr iption ), if u r s=0 an d u d is= 0 in the timx_cr1 reg i ste r . RM0033 general-purpose timers (tim2 to tim5) doc id 15403 rev 3 403/1317 14.4.6 timx e vent g enerat ion register (timx_egr) ad dre s s of f s e t : 0x14 re se t v a lu e: 0x 00 0 0 1 5 1 4 1 3 1 2 1 1 1 0 987 654321 0 re s e r v ed tg res . cc4g cc3g cc2g cc1g u g w wwwww bi ts 15 :7 re se r v e d , al w a ys re ad as 0. bit 6 tg : t r i gge r ge neration t h is bit is se t b y soft w a re in o r d e r to ge nerate an e v ent, it is automaticall y cle a red b y hardw a re . 0: no action 1: the tif fl ag is set in timx_sr reg i ste r . r e lated in te rr upt or d m a tr ansf e r ca n o ccur i f en ab l ed. bi t 5 r e se r v e d , al w a ys re ad as 0. bit 4 cc 4 g : cap t ure / comp are 4 gene r a tio n ref e r to cc1g descr ipt i on bit 3 cc 3 g : cap t ure / comp are 3 gene r a tio n ref e r to cc1g descr ipt i on bit 2 cc 2 g : cap t ure / comp are 2 gene r a tio n ref e r to cc1g descr ipt i on bit 1 cc 1 g : cap t ure / comp are 1 gene r a tio n t h is bit is se t b y soft w a re in o r d e r to ge nerate an e v ent, it is automaticall y cle a red b y hardw a re . 0: no action 1: a cap t u r e/co mp are e v ent is g ene r a ted on cha nne l 1: i f ch ann e l cc1 is c o n f ig ur ed as o u tp ut: cc1 if fla g is se t, correspo nding interr up t or dma req uest i s sen t if enab led. if c h an nel cc1 i s co nfi g u r ed as in pu t: the current v a lu e of the coun te r is capture d in timx_ccr1 reg i ste r . the cc1 if fla g is se t, the correspo ndi ng interr up t or dma re quest is se nt if ena b l ed . th e cc1of flag is set i f the cc1 if flag w a s a l read y hi gh. bit 0 ug : u pdate ge ner a t i o n this bit c a n be set b y softw are , it i s au to ma tica l l y cl ea re d b y h a r dw are . 0: no action 1: r e -ini tia liz e the cou n te r an d ge nerates an up date of th e re gisters . no te that the presca ler cou n ter i s cle a red too (an yw a y the presca ler r a ti o is not aff e cted). the cou n ter i s cle a red if the center-al i gn ed mode is sele cted o r if dir = 0 (upco unting ) , else it ta k e s the a u to-reloa d v a lue (timx_arr) if dir=1 (do w nco unting ) . general-purpose timers (tim2 to tim5) RM0033 404/1317 doc id 15403 rev 3 14.4.7 timx capture/compare m ode register 1 (timx_ccmr1) ad dre s s of f s e t : 0x18 re se t v a lu e: 0x 00 0 0 th e chan ne ls can be used in in put (cap tu re m ode ) or in out p u t ( c omp a re m ode ). the dir e c t io n of a ch an n e l is d e f i ne d b y co nfig u r ing th e co rr es po n d in g ccx s b i ts . all th e ot he r b i ts of t h is r egist er h a v e a d i ff e r en t f u n c t i on in inpu t a nd in ou t put mod e . f o r a giv e n bit , o c xx d e scr ibes it s f unct i on whe n t he chan ne l is co nf igu r e d in out p u t , i c xx descr ibe s it s f u n c t i on wh en t h e cha nne l is conf ig ure d in inp u t . so y o u m u st t a k e car e t hat th e same b i t can h a v e a dif f e r e n t m ean ing f o r t h e inpu t st age a n d f o r t h e out pu t st age . output compare mode 1 5 1 4 1 3 1 2 1 1 1 0 987 654321 0 oc2ce o c 2 m[2: 0] o c 2pe o c 2 fe cc2s[ 1: 0] oc 1c e o c 1 m [ 2 : 0] o c 1 p e o c 1 f e cc1s [ 1: 0] ic2 f [ 3 :0 ] i c2 ps c[1 : 0] ic1 f [ 3 : 0 ] i c 1 p s c [1 :0 ] rw rw rw rw r w r w rw rw rw rw rw r w rw rw rw rw bit 15 oc2ce: ou tpu t compa r e 2 cle a r enab le bi ts 14:12 oc2m[2:0] : output compare 2 mode bit 11 oc2pe : output co mpare 2 prel oad en ab le bit 10 oc2fe : ou tp ut compa r e 2 f ast en ab le bits 9:8 cc2 s[1:0] : ca pture/compare 2 sel e cti o n th is b it-fie ld defin es the d irection of th e ch ann el (inpu t/ou tp ut) as w e ll as th e used in put. 00: cc2 chan nel is config ured as outpu t 01: cc2 chan nel is config ured as inp u t, ic2 is ma pped o n ti2 10: cc2 chan nel is config ured as inp u t, ic2 is ma pped o n ti1 11: cc2 chan nel is config ured as inp u t, ic2 is ma pped o n trc . this mode is w o r king o n ly if a n inter nal tr ig ger inpu t is sele cted throu gh the ts bit (timx_ smc r re gister) no te : cc2s bits a r e wr itab l e only whe n the ch anne l is off (cc2e = 0 in timx_ccer). bit 7 oc1ce: ou tpu t compa r e 1 cle a r enab le oc 1ce: output compare 1 cle ar en ab l e 0: oc1r ef is no t aff e cted b y th e etrf i nput 1: oc1r ef is clea red as soon as a high l e v e l is detected on etr f inp u t RM0033 general-purpose timers (tim2 to tim5) doc id 15403 rev 3 405/1317 bits 6:4 oc1m : output co mp are 1 mode th ese bi ts de fi ne the b eha vi or of th e outpu t ref e rence si gnal oc1 ref from which oc1 and oc 1n are der i v ed. oc1 r ef is activ e hig h where a s oc1 an d oc1n a c tiv e l e v e l dep end s on cc1 p a nd cc1np bi ts . 000 : f r oz en - the compa r ison be tw ee n the o u tput co mp are regi ster timx_ccr1 a nd the coun te r timx_cn t has no eff e ct on th e outputs . (this mode i s use d to ge nerate a timin g base ) . 001 : set chan nel 1 to activ e le v e l on match . oc1 ref signa l i s f o rced hig h w hen th e co unter timx_cnt ma tches the cap t ure / compare register 1 (timx_ ccr1). 010: set ch ann el 1 to in activ e le v e l o n ma tch. oc1 ref sign al is f o rced lo w wh en the coun te r timx_cn t ma tch e s the cap t u r e/co mp are regi ster 1 (timx_ccr1 ). 011: t oggl e - oc1ref togg les whe n timx_ cnt=timx_ccr 1. 100 : f o rce in acti v e le v e l - oc1 r ef is f o rced lo w . 101: f o rce activ e le v e l - oc1ref i s f o rced high. 110 : pwm mode 1 - in up countin g, cha nne l 1 i s activ e a s lo ng as timx_cnt general-purpose timers (tim2 to tim5) RM0033 406/1317 doc id 15403 rev 3 input capture mode bi ts 15 :12 ic2f : inpu t capt ure 2 filter bi ts 11 :10 ic2psc[1:0] : in put ca pture 2 prescal e r bits 9: 8 cc 2s : cap t u r e/co mp are 2 selectio n th is bit-fi eld de fin e s th e d i rection of th e c hann el (inp ut/ou t p u t) as w e ll as th e used in put. 00 : cc2 cha nnel i s con f ig ured as ou tpu t . 01 : cc2 cha nnel i s con f ig ured as inp u t, ic2 is ma pped o n ti2. 10 : cc2 cha nnel i s con f ig ured as inp u t, ic2 is ma pped o n ti1. 11 : cc2 ch ann el is config ured a s i nput, ic2 is ma pped on trc . th is mode i s w o r k i ng on ly if an in te r n al tr igge r in put is se lect ed th roug h ts bit (timx_smcr regi ste r ) no te : cc2s bits are wr itab l e only whe n th e ch ann el is off (cc2e = 0 in timx_ccer ) . bits 7: 4 ic1f : inpu t capt ure 1 filter th is bit-field defin es th e freque ncy used to sa mp le ti1 inp u t and the len g th of th e di gital filter ap plie d to ti1 . th e digi ta l fil t e r is made of an e v en t coun ter in wh ich n e v e n ts a r e n eede d to v a l i date a tr an si ti on on the ou tpu t : 00 00: n o fil t e r , sampl i ng is do ne at f dt s 1 000: f sampl i n g =f dts /8, n=6 00 01: f sampl ing =f ck_ i nt , n = 2 1 001: f sampl i n g =f dts /8, n=8 00 10: f sampl ing =f ck_ i nt , n = 4 1 010: f sampl i n g =f dts /16, n=5 00 11: f sampl ing =f ck_ i nt , n = 8 1 011: f sampl i n g =f dts /16, n=6 01 00: f sampl ing =f dt s /2 , n= 6 1 100: f sampl i n g =f dts /16, n=8 01 01: f sampl ing =f dt s /2 , n= 8 1 101: f sampl i n g =f dts /32, n=5 01 10: f sampl ing =f dt s /4 , n= 6 1 110: f sampl i n g =f dts /32, n=6 01 11: f sampl ing =f dt s /4 , n= 8 1 111: f sampl i n g =f dts /32, n=8 note: i n current silicon re vision, f dts is repla c ed in the f o r m u la b y ck_int wh en ic xf[3:0]= 1, 2 or 3 . bits 3: 2 ic1psc : inp u t ca ptu r e 1 prescale r th is bit-fi eld de fin e s th e ratio of the p r escaler acting o n cc1 inpu t (ic1). th e prescale r i s reset as so on as cc1e= 0 (timx_ ccer register). 00 : no presca ler , capture is don e each time an edg e is d e tecte d on the capture in put 01 : capture is don e once e v er y 2 e v en ts 10 : capture is don e once e v er y 4 e v en ts 11 : capture is don e once e v er y 8 e v en ts bits 1: 0 cc 1s : cap t u r e/co mpare 1 sele ctio n th is bit-fi eld de fin e s th e d i rection of th e c hann el (inp ut/ou t p u t) as w e ll as th e used in put. 00 : cc1 cha nnel i s con f ig ured as ou tpu t 01 : cc1 cha nnel i s con f ig ured as inp u t, ic1 is ma pped o n ti1 10 : cc1 cha nnel i s con f ig ured as inp u t, ic1 is ma pped o n ti2 11 : cc1 ch ann el is config ured a s i nput, ic1 is ma pped on trc . th is mode i s w o r ki ng on ly if an in te r n al tr igge r in put is se lect ed th roug h ts bit (timx_smcr regi ste r ) no te : cc1s bits are wr itab l e only whe n th e ch ann el is off (cc1e = 0 in timx_ccer ) . RM0033 general-purpose timers (tim2 to tim5) doc id 15403 rev 3 407/1317 14.4.8 timx capture/compare m ode register 2 (timx_ccmr2) ad dre s s of f s e t : 0x1c re se t v a lu e: 0x 00 0 0 ref e r to the abo v e ccmr1 re giste r de scr i p t io n. output com p are mod e 1 5 1 4 1 3 1 2 1 1 1 0 987 654321 0 oc4ce o c 4 m[2: 0] o c 4pe o c 4 fe cc4s[ 1: 0] oc 3c e o c 3 m [ 2 : 0] o c 3 p e o c 3 f e cc3s [ 1: 0] ic4 f [ 3 :0 ] i c4 ps c[1 : 0] ic3 f [ 3 : 0 ] i c 3 p s c [1 :0 ] rw rw rw rw r w r w rw rw rw rw rw r w rw rw rw rw bit 15 oc4 c e: output compare 4 clea r e nab l e bits 14:12 oc4 m : ou tp ut compa r e 4 mo de bit 11 oc4 p e : ou tp ut compa r e 4 preloa d ena b l e bit 10 oc4 f e : output compare 4 f a s t enab l e bits 9:8 cc4s : capture/comp are 4 se lection thi s bi t-fiel d define s the di re cti on of the cha nne l (i nput/output) as w e l l as the u s e d input. 00: c c 4 chann el is configu r e d as output 01: c c 4 chann el is configu r e d as input, ic4 i s mapp ed on ti4 10: c c 4 chann el is configu r e d as input, ic4 i s mapp ed on ti3 11: cc4 chan nel i s co nfigure d as inp u t, ic4 is mappe d on trc . this mode i s w o r ki ng on ly if an inter nal tr ig ger inp u t is sele cted thro ugh ts bi t (timx_smcr re gister) note: c c 4 s b i ts are wr ita b le on ly when t he cha nnel is off (cc 4 e = 0 i n timx_ ccer). bi t 7 oc3 c e: output compare 3 clea r e nab l e bits 6:4 oc3 m : ou tp ut compa r e 3 mo de bi t 3 oc3 p e : ou tp ut compa r e 3 preloa d ena b l e bi t 2 oc3 f e : output compare 3 f a s t enab l e bits 1:0 cc3s : capture/comp are 3 se lection thi s bi t-fiel d define s the di re cti on of the cha nne l (i nput/output) as w e l l as the u s e d input. 00: c c 3 chann el is configu r e d as output 01: c c 3 chann el is configu r e d as input, ic3 i s mapp ed on ti3 10: c c 3 chann el is configu r e d as input, ic3 i s mapp ed on ti4 11: cc3 chan nel i s co nfigure d as inp u t, ic3 is mappe d on trc . this mode i s w o r ki ng on ly if an inter nal tr ig ger inp u t is sele cted thro ugh ts bi t (timx_smcr re gister) note: c c 3 s b i ts are wr ita b le on ly when t he cha nnel is off (cc 3 e = 0 i n timx_ ccer). general-purpose timers (tim2 to tim5) RM0033 408/1317 doc id 15403 rev 3 inpu t capture mode 14.4.9 timx capture/compare enable register (timx_ccer) ad dre s s of f s e t : 0x20 re se t v a lu e: 0x 00 0 0 bi ts 15:12 ic4f : inpu t capture 4 filter bi ts 11:10 ic4psc : i n pu t ca pt ure 4 pre sca l e r bits 9:8 cc4s : cap t u r e / c o mpare 4 sele ctio n th is bit-fie ld de fin e s the d irection of th e ch ann el (inpu t/ou tp ut) as w e ll as th e used in put. 00: cc4 chan nel is conf ig ured as outpu t 01: cc4 chan nel is conf ig ured as inp u t, ic4 is ma pped o n ti4 10: cc4 chan nel is conf ig ured as inp u t, ic4 is ma pped o n ti3 11: cc 4 chan nel is configu r ed a s inpu t, ic4 i s ma pped on trc . thi s mo de i s w o r king o n ly i f an in te r n al tr i gge r in put is sele cted th rough ts b i t (timx_smcr regi ste r ) no te : cc4s bits are wr itab l e only whe n th e ch anne l is off (cc4e = 0 in timx_ccer). bits 7:4 ic3f : inpu t capt ure 3 filter bits 3:2 ic3psc : i n pu t ca pt ure 3 pre sca l e r bits 1:0 cc3s : cap t u r e / c o mpare 3 sele ctio n th is bit-fie ld de fin e s the d irection of th e ch ann el (inpu t/ou tp ut) as w e ll as th e used in put. 00: cc3 chan nel is conf ig ured as outpu t 01: cc3 chan nel is conf ig ured as inp u t, ic3 is ma pped o n ti3 10: cc3 chan nel is conf ig ured as inp u t, ic3 is ma pped o n ti4 11: cc 3 chan nel is configu r ed a s inpu t, ic3 i s ma pped on trc . thi s mo de i s w o r king o n ly i f an in te r n al tr i gge r in put is sele cted th rough ts b i t (timx_smcr regi ste r ) no te : cc3s bits are wr itab l e only whe n th e ch anne l is off (cc3e = 0 in timx_ccer). 1 5 1 4 1 3 1 2 1 1 1 0 987 654321 0 cc 4 np res . cc4p cc4e cc3np res . c c 3 p cc 3 e cc2np re s . cc2p cc2e c c1 n p res . cc1p cc1e rw rw rw r w rw rw rw rw r w rw rw rw bit 15 cc 4np : c a p t u r e / c o mp ar e 4 ou t p u t p o l a r i ty . ref e r to cc1 np d e scr iptio n bi t 14 r e se r v ed , al w a y s re a d as 0. bit 13 cc 4p : ca ptu r e/compare 4 ou tp ut p o lar i ty . ref e r to cc1p descr iption bit 12 cc 4e : ca ptu r e/compare 4 ou tp ut en ab l e . ref e r to cc1e descr iption bit 13 cc 3np : c a p t u r e / c o mp ar e 3 ou t p u t p o l a r i ty . ref e r to cc1np de scr i ption bi t 12 r e se r v ed , al w a y s re a d as 0. bits 11 :1 0 r e s er v e d, a l w a ys read a s 0 . bit 9 cc 3p : capture/compare 3 output polarity. refer to cc1p description RM0033 general-purpose timers (tim2 to tim5) d o c id 154 03 re v 3 409 /13 1 7 bit 8 cc 3e : ca ptu r e/compare 3 ou tp ut en ab l e . ref e r to cc1e descr iption bit 7 cc 2np : c a p t u r e / c o mp ar e 2 ou t p u t p o l a r i ty . ref e r to cc1np de scr i ption bit 6 r ese r v e d , al w a y s re a d as 0. bit 5 cc 2p : ca ptu r e/compare 2 ou tp ut p o lar i ty . ref e r to cc1p descr iption bit 4 cc 2e : ca ptu r e/compare 2 ou tp ut en ab l e . ref e r to cc1e descr iption bit 3 cc 1np : c a p t u r e / c o mp ar e 1 ou t p u t p o l a r i ty . cc1 c h annel configur ed as output: cc1 np must be k e pt cle a red in this case . cc1 c h annel configur ed as input: this bit i s u s e d in conj unction wi th cc1 p to defin e ti1fp1 /ti2fp1 p o lar i ty . re f e r to cc 1p de scr i ption . bit 2 r ese r v e d , al w a y s re a d as 0. bit 1 cc 1p : ca ptu r e/compare 1 ou tp ut p o lar i ty . cc1 c h annel configur ed as output: 0 : o c 1 ac ti v e hi g h 1 : o c 1 ac ti v e lo w cc1 c h annel configur ed as input: c c 1 n p / c c1 p bi ts se le ct ti 1f p1 a n d ti2 f p1 po l a r i t y f o r tr i g ge r or ca pt ur e op e r a t i o n s . 00 : non in v e r t e d/r ising e dge circu it is sensitiv e to tixfp1 r i sing e dge (captur e , tr i gger in reset, e xter nal clo c k or tr igge r mode ), tixfp1 i s no t in v e r t e d (tr i gger in ga te d mo de , e n code r mode ). 01 : in v e r t e d /f alli ng ed ge circu it is sensitiv e to tixfp1 f a lli ng edg e (ca p ture , tr igg e r in reset, e xte r n al cloc k or tr i gger mode ), tixfp1 i s in v e r t ed (tr i gge r in g a ted mode , e n code r mod e ). 10 : reser v ed, do not use th is co nfigu r ation . 11 : non in v e r t e d/b oth edge s circu it is sensitiv e to bo th tixfp1 r i sing a nd f a l ling e dges (capture , tr i gger in reset, e xter nal cloc k or tr igge r mod e ), tixfp1 i s no t in v e r t ed (tr i gge r in g a te d mo de). thi s con f ig ur a t i on m u st not be used f o r e n code r mode . bit 0 cc 1e : ca ptu r e/compare 1 ou tp ut en ab l e . cc1 c h annel configur ed as output: 0: of f - oc1 is no t act i v e 1: on - oc1 sig nal is ou tpu t on the corresp ondi ng outpu t pin cc1 c h annel configur ed as input: this bit d e ter m i nes if a cap t u r e o f the coun te r v a lue can actua lly be don e into th e inpu t cap t ure / comp are re gister 1 (timx_ ccr1) or not. 0: capture di sab l e d 1: capture en ab le d t a b l e 61 . o utp u t co ntr o l bi t f o r st anda r d o c x c h ann e l s ccxe b i t o cx ou tp ut state 0 o utput d i sab l ed (ocx= 0 , ocx_en= 0 ) 1 o cx=ocxref + p o lar ity , ocx_en =1 general-purpose timers (tim2 to tim5) RM0033 410/1317 doc id 15403 rev 3 no te : t he st at e of th e e x ter n al io pin s co nn ec te d to th e sta n d a r d o c x ch an ne ls de pe n d s o n the o c x ch an nel sta t e and t h e gpi o re giste r s . 14.4.10 timx counter (timx_cnt) addre s s of f s e t : 0x24 reset v a lue : 0 x 0 00000 00 14.4.11 timx prescaler (timx_psc) ad dre ss of f s e t : 0x28 re se t v a lu e: 0x 00 0 0 14.4.12 timx auto-rel oad register (timx_arr) ad dre ss of f s e t : 0x2c reset v a lue : 0 x 0 00000 00 31 30 2 9 2 8 27 26 25 24 23 2 2 21 20 19 18 17 1 6 cnt [ 3 1 : 16 ] (de pend ing on ti mers) rw rw rw rw r w r w rw rw rw rw rw r w rw rw rw rw 1 5 1 4 1 3 1 2 1 1 1 0 987 654321 0 cnt [15 : 0] rw rw rw rw r w r w rw rw rw rw rw r w rw rw rw rw bits 31:16 cnt[3 1:16] : high counter v a lue (on tim 2 and tim5). bits 15:0 cnt[1 5:0] : l o w co unter v a lu e 1 5 1 4 131 2 1 1 1 0 987 654321 0 psc[ 15: 0] rw rw rw rw r w r w rw rw rw rw rw r w rw rw rw rw bits 15: 0 psc [1 5: 0] : prescale r v a lue the coun te r clo c k freque ncy c k _ cnt is eq ual to f ck_ psc / (psc[15: 0] + 1). psc contain s the v a lue to be loa ded in the ac tiv e p r escaler regi ster at each up date e v ent. 31 30 2 9 2 8 27 26 25 24 23 2 2 21 20 19 18 17 1 6 arr[ 31: 16] (dep endin g o n time rs) rw rw rw rw r w r w rw rw rw rw rw r w rw rw rw rw 1 5 1 4 1 3 1 2 1 1 1 0 987 654321 0 arr[ 15: 0] rw rw rw rw r w rw rw rw rw rw rw rw rw rw rw rw bi ts 31:16 arr [3 1:16 ] : high a u to-reloa d v a lu e (o n tim2 and tim5 ). bits 15: 0 arr [1 5:0] : lo w a u to-reload v a lue arr is th e v a lu e to be l oade d in the actual au to -re load re gister . re f e r to the section 1 4 . 3 . 1 : ti me -base un it on p age 35 9 f o r mo re detail s ab out ar r u pda te an d beha vior . the coun te r is b l o c k ed whil e th e a u to-relo ad v a lu e is n u ll. RM0033 general-purpose timers (tim2 to tim5) doc id 15403 rev 3 411/1317 14.4.13 timx capture/compar e register 1 (timx_ccr1) ad dre s s of f s e t : 0x34 reset v a lue : 0 x 0 00000 00 14.4.14 timx capture/compar e register 2 (timx_ccr2) ad dre ss of f s e t : 0x38 reset v a lue : 0 x 0 00000 00 31 30 2 9 2 8 27 26 25 24 23 2 2 21 20 19 18 17 1 6 c c r 1 [ 3 1: 16 ] ( d ep e ndi n g o n ti m e r s) rw rw rw rw r w r w rw rw rw rw rw r w rw rw rw rw 1 5 1 4 1 3 1 2 1 1 1 0 987 654321 0 cc r1 [15 : 0 ] rw rw rw rw r w r w rw rw rw rw rw r w rw rw rw rw bits 31:16 ccr1[3 1:16] : h i gh cap t u r e/compare 1 v a lue (on tim2 an d tim5). bits 15:0 ccr1[1 5:0] : lo w ca pture/compa r e 1 v a lue i f c h ann e l cc1 is con f ig ured as o u tp ut : ccr1 is th e v a lu e to be l oade d in the actual cap t ure / compa r e 1 re gister (p reloa d v a lu e). it is l oade d per mane ntl y if th e prelo ad f e a t u r e i s no t sele cte d i n th e timx_ ccmr1 regi ster (bit oc1 p e). el se th e p r eloa d v a lu e is co pied i n the a c tiv e ca pture/compare 1 regi ste r wh en an upda te e v e n t occu rs . the a c tiv e ca pture/compare reg i ste r con t a i ns th e v a lue to be compa r ed to the cou n ter timx_ cnt an d signa led on oc1 ou tp ut. if chan ne l cc1 is co n f i g ure d as i n p u t : ccr1 is th e counter v a l ue transf e rre d b y the l a st in put ca pture 1 e v ent (ic1). 31 30 2 9 2 8 27 26 25 24 23 2 2 21 20 19 18 17 1 6 cc r2 [31 : 1 6 ] (de pend ing on t i mers) rw rw rw rw r w r w rw rw rw rw rw r w rw rw rw rw 1 5 1 4 1 3 1 2 1 1 1 0 987 654321 0 cc r2 [15 : 0 ] rw rw rw rw r w r w rw rw rw rw rw r w rw rw rw rw bit s 31 :1 6 c cr2[31 : 16] : hi gh cap t u r e / c o mpare 2 v a l ue (on tim2 and tim5 ). bits 15:0 c cr2[15 : 0] : lo w ca pture/compare 2 v a lue if c h ann e l cc2 is co nfi g u r ed as ou tpu t : cc r2 is the v a lue to be lo aded i n the a c tua l capture/compare 2 reg i ste r (pre load v a lue ) . it is loa ded p e r m a nently if the p r e l oa d f eatur e is not se lected in the timx_cc m r2 re gister (bi t oc2pe). else the prel oad v a lu e is co pie d in th e activ e capture/compa r e 2 re gister wh en a n u pda te e v en t occurs . the activ e cap t u r e / co mp are register contain s the v a lue to be compare d to the coun te r timx_c nt and sig nal led on oc2 outpu t. if c h ann e l cc2 is co nfi g u r ed as in put : c c r 2 i s th e co un te r v a l u e tr an sf e rre d b y th e l a s t i n pu t ca pt ur e 2 e v en t (ic 2 ). general-purpose timers (tim2 to tim5) RM0033 412/1317 doc id 15403 rev 3 14.4.15 timx capture/compar e register 3 (timx_ccr3) (onl y a v ailab l e on tim2 and tim5) ad dre s s of f s e t : 0x3c reset v a lue : 0 x 0 00000 00 14.4.16 timx capture/compar e register 4 (timx_ccr4) (onl y a v ailab l e on tim2 and tim5) ad dre ss of f s e t : 0x40 reset v a lue : 0 x 0 00000 00 31 30 2 9 2 8 27 26 25 24 23 2 2 21 20 19 18 17 1 6 cc r3 [31 : 1 6 ] (de pend ing on t i mers) rw rw rw rw r w r w rw rw rw rw rw r w rw rw rw rw 1 5 1 4 1 3 1 2 1 1 1 0 987 654321 0 cc r3 [15 : 0 ] rw rw rw rw r w r w rw rw rw rw rw r w rw rw rw rw bit s 31 :1 6 c cr3[31 : 16] : hi gh cap t u r e / c o mpare 3 v a l ue (on tim2 and tim5 ). bits 15:0 c cr3[15 : 0] : lo w ca ptu r e/compare v a lue i f ch ann e l cc3 is c o n f ig ur ed as o u tp ut: ccr 3 is the v a lue to be loa ded i n the a c tua l ca pture/compare 3 reg i ste r (pre load v a lue ) . it is loa ded p e r m an ently if the pre l oad f eatur e is not se lected in the timx_cc m r3 re gister (bi t oc3pe). el se th e prel oad v a lue is copie d in the a c ti v e capture / compa r e 3 regi ste r w hen an u pda te e v en t occurs . the activ e cap t ure / comp are register contain s the v a lue to be compared to the coun te r timx_cn t and sig nal led on oc3 outpu t. if c h an nel cc3is con f ig ured as i n p u t: c c r 3 i s th e co un te r v a l u e tr an sf e rre d b y th e l a st i n pu t ca pt u r e 3 e v e n t (ic 3 ). 31 30 2 9 2 8 27 26 25 24 23 2 2 21 20 19 18 17 1 6 cc r4 [31 : 1 6 ] (de pend ing on t i mers) rw rw rw rw r w r w rw rw rw rw rw r w rw rw rw rw 1 5 1 4 1 3 1 2 1 1 1 0 987 654321 0 cc r4 [15 : 0 ] rw rw rw rw r w r w rw rw rw rw rw r w rw rw rw rw bit s 3 1 :1 6 ccr4[31 : 16] : h i gh cap t u r e/c o mpare 4 v a l ue (on tim2 and tim5 ). bits 15:0 ccr4[15 : 0] : lo w ca pture/compare v a lue 1/ if cc4 chan nel is config ured as outpu t (cc4s bits): ccr4 is th e v a lu e to be l oade d in th e actu al capture / compa r e 4 re gister (p reloa d v a lu e). it i s l oade d per manen tl y if th e pr elo ad f eature is no t sele cted i n the timx_ ccmr4 register (bit oc4 p e). el se the p r eloa d v a lu e i s cop i ed in the a c tiv e ca pture/compare 4 regi ster whe n an upda te e v en t occurs . the a c tiv e ca pture/compare regi ste r con t ai ns the v a lue to be compa r ed to the cou n ter t i m x _c n t a n d si g n a l l e d on o c 4 ou t p u t . 2/ if cc4 chan nel is config ured as inp u t (cc4 s bi ts in timx_cc m r4 re gister): ccr4 is the counter value transferred by the last input capture 4 event (ic4). RM0033 general-purpose timers (tim2 to tim5) doc id 15403 rev 3 413/1317 14.4.17 timx dma cont r o l register (timx_dcr) ad dre s s of f s e t : 0x48 re se t v a lu e: 0x 00 0 0 14.4.18 timx dma ad dress f o r full transf er (timx_dmar) ad dre ss of f s e t : 0x4c re se t v a lu e: 0x 00 0 0 exam ple of h o w to us e the dma b u r s t f eatu r e i n t h is e xamp l e th e ti mer dma b u r s t f e at ur e is u s e d to u p d a t e th e cont en ts of th e ccrx r e g i st er s ( x = 2, 3 , 4) wit h t h e dma t r an sf er r i ng h a lf w o r d s int o th e ccrx r e g i st e r s . 1 5 1 4 1 3 1 2 1 1 1 0 987 654321 0 reser v e d dbl[ 4: 0] reser v ed d b a [ 4: 0] rw r w r w rw rw r w rw rw rw rw bits 1 5 :13 r eser v ed, alw a ys rea d as 0 bits 12:8 dbl[4 :0 ] : dma b u rst le ngt h thi s 5-b i t v e ctor de fin e s th e n u mb er o f dma tr a n sf ers (th e time r recog n iz es a b u rst tr a n sf er when a rea d or a wr ite a ccess is do ne to the timx_d mar ad dress). 0000 0: 1 tr a n sf er , 0000 1: 2 tr a n sf ers , 0001 0: 3 tr a n sf ers , .. . 1000 1: 1 8 transf e rs . bi ts 7:5 r eser v ed, alw a ys rea d as 0 bi ts 4: 0 db a [ 4 : 0] : dma base ad dress this 5-bi t v e ctor define s the ba se-add ress f o r dma transf e rs (whe n read/wr i t e acce ss are d one throu gh th e timx_ d mar a ddress). d b a is defin ed as an offse t sta r tin g from the a ddress of the timx_c r1 re gister . exampl e: 0 0000 : timx_cr1 , 0 0001 : timx_cr2 , 0 0010 : timx_smcr, ... example : l e t us consid er th e f o l l o win g transf e r : dbl = 7 tr a n sf ers & dba = timx_cr 1 . in this ca se th e tr a n sf er is don e to/from 7 reg i sters star ting from the timx_cr 1 addre s s . . 151 4 1 3 1 2 1 1 1 0 987 654321 0 dma b [1 5: 0] rw rw rw rw r w r w rw rw rw rw rw r w rw rw rw rw bits 15:0 d m a b [15:0] : dm a register f o r b u r s t accesses a read o r wr ite o peration to the d m ar reg iste r accesse s the regi ste r lo ca te d at the ad dress ( t im x_cr1 address) + (dba + dma inde x) x 4 w here timx_cr1 a ddress is th e addre s s of the co ntro l re gister 1, dba is th e dma ba se a ddress config ured in timx_dc r re gister , dma in de x i s au to ma ti ca lly controll ed b y th e d m a tr a n sf er , an d r a n ges from 0 to d b l (dbl con f i gured i n timx_ dcr). general-purpose timers (tim2 to tim5) RM0033 414/1317 doc id 15403 rev 3 this is done in the f o llo wing steps: 1 . conf igu r e t h e co rr espo ndin g dma cha n n e l as f o llo ws: ? d m a cha nne l p e r i p her al add re ss is t h e dmar re giste r ad dr ess ? d m a cha nne l m e mo r y add re ss is t h e a ddr ess o f t h e b u f f er in th e ram con t a i nin g t h e d a t a to b e tr an sf er re d b y dm a in to ccr x r e g i st er s . ? n u m be r of dat a t o t r an sf er = 3 ( s e e no te b elo w). ? circular mode disab l ed. 2 . conf igu r e t h e dcr r e g i st e r b y conf igu r ing t h e dba and dbl b i t f i elds as f o llo ws: dbl = 3 t r an sf er s , dba = 0 x e. 3 . ena b le t h e t i m x up da te dma re qu est ( s e t t he ude b i t in t he di er re gist er ). 4. en ab le ti m x 5. en ab le th e dm a ch an n e l note: t his e xample is f o r the ca s e where e v er y ccrx register to be updated once . if e v er y ccr x r e g i st er is t o be upd at ed t wice f o r e x a m ple , th e n u m ber of dat a t o t r an sf e r shou ld be 6. let 's t a k e t h e e xamp l e of a b u ff er in th e ram co nt ainin g da ta 1, d a t a 2 , da ta 3, dat a4 , d a t a5 an d da ta 6 . th e da ta is tr an sf er re d to th e ccr x r e g i ste r s a s f o llo w s: on th e fir st up da te d m a re qu e st, d a ta 1 is tr an sf er re d to ccr 2, d a t a 2 is tr an sf er re d to cc r3, d a t a 3 is tr an sf er re d to ccr4 a n d o n th e second upd at e dma r e q uest , d a t a4 is tr a n sf err e d t o ccr2 , d a t a5 is tr an sf er re d to cc r3 an d d a t a 6 is tr an sf er re d to cc r4. RM0033 general-purpose timers (tim2 to tim5) doc id 15403 rev 3 415/1317 14.4.19 tim2 option register (tim2_or) ad dre s s of f s e t : 0x50 re se t v a lu e: 0x 00 0 0 15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 1 0 reser v ed i t r1_rmp reser v ed rw r w bits 15 :1 2 r e s er v e d bits 11 :1 0 itr 1_rmp: inter n a l tr i gger 1 remap set and clea red b y softw a re . 00 : tim8_trgout 01 : ptp tr igge r o u tput i s con nected to tim2 _itr1 10 : o t g fs sof is conne cte d to the tim2_itr1 inpu t 11: otg hs sof is connected to the tim2_itr1 input bits 9:0 reserved general-purpose timers (tim2 to tim5) RM0033 416/1317 doc id 15403 rev 3 14.4.20 tim5 option register (tim5_or) ad dre s s of f s e t : 0x50 re se t v a lu e: 0x 00 0 0 14.4.21 timx register map ti mx re giste r s ar e map p e d as 1 6 - b it a d d r e s sab l e r egist er s a s de scr i b ed in t h e t a b l e be lo w: 15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 1 0 re s e r v ed ti 4_ rmp reser v e d rw rw bits 15:8 reser v ed bits 7:6 ti 4_rmp: timer input 4 rem a p set and clea red b y softw a re . 00 : tim5 chan nel 4 is co nnected to th e gpio: r e f e r to the al ter n a t e functio n ma ppin g tab l e in the stm3 2f2 0 x and stm3 2f2 1 x d a tashee ts . 01 : the lsi in te r n al cloc k is co nne cted to the tim5_ch 4 i npu t f o r cali br atio n pur poses 10 : the lse inter nal clo c k is conn ecte d to the tim5_ ch4 inp u t f o r cal i br a t i on pur pose s 11 : the r t c outpu t e v ent is co nnected to th e tim5_ch4 i npu t f o r calib r a tio n pur p o ses bits 5:0 r e s er v e d t a b l e 62. ti m2 t o ti m5 re gi st er map an d r ese t v a l u es offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x 00 t i mx_cr1 reserved ck d [1 :0] ar p e cms [1: 0 ] dir opm urs udis cen reset v a l u e 0 0 0 000 00 00 0x 04 t i mx_cr2 reser v ed ti1s m m s [2 :0 ] ccds reser v ed reset v a l u e 0 000 0 0x 08 t i mx_s mcr reser v ed etp ece etps [1 :0 ] etf[ 3: 0] msm ts[2: 0 ] reser v e d sms [ 2: 0] r e se t v a l u e 0 000 000 00 000 0 0 0 0x0c ti mx_di e r re s e r v ed tde comd e cc4de cc3de cc2de cc1de ud e reser v ed tie reser v ed cc4ie cc3ie cc2ie cc1ie uie reset v a l u e 0 00 000 0 0 00 00 0 0x 10 ti mx _sr reser v ed cc4of cc3of cc2of cc1of res e r v ed tif re s e r v ed cc4if cc3if cc2if cc1if uif reset v a l u e 0 000 0 0 00 00 0x 14 ti mx_e gr reser v e d tg reser v ed cc4g cc3g cc2g cc1g ug reset v a l u e 0 0 00 00 0x 18 timx_ccmr1 out put c o mpare mode reser v ed oc2 c e oc2 m [2 :0 ] oc2 p e oc2 f e cc 2 s [1 :0] oc1 c e oc1 m [2 :0 ] oc1 p e oc1 f e cc 1 s [1: 0 ] r e se t v a l u e 0 000 000 00 000 00 00 timx_ccmr1 i nput c a ptu r e mode reser v ed i c 2f [3 :0 ] ic2 psc [1 :0 ] cc 2 s [1 :0] i c 1f [3 :0 ] ic1 psc [1 :0 ] cc 1 s [1: 0 ] r e se t v a l u e 0 000 000 00 000 00 00 RM0033 general-purpose timers (tim2 to tim5) doc id 15403 rev 3 417/1317 ref e r to t a b l e 1 on p age 5 0 f o r t h e r e g i st er bou nd ar y ad dr esse s . 0x1c timx_ccmr2 out put co mpare mode reser v ed o2 4ce oc4 m [2 :0 ] oc4 p e oc 4fe cc 4 s [1 :0] oc3ce oc3 m [2 :0 ] oc3 p e oc 3fe cc 3 s [1: 0 ] r e se t v a l u e 0 000 000 00 000 00 00 timx_ccmr2 i nput c a ptu r e mode reser v ed i c 4f [3 :0 ] ic4 psc [1 :0 ] cc 4 s [1 :0] i c 3f [3 :0 ] ic3 psc [1 :0 ] cc 3 s [1: 0 ] r e se t v a l u e 0 000 000 00 000 00 00 0x 20 timx_ccer reser v ed cc4n p re se r v e d cc4p cc4e cc3n p re se r v e d cc3p cc3e cc2n p re se r v e d cc2p cc2e cc1n p re se r v e d cc1p cc1e r e se t v a l u e 0 00 0 0 00 00 0 00 0x 24 ti mx_ c n t cnt[31 : 16 ] (ti m 2 a nd tim5 onl y , re ser v ed on t he ot her t i mers) cnt[ 15: 0] r e se t v a l u e 00 00 000 000 00 000 00 000 000 00 000 00 00 0x 28 timx _psc reser v ed p s c[ 15: 0] r e se t v a l u e 0 000 000 00 000 00 00 0x2c timx_arr arr[ 31: 16] (ti m 2 a nd tim5 onl y , re ser v ed on t he ot her t i mers) arr[1 5 :0 ] r e se t v a l u e 00 00 000 000 00 000 00 000 000 00 000 00 00 0x 30 re s e r v ed 0x 34 t i mx_ c cr1 c c r 1[ 31 : 16 ] (ti m 2 a nd tim5 onl y , re se r v ed on t he ot her t i mers) ccr1[15:0] r e s e t v a l u e 00 00 000 000 00 000 00 000 000 00 000 00 00 0x 38 t i mx_ c cr2 c c r 2[ 31: 16] (ti m 2 a nd tim5 onl y , re ser v ed on t he ot her t i mers) ccr2[15:0] r e se t v a l u e 00 00 000 000 00 000 00 000 000 00 000 00 00 0x3c t i mx_ c cr3 c c r 3[ 31: 16] (ti m 2 a nd tim5 onl y , re ser v ed on t he ot her t i mers) ccr3[15:0] r e se t v a l u e 00 00 000 000 00 000 00 000 000 00 000 00 00 0x 40 t i mx_ c cr4 c c r 4[ 31: 16] (ti m 2 a nd tim5 onl y , re ser v ed on t he ot her t i mers) ccr4[15:0] r e se t v a l u e 00 00 000 000 00 000 00 000 000 00 000 00 00 0x 44 reserved 0x48 timx_dcr reserved dbl[4:0] reserv e d dba[ 4: 0] reset v a l u e 0 000 0 0 00 00 0x4c timx_ d ma r reser v ed dmab[ 15 :0] r e se t v a l u e 0 000 000 00 000 00 00 0x 50 ti m2_o r not a v ailab l e r eser v e d it r1_ rm p reser v ed reset v a l u e 00 0x 50 ti m5_o r not a v ailab l e r eser v e d i t 4_r mp re se r v e d reset v a l u e 00 t a b l e 62. ti m2 t o ti m5 re gi st er map an d r ese t v a l u es ( c on ti n u ed) offset re gister 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 general-purpose timers (tim9 to tim14) RM0033 418/1317 doc id 15403 rev 3 15 general-purpose timers (tim9 to tim14) this section applies to the whole stm32f20x and stm32f21x family, unless otherwise specified. 15.1 tim9 to tim14 introduction the tim9 to tim14 general-purpose timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. they may be used for a variety of purposes, in cluding measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, pwm). pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the rcc clock controller prescalers. the tim9 to tim14 timers are completely independent, and do not share any resources. they can be synchronized together as described in section 15.4.12 . 15.2 tim9 to tim14 main features 15.2.1 tim9/tim12 main features the features of the tim9/tim12 general-purpose timers include: 16-bit auto-reload upcounter 16-bit programmable prescaler used to divide the counter clock frequency by any factor between 1 and 65535 (can be changed ?on the fly?) up to 2 independent channels for: ? input capture ? output compare ? pwm generation (edge-aligned mode) ? one-pulse mode output synchronization circuit to control the timer with external signals and to interconnect several timers together interrupt generation on the following events: ? update: counter overflow, counter initialization (by software or internal trigger) ? trigger event (counter start, stop, initialization or count by internal trigger) ? input capture output compare RM0033 general-purpose timers (tim9 to tim14) doc id 15403 rev 3 419/1317 figure 159. general-purpose timer block diagram (tim9 and tim12) 15.3 tim10/tim11 and tim13/tim14 main features the features of general-purpose timers tim10/tim11 and tim13/tim14 include: 16-bit auto-reload upcounter 16-bit programmable prescaler used to divide the counter clock frequency by any factor between 1 and 65535 (can be changed ?on the fly?) independent channel for: ? input capture ? output compare ? pwm generation (edge-aligned mode) interrupt generation on the following events: ? update: counter overflow, counter initialization (by software) ? input capture ? output compare a u to-relo a d regi s ter c a pt u re/comp a re 1 regi s ter c a pt u re/comp a re 2 regi s ter u u u cc1i cc2i tr i g g e r controller s top, cle a r ti1fp1 ti2fp2 itr0 itr1 itr2 itr 3 trgi o u tp u t control oc1 oc1ref oc2ref u ui re s et, en ab le, co u nt ic1 ic2 pre s c a ler pre s c a ler inp u t filter & edge detector ic2p s ic1p s ti1fp1 o u tp u t control oc2 reg event note s : prelo a d regi s ter s tr a n s ferred to a ctive regi s ter s on u event a ccording to control b it interr u pt tgi trc trc itr trc ti1f_ed inp u t filter & edge detector cc1i cc2i ti1fp2 ti2fp1 ti2fp2 ti1 ti2 timx_ch1 timx_ch2 timx_ch1 timx_ch2 pre s c a ler counter +/- ck_p s c p s c cnt ck_cnt controller mode s l a ve internal clock (ck_int) a i17190 general-purpose timers (tim9 to tim14) RM0033 420/1317 doc id 15403 rev 3 figure 160. general-purpose time r block diagram (tim10/11/13/14) a u torelo a d regi s ter c a pt u re/comp a re 1 regi s ter u u cc1i s top, cle a r o u tp u t control oc1 oc1ref u ui ic1 pre s c a ler inp u t filter & edge detector ic1p s ti1fp1 reg event note s : prelo a d regi s ter s tr a n s ferred to a ctive regi s ter s on u event a ccording to control b it interr u pt & dma o u tp u t cc1i ti1 timx_ch1 pre s c a ler co u nter +/- ck_p s c p s c cnt ck_cnt intern a l clock (ck_int) a i17725 b trigger controller en ab le co u nter trgo timx_ch1 RM0033 general-purpose timers (tim9 to tim14) doc id 15403 rev 3 421/1317 15.4 tim9 to tim14 functional description 15.4.1 time-base unit the main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. the counter can count up. the counter clock can be divided by a prescaler. the counter, the auto-reload register and the prescaler register can be written or read by software. this is true even when the counter is running. the time-base unit includes: counter register (timx_cnt) prescaler register (timx_psc) auto-reload register (timx_arr) the auto-reload register is preloaded. writing to or reading from the auto-reload register accesses the preload register. the content of the preload register are transferred into the shadow register permanently or at each update event (uev), depending on the auto-reload preload enable bit (arpe) in timx_cr1 register. the update event is sent when the counter reaches the overflow and if the udis bit equals 0 in the timx_cr1 register. it can also be generated by software. the generation of the update event is described in detailed for each configuration. the counter is clocked by the prescaler output ck_cnt, which is enabled only when the counter enable bit (cen) in timx_cr1 register is set (refer also to the slave mode controller description to get more details on counter enabling). note that the counter starts counting 1 clock cycle after setting the cen bit in the timx_cr1 register. prescaler description the prescaler can divide the counter clock frequency by any factor between 1 and 65536. it is based on a 16-bit counter controlled through a 16-bit register (in the timx_psc register). it can be changed on the fly as this control register is buffered. the new prescaler ratio is taken into account at the next update event. figure 162 and figure 163 give some examples of the counter behavior when the prescaler ratio is changed on the fly. general-purpose timers (tim9 to tim14) RM0033 422/1317 doc id 15403 rev 3 figure 161. counter timing diagram with prescaler division change from 1 to 2 figure 162. counter timing diagram with prescaler division change from 1 to 4 15.4.2 counter modes upcounting mode in upcounting mode, the counter counts from 0 to the auto-reload value (content of the timx_arr register), then restarts from 0 and generates a counter overflow event. setting the ug bit in the timx_egr register (by software or by using the slave mode controller on tim9 and tim12) also generates an update event. the uev event can be disabled by software by setting the udis bit in the timx_cr1 register. this is to avoid updating the shadow registers while writing new values in the preload registers. then no update event occurs until the udis bit has been written to 0. however, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). in addition, if the urs bit (update request selection) in timx_cr1 register is set, setting the ug bit generates an update event uev but without ck_psc 00 cen timer clock = ck_cnt counter register update event (uev) 0 f9 fa fb fc f7 prescaler control register 01 write a new value in timx_psc 01 02 03 prescaler buffer 01 prescaler counter 0 1 0 1 0 1 0 1 f8 ck_psc 00 cen timer clock = ck_cnt counter register update event (uev) 0 f9 fa fb fc f7 prescaler control register 03 write a new value in timx_psc prescaler buffer 03 prescaler counter 0 1 2 3 0 1 2 3 f8 01 RM0033 general-purpose timers (tim9 to tim14) doc id 15403 rev 3 423/1317 setting the uif flag (thus no interrupt is sent). this is to avoid generating both update and capture interrupts when clearing the counter on the capture event. when an update event occurs, all the registers are updated and the update flag (uif bit in timx_sr register) is set (depending on the urs bit): the auto-reload shadow register is updated with the preload value (timx_arr), the buffer of the prescaler is reloaded with the preload value (content of the timx_psc register). the following figures show some examples of the counter behavior for different clock frequencies when timx_arr=0x36. figure 163. counter timing diagra m, internal clock divided by 1 figure 164. counter timing diagra m, internal clock divided by 2 ck_psc 00 cnt_en timer clock = ck_cnt counter register update interrupt flag (uif) counter overflow update event (uev) 01 02 03 04 05 06 07 32 33 34 35 36 31 ck_psc 0035 0000 0001 0002 0003 cnt_en timer clock = ck_cnt counter register update interrupt flag (uif) 0034 0036 counter overflow update event (uev) general-purpose timers (tim9 to tim14) RM0033 424/1317 doc id 15403 rev 3 figure 165. counter timing diagra m, internal clock divided by 4 figure 166. counter timing diagra m, internal clock divided by n figure 167. counter timing diagram, u pdate event when arpe=0 (timx_arr not preloaded) ck_psc 0000 0001 cnt_en timer clock = ck_cnt counter register update interrupt flag (uif) 0035 0036 counter overflow update event (uev) timer clock = ck_cnt counter register 00 1f 20 update interrupt flag (uif) counter overflow update event (uev) ck_psc ck_psc 00 cen timer clock = ck_cnt counter register update interrupt flag (uif) counter overflow update event (uev) 01 02 03 04 05 06 07 32 33 34 35 36 31 auto-reload register ff 36 write a new value in timx_arr RM0033 general-purpose timers (tim9 to tim14) doc id 15403 rev 3 425/1317 figure 168. counter timing diagram, update event when arpe=1 (timx_arr preloaded) 15.4.3 clock selection the counter clock can be provided by the following clock sources: internal clock (ck_int) external clock mode1 (for tim9 and tim12 ): external input pin (tix) internal trigger inputs (itrx) (for tim9 and tim12 ): connecting the trigger output from another timer. refer to using one timer as prescaler for another for more details. internal clock source (ck_int) the internal clock source is the default clock source for tim10/tim11 and tim13/tim14. for tim9 and tim12, the internal clock source is selected when the slave mode controller is disabled (sms=?000?). the cen bit in the timx_cr1 register and the ug bit in the timx_egr register are then used as control bits and can be changed only by software (except for ug which remains cleared). as soon as the cen bit is programmed to 1, the prescaler is clocked by the internal clock ck_int. figure 169 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler. ck_psc 00 cen timer clock = ck_cnt counter register update interrupt flag (uif) counter overflow update event (uev) 01 02 03 04 05 06 07 f1 f2 f3 f4 f5 f0 auto-reload preload register f5 36 auto-reload shadow register f5 36 write a new value in timx_arr general-purpose timers (tim9 to tim14) RM0033 426/1317 doc id 15403 rev 3 figure 169. control circuit in normal mode, internal clock divided by 1 external clock source mode 1( tim9 and tim12) this mode is selected when sms=?111? in the timx_smcr register. the counter can count at each rising or falling edge on a selected input. figure 170. ti2 external clock connection example for example, to configure the upcounter to count in response to a rising edge on the ti2 input, use the following procedure: 1. configure channel 2 to detect rising edges on the ti2 input by writing cc2s = ?01? in the timx_ccmr1 register. 2. configure the input filter duration by writing the ic2f[3:0] bits in the timx_ccmr1 register (if no filter is needed, keep ic2f=?0000?). 3. select the rising edge polarity by writ ing cc2p=?0? and cc2np=?0? in the timx_ccer register. 4. configure the timer in external clock mode 1 by writing sms=?111? in the timx_smcr register. 5. select ti2 as the trigger input source by writing ts=?110? in the timx_smcr register. 6. enable the counter by writing cen=?1? in the timx_cr1 register. note: the capture prescaler is not used for triggering, so you don?t need to configure it. when a rising edge occurs on ti2, the counter counts once and the tif flag is set. the delay between the rising edge on ti2 and the actual clock of the counter is due to the resynchronization circuit on ti2 input. internal clock 00 counter clock = ck_cnt = ck_psc counter register 01 02 03 04 05 06 07 32 33 34 35 36 31 cen=cnt_en ug cnt_init ck_int external clock mode 1 internal clock mode trgi ti1f ti2f or or or (internal clock) ck_psc timx_smcr sms[2:0] itrx ti1_ed ti1fp1 ti2fp2 timx_smcr ts[2:0] ti2 0 1 timx_ccer cc2p filter icf[3:0] timx_ccmr1 edge detector ti2f_rising ti2f_falling 110 0xx 100 101 RM0033 general-purpose timers (tim9 to tim14) doc id 15403 rev 3 427/1317 figure 171. control circuit in external clock mode 1 15.4.4 capture/compare channels each capture/compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control). figure 172 to figure 174 give an overview of one capture/compare channel. the input stage samples the corresponding tix input to generate a filtered signal tixf. then, an edge detector with polarity selection generates a signal (tixfpx) which can be used as trigger input by the slave mode controller or as the capture command. it is prescaled before the capture register (icxps). figure 172. capture/compare channel (example: channel 1 input stage) the output stage generates an intermediate waveform which is then used for reference: ocxref (active high). the polarity acts at the end of the chain. counter clock = ck_cnt = ck_psc counter register 35 36 34 ti2 cnt_en tif write tif=0 ti1 0 1 timx_ccer cc1p/cc1np divider /1, /2, /4, /8 icps[1:0] ti1f_ed filter icf[3:0] downcounter timx_ccmr1 edge detector ti1f_rising ti1f_falling to the slave mode controller ti1fp1 11 01 timx_ccmr1 cc1s[1:0] ic1 ti2fp1 trc (from channel 2) (from slave mode controller) 10 f dts timx_ccer cc1e ic1ps ti1f 0 1 ti2f_rising ti2f_falling (from channel 2) general-purpose timers (tim9 to tim14) RM0033 428/1317 doc id 15403 rev 3 figure 173. capture/compare channel 1 main circuit figure 174. output stage of capture/compare channel (channel 1) the capture/compare block is made of one preload register and one shadow register. write and read always access the preload register. in capture mode, captures are actually done in the shadow register, which is copied into the preload register. in compare mode, the content of the preload register is copied into the shadow register which is compared to the counter. 15.4.5 input capture mode in input capture mode, the capture/compare registers (timx_ccrx) are used to latch the value of the counter after a transition detected by the corresponding icx signal. when a capture occurs, the corresponding ccxif flag (timx_sr register) is set and an interrupt or a dma request can be sent if they are enabled. if a capture occurs while the ccxif flag was already high, then the over-capture flag ccx of (timx_sr register) is set. ccxif can be cc1e capture/compare shadow register comparator capture/compare preload register counter ic1ps cc1s[0] cc1s[1] capture input mode s r read ccr1h read ccr1l read_in_progress capture_transfer cc1s[0] cc1s[1] s r write ccr1h write ccr1l write_in_progress output mode uev oc1pe (from time compare_transfer apb bus 8 8 high low (if 16-bit) mcu-peripheral interface tim1_ccmr1 oc1pe base unit) cnt>ccr1 cnt=ccr1 tim1_egr cc1g / u t p u t m o d e # . 4 # # 2 # . 4 # # 2 c o n t r o l l e r 4 ) - x ? # # - 2 / # - ; = / # ? 2 % & # # 0 4 ) - x ? # # % 2 / u t p u t e n a b l e c i r c u i t / # # # % 4 ) - x ? # # % 2 4 o t h e m a s t e r m o d e c o n t r o l l e r a i RM0033 general-purpose timers (tim9 to tim14) doc id 15403 rev 3 429/1317 cleared by software by writing it to ?0? or by reading the captured data stored in the timx_ccrx register. ccxof is clea red when you write it to ?0?. the following example shows how to capture the counter value in timx_ccr1 when ti1 input rises. to do this, use the following procedure: 1. select the active input: timx_ccr1 must be linked to the ti1 input, so write the cc1s bits to ?01? in the timx_ccmr1 register. as soon as cc1s becomes different from ?00?, the channel is configured in input mode and the timx_ccr1 register becomes read- only. 2. program the input filter duration you need with respect to the signal you connect to the timer (when the input is one of the tix (icxf bits in the timx_ccmrx register). let?s imagine that, when toggling, the input signal is not stable during at must 5 internal clock cycles. we must program a filter duration longer than these 5 clock cycles. we can validate a transition on ti1 when 8 consecutive samples with the new level have been detected (sampled at f dts frequency). then write ic1f bits to ?0011? in the timx_ccmr1 register. 3. select the edge of the active transition on the ti1 channel by programming cc1p and cc1np bits to ?00? in the timx_ccer register (rising edge in this case). 4. program the input prescaler. in our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write ic1ps bits to ?00? in the timx_ccmr1 register). 5. enable capture from the counter into the capture register by setting the cc1e bit in the timx_ccer register. 6. if needed, enable the related interrupt request by setting the cc1ie bit in the timx_dier register. when an input capture occurs: the timx_ccr1 register gets the value of the counter on the active transition. cc1if flag is set (interrupt flag). cc1of is also set if at least two consecutive captures occurred whereas the flag was not cleared. an interrupt is generated depending on the cc1ie bit. in order to handle the overcapture, it is recommended to read the data before the overcapture flag. this is to avoid missing an overcapture which could happen after reading the flag and before reading the data. note: ic interrupt requests can be generated by software by setting the corresponding ccxg bit in the timx_egr register. 15.4.6 pwm input mode (only for tim9/12) this mode is a particular case of input c apture mode. the procedure is the same except: two icx signals are mapped on the same tix input. these 2 icx signals are active on edges with opposite polarity. one of the two tixfp signals is selected as trigger input and the slave mode controller is configured in reset mode. for example, you can measure the period (in timx_ccr1 register) and the duty cycle (in timx_ccr2 register) of the pwm applied on ti1 using the following procedure (depending on ck_int frequency and prescaler value): general-purpose timers (tim9 to tim14) RM0033 430/1317 doc id 15403 rev 3 1. select the active input for timx_ccr1: writ e the cc1s bits to ?01? in the timx_ccmr1 register (ti1 selected). 2. select the active polarity for ti1fp1 (used both for capture in timx_ccr1 and counter clear): program the cc1p and cc1np bits to ?00? (active on rising edge). 3. select the active input fo r timx_ccr2: write the cc2s bits to ?10? in the timx_ccmr1 register (ti1 selected). 4. select the active polarity for ti1fp2 (u sed for capture in ti mx_ccr2): program the cc2p and cc2np bits to ?11? (active on falling edge). 5. select the valid trigger input: write the ts bits to ?101? in the timx_smcr register (ti1fp1 selected). 6. configure the slave mode controller in reset mode: write the sms bits to ?100? in the timx_smcr register. 7. enable the captures: write the cc1e and cc2e bits to ?1? in the timx_ccer register. figure 175. pwm input mode timing 1. the pwm input mode can be used only with the timx _ch1/timx_ch2 signals due to the fact that only ti1fp1 and ti2fp2 are connected to the slave mode controller. 15.4.7 forced output mode in output mode (ccxs bits = ?00? in the timx_ccmrx register), each output compare signal (ocxref and then ocx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. to force an output compare signal (ocxref/ocx) to its active level, you just need to write ?101? in the ocxm bits in the corresponding timx_ccmrx register. thus ocxref is forced high (ocxref is always active high) and ocx get opposite value to ccxp polarity bit. for example: ccxp=?0? (ocx active high) => ocx is forced to high level. the ocxref signal can be forced low by writin g the ocxm bits to ?100? in the timx_ccmrx register. anyway, the comparison between the timx_ccrx shadow register and the counter is still performed and allows the flag to be set. interrupt requests can be sent accordingly. this is described in the output compare mode section below. ti1 timx_cnt 0000 0001 0002 0003 0004 0000 0004 timx_ccr1 timx_ccr2 0004 0002 ic1 capture ic2 capture reset counter ic2 capture pulse width ic1 capture period measurement measurement ai15413 RM0033 general-purpose timers (tim9 to tim14) doc id 15403 rev 3 431/1317 15.4.8 output compare mode this function is used to control an output waveform or indicating when a period of time has elapsed. when a match is found between the capture/compare register and the counter, the output compare function: 1. assigns the corresponding output pin to a programmable value defined by the output compare mode (ocxm bits in the timx_ccmrx register) and the output polarity (ccxp bit in the timx_ccer register). the output pin can keep its level (ocxm=?000?), be set active (ocxm=?001?), be set inactive (ocx m=?010?) or can toggl e (ocxm=?011?) on match. 2. sets a flag in the interrupt status register (ccxif bit in the timx_sr register). 3. generates an interrupt if the corresponding interrupt mask is set (ccxie bit in the timx_dier register). the timx_ccrx registers can be programmed with or without preload registers using the ocxpe bit in the timx_ccmrx register. in output compare mode, the update event uev has no effect on ocxref and ocx output. the timing resolution is one count of the counter. output compare mode can also be used to output a single pulse (in one-pulse mode). procedure: 1. select the counter clock (internal, external, prescaler). 2. write the desired data in the timx_arr and timx_ccrx registers. 3. set the ccxie bit if an interrupt request is to be generated. 4. select the output mode. for example: ? write ocxm = ?011? to toggle ocx output pin when cnt matches ccrx ? write ocxpe = ?0? to disable preload register ? write ccxp = ?0? to select active high polarity ? write ccxe = ?1? to enable the output 5. enable the counter by setting the cen bit in the timx_cr1 register. the timx_ccrx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (ocxpe=?0?, else timx_ccrx shadow register is updated only at the next update event uev). an example is given in figure 176 . general-purpose timers (tim9 to tim14) RM0033 432/1317 doc id 15403 rev 3 figure 176. output compare mode, toggle on oc1. 15.4.9 pwm mode pulse width modulation mode allows you to generate a signal with a frequency determined by the value of the timx_arr register and a duty cycle determined by the value of the timx_ccrx register. the pwm mode can be selected independently on each channel (one pwm per ocx output) by writing ?110? (pwm mode 1) or ?111? (pwm mode 2) in the ocxm bits in the timx_ccmrx register. you must enable the corresponding preload register by setting the ocxpe bit in the timx_ccmrx register, and even tually the auto-reload preload register (in upcounting or center-aligned modes) by setting the arpe bit in the timx_cr1 register. as the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, you have to initialize all the registers by setting the ug bit in the timx_egr register. the ocx polarity is software programmable using the ccxp bit in the timx_ccer register. it can be programmed as active high or active low. the ocx output is enabled by the ccxe bit in the timx_ccer register. refer to the timx_ccerx register description for more details. in pwm mode (1 or 2), timx_cnt and timx_ccrx are always compared to determine whether timx_cnt timx_ccrx. the timer is able to generate pwm in edge-aligned mode only since the counter is upcounting. pwm edge-aligned mode in the following example, we consider pwm mo de 1. the reference pwm signal ocxref is high as long as timx_cnt < timx_ccrx else it becomes low. if the compare value in timx_ccrx is greater than the auto-reload valu e (in timx_arr) then ocxref is held at ?1?. if the compare value is 0 then ocxref is held at ?0?. figure 177 shows some edge- aligned pwm waveforms in an example where timx_arr=8. oc1ref=oc1 tim1_cnt b200 b201 0039 tim1_ccr1 003a write b201h in the cc1r register match detected on ccr1 interrupt generated if enabled 003b b201 003a RM0033 general-purpose timers (tim9 to tim14) doc id 15403 rev 3 433/1317 figure 177. edge-aligned pwm waveforms (arr=8) 15.4.10 one-pulse mode (only for tim9/12) one-pulse mode (opm) is a particular case of the previous modes. it allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. starting the counter can be controlled through the slave mode controller. generating the waveform can be done in output compare mode or pwm mode. you select one-pulse mode by setting the opm bit in the timx_cr1 register. this makes the counter stop automatically at the next update event uev. a pulse can be correctly generated only if the compare value is different from the counter initial value. before starting (when the timer is waiting for the trigger), the configuration must be as follows: cnt < ccrx arr (in particular, 0 < ccrx) figure 178. example of one pulse mode. counter register ?? 0 1234567801 ?? ocxref ccxif ocxref ccxif ocxref ccxif ocxref ccxif ccrx=4 ccrx=8 ccrx>8 ccrx=0 ti2 oc1ref counter t 0 tim1_arr tim1_ccr1 oc1 t delay t pulse general-purpose timers (tim9 to tim14) RM0033 434/1317 doc id 15403 rev 3 for example you may want to generate a positive pulse on oc1 with a length of t pulse and after a delay of t delay as soon as a positive edge is detected on the ti2 input pin. use ti2fp2 as trigger 1: 1. map ti2fp2 to ti2 by writing cc2s =?01? in the timx_ccmr1 register. 2. ti2fp2 must detect a rising edge, writ e cc2p=?0? and cc2np = ?0? in the timx_ccer register. 3. configure ti2fp2 as trigger for the slave mode controller (trgi) by writing ts=?110? in the timx_smcr register. 4. ti2fp2 is used to start the counter by writing sms to ?110? in the timx_smcr register (trigger mode). the opm waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). the t delay is defined by the value writte n in the timx_ccr1 register. the t pulse is defined by the difference between the auto-reload value and the compare value (timx_arr - timx_ccr1). let?s say you want to build a waveform with a transition from ?0? to ?1? when a compare match occurs and a transition from ?1? to ?0? when the counter reaches the auto-reload value. to do this you enable pwm mode 2 by writing oc1m=?111? in the timx_ccmr1 register. you can optionally enable the preload registers by writing oc1pe=?1? in the timx_ccmr1 register and arpe in the timx_cr1 register. in this case you have to write the compare value in the timx_ccr1 register, the auto-reload value in the timx_arr register, generate an update by setting the ug bit and wait for external trigger event on ti2. cc1p is written to ?0? in this example. you only want 1 pulse (single mode), so you write '1 in the opm bit in the timx_cr1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0). when opm bit in the timx_cr1 register is set to '0', so the repetitive mode is selected. particular case: ocx fast enable in one-pulse mode, the edge detection on tix input set the cen bit which enables the counter. then the comparison between the counter and the compare value makes the output toggle. but several clock cycles are needed for these operations and it limits the minimum delay t delay min we can get. if you want to output a waveform with the minimum delay, you can set the ocxfe bit in the timx_ccmrx register. then ocxref (and ocx) are forced in response to the stimulus, without taking in account the comparison. its new level is the same as if a compare match had occurred. ocxfe acts only if the channel is configured in pwm1 or pwm2 mode. 15.4.11 tim9/12 external trigger synchronization the tim9/12 timers can be synchronized with an external trigger in several modes: reset mode, gated mode and trigger mode. slave mode: reset mode the counter and its prescaler can be reinitialized in response to an event on a trigger input. moreover, if the urs bit from the timx_cr1 register is low, an update event uev is generated. then all the preloaded registers (timx_arr, timx_ccrx) are updated. in the following example, the upcounter is cleared in response to a rising edge on ti1 input: RM0033 general-purpose timers (tim9 to tim14) doc id 15403 rev 3 435/1317 1. configure the channel 1 to detect rising edges on ti1. configure the input filter duration (in this example, we don?t need any filter, so we keep ic1f=?0000?). the capture prescaler is not used for triggering, so you don?t need to configure it. the cc1s bits select the input capture source only, cc1s = ?01? in the timx_ccmr1 register. program cc1p and cc1np to ?00? in timx_ccer register to validate the polarity (and detect rising edges only). 2. configure the timer in reset mode by writ ing sms=?100? in timx_smcr register. select ti1 as the input source by writing ts=?101? in timx_smcr register. 3. start the counter by writing ce n=?1? in the timx_cr1 register. the counter starts counting on the internal clock, then behaves normally until ti1 rising edge. when ti1 rises, the counter is cleared and restarts from 0. in the meantime, the trigger flag is set (tif bit in the timx_sr register) and an interrupt request can be sent if enabled (depending on the tie bit in timx_dier register). the following figure shows this behavior when the auto-reload register timx_arr=0x36. the delay between the rising edge on ti1 and the actual reset of the counter is due to the resynchronization circuit on ti1 input. figure 179. control circuit in reset mode slave mode: gated mode the counter can be enabled depending on the level of a selected input. in the following example, the upcounter counts only when ti1 input is low: 1. configure the channel 1 to detect low levels on ti1. configure the input filter duration (in this example, we don?t need any filter, so we keep ic1f=?0000?). the capture prescaler is not used for triggering, so you don?t need to configure it. the cc1s bits select the input capture source only, cc1s=?01? in timx_ccmr1 register. program cc1p=?1? and cc1np= ?0? in timx_ccer regist er to validate the polarity (and detect low level only). 2. configure the timer in gated mode by writing sms=?101? in timx_smcr register. select ti1 as the input source by writing ts=?101? in timx_smcr register. 3. enable the counter by writing cen=?1? in the timx_cr1 register (in gated mode, the counter doesn?t start if cen=?0?, w hatever is the trigger input level). the counter starts counting on the internal clock as long as ti1 is low and stops as soon as ti1 becomes high. the tif flag in the timx_sr register is set both when the counter starts or stops. the delay between the rising edge on ti1 and the actual stop of the counter is due to the resynchronization circuit on ti1 input. 00 counter clock = ck_cnt = ck_psc counter register 01 02 03 00 01 02 03 32 33 34 35 36 ug ti1 31 30 tif general-purpose timers (tim9 to tim14) RM0033 436/1317 doc id 15403 rev 3 figure 180. control circuit in gated mode counter clock = ck_cnt = ck_psc counter register 35 36 37 38 32 33 34 ti1 31 30 cnt_en tif write tif=0 RM0033 general-purpose timers (tim9 to tim14) doc id 15403 rev 3 437/1317 slave mode: trigger mode the counter can start in response to an event on a selected input. in the following example, the upcounter starts in response to a rising edge on ti2 input: 1. configure the channel 2 to detect rising edges on ti2. configure the input filter duration (in this example, we don?t need any filter, so we keep ic2f=?0000?). the capture prescaler is not used for triggering, so you don?t need to configure it. the cc2s bits are configured to select the input capture source only, cc2s=?01? in timx_ccmr1 register. program cc2p=?1? and cc2np=?0? in timx_ccer register to validate the polarity (and detect low level only). 2. configure the timer in trigger mode by writing sms=?110? in timx_smcr register. select ti2 as the input source by writing ts=?110? in timx_smcr register. when a rising edge occurs on ti2, the counter starts counting on the internal clock and the tif flag is set. the delay between the rising edge on ti2 and the actual start of the counter is due to the resynchronization circuit on ti2 input. figure 181. control circuit in trigger mode 15.4.12 timer synchronization (tim9/12) the tim timers are linked together internally for timer synchronization or chaining. refer to section 14.3.15: timer synchronization on page 388 for details. 15.4.13 debug mode when the microcontroller enters debug mode (cortex-m3 core halted), the timx counter either continues to work normally or stops, depending on dbg_timx_stop configuration bit in dbg module. for more details, refer to section 32.16.2: debug support for timers, watchdog, bxcan and i 2 c . counter clock = ck_cnt = ck_psc counter register 35 36 37 38 34 ti2 cnt_en tif general-purpose timers (tim9 to tim14) RM0033 438/1317 doc id 15403 rev 3 15.5 tim9 and tim12 registers refer to section 1.1 for a list of abbreviations used in register descriptions. 15.5.1 tim9/12 control re gister 1 (timx_cr1) address offset: 0x00 reset value: 0x0000 1514131211109876543210 reserved ckd[1:0] arpe reserved opm urs udis cen rw rw rw rw rw rw rw bits 15:10 reserved, always read as 0 bits 9:8 ckd : clock division this bit-field indicates the division ratio between the timer clock (ck_int) frequency and sampling clock used by the digital filters (tix), 00: t dts = t ck_int 01: t dts = 2 t ck_int 10: t dts = 4 t ck_int 11: reserved bit 7 arpe : auto-reload preload enable 0: timx_arr register is not buffered. 1: timx_arr register is buffered. bits 6:4 reserved bit 3 opm : one-pulse mode 0: counter is not stopped on the update event 1: counter stops counting on the next update event (clearing the cen bit). bit 2 urs : update request source this bit is set and cleared by software to select the uev event sources. 0: any of the following events gener ates an update interrupt if enabled: ? counter overflow ? setting the ug bit 1: only counter overflow generates an update interrupt if enabled. bit 1 udis : update disable this bit is set and cleared by software to enable/disable update event (uev) generation. 0: uev enabled. an uev is generated by one of the following events: ? counter overflow ? setting the ug bit buffered registers are then loaded with their preload values. 1: uev disabled. no uev is generated, shadow registers keep their value (arr, psc, ccrx). the counter and the prescaler ar e reinitialized if the ug bit is set. bit 0 cen : counter enable 0: counter disabled 1: counter enabled cen is cleared automatically in one-pulse mode, when an update event occurs. RM0033 general-purpose timers (tim9 to tim14) doc id 15403 rev 3 439/1317 15.5.2 tim9/12 control re gister 2 (timx_cr2) address offset: 0x04 reset value: 0x0000 1514131211109876543210 reserved mms[2:0] reserved rw rw rw bits 15:7 reserved, always read as 0. bits 6:4 mms : master mode selection these bits are used to select the information to be sent in master mode to slave timers for synchronization (trgo). the combination is as follows: 000: reset - the ug bit in the timx_egr register is used as the trigger output (trgo). if the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on trgo is delay ed compared to the actual reset. 001: enable - the counter enable signal, cnt_en, is used as the trigger output (trgo). it is useful to start several timers at the same time or to control a window in which a slave timer is enabled. the counter enable signal is gener ated by a logic or between the cen control bit and the trigger input when configured in gated mode. when the counter enable signal is controlled by the trigger input, there is a delay on trgo, except if the master/slave mode is selected (see the msm bit description in the timx_smcr register). 010: update - the update event is selected as the trigger output (trgo). for instance a master timer can be used as a prescaler for a slave timer. 011: compare pulse - the trigger output sends a positive pulse when the cc1if flag is to be set (even if it was already high), as soon as a capture or a compare match occurs. (trgo). 100: compare - oc1ref signal is used as the trigger output (trgo). 101: compare - oc2ref signal is used as the trigger output (trgo). 110: reserved 111: reserved bits 3:0 reserved, always read as 0. general-purpose timers (tim9 to tim14) RM0033 440/1317 doc id 15403 rev 3 15.5.3 tim9/12 slave mode cont rol register (timx_smcr) address offset: 0x08 reset value: 0x0000 1514131211109876543210 reserved msm ts[2:0] res. sms[2:0] rw rw rw rw rw rw rw bits 15:8 reserved. bit 7 msm: master/slave mode 0: no action 1: the effect of an event on the trigger input (trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through trgo). it is useful in order to synchronize several timers on a single external event. bits 6:4 ts: trigger selection this bitfield selects the trigger input to be used to synchronize the counter. 000: internal trigger 0 (itr0) 001: internal trigger 1 (itr1) 010: internal trigger 2 (itr2) 011: internal trigger 3 (itr3) 100: ti1 edge detector (ti1f_ed) 101: filtered timer input 1 (ti1fp1) 110: filtered timer input 2 (ti2fp2) 111: reserved. see table 63: timx internal trigger connection on page 441 for more details on the meaning of itrx for each timer. note: these bits must be changed only when they are not used (e.g. when sms=?000?) to avoid wrong edge detections at the transition. bit 3 reserved, always read as 0. bits 2:0 sms: slave mode selection when external signals are selected, the active edge of the trigger signal (trgi) is linked to the polarity selected on the external input (see input control register and control register descriptions. 000: slave mode disabled - if cen = 1 then the prescaler is clocked directly by the internal clock 001: reserved 010: reserved 011: reserved 100: reset mode - rising edge of the selected tr igger input (trgi) reinitializes the counter and generates an update of the registers 101: gated mode - the counter clock is enabled when the trigger input (trgi) is high. the counter stops (but is not reset) as soon as the trigger becomes low. counter starts and stops are both controlled 110: trigger mode - the counter starts on a ri sing edge of the trigger trgi (but it is not reset). only the start of the counter is controlled 111: external clock mode 1 - rising edges of the selected trigger (trgi) clock the counter note: the gated mode must not be used if ti1f_ed is selected as the trigger input (ts=?100?). indeed, ti1f_ed outputs 1 puls e for each transition on ti1f, whereas the gated mode checks the level of the trigger signal. RM0033 general-purpose timers (tim9 to tim14) doc id 15403 rev 3 441/1317 15.5.4 tim9/12 interrupt enab le register (timx_dier) address offset: 0x0c reset value: 0x0000 table 63. timx internal trigger connection slave tim itr0 (ts =? 000?) itr1 (ts = ? 001?) itr2 (ts = ?010?) itr3 (ts = ?011?) tim2 tim1 tim8 tim3 tim4 tim3 tim1 tim2 tim5 tim4 tim4 tim1 tim2 tim3 tim8 tim5 tim2 tim3 tim4 tim8 tim9 tim2 tim3 tim10 tim11 tim12 tim4 tim5 tim13 tim14 1514131211109876543210 reserved tie res cc2ie cc1ie uie rw rw rw rw bit 15:7 reserved, always read as 0. bit 6 tie : trigger interrupt enable 0: trigger interrupt disabled. 1: trigger interrupt enabled. bit 5:3 reserved, always read as 0. bit 2 cc2ie : capture/compare 2 interrupt enable 0: cc2 interrupt disabled. 1: cc2 interrupt enabled. bit 1 cc1ie : capture/compare 1 interrupt enable 0: cc1 interrupt disabled. 1: cc1 interrupt enabled. bit 0 uie : update interrupt enable 0: update interrupt disabled. 1: update interrupt enabled. general-purpose timers (tim9 to tim14) RM0033 442/1317 doc id 15403 rev 3 15.5.5 tim9/12 status register (timx_sr) address offset: 0x10 reset value: 0x0000 1514131211109876543210 reserved cc2of cc1of reserved tif reserved cc2if cc1if uif rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 bit 15:11 reserved, always read as 0. bit 10 cc2of : capture/compare 2 overcapture flag refer to cc1of description bit 9 cc1of : capture/compare 1 overcapture flag this flag is set by hardware only when the corresponding channel is configured in input capture mode. it is cleared by software by writing it to ?0?. 0: no overcapture has been detected. 1: the counter value has been captured in timx_ccr1 register while cc1if flag was already set bits 8:7 reserved, always read as 0. bit 6 tif : trigger interrupt flag this flag is set by hardware on trigger event (active edge detected on trgi input when the slave mode controller is enabled in all modes but gated mode. it is set when the counter starts or stops when gated mode is selected. it is cleared by software. 0: no trigger event occurred. 1: trigger interrupt pending. bit 5:3 reserved, always read as 0 bit 2 cc2if : capture/compare 2 interrupt flag refer to cc1if description bit 1 cc1if : capture/compare 1 interrupt flag if channel cc1 is configured as output: this flag is set by hardware when the counter matches the compare value. it is cleared by software. 0: no match. 1: the content of the counte r timx_cnt matches the content of the timx_ccr1 register. when the contents of timx_c cr1 are greater than the cont ents of timx_arr, the cc1if bit goes high on the counter overflow. if channel cc1 is configured as input: this bit is set by hardware on a capture. it is cleared by software or by reading the timx_ccr1 register. 0: no input capture occurred. 1: the counter value has been captured in timx _ccr1 register (an edge has been detected on ic1 which matches the selected polarity). RM0033 general-purpose timers (tim9 to tim14) doc id 15403 rev 3 443/1317 15.5.6 tim9/12 event generat ion register (timx_egr) address offset: 0x14 reset value: 0x0000 bit 0 uif : update interrupt flag this bit is set by hardware on an update event. it is cleared by software. 0: no update occurred. 1: update interrupt pending. this bit is se t by hardware when the registers are updated: ?at overflow and if udis=?0? in the timx_cr1 register. ?when cnt is reinitialized by software using th e ug bit in timx_egr register, if urs=?0? and udis=?0? in the timx_cr1 register. ?when cnt is reinitialized by a trigger ev ent (refer to the synchro control register description), if urs=?0? and udis=?0? in the timx_cr1 register. 1514131211109876543210 reserved tg reserved cc2g cc1g ug w www bits 15:7 reserved, always read as 0. bit 6 tg : trigger generation this bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: no action 1: the tif flag is set in the timx_sr register. related interrupt can occur if enabled bits 5:3 reserved, always read as 0. bit 2 cc2g : capture/compare 2 generation refer to cc1g description bit 1 cc1g : capture/compare 1 generation this bit is set by software to generate an event, it is automatically cleared by hardware. 0: no action 1: a capture/compare event is generated on channel 1: if channel cc1 is configured as output: the cc1if flag is set, the corresponding interrupt is sent if enabled. if channel cc1 is configured as input: the current counter value is captured in the timx_ccr1 register. the cc1if flag is set, the corresponding interrupt is sent if enabled. the cc1of flag is set if the cc1if flag was already high. bit 0 ug : update generation this bit can be set by software, it is automatically cleared by hardware. 0: no action 1: re-initializes the counter and generates an update of the registers. the prescaler counter is also cleared and the prescaler ratio is not affected. the counter is cleared. general-purpose timers (tim9 to tim14) RM0033 444/1317 doc id 15403 rev 3 15.5.7 tim9/12 capture/compare m ode register 1 (timx_ccmr1) address offset: 0x18 reset value: 0x0000 the channels can be used in input (capture mode) or in output (compare mode). the direction of a channel is defined by configuring the corresponding ccxs bits. all the other bits in this register have different functions in input and output modes. for a given bit, ocxx describes its function when the channel is configured in output mode, icxx describes its function when the channel is configured in input mode. so you must take care that the same bit can have different meanings for the input stage and the output stage. output compare mode 1514131211109876543210 res. oc2m[2:0] oc2pe oc2fe cc2s[1:0] res. oc1m[2:0] oc1pe oc1fe cc1s[1:0] ic2f[3:0] ic2psc[1:0] ic1f[3:0] ic1psc[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bit 15 reserved bits 14:12 oc2m[2:0] : output compare 2 mode bit 11 oc2pe : output compare 2 preload enable bit 10 oc2fe : output compare 2 fast enable bits 9:8 cc2s[1:0] : capture/compare 2 selection this bitfield defines the direction of the c hannel (input/output) as well as the used input. 00: cc2 channel is configured as output 01: cc2 channel is configured as input, ic2 is mapped on ti2 10: cc2 channel is configured as input, ic2 is mapped on ti1 11: cc2 channel is configured as input, ic2 is mapped on trc. this mode works only if an internal trigger input is selected through the ts bit (timx_smcr register note: the cc2s bits are writable only when the channel is off (cc2e = 0 in timx_ccer). bit 7 reserved RM0033 general-purpose timers (tim9 to tim14) doc id 15403 rev 3 445/1317 bits 6:4 oc1m : output compare 1 mode these bits define the behavior of the output reference signal oc1ref from which oc1 and oc1n are derived. oc1ref is active high whereas the active levels of oc1 and oc1n depend on the cc1p and cc1np bits, respectively. 000: frozen - the comparison between the ou tput compare register timx_ccr1 and the counter timx_cnt has no effect on the outputs.(this mode is used to generate a timing base). 001: set channel 1 to active level on match. the oc1ref signal is forced high when the timx_cnt counter matches the capt ure/compare register 1 (timx_ccr1). 010: set channel 1 to inactive level on match. the oc1ref signal is forced low when the timx_cnt counter matches the capt ure/compare register 1 (timx_ccr1). 011: toggle - oc1ref toggles when timx_cnt=timx_ccr1 100: force inactive level - oc1ref is forced low 101: force active level - oc1ref is forced high 110: pwm mode 1 - in upcounting, channel 1 is active as long as timx_cnt general-purpose timers (tim9 to tim14) RM0033 446/1317 doc id 15403 rev 3 input capture mode bits 15:12 ic2f : input capture 2 filter bits 11:10 ic2psc[1:0] : input capture 2 prescaler bits 9:8 cc2s : capture/compare 2 selection this bitfield defines the direction of the channel (input/output) as well as the used input. 00: cc2 channel is configured as output 01: cc2 channel is configured as input, ic2 is mapped on ti2 10: cc2 channel is configured as input, ic2 is mapped on ti1 11: cc2 channel is configured as input, ic2 is mapped on trc. this mode works only if an internal trigger input is selected th rough the ts bit (timx_smcr register) note: the cc2s bits are writable only when the channel is off (cc2e = 0 in timx_ccer). bits 7:4 ic1f : input capture 1 filter this bitfield defines the frequency used to samp le the ti1 input and the length of the digital filter applied to ti1. the digital filter is made of an event counter in which n events are needed to validate a transition on the output: 0000: no filter, sampling is done at f dts 1000: f sampling =f dts /8, n=6 0001: f sampling =f ck_int , n=2 1001: f sampling =f dts /8, n=8 0010: f sampling =f ck_int , n=4 1010: f sampling =f dts /16, n=5 0011: f sampling =f ck_int , n=8 1011: f sampling =f dts /16, n=6 0100: f sampling =f dts /2, n=6 1100: f sampling =f dts /16, n=8 0101: f sampling =f dts /2, n=8 1101: f sampling =f dts /32, n=5 0110: f sampling =f dts /4, n=6 1110: f sampling =f dts /32, n=6 0111: f sampling =f dts /4, n=8 1111: f sampling =f dts /32, n=8 note: in the current silicon revision, f dts is replaced in the formula by ck_int when icxf[3:0]= 1, 2 or 3. bits 3:2 ic1psc : input capture 1 prescaler this bitfield defines the ratio of the prescaler acting on the cc1 input (ic1). the prescaler is reset as soon as cc1e=?0? (timx_ccer register). 00: no prescaler, capture is done each ti me an edge is detect ed on the capture input 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events bits 1:0 cc1s : capture/compare 1 selection this bitfield defines the direction of the channel (input/output) as well as the used input. 00: cc1 channel is configured as output 01: cc1 channel is configured as input, ic1 is mapped on ti1 10: cc1 channel is configured as input, ic1 is mapped on ti2 11: cc1 channel is configured as input, ic1 is mapped on trc. this mode is working only if an internal trigger input is selected through ts bit (timx_smcr register) note: the cc1s bits are writable only when the channel is off (cc1e = 0 in timx_ccer). RM0033 general-purpose timers (tim9 to tim14) doc id 15403 rev 3 447/1317 15.5.8 tim9/12 capture/compare enable register (timx_ccer) address offset: 0x20 reset value: 0x0000 1514131211109876543210 reserved cc2np res. cc2p cc2e cc1np res. cc1p cc1e rw rw rw rw rw rw bits 15:8 reserved, always read as 0. bit 7 cc2np : capture/compare 2 output polarity refer to cc1np description bits 6 reserved, always read as 0. bit 5 cc2p : capture/compare 2 output polarity refer to cc1p description bit 4 cc2e : capture/compare 2 output enable refer to cc1e description bit 3 cc1np : capture/compare 1 complementary output polarity cc1 channel configured as outpu t: cc1np must be kept cleared cc1 channel configured as input: cc1np is used in conjunction with cc1p to define ti1fp1/ti2fp1 polarity (refer to cc1p description). bits 2 reserved, always read as 0. bit 1 cc1p : capture/compare 1 output polarity . cc1 channel configured as output: 0: oc1 active high. 1: oc1 active low. cc1 channel configured as input: cc1np/cc1p bits select ti1fp1 and ti2fp1 polarity for trigger or capture operations. 00: noninverted/rising edge circuit is sensitive to tixfp1 rising edge (captu re, trigger in reset, external clock or trigger mode), tixfp1 is not inverted (tri gger in gated mode, encoder mode). 01: inverted/falling edge circuit is sensitive to tixfp1 falling edge (captu re, trigger in reset, external clock or trigger mode), tixfp1 is inverted (trigg er in gated mode, encoder mode). 10: reserved, do not use this configuration. note: 11: noninverted/both edges circuit is sensitive to both tixfp1 rising and falling edges (capture, trigger in reset, external clock or trigger mode), tixfp1 is not inverted (trigger in gated mode). this configuration must not be used for encoder mode. bit 0 cc1e : capture/compare 1 output enable . cc1 channel configured as output: 0: off - oc1 is not active. 1: on - oc1 signal is output on the corresponding output pin. cc1 channel configured as input: this bit determines if a capture of the count er value can actually be done into the input capture/compare register 1 (timx_ccr1) or not. 0: capture disabled. 1: capture enabled. general-purpose timers (tim9 to tim14) RM0033 448/1317 doc id 15403 rev 3 note: the states of the external i/o pins connected to the standard ocx channels depend on the state of the ocx channel and on the gpio registers. 15.5.9 tim9/12 counter (timx_cnt) address offset: 0x24 reset value: 0x0000 0000 15.5.10 tim9/12 prescaler (timx_psc) address offset: 0x28 reset value: 0x0000 15.5.11 tim9/12 auto-re load register (timx_arr) address offset: 0x2c reset value: 0x0000 0000 table 64. output control bit for standard ocx channels ccxe bit ocx output state 0 output disabled (ocx=?0?, ocx_en=?0?) 1 ocx=ocxref + polarity, ocx_en=?1? 1514131211109876543210 cnt[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 15:0 cnt[15:0] : counter value 1514131211109876543210 psc[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 15:0 psc[15:0] : prescaler value the counter clock frequency ck_cnt is equal to f ck_psc / (psc[15:0] + 1). psc contains the value to be loaded into the active prescaler register at each update event. 1514131211109876543210 arr[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 15:0 arr[15:0] : auto-reload value arr is the value to be loaded into the actual auto-reload register. refer to the section 15.4.1: time-base unit on page 421 for more details about arr update and behavior. the counter is blocked while the auto-reload value is null. RM0033 general-purpose timers (tim9 to tim14) doc id 15403 rev 3 449/1317 15.5.12 tim9/12 capture/compare register 1 (timx_ccr1) address offset: 0x34 reset value: 0x0000 0000 15.5.13 tim9/12 capture/compare register 2 (timx_ccr2) address offset: 0x38 reset value: 0x0000 0000 15.5.14 tim9/12 register map tim9/12 registers are mapped as 16-bit addressable registers as described in the table below: 1514131211109876543210 ccr1[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 15:0 ccr1[15:0] : capture/compare 1 value if channel cc1 is configured as output : ccr1 is the value to be loaded into the actual capture/compare 1 register (preload value). it is loaded permanently if the preload feature is not selected in the timx_ccmr1 register (oc1pe bit). else the preload value is copied into the active capture/compare 1 register when an update event occurs. the active capture/compare register contains the value to be compared to the timx_cnt counter and signaled on the oc1 output. if channel cc1is configured as input : ccr1 is the counter value transferred by the last input capture 1 event (ic1). 1514131211109876543210 ccr2[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 15:0 ccr2[15:0] : capture/compare 2 value if channel cc2 is configured as output: ccr2 is the value to be loaded into the actual capture/compare 2 register (preload value). it is loaded permanently if the preload feature is not selected in the timx_ccmr2 register (oc2pe bit). else the preload value is copied in to the active capture/compare 2 register when an update event occurs. the active capture/compare register contains the value to be compared to the timx_cnt counter and signalled on the oc2 output. if channel cc2 is configured as input: ccr2 is the counter value transferred by the last input capture 2 event (ic2). table 65. tim9/12 register map and reset values offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 timx_cr1 reserved ckd [1:0] arpe reserved reserved reserved opm urs udis cen reset value 000 0000 general-purpose timers (tim9 to tim14) RM0033 450/1317 doc id 15403 rev 3 refer to table 1 on page 50 for the register boundary addresses. 0x04 timx_cr2 reserved mms[2:0] reserved reset value 000 0x08 timx_smcr reserved msm ts[2:0] reserved sms[2:0] reset value 0000 000 0x0c timx_dier reserved tie reserved reserved reserved cc2ie cc1ie uie reset value 0 000 0x10 timx_sr reserved cc2of cc1of reserved reserved tif reserved reserved reserved cc2if cc1if uif reset value 00 0 000 0x14 timx_egr reserved tg reserved reserved reserved cc2g cc1g ug reset value 0000 0x18 timx_ccmr1 output compare mode reserved oc2m [2:0] oc2pe oc2fe cc2s [1:0] reserved oc1m [2:0] oc1pe oc1fe cc1s [1:0] reset value 0000000 0000000 timx_ccmr1 input capture mode reserved ic2f[3:0] ic2 psc [1:0] cc2s [1:0] ic1f[3:0] ic1 psc [1:0] cc1s [1:0] reset value 0000000000000000 0x1c reserved 0x20 timx_ccer reserved cc2np reserved cc2p cc2e cc1np reserved cc1p cc1e reset value 000000 0x24 timx_cnt reserved cnt[15:0] reset value 0000000000000000 0x28 timx_psc reserved psc[15:0] reset value 0000000000000000 0x2c timx_arr reserved arr[15:0] reset value 0000000000000000 0x30 reserved 0x34 timx_ccr1 reserved ccr1[15:0] reset value 0000000000000000 0x38 timx_ccr2 reserved ccr2[15:0] reset value 0000000000000000 0x3c to 0x4c reserved table 65. tim9/12 register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RM0033 general-purpose timers (tim9 to tim14) doc id 15403 rev 3 451/1317 15.6 tim10/11/13/14 registers 15.6.1 tim10/11/13/14 contro l register 1 (timx_cr1) address offset: 0x00 reset value: 0x0000 15.6.2 tim10/11/13/14 interrupt enable register (timx_dier) address offset: 0x0c 1514131211109876543210 reserved ckd[1:0] arpe reserved urs udis cen rw rw rw rw rw rw bits 15:10 reserved, always read as 0. bits 9:8 ckd : clock division this bit-field indicates the division ratio between the timer clock (ck_int) frequency and sampling clock used by the digital filters (etr, tix), 00: t dts = t ck_int 01: t dts = 2 t ck_int 10: t dts = 4 t ck_int 11: reserved bit 7 arpe : auto-reload preload enable 0: timx_arr register is not buffered 1: timx_arr register is buffered bits 6:3 reserved, always read as 0. bit 2 urs : update request source this bit is set and cleared by software to select the update interrupt (uev) sources. 0: any of the following events generate an uev if enabled: ? counter overflow ? setting the ug bit 1: only counter overflow generates an uev if enabled. bit 1 udis : update disable this bit is set and cleared by software to enable/disable update interrupt (uev) event generation. 0: uev enabled. an uev is generated by one of the following events: ? counter overflow ? setting the ug bit. buffered registers are then loaded with their preload values. 1: uev disabled. no uev is generated, shadow registers keep their value (arr, psc, ccrx). the counter and the prescaler ar e reinitialized if the ug bit is set. bit 0 cen : counter enable 0: counter disabled 1: counter enabled general-purpose timers (tim9 to tim14) RM0033 452/1317 doc id 15403 rev 3 reset value: 0x0000 15.6.3 tim10/11/13/14 st atus register (timx_sr) address offset: 0x10 reset value: 0x0000 1514131211109876543210 reserved cc1ie uie rw rw bits 15:2 reserved, always read as 0. bit 1 cc1ie : capture/compare 1 interrupt enable 0: cc1 interrupt disabled 1: cc1 interrupt enabled bit 0 uie : update interrupt enable 0: update interrupt disabled 1: update interrupt enabled 1514131211109876543210 reserved cc1of reserved cc1if uif rc_w0 rc_w0 rc_w0 bit 15:10 reserved, always read as 0. bit 9 cc1of : capture/compare 1 overcapture flag this flag is set by hardware only when the corresponding channel is configured in input capture mode. it is cleared by software by writing it to ?0?. 0: no overcapture has been detected. 1: the counter value has been captured in timx_ccr1 register while cc1if flag was already set bits 8:2 reserved, always read as 0. bit 1 cc1if : capture/compare 1 interrupt flag if channel cc1 is configured as output: this flag is set by hardware when the counter matches the compare value. it is cleared by software. 0: no match. 1: the content of the counter timx_cnt matches the conten t of the timx_ccr1 register. when the contents of timx_ccr1 are greater t han the contents of ti mx_arr, the cc1if bit goes high on the counter overflow. if channel cc1 is configured as input: this bit is set by hardware on a capture. it is cleared by software or by reading the timx_ccr1 register. 0: no input capture occurred. 1: the counter value has been captured in ti mx_ccr1 register (an edge has been detected on ic1 which matches the selected polarity). RM0033 general-purpose timers (tim9 to tim14) doc id 15403 rev 3 453/1317 15.6.4 tim10/11/13/14 event ge neration register (timx_egr) address offset: 0x14 reset value: 0x0000 bit 0 uif : update interrupt flag this bit is set by hardware on an update event. it is cleared by software. 0: no update occurred. 1: update interrupt pending. this bit is set by hardware when the registers are updated: ? at overflow and if udis=?0? in the timx_cr1 register. ? when cnt is reinitialized by software using the ug bit in timx_egr register, if urs=?0? and udis=?0? in the timx_cr1 register. 1514131211109876543210 reserved cc1g ug ww bits 15:2 reserved, always read as 0. bit 1 cc1g : capture/compare 1 generation this bit is set by software in order to ge nerate an event, it is automatically cleared by hardware. 0: no action 1: a capture/compare event is generated on channel 1: if channel cc1 is configured as output: cc1if flag is set, corresponding interrupt or is sent if enabled. if channel cc1 is configured as input: the current value of the counter is captured in timx_ccr1 register. the cc1if flag is set, the corresponding interrupt is sent if enabled. the cc1of flag is set if the cc1if flag was already high. bit 0 ug : update generation this bit can be set by software, it is automatically cleared by hardware. 0: no action 1: re-initialize the counter and generates an up date of the registers. note that the prescaler counter is cleared too (anyway the prescaler ra tio is not affected). the counter is cleared. general-purpose timers (tim9 to tim14) RM0033 454/1317 doc id 15403 rev 3 15.6.5 tim10/11/13/14 captur e/compare mode register 1 (timx_ccmr1) address offset: 0x18 reset value: 0x0000 the channels can be used in input (capture mode) or in output (compare mode). the direction of a channel is defined by configuring the corresponding ccxs bits. all the other bits of this register have a different function in input and in output mode. for a given bit, ocxx describes its function when the channel is configured in output, icxx describes its function when the channel is configured in input. so you must take care that the same bit can have a different meaning for the input stage and for the output stage. output compare mode 1514131211109876543210 reserved oc1m[2:0] oc1pe oc1fe cc1s[1:0] reserved ic1f[3:0] ic1psc[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 15:7 reserved bits 6:4 oc1m : output compare 1 mode these bits define the behavior of the output reference signal oc1ref from which oc1 is derived. oc1ref is active high whereas oc1 active level depends on cc1p bit. 000: frozen. the comparison between the output compare regist er timx_ccr1 and the counter timx_cnt has no effect on the outputs. 001: set channel 1 to active level on match. oc1ref signal is forced high when the counter timx_cnt matches the capture/co mpare register 1 (timx_ccr1). 010: set channel 1 to inactive level on match. oc1ref signal is forced low when the counter timx_cnt matches the captur e/compare register 1 (timx_ccr1). 011: toggle - oc1ref toggles when timx_cnt = timx_ccr1. 100: force inactive level - oc1ref is forced low. 101: force active level - oc1ref is forced high. 110: pwm mode 1 - channel 1 is active as long as timx_cnt < timx_ccr1 else inactive. 111: pwm mode 2 - channel 1 is inactive as long as timx_cnt < timx_ccr1 else active. note: in pwm mode 1 or 2, the ocref level c hanges when the result of the comparison changes or when the output compare mode switches from frozen to pwm mode. bit 3 oc1pe : output compare 1 preload enable 0: preload register on timx_ccr1 disabled . timx_ccr1 can be written at anytime, the new value is taken in account immediately. 1: preload register on timx_ccr1 enabled. read/write operations access the preload register. timx_ccr1 preload value is loaded in the active register at each update event. note: the pwm mode can be used without validating the preload register only in one pulse mode (opm bit set in timx_cr1 register). else the behavior is not guaranteed. RM0033 general-purpose timers (tim9 to tim14) doc id 15403 rev 3 455/1317 input capture mode bit 2 oc1fe : output compare 1 fast enable this bit is used to accelerate the effect of an event on the trigger in input on the cc output. 0: cc1 behaves normally depending on counter and ccr1 values even when the trigger is on. the minimum delay to activate cc1 output when an edge occurs on the trigger input is 5 clock cycles. 1: an active edge on the trigger input acts like a compare match on cc1 output. oc is then set to the compare level independently of the result of the comparison. delay to sample the trigger input and to activate cc1 output is reduced to 3 clock cycles. oc1fe acts only if the channel is configured in pwm1 or pwm2 mode. bits 1:0 cc1s : capture/compare 1 selection this bit-field defines the direction of the ch annel (input/output) as well as the used input. 00: cc1 channel is configured as output. 01: cc1 channel is configured as input, ic1 is mapped on ti1. 10: reserved 11: reserved note: cc1s bits are writable only when the channel is off (cc1e = 0 in timx_ccer). bits 15:8 reserved bits 7:4 ic1f : input capt ure 1 filter this bit-field defines the frequency used to sample ti1 input and the length of the digital filter applied to ti1. the digital filter is made of an event counter in which n events are needed to validate a transition on the output: 0000: no filter, sampling is done at f dts 1000: f sampling =f dts /8, n=6 0001: f sampling =f ck_int , n=2 1001: f sampling =f dts /8, n=8 0010: f sampling =f ck_int , n=4 1010: f sampling =f dts /16, n=5 0011: f sampling =f ck_int , n=8 1011: f sampling =f dts /16, n=6 0100: f sampling =f dts /2, n=6 1100: f sampling =f dts /16, n=8 0101: f sampling =f dts /2, n=8 1101: f sampling =f dts /32, n=5 0110: f sampling =f dts /4, n=6 1110: f sampling =f dts /32, n=6 0111: f sampling =f dts /4, n=8 1111: f sampling =f dts /32, n=8 note: in current silicon revision, f dts is replaced in the formula by ck_int when icxf[3:0]= 1, 2 or 3. bits 3:2 ic1psc : input capture 1 prescaler this bit-field defines the ratio of the prescaler acting on cc1 input (ic1). the prescaler is reset as soon as cc1e=?0? (timx_ccer register). 00: no prescaler, capture is done each time an edge is detected on the capture input 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events bits 1:0 cc1s : capture/compare 1 selection this bit-field defines the direction of the c hannel (input/output) as well as the used input. 00: cc1 channel is configured as output 01: cc1 channel is configured as input, ic1 is mapped on ti1 10: reserved 11: reserved note: cc1s bits are writable only when the channel is off (cc1e = 0 in timx_ccer). general-purpose timers (tim9 to tim14) RM0033 456/1317 doc id 15403 rev 3 15.6.6 tim10/11/13/14 capt ure/compare enable register (timx_ccer) address offset: 0x20 reset value: 0x0000 note: the state of the external i/o pins connected to the standard ocx channels depends on the ocx channel state and the gpio registers. 1514131211109876543210 reserved cc1np res. cc1p cc1e rw rw rw bits 15:4 reserved, always read as 0. bit 3 cc1np : capture/compare 1 comple mentary output polarity. cc1 channel configured as output : cc1np must be kept cleared. cc1 channel configured as input: cc1np bit is used in conjunction with cc1p to define ti1fp1 polarity (refer to cc1p description). bit 2 reserved, always read as 0. bit 1 cc1p : capture/compare 1 output polarity. cc1 channel configured as output: 0: oc1 active high 1: oc1 active low cc1 channel configured as input: the cc1p bit selects ti1fp1 and ti2fp1 polarity for trigger or capture operations. 00: noninverted/rising edge circuit is sensitive to ti1fp1 rising edge (capture mode), ti1fp1 is not inverted. 01: inverted/falling edge circuit is sensitive to ti1fp1 falling edge (capture mode), ti1fp1 is inverted. 10: reserved, do not use this configuration. 11: noninverted/both edges circuit is sensitive to both ti1fp1 rising and falling edges (capture mode), ti1fp1 is not inverted. bit 0 cc1e : capture/compare 1 output enable. cc1 channel configured as output: 0: off - oc1 is not active 1: on - oc1 signal is output on the corresponding output pin cc1 channel configured as input: this bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (timx_ccr1) or not. 0: capture disabled 1: capture enabled table 66. output control bit for standard ocx channels ccxe bit ocx output state 0 output disabled (ocx=?0?, ocx_en=?0?) 1 ocx=ocxref + polarity, ocx_en=?1? RM0033 general-purpose timers (tim9 to tim14) doc id 15403 rev 3 457/1317 15.6.7 tim10/11/13/14 counter (timx_cnt) address offset: 0x24 reset value: 0x0000 15.6.8 tim10/11/13/14 prescaler (timx_psc) address offset: 0x28 reset value: 0x0000 15.6.9 tim10/11/13/14 auto-r eload register (timx_arr) address offset: 0x2c reset value: 0x0000 1514131211109876543210 cnt[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 15:0 cnt[15:0] : counter value 1514131211109876543210 psc[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 15:0 psc[15:0] : prescaler value the counter clock frequency ck_cnt is equal to f ck_psc / (psc[15:0] + 1). psc contains the value to be loaded in the ac tive prescaler register at each update event. 1514131211109876543210 arr[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 15:0 arr[15:0] : auto-reload value arr is the value to be loaded in the actual auto-reload register. refer to the section 15.4.1: time-base unit on page 421 for more details about arr update and behavior. the counter is blocked while the auto-reload value is null. general-purpose timers (tim9 to tim14) RM0033 458/1317 doc id 15403 rev 3 15.6.10 tim10/11/13/14 capture/ compare register 1 (timx_ccr1) address offset: 0x34 reset value: 0x0000 15.6.11 tim11 option r egister 1 (tim11_or) address offset: 0x50 reset value: 0x0000 15.6.12 tim10/11/13/14 register map timx registers are mapped as 16-bit addressable registers as described in the tables below: 1514131211109876543210 ccr1[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 15:0 ccr1[15:0] : capture/compare 1 value if channel cc1 is configured as output : ccr1 is the value to be loaded in the actual capture/compare 1 register (preload value). it is loaded permanently if the preload feature is not selected in the timx_ccmr1 register (bit oc1pe). else the preload value is copied in the active capture/compare 1 register when an update event occurs. the active capture/compare register contains the value to be compared to the counter timx_cnt and signaled on oc1 output. if channel cc1is configured as input : ccr1 is the counter value transferred by the last input capture 1 event (ic1). 1514131211109876543210 reserved ti1_rmp rw bits 15:2 reserved bits 1:0 ti1_rmp : tim11 input 1 remapping capability set and cleared by software. 00,01,11: tim11 channel1 is co nnected to the gpio (refer to the alternate function mapping table in the datasheets). 10: hse_rtc clock (hse divided by programmable prescaler) is connected to the tim11_ch1 input for measurement purposes table 67. tim10/11/13/14 register map and reset values offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 timx_cr1 reserved ckd [1:0] arpe reserved reserved reserved reserved urs udis cen reset value 000 000 0x08 timx_smcr not available reset value RM0033 general-purpose timers (tim9 to tim14) doc id 15403 rev 3 459/1317 refer to table 1 on page 50 for the register boundary addresses. 0x0c timx_dier reserved cc1ie uie reset value 00 0x10 timx_sr reserved cc1of reserved cc1if uif reset value 000 0x14 timx_egr reserved cc1g ug reset value 00 0x18 timx_ccmr1 output compare mode reserved oc1m [2:0] oc1pe oc1fe cc1s [1:0] reset value 0000000 timx_ccmr1 input capture mode reserved ic1f[3:0] ic1 psc [1:0] cc1s [1:0] reset value 00000000 0x1c reserved 0x20 timx_ccer reserved reserved reserved reserved reserved reserved reserved reserved cc1np reserved cc1p cc1e reset value 000 0x24 timx_cnt reserved cnt[15:0] reset value 0000000000000000 0x28 timx_psc reserved psc[15:0] reset value 0000000000000000 0x2c timx_arr reserved arr[15:0] reset value 0000000000000000 0x30 reserved 0x34 timx_ccr1 reserved ccr1[15:0] reset value 0000000000000000 0x38 to 0x4c reserved 0x50 tim11_or reserved ti1_rmp reset value 00 table 67. tim10/11/13/14 register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 basic timers (tim6&tim7) RM0033 460/1317 doc id 15403 rev 3 16 basic timers (tim6&tim7) 16.1 tim6&tim7 introduction the basic timers tim6 and tim7 consist of a 16-bit auto-reload counter driven by a programmable prescaler. they may be used as generic timers for time-base generation but they are also specifically used to drive the digital-to-analog converter (dac). in fact, the timers are internally connected to the dac and are able to drive it through their trigger outputs. the timers are completely independent, and do not share any resources. 16.2 tim6&tim7 main features basic timer (tim6&tim7) features include: 16-bit auto-reload upcounter 16-bit programmable prescaler used to divide (also ?on the fly?) the counter clock frequency by any factor between 1 and 65535 synchronization circuit to trigger the dac interrupt/dma generation on the update event: counter overflow figure 182. basic timer block diagram u trigger controller stop, clear or up trgo u ui reset, enable, count, event preload registers transferred to active registers on u event according to control bit interrupt & dma output to dac counter ck_psc cnt ck_cnt controller internal clock (ck_int) timxclk from rcc prescaler psc auto-reload register flag ai14749b RM0033 basic timers (tim6&tim7) doc id 15403 rev 3 461/1317 16.3 tim6&tim7 functional description 16.3.1 time-base unit the main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. the counter clock can be divided by a prescaler. the counter, the auto-reload register and the prescaler register can be written or read by software. this is true even when the counter is running. the time-base unit includes: counter register (timx_cnt) prescaler register (timx_psc) auto-reload register (timx_arr) the auto-reload register is preloaded. the preload register is accessed each time an attempt is made to write or read the auto-reload register. the contents of the preload register are transferred into the shadow register permanently or at each update event uev, depending on the auto-reload preload enable bit (arpe) in the timx_cr1 register. the update event is sent when the counter reaches the overflow value and if the udis bit equals 0 in the timx_cr1 register. it can also be generated by software. the generation of the update event is described in detail for each configuration. the counter is clocked by the prescaler output ck_cnt, which is enabled only when the counter enable bit (cen) in the timx_cr1 register is set. note that the actual counter enable signal cnt_en is set 1 clock cycle after cen. prescaler description the prescaler can divide the counter clock frequency by any factor between 1 and 65536. it is based on a 16-bit counter controlled through a 16-bit register (in the timx_psc register). it can be changed on the fly as the timx_psc control register is buffered. the new prescaler ratio is taken into account at the next update event. figure 183 and figure 184 give some examples of the counter behavior when the prescaler ratio is changed on the fly. basic timers (tim6&tim7) RM0033 462/1317 doc id 15403 rev 3 figure 183. counter timing diagram with prescaler division change from 1 to 2 figure 184. counter timing diagram with prescaler division change from 1 to 4 16.3.2 counting mode the counter counts from 0 to the auto-reload value (contents of the timx_arr register), then restarts from 0 and generates a counter overflow event. an update event can be generate at each counter overflow or by setting the ug bit in the timx_egr register (by software or by using the slave mode controller). the uev event can be disabled by software by setting the udis bit in the timx_cr1 register. this avoids updating the shadow registers while writing new values into the preload registers. in this way, no update event occurs until the udis bit has been written to 0, however, the counter and the prescaler counter both restart from 0 (but the prescale rate does not change). in addition, if the urs (update request selection) bit in the timx_cr1 ck_psc 00 cnt_en timer clock = ck_cnt counter register update event (uev) 0 f9 fa fb fc f7 prescaler control register 01 write a new value in timx_psc 01 02 03 prescaler buffer 01 prescaler counter 0 1 0 1 0 1 0 1 f8 ck_psc 00 cnt_en timer clock = ck_cnt counter register update event (uev) 0 f9 fa fb fc f7 prescaler control register 03 write a new value in timx_psc prescaler buffer 03 prescaler counter 0 1 2 3 0 1 2 3 f8 01 RM0033 basic timers (tim6&tim7) doc id 15403 rev 3 463/1317 register is set, setting the ug bit generates an update event uev, but the uif flag is not set (so no interrupt or dma request is sent). when an update event occurs, all the registers are updated and the update flag (uif bit in the timx_sr register) is set (depending on the urs bit): the buffer of the prescaler is reloaded with the preload value (contents of the timx_psc register) the auto-reload shadow register is updated with the preload value (timx_arr) the following figures show some examples of the counter behavior for different clock frequencies when timx_arr = 0x36. figure 185. counter timing diagra m, internal clock divided by 1 figure 186. counter timing diagra m, internal clock divided by 2 ck_int 00 cnt_en timer clock = ck_cnt counter register update interrupt flag (uif) counter overflow update event (uev) 01 02 03 04 05 06 07 32 33 34 35 36 31 ck_int 0035 0000 0001 0002 0003 cnt_en timer clock = ck_cnt counter register update interrupt flag (uif) 0034 0036 counter overflow update event (uev) basic timers (tim6&tim7) RM0033 464/1317 doc id 15403 rev 3 figure 187. counter timing diagra m, internal clock divided by 4 figure 188. counter timing diagra m, internal clock divided by n figure 189. counter timing diagram, update event when arpe = 0 (timx_arr not preloaded) 0000 0001 cnt_en timer clock = ck_cnt counter register update interrupt flag (uif) 0035 0036 counter overflow update event (uev) ck_int timer clock = ck_cnt counter register 00 1f 20 update interrupt flag (uif) counter overflow update event (uev) ck_int 00 cnt_en timer clock = ck_cnt counter register update interrupt flag (uif) counter overflow update event (uev) 01 02 03 04 05 06 07 32 33 34 35 36 31 auto-reload register ff 36 write a new value in timx_arr ck_int RM0033 basic timers (tim6&tim7) doc id 15403 rev 3 465/1317 figure 190. counter timing diagram, update event when arpe=1 (timx_arr preloaded) 16.3.3 clock source the counter clock is provided by the internal clock (ck_int) source. the cen (in the timx_cr1 register) and ug bi ts (in the timx_egr register) are actual control bits and can be changed only by software (except for ug that remains cleared automatically). as soon as the cen bit is written to 1, the prescaler is clocked by the internal clock ck_int. figure 191 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler. figure 191. control circuit in normal mode, internal clock divided by 1 16.3.4 debug mode when the microcontroller enters the debug mode (cortex-m3 core - halted), the timx counter either continues to work normally or stops, depending on the dbg_timx_stop configuration bit in the dbg modu le. for more details, refer to section 32.16.2: debug support for timers, watchdog, bxcan and i 2 c . 00 cnt_en timer clock = ck_cnt counter register update interrupt flag (uif) counter overflow update event (uev) 01 02 03 04 05 06 07 f1 f2 f3 f4 f5 f0 auto-reload preload register f5 36 auto-reload shadow register f5 36 write a new value in timx_arr ck_psc ck_int 00 counter clock = ck_cnt = ck_psc counter register 01 02 03 04 05 06 07 32 33 34 35 36 31 cen=cnt_en ug cnt_init basic timers (tim6&tim7) RM0033 466/1317 doc id 15403 rev 3 16.4 tim6&tim7 registers refer to section 1.1 on page 46 for a list of abbreviations used in register descriptions. the peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 16.4.1 tim6&tim7 control register 1 (timx_cr1) address offset: 0x00 reset value: 0x0000 1514131211109876543210 reserved arpe reserved opm urs udis cen rw rw rw rw rw bits 15:8 reserved, always read as 0 bit 7 arpe : auto-reload preload enable 0: timx_arr register is not buffered. 1: timx_arr register is buffered. bits 6:4 reserved, always read as 0 bit 3 opm : one-pulse mode 0: counter is not stopped at update event 1: counter stops counting at the next update event (clearing the cen bit). bit 2 urs : update request source this bit is set and cleared by software to select the uev event sources. 0: any of the following events generates an update interrupt or dma request if enabled. these events can be: ? counter overflow/underflow ? setting the ug bit ? update generation through the slave mode controller 1: only counter overflow/underflow generates an update interrupt or dma request if enabled. bit 1 udis : update disable this bit is set and cleared by software to enable/disable uev event generation. 0: uev enabled. the update (uev) event is generated by one of the following events: ? counter overflow/underflow ? setting the ug bit ? update generation through the slave mode controller buffered registers are then loaded with their preload values. 1: uev disabled. the update event is not generated, shadow registers keep their value (arr, psc). however the counter and the prescaler are reinitialized if the ug bit is set or if a hardware reset is received from the slave mode controller. bit 0 cen : counter enable 0: counter disabled 1: counter enabled note: gated mode can work only if the cen bit has been previously set by software. however trigger mode can set the cen bit automatically by hardware. cen is cleared automatically in one-pulse mode, when an update event occurs. RM0033 basic timers (tim6&tim7) doc id 15403 rev 3 467/1317 16.4.2 tim6&tim7 control register 2 (timx_cr2) address offset: 0x04 reset value: 0x0000 16.4.3 tim6&tim7 dma/interrupt enable register (timx_dier) address offset: 0x0c reset value: 0x0000 1514131211109876543210 reserved mms[2:0] reserved rw rw rw bits 15:7 reserved, always read as 0. bits 6:4 mms : master mode selection these bits are used to select the information to be sent in master mode to slave timers for synchronization (trgo). the co mbination is as follows: 000: reset - the ug bit from the timx_egr register is used as a trigger output (trgo). if reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on trgo is delayed compared to the actual reset. 001: enable - the counter enable signal, cnt_en, is us ed as a trigger output (trgo). it is useful to start several timers at the same time or to control a window in which a slave timer is enabled. the counter enable signal is generated by a logic or between cen control bit and the trigger input when configured in gated mode. when the counter enable signal is controlled by the trigger input, there is a delay on trgo, except if the master/slave m ode is selected (see the msm bit description in the timx_smcr register). 010: update - the update event is selected as a tr igger output (trgo). for instance a master timer can then be used as a prescaler for a slave timer. bits 3:0 reserved, always read as 0 1514131211109876543210 reserved ude reserved uie rw rw bit 15:9 reserved, always read as 0. bit 8 ude : update dma request enable 0: update dma request disabled. 1: update dma request enabled. bit 7:1 reserved, always read as 0. bit 0 uie : update interrupt enable 0: update interrupt disabled. 1: update interrupt enabled. basic timers (tim6&tim7) RM0033 468/1317 doc id 15403 rev 3 16.4.4 tim6&tim7 stat us register (timx_sr) address offset: 0x10 reset value: 0x0000 16.4.5 tim6&tim7 event gene ration register (timx_egr) address offset: 0x14 reset value: 0x0000 16.4.6 tim6&tim7 counter (timx_cnt) address offset: 0x24 reset value: 0x0000 1514131211109876543210 reserved uif rc_w0 bits 15:1 reserved, always read as 0. bit 0 uif : update interrupt flag this bit is set by hardware on an update event. it is cleared by software. 0: no update occurred. 1: update interrupt pending. this bit is se t by hardware when the registers are updated: ?at overflow or underflow regarding the repetit ion counter value and if udis = 0 in the timx_cr1 register. ?when cnt is reinitialized by software usi ng the ug bit in the timx_egr register, if urs = 0 and udis = 0 in the timx_cr1 register. 1514131211109876543210 reserved ug w bits 15:1 reserved, always read as 0. bit 0 ug : update generation this bit can be set by software, it is automatically cleared by hardware. 0: no action. 1: re-initializes the timer counter and generates an update of the registers. note that the prescaler counter is cleared too (but the prescaler ratio is not affected). 1514131211109876543210 cnt[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 15:0 cnt[15:0] : counter value RM0033 basic timers (tim6&tim7) doc id 15403 rev 3 469/1317 16.4.7 tim6&tim7 pr escaler (timx_psc) address offset: 0x28 reset value: 0x0000 16.4.8 tim6&tim7 auto-rel oad register (timx_arr) address offset: 0x2c reset value: 0x0000 1514131211109876543210 psc[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 15:0 psc[15:0] : prescaler value the counter clock frequency ck_cnt is equal to f ck_psc / (psc[15:0] + 1). psc contains the value to be loaded into the ac tive prescaler register at each update event. 1514131211109876543210 arr[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 15:0 arr[15:0] : prescaler value arr is the value to be loaded into the actual auto-reload register. refer to section 16.3.1: time-base unit on page 461 for more details about arr update and behavior. the counter is blocked while the auto-reload value is null. basic timers (tim6&tim7) RM0033 470/1317 doc id 15403 rev 3 16.4.9 tim6&tim7 register map timx registers are mapped as 16-bit addressable registers as described in the table below: refer to table 1 on page 50 for the register boundary addresses. table 68. tim6&tim7 register map and reset values offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 timx_cr1 reserved arpe reserved opm urs udis cen reset value 00000 0x04 timx_cr2 reserved mms[2:0] reserved reset value 000 0x08 reserved 0x0c timx_dier reserved ude reserved uie reset value 00 0x10 timx_sr reserved uif reset value 0 0x14 timx_egr reserved ug reset value 0 0x18 reserved 0x1c reserved 0x20 reserved 0x24 timx_cnt reserved cnt[15:0] reset value 0000000000000000 0x28 timx_psc reserved psc[15:0] reset value 0000000000000000 0x2c timx_arr reserved arr[15:0] reset value 0000000000000000 RM0033 independent watchdog (iwdg) doc id 15403 rev 3 471/1317 17 independent watc hdog (iwdg) 17.1 iwdg intr oduction th e stm3 2f2 0 x a n d stm 32f 21x ha v e tw o em bed ded w a t c h d o g per i phe r a ls wh ich of f e r a combination of high saf e ty le v e l, ti ming ac cur a cy and fle xibility of use . both w a tc hdog p e r i ph er a l s ( i n d e pen den t a nd wind o w ) ser v e t o det e c t and r e solv e m a lf un ct ion s du e t o sof t w ar e f a ilur e , a nd t o tr i gge r syst em r e set o r an in t e rr u p t (wind o w w a tchd og o n ly) when t h e cou n t e r rea ches a giv e n t i me ou t v a lu e . th e ind epe nd ent w a t chdo g (i wdg) is clo c k e d b y it s o w n d edicat e d lo w- sp ee d clo c k ( l si ) a nd t h u s sta y s act i v e e v en if the main clo c k f a ils . the win do w w a t c h dog ( w wdg ) cloc k is prescaled from the apb1 cloc k and has a configur ab le time-windo w that can be p r o g r a mm ed t o de te ct ab nor mally lat e or e a r l y app licat ion be ha vior . the iw dg is best suited to applic ations w h ic h re qu ire t h e w a t ch d o g to r u n as a to ta lly in dep en den t pr ocess out side t h e m a in ap plicat ion , b u t ha v e lo w e r timi ng accur a cy co ns tr ain t s . th e wwd g is b e s t s u it ed to a p p lic at ions wh ich re quir e t he w a tchd og t o r eact wit hin a n accu r a t e t i ming win d o w . f o r f u r t h e r in f o r m at ion on t h e win d o w w a t c h d o g , r e f e r to se ct ion 1 8 on p age 4 7 6 . 17.2 iwdg main f e atures f r e e -r u n n i ng do wnco unt er cloc k e d from an independent rc osc illator (c an oper a te in standb y an d stop modes) re se t (if w a tc hd og a ct i v a t e d ) wh en th e d o wn co un te r v a lu e of 0 x00 0 is re ac he d 17.3 iwdg functional description fig u r e 19 2 sh o w s th e f unct i on al b l o c ks of th e ind epe nde nt w a t chdo g mod u le . when the independent w a tc hdog is s t ar ted b y wr iting the v a lue 0xc ccc in the k e y register ( i wdg_ kr) , t h e cou n t e r st ar t s cou n t i ng d o wn f r om t he r e set v a lue of 0xfff . when it r e a c h e s t h e end o f cou n t v a lue ( 0 x000 ) a r e set sig nal is gen er a t e d (i wdg rese t) . whene v er the k e y v a lue 0xaaaa is wr itten in the iwdg_kr register , the iwdg_rlr v a lue is re load ed in t h e cou n t e r and t h e w a t chdo g re se t is pre v ent e d . 17.3.1 har d ware watc hdog i f t h e ? h ar dw a r e w a tch dog ? f eat ur e is e n a b le d th ro ug h th e de vice op tio n bit s , th e w a t chd og is automatically enab le d at po w e r-on, and will gener ate a reset unless the k e y regis t er is wr it te n b y t he sof t w ar e be f o re t h e cou n t e r r e a c h e s end o f cou n t . independent watchdog (iwdg) RM0033 472/1317 doc id 15403 rev 3 17.3.2 register access pr otection wr it e access t o t he i w dg _pr a nd i w dg _rlr reg i ste r s is pr ot ect ed. t o mo dif y t h e m , y o u m u st fir s t wr ite t h e co de 0 x 5 555 in th e iwdg_ k r re gist er . a wr ite a c ce ss to t h is re gist er with a diff erent v a lue will break the sequenc e and regis t er ac c e s s will be protected again. this implies that it is the case of the reload oper ation (wr i ting 0xaaaa). a st at u s re giste r is a v aila b l e t o ind i ca te t h a t an u pda te o f t he pr escaler o r t he do wn- c o u n t e r r e lo ad v a lu e is o n goin g . 17.3.3 deb u g mode whe n t he micro c ont r o ller ent er s d e b u g mo de ( c or te x-m3 cor e ha lt ed) , t h e i w dg co unt e r e i th er con t in ues to w o r k nor mally or st op s , d epe ndin g on dbg_ iwdg_ s t o p co nf igur at ion bit in dbg module . f o r more details , ref e r to sect ion 3 2 . 16. 2: de b ug supp or t f o r tim e r s , w a t c h dog, b x can a nd i 2 c . figu re 19 2. inde pen d ent wat c hdo g b l oc k dia g r a m not e : t h e w a tchd og f u n c t i on is imp l eme n t ed in t h e v dd v o ltage domain that is still func tional in st op a nd st and b y mo des . 17.4 iwdg register s ref e r to se ct ion 1 . 1 on p age 4 6 f o r a list o f ab b r e v ia t i ons used in r e g i st er descr ipt i on s . iwdg reset prescaler 12-bit downcounte r iw dg _ p r presca ler regist er iwdg_ r lr r e load register 8-bit lsi iwdg_kr key register 1 . 2 v v o lt ag e do main v dd voltage domain iwdg_sr statu s register 1 2 -bit reload value t a b l e 69 . m in/ m ax iwdg ti meou t pe rio d at 3 2 khz ( l si) (1) 1. th ese timing s are given for a 32 kh z clock b u t the mi crocontro ller?s intern al rc frequency can va ry from 30 to 60 khz. moreover, given an exac t rc oscillator frequency, the exac t timings still depend on the ph asing of the apb interface clock versus the lsi clock so that there is always a full rc period of uncertainty. pres caler div i der p r[2:0 ] bits min timeout (ms) rl[11:0] = 0 x00 0 max timeout (ms) rl[ 1 1:0]= 0xfff /4 0 0 .12 5 512 /8 1 0 .25 1024 /16 2 0.5 204 8 /32 3 1 409 6 /64 4 2 819 2 /1 28 5 4 1 6384 /2 56 6 8 3 2768 RM0033 independent watchdog (iwdg) doc id 15403 rev 3 473/1317 17.4.1 k e y register (iwdg_kr) ad dre s s of f s e t : 0x00 reset v a lue : 0 x 0 000 000 0 (r eset b y sta ndb y mod e ) 31 30 2 9 28 27 26 25 24 23 2 2 21 20 1 9 18 17 16 15 14 13 1 2 11 10 9 8 7 6 5 4 3 2 1 0 reser v ed k ey[ 15: 0] ww wwww w w w w w w w w w w bi ts 31:16 re se r v e d , rea d as 0 . bits 15: 0 key[15: 0 ]: k e y v a l ue (wr i te onl y , read 0 000h ) these bits m u st be wr itten b y softw a re at regul ar inter v als with the k e y v a lue aaaa h, otherwi se the w a tchd og gen er a t e s a reset when the cou n ter re aches 0. wr i t i ng th e k e y v a lue 5 555h to en ab le a c ce ss to th e iw dg_ p r a nd iw dg_rlr regi ste r s (see se cti o n 1 7. 3. 2 ) wr i t i ng th e k e y v a lu e c ccch star ts the w a tchdo g (e xcep t if the h a rdw a re w a tchdo g option i s selected) independent watchdog (iwdg) RM0033 474/1317 doc id 15403 rev 3 17.4.2 prescaler register (iwdg_pr) ad dre s s of f s e t : 0x04 reset v a lue : 0 x 0 000 000 0 17.4.3 reload register (iwdg_rlr) ad dre s s of f s e t : 0x08 reset v a lue : 0 x 0 000 0fff ( r e s e t b y st an db y mo de) 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 765432 1 0 reser v ed pr [2 :0 ] r w rw rw bi ts 31:3 r eser v e d , read a s 0. bits 2:0 pr[2:0]: pr escaler divider t h ese b i ts ar e w r i t e acce ss pr ot ect e d see se cti o n 1 7. 3. 2 . th e y a r e wr it te n b y so ft w a re t o se lect the pre s ca ler di vider f e edin g the cou n ter cloc k. pvu bit of iwdg_sr m u st be reset in order to b e ab le to chan ge the prescal e r d i vide r . 000: divid e r /4 001: divid e r /8 010: divid e r /16 011: divid e r /32 100: divid e r /64 101: divid e r /12 8 110: divid e r /25 6 111: divid e r /25 6 note: r e adi ng th is re gister re tu r n s the presca ler v a lu e from th e vdd v o ltage d o main . th is v a lue ma y n o t be u p to da te /v a lid if a wr i t e ope r a tion to this reg iste r is on goin g . f o r this rea s on the v a lu e read from thi s reg i ste r is v a lid on ly w hen the pvu bit i n th e iw dg_ s r register is reset. 31 30 2 9 28 27 26 25 24 23 2 2 21 20 1 9 18 17 16 15 14 13 1 2 11 10 9 8 7 6 5 4 3 2 1 0 reser v e d rl[1 1: 0] rw rw rw rw rw r w rw rw rw rw rw rw bi ts 31:12 rese r v ed , rea d a s 0 . bi ts11 :0 rl[11:0]: w a tchd og coun ter relo ad v a l ue th ese bits a r e wr ite access p r otecte d see section 1 7.3.2 . the y a r e w r itte n b y softw are to defin e the v a lue to be lo aded i n the w a tchd og coun te r ea ch time the v a l ue aaaah is wr itten in the iw dg_kr re gister . th e w a tch dog cou n te r cou n ts d o wn from this v a lu e . th e ti me out per i od is a fu ncti on of thi s v a lue an d th e cl oc k p r escaler . re f e r to ta b l e 6 9 . th e r v u bit in the iw dg_ s r register m u st be reset in o r d e r to be a b le to ch ang e th e relo ad va l u e . note: reading this register returns the reload value from the vdd voltage domain. this value may not be up to date/valid if a write operation to this register is ongoing on this register. for this reason the value read from this register is valid only when the rvu bit in the iwdg_sr register is reset. RM0033 independent watchdog (iwdg) doc id 15403 rev 3 475/1317 17.4.4 status register (iwdg_sr) ad dre s s of f s e t : 0x0c re se t v a lu e: 0x 00 0 0 0 0 0 0 ( n o t re se t b y st an db y m o de ) not e : i f se v e r a l re loa d v a lue s o r pr esca ler v a lues ar e used b y a p p lica t io n, it is m and at or y t o w a it u n t il r v u bit is r e set b e f o r e ch an ging t h e re load v a lue an d t o w a it unt il pvu bit is r e set b e f o r e ch an ging t h e pre sca ler v a lu e . ho w e v e r , af t e r u pda t i ng t he p r escale r an d/ or t h e r e lo ad v a lu e it is not nece s sar y t o w a it un til r v u or pvu is re se t b e f o r e co nt in uin g co de e x e c u t i on (e v en in case o f lo w-po w e r m ode e n t r y , t h e wr it e op er a t io n is t a k e n int o accoun t and will c o mplete) 17.4.5 iwdg register map th e f o llo wing t a b l e giv e s t he i w dg r e g i st er map a n d r e set v a lue s . ref e r to t a b l e 1 on p age 50 f o r t h e r e g i st er bou nd ar y ad dr esse s . 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 76 5432 1 0 reser v ed rv u p v u rr bits 31:2 r eser v e d bit 1 rv u : w a tchd og coun ter relo ad v a l ue upd ate thi s bi t is set b y ha rd w a re to i ndica te that an upd ate of the rel oad v a l ue is ong oing . it is reset b y h a rdw a re wh en th e re loa d v a lu e u pda te op er a t i on is completed i n the v dd v o l t ag e domai n (tak e s up to 5 rc 40 khz cycle s ). r e loa d v a lu e can be up dated on ly wh en r v u b i t is reset. bit 0 pvu: w a tch dog presca ler v a lu e upda te thi s bi t is set b y ha rd w a re to i ndica te that an upd ate of the pre s ca ler v a lu e is o ngo ing. it is re set b y ha rd w a re when the p r e s ca ler upd ate operation is compl e te d in th e v dd v o ltage domain (tak es up to 5 rc 40 khz cycles ). pres ca ler v a lu e can be up dated on ly w hen pvu bit i s rese t. t a b l e 70. i w dg r e gi st er map a nd res e t v a lue s offset regis t er 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x 00 iw dg _kr re s e r v ed ke y[ 15: 0] r e s e t v a l u e 0 00 000 000 00 000 00 0x 04 iw dg _pr reser v e d pr[2:0] re se t v a l u e 00 0 0x 08 iw dg _ r lr reser v ed rl[ 11: 0] re se t v a lue 111111111111 0x0c iwdg_s r reser v ed rv u pvu re se t v a l u e 00 window watchdog (wwdg) rm0072 476/1317 doc id 18341 rev 1alpha 18 windo w watc hdog (wwdg) 18.1 wwdg intr oduction th e windo w w a t c hdo g is u s e d t o det ect th e occurr en ce o f a sof t w ar e f ault , usually ge n e r a te d b y e x t e r n al in te rf er en ce o r b y un f o re se en lo g i c a l co nd itio ns , wh ich ca us es th e a pplica t io n pr og r a m to a ban do n its nor mal seq uen ce . the w a t c h d o g cir c uit g e n e r a t e s an mcu re se t on e x pir y of a pr og r a mmed time per io d, unle s s th e pr og r a m re fr eshe s t h e con t e n t s o f t he d o wn co unt er bef or e t h e t6 bit b e come s clea re d. an m c u re se t is a l so g ene r a t e d if t he 7- bit do wncou n t e r v a lu e (in th e co nt ro l r e g i st e r ) is re fr eshe d be f o re t h e d o wn co unt e r ha s re ache d th e windo w re giste r v a lu e . thi s imp lies t h a t t h e cou n t e r m u st be re fr es he d in a limit ed win d o w . 18.2 wwdg main f eatures pro g r a m m ab le f r e e -r unn ing do wnco unt er conditional reset ? r e s e t ( i f w a tchd og a c t i v a t e d ) when th e do wncou n t e r v a lu e be co mes less t h a n 0x40 ? r e s e t ( i f w a tchd og a c t i v a t e d ) if t h e do wncoun te r is r e lo ad ed ou tsid e th e win d o w (see fig u r e 19 4 ) ear l y w a k e up int e rr up t ( e wi ) : t r igg e re d (if en ab led a nd t he w a tchd og a c t i v a t e d ) whe n t he do wncou n t e r is eq ual t o 0x40 . 18.3 wwdg functional description if th e w a tc hd og is a c tiv a te d (t he wd ga bit is s e t in th e wwdg _ cr re gis t er ) an d wh en t h e 7-bit downcounter (t[6:0] bits) rolls over from 0x40 to 0x3f (t6 becomes cleared), it initiates a reset. if the software reloads the counter while the counter is greater than the value stored in the window register, then a reset is generated. rm0072 window watchdog (wwdg) doc id 18341 rev 1alpha 477/1317 figu re 19 3. w a t c hdog b l oc k dia g ra m t h e a p p lica t io n pr og r a m m u st w r ite in th e wwdg _ cr re gis t er a t r e gu lar in te r v a l s du r i ng n o r m al o per at ion t o p r e v e n t a n mcu r e set . th is ope r a t i on m u st occur o n ly when t h e coun te r v a l ue is lo w e r t h a n th e windo w re giste r v a lu e . th e v a lue t o be st or ed in t h e wwdg_ c r r e g i st er m u st be b e t w e en 0xff a nd 0xc0: enab li ng the watc hdog th e w a tchd og is alw a ys disab l ed a f t e r a re se t. i t is e nab le d b y se t t in g th e wdg a b i t in t h e wwdg _ cr r e g i st er , th en it ca nno t b e disab l ed a g a i n e xce pt b y a re se t. contr o lling th e do wn counter th is do wncou n t e r is fr ee- r u n n in g: i t coun t s do wn e v en if t h e w a tchd og is d i sa b l e d . wh en th e w a tc hd o g is e n a b le d, th e t 6 bit m u st be se t to pr e v en t ge ne r a t i ng a n im me d i ate r e set . th e t[ 5: 0] bit s con t a i n th e n u mbe r of in cr eme n t s which rep r e s e n t s t he tim e d e la y be f o re t he w a t c h dog p r o d u c e s a r e set . th e ti ming v a r i es b e t w e en a min i m u m an d a maxim u m v a lue d ue t o t he un kn o w n st at us of th e pr esca ler whe n wr itin g t o th e wwdg_ c r re gist er ( s e e fig u r e 19 4 ). t h e co nf ig u r atio n re gis ter (ww d g _ c f r ) co nt ain s th e hig h lim it o f th e w i nd o w : t o pre v ent a re set , t he do wnco unt er m u st be r e lo ade d when its v a lue is lo w e r th an t h e wind o w r egist er v a lue an d g r e a t e r th an 0x3 f . fig u r e 194 descr ibe s t he wind o w w a t chd og pr oc es s . not e : t h e t6 b i t can b e used t o ge ner at e a sof t w a re re se t ( t h e w d g a b i t is se t a n d the t6 b i t is clea re d) . ad v a nced watc h dog interrupt f e a t ure th e ear l y w a k e up i n t e r r up t ( e wi ) can b e used if sp ecif ic saf e t y o per at ions or d a t a log g in g m u st be pe rf or med b e f o r e t he act u a l r e set is ge ne r a t e d . th e ewi int e r r upt is e nab le d b y se ttin g th e ewi bit in th e wwdg _ cf r r e g i st er . wh en t h e d o wn co un te r re ac he s th e v a lu e 0 x 4 0 , a n ewi int e r r up t is gen er a t e d an d th e co rr espo ndi ng int e r r up t ser v ice r o u t in e (i sr) ca n be u se d to tr ig ge r sp ec ific a ct i on s ( su c h as co mm un ica t io ns or d a t a log g ing ) , bef or e re se ttin g th e de vic e . i n some a p p lica t io ns , th e ewi int e r r up t can b e used t o ma nag e a sof t w a re syste m ch ec k a nd/ or syste m re co v e r y/g r a cef u l de g r ad at ion , with o u t ge ner at ing a wwdg rese t. in t h is reset wdga 6-bit do wncounte r (c nt) t6 wa tchdog control register (wwdg_cr) t1 t2 t3 t4 t5 - w6 w0 w a tchdog configur ation register (wwd g_c f r) w1 w2 w3 w4 w5 compar ator t6:0 > w6:0 cmp = 1 when wr i t e wwdg_cr wdg prescaler (w dg tb) pclk1 t0 (from rcc cloc k co ntrolle r) window watchdog (wwdg) rm0072 478/1317 doc id 18341 rev 1alpha case , t h e co rr espo ndin g int e r r up t ser v ice r o u t in e (i sr) sho u ld r e loa d t he wwdg co unt e r t o a v oid t h e wwdg re se t, t hen t r igg e r t h e req u ir ed a c t i on s . th e ewi int e r r up t is cle a r ed b y wr it ing '0 ' t o t h e ewi f bit in t h e wwdg_ s r re gist er . not e : w he n t he ewi int e rr upt cann ot be ser v ed , e . g. due to a syst em loc k in a high er pr ior i t y ta sk, the wwdg res e t will e v entu ally be gener ated. 18.4 ho w to pr ogram the watc hdog timeout you can use the formula in figure 194 to calculate the wwdg timeout. warning: when writing to the wwdg_cr register, always write 1 in the t6 bit to avoid generating an immediate reset. rm0072 window watchdog (wwdg) doc id 18341 rev 1alpha 479/1317 figu re 19 4. windo w wa tc h dog timing dia g ra m th e f o r m u l a to ca lcu l at e t he t i meo u t v a lue is giv e n b y: wh er e: t wwdg : wwdg tim eou t t pc lk1 : apb1 clo c k pe r i od m easur ed in m s a i b 7 ; = 4 ; = # . 4 d o w n c o u n t e r 2 e f r e s h n o t a l l o w e d x & 2 e f r e s h a l l o w e d 4 i m e 4 b i t 2 % 3 % 4 t6 b it re s et w[6:0] t[6: 0] cnt d o wnco u nt er ti m e ref re s h window refre s h not a l l owed 0x 3 f a i17101 t wwdg t pc l k1 40 96 2 wd gtb t 5: 0 [] 1 + () = ms () window watchdog (wwdg) rm0072 480/1317 doc id 18341 rev 1alpha th e f o r m u l a to ca lcu l at e t he t i meo u t v a lue is giv e n b y : where t ww dg is the wwdg timeout t pclk1 is the apb1 cloc k per i od e xpressed in ms . ref e r to ta b l e 7 1 f o r th e minim u m and m a xim u m v a lu es o f t h e t ww dg . 18 .5 deb u g mode whe n t he micro cont r o ller ent er s d e b u g mo de ( c or te x-m3 cor e ha lt ed) , t h e wwdg co un te r e i th er co nt in ue s to w o r k n o r m ally or sto p s , de pe ndin g o n dbg_wwdg_st o p co nf igu r at ion bit in dbg module . f o r more details, ref e r to sect ion 3 2 . 16. 2: de b ug supp or t f o r tim e r s , w a t c h dog, b x can a nd i 2 c . t ab l e 71 . t ime out v al u e s at 3 0 mhz ( f pclk 1 ) pres caler w d gtb min timeout ( s) t[5 : 0] = 0x00 max timeout ( m s) t[5: 0] = 0x 3 f 1 0 136 .5 3 8.74 2 1 273 .0 7 1 7.48 4 2 546 .1 3 3 4.95 8 3 10 92.27 6 9 .91 t ww dg t pcl k 1 4096 2 wdg t b t[5:0] 1 + () (in ms) = rm0072 window watchdog (wwdg) doc id 18341 rev 1alpha 481/1317 18.6 wwdg regi ster s ref e r to se ct ion 1 . 1 on p age 4 6 f o r a list o f ab b r e v ia t i ons used in r e g i st er descr ipt i on s . 18.6.1 contr o l register (wwdg_cr) ad dre ss of f s e t : 0x00 re se t v a lu e: 0x 7f 31 30 2 9 28 27 26 25 2 4 23 22 2 1 20 19 18 1 7 16 reser v ed 15 14 1 3 12 11 10 9 8 7 6 5 4 3 2 1 0 re s e r v ed wdg a t[6 : 0] rs r w bits 31: 8 res e r v ed bit 7 wdg a : acti v a t i on bi t t h is bit is set b y sof t w a re and only cleared b y hardw a re after a reset. when wdga = 1 , the w a tchdog ca n gene r a te a reset. 0: w a tchdo g d i sab l ed 1: w a tchdo g e nab led bits 6:0 t[6:0]: 7 - bit co unter (msb to l s b) these bits contain the value of the watchd og counter. it is decremented every (4096 x 2 wdgtb ) pclk1 cycles. a reset is produced when it rolls over from 0x40 to 0x3f (t6 becomes cleared). window watchdog (wwdg) rm0072 482/1317 doc id 18341 rev 1alpha 18.6.2 configuration register (wwdg_cfr) ad dre s s of f s e t : 0x04 re se t v a lu e: 0x 7f 18.6.3 status register (wwdg_sr) ad dre ss of f s e t : 0x08 re se t v a lu e: 0x 00 31 30 2 9 28 27 26 25 2 4 23 22 2 1 20 19 18 1 7 16 reser v ed 15 14 1 3 12 11 10 9 8 7 6 5 4 3 2 1 0 reser v e d ewi wdgtb[ 1: 0] w[ 6: 0] rs rw rw bit 3 1 :1 0 r eser v e d bit 9 ewi: ear l y w a k e up interr upt w hen set, a n in te rr upt occurs wh ene v e r the coun te r reache s th e v a l ue 0 x 40 . this in te rr upt is on l y cl e a r ed b y ha rd w a re a fte r a re set . bits 8:7 wdgtb[1 : 0]: timer base the time base of the p r escale r can be mod i fied as f o l l o w s: 0 0 : ck cou n te r cl oc k (pcl k1 d i v 4096 ) d i v 1 0 1 : ck cou n te r cl oc k (pcl k1 d i v 4096 ) d i v 2 1 0 : ck cou n te r cl oc k (pcl k1 d i v 4096 ) d i v 4 1 1 : ck cou n te r cl oc k (pcl k1 d i v 4096 ) d i v 8 bits 6:0 w[ 6:0 ] : 7 - b i t wi ndo w v a lue these bi ts contai n the wi ndo w v a lue to be compare d to the do wn counter . 31 30 2 9 28 27 26 25 2 4 23 22 2 1 20 19 18 1 7 16 reser v ed 15 14 1 3 12 11 10 9 8 7 6 5 4 3 2 1 0 reser v ed ewi f rc _w 0 bit 31:1reser v ed bit 0 ewif: ear l y w a k e up interr upt flag thi s b it is set by hardware when the counter has reached the value 0x40. it must be cleared by software by writing ?0. a write of ?1 has no effe ct. this bit is also set if the interrupt is not enabled. rm0072 window watchdog (wwdg) doc id 18341 rev 1alpha 483/1317 18.6.4 wwdg register map th e f o llo wing t a b l e giv e s t he wwdg r e g i st e r map a n d r e set v a lue s . ref e r to t a b l e 1 on p age 50 f o r t h e r e g i st er bou nd ar y ad dr esse s . t a b l e 72. wwdg regi st er ma p a nd re set v a lue s offset regis t er 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x 00 wwdg _ cr reser v e d wdga t[ 6 : 0] re se t v a l u e 0 11 111 11 0x 04 wwdg_cfr reser v ed ew i wdg t b1 wdg t b0 w[ 6: 0] re se t v a l u e 000 11 111 11 0x 08 wwdg_ sr re se r v e d ewi f re se t v a l u e 0 cryptographic processor (cryp) RM0033 484/1317 doc id 15403 rev 3 19 cryptographic processor (cryp) 19.1 cryp introduction the cryptographic processor can be used to both encipher and decipher data using the des, triple-des or aes (128, 192, or 256) algorithms. it is a fully compliant implementation of the following standards: the data encryption standard (des) and triple-des (tdes) as defined by federal information processing standards publicat ion (fips pub 46-3, 1999 october 25). it follows the american national standards institute (ansi) x9.52 standard. the advanced encryption st andard (aes) as defined by federal information processing standards publication (fips pub 197, 2001 november 26) the cryp processor performs data encryption and decryption using des and tdes algorithms in electronic codebook (ecb) or cipher block chaining (cbc) mode. the cryp peripheral is a 32-bit ahb2 peripheral. it supports dma transfer for incoming and processed data, and has input and output fifos (each 8 words deep). 19.2 cryp main features suitable for aes, des and tdes enciphering and deciphering operations aes ? supports the ecb, cbc and ctr chaining algorithms ? supports 128-, 192- and 256-bit keys ? 4 32-bit initialization vectors (i v) used in the cbc and ctr modes ? 14 hclk cycles to process one 128-bit block in aes ? 16 hclk cycles to process one 192-bit block in aes ? 18 hclk cycles to process one 256-bit block in aes des/tdes ? direct implementation of simple des al gorithms (a single key, k1, is used) ? supports the ecb and cbc chaining algorithms ? supports 64-, 128- and 192-bit keys (including parity) ? 2 32-bit initialization vect ors (iv) used in the cbc mode ? 16 hclk cycles to process one 64-bit block in des ? 48 hclk cycles to process one 64-bit block in tdes common to des/tdes and aes ? in and out fifo (each with an 8-word depth, a 32-bit width, corresponding to 4 des blocks or 2 aes blocks) ? automatic data flow control with support of direct memory access (dma) (using 2 channels, one for incoming data the other for processed data) ? data swapping logic to support 1-, 8-, 16- or 32-bit data RM0033 cryptographic processor (cryp) doc id 15403 rev 3 485/1317 19.3 cryp functional description the cryptographic processor implements a triple-des (tdes, that also supports des) core and an aes cryptographic core. section 19.3.1 and section 19.3.2 provide details on these cores. since the tdes and the aes algorithms use bl ock ciphers, incomplete input data blocks have to be padded prior to encryption (extra bits should be appended to the trailing end of the data string). after decryption, the padding has to be discarded. the hardware does not manage the padding operation, the software has to handle it. figure 195 shows the block diagram of the cryptographic processor. figure 195. block diagram 19.3.1 des/tdes cryptographic core the des/triple-des cryptographic core consists of three components: the des algorithm (dea) multiple keys (1 for the des algorithm, 1 to 3 for the tdes algorithm) the initialization vector (used in the cbc mode) the basic processing involved in the tdes is as follows: an input block is read in the dea and encrypted using the first key, k1 (k0 is not used in tdes mode). the output is then decrypted using the second key, k2, and encrypted using the third key, k3. the key depends on the algorithm which is used: des mode: key = [k1] tdes mode: key = [k3 k2 k1] where kx=[kxr kxl], r = right, l = left b i t ! ( " b u s 0 r o c e s s o r c o r e $ % 3 4 $ % 3 ! % 3 # 2 9 0 ? $ ) . # 2 9 0 ? $ / 5 4 s w a p p i n g s w a p p i n g b i t ) . & ) & / b i t / 5 4 & ) & / # 2 9 0 ? # 2 # 2 9 0 ? + + # 2 9 0 ? ) 6 ) 6 ) 6 ) 6 k k # 2 9 0 ? ) - 3 # 2 # 2 9 0 ? 2 ) 3 # 2 9 0 ? - ) 3 2 # 2 9 0 ? $ - ! # 2 # 2 9 0 ? 3 2 3 t a t u s $ - ! c o n t r o l r e g i s t e r ) n t e r r u p t r e g i s t e r s # o n t r o l r e g i s t e r ) n i t i a l i z a t i o n v e c t o r s + e y a i b cryptographic processor (cryp) RM0033 486/1317 doc id 15403 rev 3 according to the mode implemented, the resultant output block is used to calculate the ciphertext. note that the outputs of the intermediate dea stages is never revealed outside the cryptographic boundary. the tdes allows three different keying options: three independent keys the first option specifies that all the keys are independent, that is, k1, k2 and k3 are independent. fips pub 46-3 ? 1999 (and ansi x9.52 ? 1998) refers to this option as the keying option 1 and, to the tdes as 3-key tdes. two independent keys the second option specifies that k1 and k2 are independent and k3 is equal to k1, that is, k1 and k2 are independent, k3 = k1. fips pub 46-3 ? 1999 (and ansi x9.52 ? 1998) refers to this second option as th e keying option 2 and, to the tdes as 2-key tdes. three equal keys the third option specifies that k1, k2 and k3 are equal, that is, k1 = k2 = k3. fips pub 46-3 ? 1999 (and ansi x9.52 ? 1998) refers to the third option as the keying option 3. this ?1-key? tdes is equivalent to single des. fips pub 46-3 ? 1999 (and ansi x9.52-1998) provides a thorough explanation of the processing involved in the four operation modes supplied by the tdea (tdes algorithm): tdes-ecb encryption, tdes-ecb decryption, tdes-cbc encryption and tdes-cbc decryption. this reference manual only gives a brief explanation of each mode. des and tdes electronic codebook (des/tdes-ecb) mode des/tdes-ecb mode encryption figure 196 illustrates the encryption in d es and tdes electronic codebook (des/tdes-ecb) mode. a 64-bit plaintext data block (p) is used after bit/byte/half- word swapping (refer to section 19.3.3: data type on page 497 ) as the input block (i). the input block is processed through the dea in the encrypt state using k1. the output of this process is fed back directly to the input of the dea where the des is performed in the decrypt state using k2. the output of this process is fed back directly to the input of the dea where the des is performed in the encrypt state using k3. the resultant 64- bit output block (o) is used, after bit/byte/half-word swapping, as ciphertext (c) and it is pushed into the out fifo. des/tdes-ecb mode decryption figure 197 illustrates the des/tdes-ecb decryption. a 64-bit ciphertext block (c) is used, after bit/byte/half-word swapping, as the input block (i). the keying sequence is reversed compared to that used in the encryption process. the input block is processed through the dea in the decrypt state using k3. the output of this process is fed back directly to the input of the dea where the des is performed in the encrypt state using k2. the new result is directly fed to the input of the dea where the des is performed in the decrypt state using k1. the resultant 64-bit output block (o), after bit/byte/half-word swapping, produces the plaintext (p). RM0033 cryptographic processor (cryp) doc id 15403 rev 3 487/1317 figure 196. des/tdes-ecb mode encryption 1. k: key; c: cipher text; i: input blo ck; o: output block; p: plain text. figure 197. des/tdes-ecb mode decryption 1. k: key; c: cipher text; i: input blo ck; o: output block; p: plain text. ) . & ) & / $ % ! e n c r y p t + 0 b i t s $ % ! d e c r y p t + $ % ! e n c r y p t + / 5 4 & ) & / p l a i n t e x t 0 c i p h e r t e x t # s w a p p i n g / b i t s # b i t s s w a p p i n g $ ! 4 ! 4 9 0 % $ ! 4 ! 4 9 0 % a i b ) . & ) & / # b i t s / 5 4 & ) & / c i p h e r t e x t # p l a i n t e x t 0 $ % ! d e c r y p t + $ % ! e n c r y p t + $ % ! d e c r y p t + ) b i t s s w a p p i n g / b i t s $ ! 4 ! 4 9 0 % $ ! 4 ! 4 9 0 % 0 b i t s s w a p p i n g - 3 6 cryptographic processor (cryp) RM0033 488/1317 doc id 15403 rev 3 des and tdes cipher block chaining (des/tdes-cbc) mode des/tdes-cbc mode encryption figure 198 illustrates the des and triple-des ci pher block chaining (des/tdes-cbc) mode encryption. this mode begins by dividing a plaintext message into 64-bit data blocks. in tcbc encryption, the first input block (i 1 ), obtained after bit/byte/half-word swapping (refer to section 19.3.3: data type on page 497 ), is formed by exclusive- oring the first plaintext data block (p 1 ) with a 64-bit initialization vector iv (i 1 = iv p 1 ). the input block is processed through the dea in the encrypt state using k1. the output of this process is fed back directly to the input of the dea, which performs the des in the decrypt state using k2. the output of this process is fed directly to the input of the dea, which performs the des in the encrypt state using k3. the resultant 64-bit output block (o 1 ) is used directly as the ciphertext (c 1 ), that is, c 1 = o 1 . this first ciphertext block is then exclusive-ored with the second plaintext data block to produce the second input block, (i 2 ) = (c 1 p 2 ). note that i 2 and p 2 now refer to the second block. the second input block is processed through the tdea to produce the second ciphertext block. this encryption process continues to ?chain? successive cipher and plaintext blocks together until the last plaintext block in the message is encrypted. if the message does not consist of an integral number of data blocks, then the final partial data block should be encrypted in a manner specified for the application. des/tdes-cbc mode decryption in des/tdes-cbc decryption (see figure 199 ), the first ciphertext block (c 1 ) is used directly as the input block (i 1 ). the keying sequence is reversed compared to that used for the encrypt process. the input block is processed through the dea in the decrypt state using k3. the output of this process is fed directly to the input of the dea where the des is processed in the encrypt state using k2. this resulting value is directly fed to the input of the dea where the des is processed in the decrypt state using k1. the resulting output block is exclusive-ored with the iv (which must be the same as that used during encryption) to produce the first plaintext block (p 1 = o 1 iv). the second ciphertext block is then used as the next input block and is processed through the tdea. the resulting output block is exclusive-ored with the first ciphertext block to produce the second plaintext data block (p 2 = o 2 c 1 ). (note that p 2 and o 2 refer to the second block of data.) the tcbc decryption process continues in this manner until the last complete ciphertext block has been decrypted. ciphertext representing a partial data block must be decrypted in a manner specified for the application. RM0033 cryptographic processor (cryp) doc id 15403 rev 3 489/1317 figure 198. des/tdes-cbc mode encryption 1. k: key; c: cipher text; i: input block; o: output block; ps: plain text bef ore swapping (when decoding) or after swapping (when encoding); p: pl ain text; iv: initialization vectors. ) . & ) & / $ % ! e n c r y p t + 0 b i t s $ % ! d e c r y p t + $ % ! e n c r y p t + / 5 4 & ) & / / b i t s p l a i n t e x t 0 c i p h e r t e x t # 0 s b i t s s w a p p i n g ) 6 , 2 ) b i t s b e f o r e # 2 9 0 i s e n a b l e d / i s w r i t t e n b a c k i n t o ) 6 a t t h e s a m e t i m e a s i t i s p u s h e d i n t o t h e / 5 4 & ) & / s w a p p i n g # b i t s $ ! 4 ! 4 9 0 % $ ! 4 ! 4 9 0 % ! ( " d a t a w r i t e a i b cryptographic processor (cryp) RM0033 490/1317 doc id 15403 rev 3 figure 199. des/tdes-cbc mode decryption 1. k: key; c: cipher text; i: input block; o: output block; ps: plain text bef ore swapping (when decoding) or after swapping (when encoding); p: pl ain text; iv: initialization vectors. 19.3.2 aes cryptographic core the aes cryptographic core co nsists of three components: the aes algorithm (aea: advanced encryption algorithm ) multiple keys initialization vector(s) the aes utilizes keys of 3 possib le lengths: 128, 192 or 2 56 bits and, depending on the operation mode used, zero or one 128-bit initialization vector (iv). the basic processing involved in the aes is as follows: an input block of 128 bits is read from the input fifo and sent to the aea to be encrypted us ing the key (k0...3). the key format depends on the key size: if key size = 128: key = [k3 k2] if key size = 192: key = [k3 k2 k1] if key size = 256: key = [k3 k2 k1 k0] where kx=[kxr kxl],r=right, l=left according to the mode implemented, the resultant output block is used to calculate the ciphertext. fips pub 197 (november 26, 2001) provides a thorough explanation of the processing involved in the four operation modes supp lied by the aes core: aes-ecb encryption, aes- ) . & ) & / ) b i t s / 5 4 & ) & / 0 s b i t s c i p h e r t e x t # p l a i n t e x t 0 0 b i t s s w a p p i n g $ % ! d e c r y p t + $ % ! e n c r y p t + $ % ! d e c r y p t + ) 6 , 2 ! ( " d a t a w r i t e b e f o r e # 2 9 0 i s e n a b l e d / b i t s ) i s w r i t t e n b a c k i n t o ) 6 a t t h e s a m e t i m e a s 0 i s p u s h e d i n t o t h e / 5 4 & ) & / # b i t s s w a p p i n g $ ! 4 ! 4 9 0 % $ ! 4 ! 4 9 0 % - 3 6 RM0033 cryptographic processor (cryp) doc id 15403 rev 3 491/1317 ecb decryption, aes-cbc encryption and aes- cbc decryption.this reference manual only gives a brief explanation of each mode. aes electronic codebook (aes-ecb) mode aes-ecb mode encryption figure 200 illustrates the aes electronic cod ebook (aes-ecb) mo de encryption. in aes-ecb encryption, a 128- bit plaintext data block (p) is used after bit/byte/half- word swapping (refer to section 19.3.3: data type on page 497 ) as the input block (i). the input block is proc essed through the aea in the encryp t state using th e 128, 192 or 256-bit key. the resultant 128-bit output block (o) is used after bit/byte/half-word swapping as ciphertext (c). it is then pushed into the out fifo. aes-ecb mode decryption figure 201 illustrates the aes electronic cod ebook (aes-ecb) mode encryption. to perform an aes decryption in the ecb mode, the secret key has to be prepared (it is necessary to execute the complete key schedule for encryption) by collecting the last round key, and using it as the first round ke y for the decryption of the ciphertext. this preparation function is computed by the aes core. refer to section 19.3.6: procedure to perform an encryption or a decryption for more details on how to prepare the key. in aes-ecb decryption, a 128-bit ciphertext block (c) is used after bit/byte/half-word swapping as the input block (i). the keying sequence is reversed compared to that of the encryption process. the resultant 128-bit output block (o), after bit/byte or half- word swapping, produces the plaintext (p). figure 200. aes-ecb mode encryption 1. k: key; c: cipher text; i: input blo ck; o: output block; p: plain text. 2. if key size = 128: key = [k3 k2]. if key size = 192: key = [k3 k2 k1] if key size = 256: key = [k3 k2 k1 k0]. ) . & ) & / ! % ! e n c r y p t + 0 b i t s / 5 4 & ) & / p l a i n t e x t 0 c i p h e r t e x t # ) b i t s s w a p p i n g # b i t s s w a p p i n g $ ! 4 ! 4 9 0 % $ ! 4 ! 4 9 0 % o r a i b cryptographic processor (cryp) RM0033 492/1317 doc id 15403 rev 3 figure 201. aes-ecb mode decryption 1. k: key; c: cipher text; i: input blo ck; o: output block; p: plain text. 2. if key size = 128 => key = [k3 k2]. if key size = 192 => key = [k3 k2 k1] if key size = 256 => key = [k3 k2 k1 k0]. aes cipher block chaining (aes-cbc) mode aes-cbc mode encryption the aes cipher block chaining (aes-cb c) mode decryption is shown on figure 202 . in aes-cbc encryption, the first input block (i 1 ) obtained after bit/byte/half-word swapping (refer to section 19.3.3: data type on page 497 ) is formed by exclusive- oring the first plaintext data block (p 1 ) with a 128-bit initialization vector iv (i 1 = iv p 1 ). the input block is processed through th e aea in the encrypt st ate using the 128-, 192- or 256-bit key (k0...k3). the resultant 128-bit output block (o 1 ) is used directly as ciphertext (c 1 ), that is, c 1 = o 1 . this first ciphertext block is then exclusive-ored with the second plaintext data block to produce the second input block, (i 2 ) = (c 1 p 2 ). note that i 2 and p 2 now refer to the second block. the second input block is processed through the aea to prod uce the second cip hertext block. this encryption process continues to ?chain? successive cipher and plaintext blocks together until the last plaintext block in the message is encrypte d. if the message does not consist of an integral number of data blocks, then the final partial data block should be encrypted in a manner specified for the application. in the cbc mode, like in the ecb mode, the secret key must be prepared to perform an aes decryption. refer to section 19.3.6: procedure to perform an encryption or a decryption on page 502 for more details on how to prepare the key. aes-cbc mode decryption in aes-cbc decryption (see figure 203 ), the first 128-bit ciphertext block (c 1 ) is used directly as the input block (i 1 ). the input block is processed through the aea in the decrypt state using the 128-, 192- or 256-bit key. the resulting output block is exclusive-ored with the 128-bit initialization vector iv (which must be the same as that used during encryption) to produce the first plaintext block (p 1 = o 1 iv). the second ciphertext block is then used as the next input block and is processed through the aea. the resulting output block is exclusive-ored with the first ciphertext block to produce the second plaintext data block (p 2 = o 2 c 1 ). (note that p 2 and o 2 refer to the second ) . & ) & / # b i t s / 5 4 & ) & / c i p h e r t e x t # p l a i n t e x t 0 ! % ! d e c r y p t ) b i t s s w a p p i n g / b i t s $ ! 4 ! 4 9 0 % $ ! 4 ! 4 9 0 % 0 b i t s s w a p p i n g + o r - 3 6 RM0033 cryptographic processor (cryp) doc id 15403 rev 3 493/1317 block of data.) the aes-cbc de cryption process continues in this manner until the last complete ciphertext block has been decrypted. ciphertext representing a partial data block must be decrypted in a manner specified for the application. figure 202. aes-cbc mode encryption 1. k: key; c: cipher text; i: input block; o: output block; ps: plain text bef ore swapping (when decoding) or after swapping (when encoding); p: pl ain text; iv: initialization vectors. 2. ivx=[ivxr ivxl], r=right, l=left. 3. if key size = 128 => key = [k3 k2]. if key size = 192 => key = [k3 k2 k1] if key size = 256 => key = [k3 k2 k1 k0]. ) . & ) & / ! % ! e n c r y p t 0 b i t s / 5 4 & ) & / / b i t s p l a i n t e x t 0 c i p h e r t e x t # s w a p p i n g ) 6 ; ) 6 ) 6 = ) b i t s ! ( " d a t a w r i t e b e f o r e # 2 9 0 i s e n a b l e d / i s w r i t t e n b a c k i n t o ) 6 a t t h e s a m e t i m e a s i t i s p u s h e d i n t o t h e / 5 4 & ) & / s w a p p i n g # b i t s $ ! 4 ! 4 9 0 % $ ! 4 ! 4 9 0 % + o r 0 s b i t s a i b cryptographic processor (cryp) RM0033 494/1317 doc id 15403 rev 3 figure 203. aes-cbc mode decr yption 1. k: key; c : cipher text ; i: inp ut block; o: output block; ps: plain te xt bef ore swapping (w hen decoding) or after sw appin g (when enco d ing); p: pl ain text; iv: initialization vectors. 2. ivx= [ivxr ivxl], r=r i ght, l = left. 3. if key size = 128 => key = [k3 k2]. if key size = 192 => key = [k3 k2 k1] if key size = 256 => key = [k3 k2 k1 k0]. aes counte r mode (aes-ctr) mode the aes counter mode uses the aes b l oc k as a k e y stream gener ator . the gener ated k e ys a r e the n xo red with t h e p l aint e xt t o ob t a in the ciphe r . f o r th is r eason , it m a k e s no sense t o sp ea k of d i f f e r e n t ct r en cr ypt i on /d e cr y pt ion, s i nc e t h e t w o o p e r at ion s ar e e x act l y t h e same . in f a ct , g i v e n: pla i nte x t: p[0 ], p[1 ], .. ., p[n ] (1 28 b i ts ea ch ) a k e y k to b e use d ( t he s i z e d o e s no t ma tt er ) an initial counter b l oc k (call it icb b u t it ha s t h e s a m e fu nc tio n a lity as t h e iv of cbc) th e ciphe r is co mpu t e d as f o l l o w s: c[i] = enck(iv[i]) xor p[ i] , wher e: i v[0] = icb an d iv [i+1] = func(iv[i]) , wher e func is a n upd at e f unct i on applied to the pre v ious iv b l oc k; func is basically an incr eme n t o f o ne of th e f i elds comp osing t h e iv b l o c k. g i v en t hat t h e icb f o r d e cr ypt i on is t he same a s t h e o n e f o r e n cr yp tio n , t he k e y st r eam g ene r a t e d d u r i ng d e cr ypt i on is t h e sam e as t h e on e gen er a t e d dur in g encr y p t io n. t hen , the cip h e r t e xt is x o r e d wit h t h e k e y st re am in o r de r to r e tr ie v e t h e or ig in al p l a i nte xt . t h e de cr yp tio n op er a t io n th er ef or e ac ts e xa ct l y in th e sa m e w a y as th e en cr yp tion o p e r a tio n . ) . & ) & / ) b i t s / 5 4 & ) & / c i p h e r t e x t # p l a i n t e x t 0 0 b i t s s w a p p i n g ! % ! d e c r y p t + ! ( " d a t a w r i t e b e f o r e # 2 9 0 i s e n a b l e d / b i t s ) i s w r i t t e n b a c k i n t o ) 6 a t t h e s a m e t i m e a s 0 i s p u s h e d i n t o t h e / 5 4 & ) & / # b i t s s w a p p i n g $ ! 4 ! 4 9 0 % $ ! 4 ! 4 9 0 % o r 0 s b i t s - 3 6 ) 6 ; ) 6 ) 6 = RM0033 cryptographic processor (cryp) doc id 15403 rev 3 495/1317 figure 204 and figure 205 illustrate aes-ctr encryption an d decryption, respectively. figure 204. aes-ctr mode encryption 1. k: key; c: cipher text; i: input block; o: output block; ps: plain text befo re swapping (when decoding) or after swapping (when encoding); cs: cipher text after swapping (when decoding) or before swapping (when encoding); p: plain text; iv : initialization vectors. ) . & ) & / ! % ! e n c r y p t p, 1 2 8 b i t s / 5 4 & ) & / cs, 128 bit p l a i n t e x t 0 c i p h e r t e x t # s w a p p i n g ) 6 , 2 o, 128 bits i, 128 bits ahb2 data write (before cryp is enabled) (i + 1) is written back into iv at same time than c is pushed in out fifo s w a p p i n g c, 128 bits datatype datatype + o r ps, 128 bits a i b cryptographic processor (cryp) RM0033 496/1317 doc id 15403 rev 3 figure 205. aes-ctr mode encryption 1. k: key; c: cipher text; i: input block; o: output block; ps: plain text befo re swapping (when decoding) or after swapping (when encoding); cs: cipher text after swapping (when decoding) or before swapping (when encoding); p: plain text; iv : initialization vectors. figure 206 shows the structure of the iv block as defined by the standard [2]. it is composed of three distinct fields. figure 206. initial counter block structure for the counter mode nonce is a 32-bit, single-use value. a new nonce should be assigned to each different communication. the initialization vector (iv) is a 64-bit value and the standard specifies that the encryptor must choose iv so as to ensure that a given value is used only once for a given key the counter is a 32-bit big-endian integer that is incremented each time a block has been encrypted. the initial value of the counter should be set to 1. the block increments the least significant 32 bi ts, while it leaves the other (most significant) 96 bits unchanged. ) . & ) & / ! % ! e n c r y p t c, 128 bits / 5 4 & ) & / ps, 128 bits c i p h e r t e x t 0 p l a i n t e x t # s w a p p i n g ) 6 , 2 i, 128 bits ahb2 data write (before cryp is enabled) (i + 1) is written back into iv at same time than p is pushed in out fifo s w a p p i n g p, 128 bits datatype datatype + 128, 192 or 256 cs, 128 bits o, 128 bits - 3 6 . o n c e b i t s ) n i t i a l i z a t i o n v e c t o r ) 6 b i t s # o u n t e r b i t s a i RM0033 cryptographic processor (cryp) doc id 15403 rev 3 497/1317 19.3.3 data type data enter the cryp processor 32 bits (word) at a time as they are written into the cryp_din register. the principle of the des is that streams of data are processed 64 bits by 64 bits and, for each 64-bit block, the bits are numbered from m1 to m64, with m1 the left- most bit and m64 the right-most bit of the block. the same principle is used for the aes, but with a 128-bit block size. the system memory organization is little-endian: whatever the data type (bit, byte, 16-bit half-word, 32-bit word) used, the least-significant data occupy the lowest address locations. a bit, byte, or half-word swapping operation (depending on the kind of data to be encrypted) therefore has to be performed on the data read from the in fifo before they enter the cryp processor. the same swapping operation should be performed on the cryp data before they are written into the out fifo. for example, the operation would be byte swapping for an ascii text stream. the kind of data to be proc essed is configured with the datatype bitfield in the cryp control register (cryp_cr). table 73. data types datatype in cryp_cr swapping performed system memory data (plaintext or cypher) 00b no swapping example: tdes block value 0x abcd7720 6973fe01 is represented in syst em memory as: 01b half-word (16-bit) swapping example: tdes block value 0x abcd 7720 6973 fe01 is represented in syst em memory as: 0x abcd7720 6973fe01 tdes block size = 64bit = 2x 32 bit 0x abcd7720 0x 6973fe01 @ @+4 system memory 0x abcd 7720 6973 fe01 tdes block size = 64bit = 2x 32 bit 0x 7720 abcd 0xfe01 6973 @ @+4 system memory cryptographic processor (cryp) RM0033 498/1317 doc id 15403 rev 3 figure 207 shows how the 64-bit data block m1...64 is constructed from two consecutive 32- bit words popped off the in fifo by the cryp processor, according to the datatype value. the same schematic can easily be extended to form the 128-bit block for the aes cryptographic algorithm (for the aes, the block length is four 32-bit words, but swapping only takes place at word level, so it is identical to the one described here for the tdes). note: the same swapping is performed between the in fifo and the cryp data block, and between the cryp data block and the out fifo. 10b byte (8-bit) swapping example: tdes block value 0x abcd 7720 6973 fe01 is represented in syst em memory as: 11b bit swapping tdes block value 0x 4e6f772069732074 is represented in system memory as: table 73. data types datatype in cryp_cr swapping performed system memory data (plaintext or cypher) 0x ab cd 77 20 69 73 fe 01 tdes block size = 64bit = 2x 32 bit 0x 20 77 cd ab 0x 01 fe 73 69 @ @+4 system memory 0x4e 6f 77 20 69 73 20 74 0x04 ee f6 72 0x2e 04 ce 96 @ @+4 0000 0100 1110 1110 1111 0110 0111 0010 0100 1110 0110 1111 0111 0111 0010 0000 0110 1001 0111 0011 0010 0000 0111 0100 0010 1110 0000 0100 1100 111 0 1001 0110 @ @+4 system memory tdes bloc size = 64bit = 2x 32 bit RM0033 cryptographic processor (cryp) doc id 15403 rev 3 499/1317 figure 207. 64-bit block construction according to datatype 19.3.4 initialization vector s - cryp_iv0...1(l/r) initialization vectors are considered as two 64-bit data items. they therefore do not have the same data format and representation in system memory as plaintext or cypher data, and they are not affected by the datatype value. initialization vectors are defined by two consecutive 32-bit words, cryp_ivl (left part, noted as bits iv1...32) and cryp_ivr (right part, noted as bits iv33...64). " y t e " y t e " y t e " y t e - - - - ) . & ) & / b i t s t r i n g - - - - - b i t s w a p p i n g o p e r a t i o n ) . & ) & / b i t s t r i n g b y t e s w a p p i n g o p e r a t i o n " y t e " y t e " y t e " y t e b i t s b i t s b i t s b i t s ) . & ) & / b i t s t r i n g h a l d w o r d s w a p p i n g o p e r a t i o n ( a l f w o r d b i t s $ ! 4 ! 4 9 0 % b $ ! 4 ! 4 9 0 % b $ ! 4 ! 4 9 0 % b ( a l f w o r d b i t s ( a l f w o r d - ( a l f w o r d - - - - - - b i t b i t b i t b i t b i t b i t b i t b i t b i t b i t f i r s t w o r d w r i t t e n i n t o t h e # 2 9 0 ? $ ) . r e g i s t e r s e c o n d w o r d w r i t t e n i n t o t h e # 2 9 0 ? $ ) . r e g i s t e r " y t e " y t e " y t e " y t e b i t s b i t s b i t s b i t s f i r s t w o r d w r i t t e n i n t o t h e # 2 9 0 ? $ ) . r e g i s t e r s e c o n d w o r d w r i t t e n i n t o t h e # 2 9 0 ? $ ) . r e g i s t e r " y t e " y t e " y t e " y t e - - - - b i t o r d e r i n g w i t h i n b y t e i s u n c h a n g e d ( a l f w o r d b i t s ( a l f w o r d b i t s f i r s t w o r d w r i t t e n i n t o t h e # 2 9 0 ? $ ) . r e g i s t e r s e c o n d w o r d w r i t t e n i n t o t h e # 2 9 0 ? $ ) . r e g i s t e r ( a l f w o r d - ( a l f w o r d - ) . & ) & / b i t s t r i n g . o s w a p p i n g o p e r a t i o n $ ! 4 ! 4 9 0 % b 7 o r d b i t s 7 o r d - 7 o r d b i t s f i r s t w o r d w r i t t e n i n t o t h e # 2 9 0 ? $ ) . r e g i s t e r s e c o n d w o r d w r i t t e n i n t o t h e # 2 9 0 ? $ ) . r e g i s t e r 7 o r d - a i cryptographic processor (cryp) RM0033 500/1317 doc id 15403 rev 3 during the des or tdes cbc encryption, the cryp_iv0(l/r) bits are xored with the 64- bit data block popped off the in fifo after swapping (acc ording to the datatype value), that is, with the m1...64 bits of the data block. when the output of the dea3 block is available, it is copied back into the cryp_iv0(l/r) vector, and this new content is xored with the next 64-bit data block popped off the in fifo, and so on. during the des or tdes cbc decryption, the cryp_iv0(l/r) bits are xored with the 64- bit data block (that is, with the m1...64 bits) delivered by the tdea1 block before swapping (according to the datatype value), and pushed into the out fifo. when the xored result is swapped and pushed into the out fifo, the cryp_iv0(l/r) value is replaced by the output of the in fifo, then the in fifo is popped, and a new 64-bit data block can be processed. during the aes cbc encryption , the cryp_iv0...1(l/r) bits are xored with the 128-bit data block popped off the in fifo after swa pping (according to the datatype value). when the output of the aes core is av ailable, it is copied back in to the cryp_iv0...1(l/r) vector, and this new content is xored with the next 128-bit data block popped off the in fifo, and so on. during the aes cbc decryption , the cryp_iv0...1(l/r) bits are xored with the 128-bit data block delivered by the aes core before swapping (according to the datatype value) and pushed into the out fifo. when the xored result is swapped and pushed into the out fifo, the cryp_iv0...1(l/r) value is replaced by the output of the in fifo, then the in fifo is popped, and a new 128-bit data block can be processed. during the aes ctr encryption or decryption, the cryp_iv0...1(l/r) bits are encrypted by the aes core. then the result of the encryption is xored with the 128-bit data block popped off the in fifo after swapping (according to the datatype va lue). when the xored result is swapped and pushed into the out fifo, the counter part of the cryp_iv0...1(l/r) value (32 lsb) is incremented. any write operation to the cryp_iv0...1(l/r) registers when bit busy = 1b in the cryp_sr register is disregarded (cryp_iv0...1(l/r) register content not modified). thus, you must check that bit busy = 0b before modifying initialization vectors. RM0033 cryptographic processor (cryp) doc id 15403 rev 3 501/1317 figure 208. initializa tion vectors use in the tdes-cbc encryption 19.3.5 cryp busy state when there is enough data in the input fifo (at least 2 words for the des or tdes algorithm mode, 4 words for the aes algorithm mode) and enough free-space in the output fifo (at least 2 (des/tdes) or 4 (aes) word locations), and when the bit crypen = 1 in the cryp_cr register, then the cryptographic processor automatically starts an encryption or decryption process (according to the value of the algodir bit in the cryp_cr register). this process takes 48 ahb2 clock cycles for the triple-des algorithm, 16 ahb2 clock cycles for the simple des algorithm, and 14, 16 or 18 ahb2 clock cycles for the aes with key lengths of 128, 192 or 256 bits, respectively. during the whole process, the busy bit in the cryp_sr register is set to 1. at the end of the process, two (des /tdes) or four (aes) words are written by the cryp core into the output fifo, and the busy bit is cleared. in the cbc or ctr mode, the initialization vector s cryp_ivx(l/r)r (x = 0..3) are updated as well. # 2 9 0 ? ) 6 , b i t s t r i n g - - - - - 4 $ % 3 # " # e n c r y p t i o n e x a m p l e $ ! 4 ! 4 9 0 % b - - - - - b i t b i t b i t b i t b i t b i t b i t b i t b i t b i t f i r s t w o r d w r i t t e n i n t o t h e # 2 9 0 ? $ ) . r e g i s t e r s e c o n d w o r d w r i t t e n i n t o t h e # 2 9 0 ? $ ) . r e g i s t e r ) 6 # 2 9 0 ? ) 6 2 $ % ! % n c r y p t + $ % ! $ e c r y p t + $ % ! % n c r y p t + # 2 9 0 ? ) 6 , # 2 9 0 ? ) 6 2 # 2 9 0 r e s u l t i s c o p i e d b a c k t o t h e # 2 9 0 ? ) 6 , 2 r e g i s t e r s a f t e r c y p h e r i n g / 5 4 & ) & / & i r s t w o r d f r o m t h e / 5 4 & ) & / c o n t a i n s t h e l e f t p a r t o f t h e c y p h e r t e x t b l o c k / 3 e c o n d w o r d f r o m / 5 4 & ) & / c o n t a i n s t h e r i g h t p a r t o f c y p h e r t e x t b l o c k / ) 6 ) 6 ) 6 ) 6 ) 6 ) 6 ) 6 ) 6 ) 6 ) ) ) ) ) ) ) ) ) ) ) 6 ) 6 ) 6 ) 6 ) 6 ) 6 ) 6 ) 6 ) 6 ) 6 a i cryptographic processor (cryp) RM0033 502/1317 doc id 15403 rev 3 a write operation to the key registers (cryp_kx(l/r)r, x = 0..3), the initialization registers (cryp_ivx(l/r)r, x = 0..3), or to bits [9:2] in the cryp_cr register are ignored when the cryptographic processor is busy (bit busy = 1b in the cryp_sr register), and the registers are not modified. it is thus not possible to modify the configuration of the cryptographic processor while it is processing a block of data. it is however possible to clear the crypen bit while busy = 1, in whic h case the ongoing des, tdes or aes processing is completed and the two/four word results are written into the output fifo, and then, only then, the busy bit is cleared. note: when a block is being processed in the des or tdes mode, if the output fifo becomes full and if the input fifo contains at least one new block, then the new block is popped off the input fifo and the busy bit remains high until there is enough space to store this new block into the output fifo. 19.3.6 procedure to perform an encryption or a decryption initialization 1. initialize the peripheral (the order of operations is not important except for the key preparation for aes-ecb or aes-cbc decryption. the key size and the key value must be entered before preparing the key and the algorithm must be configured once the key has been prepared): a) configure the key size (128-, 192- or 256-bit, in the aes only) with the keysize bits in the cryp_cr register b) write the symmetric key into the cryp_kxl/r registers (2 to 8 registers to be written depending on the algorithm) c) configure the data type (1-, 8-, 16- or 32-bit), with the datatype bits in the cryp_cr register d) in case of decryption in aes-ecb or aes-cbc, you must prepare the key: configure the key preparation mode by setting the algomode bits to ?111? in the cryp_cr register. then write the crypen bit to 1: the busy bit is set. wait until busy returns to 0 (crypen is automatically cleared as well): the key is prepared for decryption e) configure the algorithm and chaining (the des/tdes in ecb/cbc, the aes in ecb/cbc/ctr) with the algomode bits in the cryp_cr register f) configure the direction (encryption/decryption), with the algodir bit in the cryp_cr register g) write the initialization vectors into the cryp_ivxl/r register (in cbc or ctr modes only) 2. flush the in and out fifos by writing the fflush bit to 1 in the cryp_cr register processing when the dma is used to transfer the data from/to the memory 1. configure the dma controller to transfer the input data from the memory. the transfer length is the length of the message. as message padding is not managed by the peripheral, the message length must be an entire number of blocks. the data are transferred in burst mode. the burst length is 4 words in the aes and 2 or 4 words in the des/tdes. the dma should be configured to set an interrupt on transfer completion of the output data to indicate that the processing is finished. 2. enable the cryptographic processor by wr iting the crypen bit to 1. enable the dma requests by setting the dien and doen bits in the cryp_dmacr register. RM0033 cryptographic processor (cryp) doc id 15403 rev 3 503/1317 3. all the transfers and processing are managed by the dma and the cryptographic processor. the dma interrupt indicates that the processing is complete. both fifos are normally empty and busy = 0. processing when the data are transferred by the cpu during interrupts 1. enable the interrupts by setting the inim and outim bits in the cryp_imscr register. 2. enable the cryptographic processor by setting the crypen bit in the cryp_cr register. 3. in the interrupt managing the input data: load the input message into the in fifo. you can load 2 or 4 words at a time, or load data until the fifo is full. when the last word of the message has been entered into the fifo, disable the interrupt by clearing the inim bit. 4. in the interrupt managing the output data: read the output message from the out fifo. you can read 1 block (2 or 4 words) at a time or read data until the fifo is empty. when the last word has been read, inim=0, busy=0 and both fifos are empty (ifem=1 and ofne=0). you can disable the interrupt by clearing the outim bit and, the peripheral by cl earing the crypen bit. processing without using the dma nor interrupts 1. enable the cryptographic processor by setting the crypen bit in the cryp_cr register. 2. write the first blocks in the input fifo (2 to 8 words). 3. repeat the following sequence until the complete message has been processed: a) wait for ofne=1, then read the out-fifo (1 block or until the fifo is empty) b) wait for ifnf=1, then write the in fifo (1 block or until the fifo is full) 4. at the end of the processing, busy=0 and both fifos are empty (ifem=1 and ofne=0). you can disable the peripheral by clearing the crypen bit. 19.3.7 context swapping if a context switching is needed because a new task launched by the os requires this resource, the following tasks have to be perform ed for full context restoration (example when the dma is used): case of the aes and des 1. context saving a) stop dma transfers on the in fifo by clearing the dien bit in the cryp_dmacr register. b) wait until both the in and out fifos are empty (ifem=1 and ofne=0 in the cryp_sr register) and the busy bit is cleared. c) stop dma transfers on the out fifo by writing the doen bit to 0 in the cryp_dmacr register an d clear the crypen bit. d) save the current configuration (bits [9:2] in the cryp_cr register) and, if not in ecb mode, the initialization vectors. the key value must already be available in the memory. when needed, save the dma status (pointers for in and out messages, number of remaining bytes, etc.) 2. configure and execute the other processing. cryptographic processor (cryp) RM0033 504/1317 doc id 15403 rev 3 3. context restoration a) configure the processor as in section 19.3.6: procedure to perform an encryption or a decryption on page 502 , initialization with the saved configuration. for the aes-ecb or aes-cbc decryption, the key must be prepared again. b) if needed, reconfigure the dma controller to transfer the rest of the message. c) enable the processor by setting the crypen bit and, t he dma requests by setting the dien and doen bits. case of the tdes context swapping can be done in the tdes in the same way as in the aes. but as the input fifo can contain up to 4 unprocessed blocks and as the processing duration per block is higher, it can be faster in certain cases to interrupt the processing without waiting for the in fifo to be empty. 1. context saving a) stop dma transfers on the in fifo by clearing the dien bit in the cryp_dmacr register. b) disable the processor by clearing the cr ypen bit (the processing will stop at the end of the current block). c) wait until the out fifo is empty (ofne=0 in the cryp_sr register) and the busy bit is cleared. d) stop dma transfers on the out fifo by writing the doen bit to 0 in the cryp_dmacr register. e) save the current configuration (bits [9:2] in the cryp_cr register) and, if not in ecb mode, the initialization vectors. the key value must already be available in the memory. when needed, save the dma status (pointers for in and out messages, number of remaining bytes, etc.). read back the data loaded in the in fifo that have not been processed and save them in the memory until the fifo is empty. 2. configure and execute the other processing. 3. context restoration a) configure the processor as in section 19.3.6: procedure to perform an encryption or a decryption on page 502 , initialization with the saved configuration. for the aes-ecb or aes-cbc decryption, the key must be prepared again. b) write the data that were saved during context saving into the in fifo. c) if needed, reconfigure the dma controller to transfer the rest of the message. d) enable the processor by setting the crypen bit and, t he dma requests by setting the dien and doen bits. 19.4 cryp interrupts there are two individual maskable interrupt sources generated by the cryp. these two sources are combined into a single interrupt signal, which is the only interrupt signal from the cryp that drives the nvic (nested vectored interrupt controller). this combined interrupt, which is an or function of the individual masked sources, is asserted if any of the individual interrupts listed below is asserted and enabled. you can enable or disable the interrupt sources individually by changing the mask bits in the cryp_imscr register. setting the appropriate mask bit to 1 enables the interrupt. RM0033 cryptographic processor (cryp) doc id 15403 rev 3 505/1317 the status of the individual interrupt sources can be read either from the cryp_risr register, for raw interrupt status, or from the cryp_misr register, for the masked interrupt status. output fifo service interrupt - outmis the output fifo service interrupt is asserted when there is one or more (32-bit word) data items in the output fifo. this interrupt is cleared by reading data from the output fifo until there is no valid (32-bit) word left (that is, th e interrupt follows the state of the ofne (output fifo not empty) flag). the output fifo service interrupt outmis is not enabled with the cryp enable bit. consequently, disabling the cryp will not force the outmis signal low if the output fifo is not empty. input fifo service interrupt - inmis the input fifo service interrupt is asserted when there are less than four words in the input fifo. it is cleared by performing write operations to the input fifo until it holds four or more words. the input fifo service interrupt inmis is enabled with the cryp enable bit. consequently, when cryp is disabled, the inmis signal is low even if the input fifo is empty. figure 209. cryp interrupt mapping diagram 19.5 cryp dma interface the cryptographic processor provides an interface to connect to the dma controller. the dma operation is controlled through the cryp dma control register, cryp_dmacr. the burst and single transfer request signals are not mutually exclusive. they can both be asserted at the same time. for example, when there are 6 words available in the out fifo, the burst transfer request and the single transf er request are asserted. after a burst transfer of 4 words, the single transfer request only is asserted to transfer the last 2 available words. this is useful for situations where the number of words left to be received in the stream is less than a burst. each request signal remains asserted until the relevant dma clear signal is asserted. after the request clear signal is deasserted, a request signal can become active again, depending on the above described conditions. all request signals are deasserted if the cryp peripheral is disabled or the dma enable bit is cleared (dien bit for the in fifo and doen bit for the out fifo in the cryp_dmacr register). note: 1 the dma controller must be configured to perform burst of 4 words or less. otherwise some data could be lost. 2 in order to let the dma controller empty the out fifo before filling up the in fifo, the outdma channel should have a higher priority than the indma channel. ) . 2 ) 3 ) . ) - # 2 9 0 % . ) . - ) 3 ) . & ) & / ) n t e r r u p t ) . - ) 3 / 5 4 2 ) 3 / 5 4 ) - / 5 4 - ) 3 / 5 4 & ) & / ) n t e r r u p t / 5 4 - ) 3 ' l o b a l ) n t e r r u p t a i cryptographic processor (cryp) RM0033 506/1317 doc id 15403 rev 3 19.6 cryp registers the cryptographic core is associated with several control and status registers, eight key registers and four initialization vectors registers. 19.6.1 cryp control register (cryp_cr) address offset: 0x00 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543 2 10 crypen fflush reserved keysize datatype algomode algodir reserved rw w rwrwrwrwrwrwrw rw bit 31:16 reserved, forced by hardware to 0. bit 15 crypen: cryptographic processor enable 0: cryp processor is disabled 1: cryp processor is enabled note: the crypen bit is automatically cleare d by hardware when the key preparation process ends (algomode=111b). bit 14 fflush: fifo flush when crypen = 0, writing this bit to 1 flushes the in and out fifos (that is read and write pointers of the fifos are reset. writ ing this bit to 0 has no effect. when crypen = 1, writing this bit to 0 or 1 has no effect. reading this bit always returns 0. bits 13:10 reserved, forced by hardware to 0. bits 9:8 keysize[1:0]: key size selection (aes mode only) this bitfield defines the bit-length of t he key used for the aes cryp tographic core. this bitfield is ?don?t care? in the des or tdes modes. 00: 128 bit key length 01: 192 bit key length 10: 256 bit key length 11: reserved, do not use this value bits 7:6 datatype[1:0]: data type selection this bitfield defines the format of data entered in the cryp_din register (refer to section 19.3.3: data type ). 00: 32-bit data. no swapping of each word. first word pushed into the in fifo (or popped off the out fifo) forms bits 1...32 of the dat a block, the second word forms bits 33...64. 01: 16-bit data, or half-word. each word pushed into the in fifo (or popped off the out fifo) is considered as 2 half-words, which are swapped with each other. 10: 8-bit data, or bytes. each word pushed in to the in fifo (or popped off the out fifo) is considered as 4 bytes, which are swapped with each other. 11: bit data, or bit-string. each word pushed into the in fifo (or popped off the out fifo) is considered as 32 bits (1st bit of the string at position 0), which are swapped with each other. RM0033 cryptographic processor (cryp) doc id 15403 rev 3 507/1317 note: writing to the keysize, datatype, algo mode and algodir bits while busy=1 has no effect. these bits can only be configured when busy=0. the fflush bit has to be set only when busy=0. if not, the fifo is flushed, but the block being processed may be pushed into the output fifo just after the flush operation, resulting in a nonempty fifo condition. bits 5:3 algomode[2:0]: algorithm mode 000: tdes-ecb (triple-des electronic codebook): no feedback between blocks of data. initialization vectors (cryp_iv0( l/r)) are not used, three key vectors (k1, k2, and k3) are used (k0 is not used). 001: tdes-cbc (triple-des cipher block c haining): output block is xored with the subsequent input block before its entry into the algorithm. initialization vectors (cryp_iv0l/r) must be initialized, three key vectors (k1, k2, and k3) are used (k0 is not used). 010: des-ecb (simple des electronic codebook): no feedback between blocks of data. initialization vectors (cryp_iv0l/r) are not used, only one key vector (k1) is used (k0, k2, k3 are not used). 011: des-cbc (simple des cipher block chaining): output block is xored with the subsequent input block before its entry into the algorithm. initialization vectors (cryp_iv0l/r) must be initialized. only one ke y vector (k1) is used (k0, k2, k3 are not used). 100: aes-ecb (aes electronic codebook): no feedback between blocks of data. initialization vectors (cryp_iv0l/r...1l/r) are not used. all four key vectors (k0...k3) are used. 101: aes-cbc (aes cipher block chaining): ou tput block is xored with the s ubsequent input block before its entry into the algorithm . initialization vectors (cryp_iv0l/r...1l/r) must be initialized. all four key vectors (k0...k3) are used. 110: aes-ctr (aes counter mode): output bloc k is xored with the subsequent input block before its entry into the algo rithm. initialization vectors (cryp_iv0l/r...1l/r) must be initialized. all four key vectors (k0...k3) are used. ctr decryption does not differ from ctr encryption, since the core always encrypts the current counter block to produce the key stream that will be xored with t he plaintext or cipher in input. thus, algodir is don?t care when algomode = 110b, and the key must not be unrolled (prepared) for decryption. 111: aes key preparation for decryption mode. writing this value when crypen = 1 immediately starts an aes round for key preparati on. the secret key must have previously been loaded into the k0...k3 registers. the bu sy bit in the cryp_sr register is set during the key preparation. after key processing, the resulting key is copied back into the k0...k3 registers, and the busy bit is cleared. bit 2 algodir: algorithm direction 0: encrypt 1: decrypt bit 1:0 reserved, must be kept to 0. cryptographic processor (cryp) RM0033 508/1317 doc id 15403 rev 3 19.6.2 cryp status register (cryp_sr) address offset: 0x04 reset value: 0x0000 0003 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 reserved busy offu ofne ifnf ifem rrrrr bit 31:5 reserved, forced by hardware to 0. bit 4 busy: busy bit 0: the cryp core is not processing an y data. the reason is either that: ? the cryp core is disabled (crypen=0 in the cryp_cr regist er) and the last processing has completed, or ? the cryp core is waiting for enough data in the input fifo or enough free space in the output fifo (that is in each case at least 2 words in the des, 4 words in the aes). 1: the cryp core is currently processing a bl ock of data or a key preparation (for aes decryption). bit 3 offu: output fifo full 0: output fifo is not full 1: output fifo is full bits 2 ofne: output fifo not empty 0: output fifo is empty 1: output fifo is not empty bit 1 ifnf: input fifo not full 0: input fifo is full 1: input fifo is not full bits 0 ifem: input fifo empty 0: input fifo is not empty 1: input fifo is empty RM0033 cryptographic processor (cryp) doc id 15403 rev 3 509/1317 19.6.3 cryp data input register (cryp_din) address offset: 0x08 reset value: 0x0000 0000 the cryp_din is the data input register. it is 32-bit wide. it is used to enter up to four 64-bit (tdes) or two 128-bit (aes) plaintext (when encrypting) or cipherte xt (when decrypting) blocks into the input fifo, one 32-bit word at a time. the first word written into the fifo is the msb of the input block. the lsb of the input block is written at the end. disregarding the data swapping, this gives: in the des/tdes modes: a block is a sequence of bits numbered from bit 1 (leftmost bit) to bit 64 (rightmost bit). bit 1 corresponds to the msb (bit 31) of the first word entered into the fifo, bit 64 corresponds to the lsb (bit 0) of the second word entered into the fifo. in the aes mode: a block is a sequence of bits numbered from 0 (leftmost bit) to 127 (rightmost bit). bit 0 corresponds to the msb (bit 31) of the first word written into the fifo, bit 127 corresponds to the lsb (bit 0) of the 4th word written into the fifo. to fit different data sizes, the data written in the cryp_din register can be swapped before being processed by configurin g the datatype bits in the cryp_cr register. refer to section 19.3.3: data type on page 497 for more details. when cryp_din is written to, the data are pushed into the input fifo. when at least two 32-bit words in the des/tdes mode (or four 32-bit words in the aes mode) have been pushed into the input fifo, and when at least 2 words are free in the output fifo, the cryp engine starts an encrypting or decrypting process. this process takes two 32-bit words in the des/tdes mode (or four 32-bit words in the aes mode) from the input fifo and delivers two 32-bit words (or 4, respectively) to the output fifo per process round. when cryp_din is read: if crypen = 0, the fifo is popped, and then the data present in the input fifo are returned, from the oldest one (first reading) to the newest one (last reading). the ifem flag must be checked before each read operation to make sure that the fifo is not empty. if crypen = 1, an undefin ed value is returned. after the cryp_din register has been read once or several times, the fifo must be flushed by setting the fflush bit prior to processing new data. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 datain rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 datain rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bit 31:0 datain: data input read = returns input fifo content if cry pen = 0, else returns an undefined value. write = input fifo is written. cryptographic processor (cryp) RM0033 510/1317 doc id 15403 rev 3 19.6.4 cryp data output register (cryp_dout) address offset: 0x0c reset value: 0x0000 0000 the cryp_dout is the data output register. it is read-only and 32-bit wide. it is used to retrieve up to four 64-bit (tdes mode) or two 128-bit (aes mode) ciphertext (when encrypting) or plaintext (when decrypting) blocks from the output fifo, one 32-bit word at a time. like for the input data, the msb of the output block is the first word read from the output fifo. the lsb of the output block is read at the end. disregarding data swapping, this gives: in the des/tdes modes: bit 1 (leftmost bit) corresponds to the msb (bit 31) of the first word read from the fifo, bit 64 (rightmost bit) corresponds to the lsb (bit 0) of the second word read from the fifo. in the aes mode: bit 0 (leftmost bit) corresponds to the msb (bit 31) of the first word read from the fifo, bit 127 (rightmost bit) corresponds to the lsb (bit 0) of the 4th word read from the fifo. to fit different data sizes, the data can be swapped after processing by configuring the datatype bits in the cryp_cr register. refer to section 19.3.3: data type on page 497 for more details. when cryp_dout is read, the last data entered into the output fifo (pointed to by the read pointer) is returned. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 dataout rrrrrrrrrrrrrrrr 1514131211109876543210 dataout rrrrrrrrrrrrrrrr bit 31:0 dataout: data output read = returns output fifo content. write = no effect. RM0033 cryptographic processor (cryp) doc id 15403 rev 3 511/1317 19.6.5 cryp dma control register (cryp_dmacr) address offset: 0x10 reset value: 0x0000 0000 19.6.6 cryp interrupt mask set/c lear register (cryp_imscr) address offset: 0x14 reset value: 0x0000 0000 the cryp_imscr register is the interrupt mask set or clear register. it is a read/write register. on a read operation, this register gives the current value of the mask on the relevant interrupt. writing 1 to the particular bit sets the mask, enabling the interrupt to be read. writing 0 to this bit clears the corresp onding mask. all the bits are cleared to 0 when the peripheral is reset. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 reserved doen dien rw rw bit 31:2 reserved, forced by hardware to 0. bit 1 doen: dma output enable 0: dma for outgoing data transfer is disabled 1: dma for outgoing data transfer is enabled bit 0 dien: dma input enable 0: dma for incoming data transfer is disabled 1: dma for incoming data transfer is enabled 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 reserved outim inim rw rw bit 31:2 reserved, forced by hardware to 0. bit 1 outim: output fifo service interrupt mask 0: output fifo service interrupt is masked 1: output fifo service interrupt is not masked bit 0 inim: input fifo service interrupt mask 0: input fifo service interrupt is masked 1: input fifo service interrupt is not masked cryptographic processor (cryp) RM0033 512/1317 doc id 15403 rev 3 19.6.7 cryp raw interrupt st atus register (cryp_risr) address offset: 0x18 reset value: 0x0000 0001 the cryp_risr register is the raw interrupt status register. it is a read-only register. on a read, this register gives the current raw status of the corresponding interrupt prior to masking. a write has no effect. 19.6.8 cryp masked interrupt st atus register (cryp_misr) address offset: 0x1c reset value: 0x0000 0000 the cryp_misr register is the masked interrupt status register. it is a read-only register. on a read, this register gives the current masked status of the corresponding interrupt prior to masking. a write has no effect. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15141312111098765432 1 0 reserved outris inris rr bit 31:2 reserved, forced by hardware to 0. bit 1 outris: output fifo service raw interrupt status gives the raw interrupt state prior to maski ng of the output fifo service interrupt. 0: raw interrupt not pending 1: raw interrupt pending bit 0 inris: input fifo service raw interrupt status gives the raw interrupt state prior to maski ng of the input fifo service interrupt. 0: raw interrupt not pending 1: raw interrupt pending 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved outmis inmis rr bit 31:2 reserved, forced by hardware to 0. bit 1 outmis: output fifo service masked interrupt status gives the interrupt state after masking of the output fifo service interrupt. 0: interrupt not pending 1: interrupt pending RM0033 cryptographic processor (cryp) doc id 15403 rev 3 513/1317 19.6.9 cryp key registers (cryp_k0...3(l/r)r) address offset: 0x20 to 0x3c reset value: 0x0000 0000 these registers contain the cryptographic keys. in the tdes mode, keys are 64-bit binary values (number from left to right, that is the leftmost bit is bit 1), named k1, k2 and k3 (k0 is not used), each key consists of 56 information bits and 8 parity bits. the parity bits are reserved for error detection purposes and are not used by the current block. thus, bits 8, 16, 24, 32, 40, 48, 56 and 64 of each 64- bit key value kx[1:64] are not used. in the aes mode, the key is considered as a single 128-, 192- or 256-bit long bit sequence, k 0 k 1 k 2 ...k 127/191/255 (k 0 being the leftmost bit). the aes key is entered into the registers as follows: for aes-128: k 0 ..k 127 corresponds to b 127 ..b 0 (b 255 ..b 128 are not used), for aes-192: k 0 ..k 191 corresponds to b 191 ..b 0 (b 255 ..b 192 are not used), for aes-256: k 0 ..k 255 corresponds to b 255 ..b 0 . in any case b 0 is the rightmost bit. cryp_k0lr (address offset: 0x20) cryp_k0rr (address offset: 0x24) cryp_k1lr (address offset: 0x28) bit 0 inmis: input fifo service masked interrupt status gives the interrupt state after masking of the input fifo service interrupt. 0: interrupt not pending 1: interrupt pending when crypen = 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 b255 b254 b253 b252 b251 b250 b249 b248 b247 b246 b245 b244 b243 b242 b241 b240 wwwwwwwwwwwwwwww 1514131211109876543210 b239 b238 b237 b236 b235 b234 b233 b232 b231 b230 b229 b228 b227 b226 b225 b224 wwwwwwwwwwwwwwww 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 b223 b222 b221 b220 b219 b218 b217 b216 b215 b214 b213 b212 b211 b210 b209 b208 wwwwwwwwwwwwwwww 1514131211109876543210 b207 b206 b205 b204 b203 b202 b201 b200 b199 b198 b197 b196 b195 b194 b193 b192 wwwwwwwwwwwwwwww 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 k1.1 b191 k1.2 b190 k1.3 b189 k1.4 b188 k1.5 b187 k1.6 b186 k1.7 b185 k1.8 b184 k1.9 b183 k1.10 b182 k1.11 b181 k1.12 b180 k1.13 b179 k1.14 b178 k1.15 b177 k1.16 b176 wwwwwwwwwwwwwwww cryptographic processor (cryp) RM0033 514/1317 doc id 15403 rev 3 cryp_k1rr (address offset: 0x2c) cryp_k2lr (address offset: 0x30) cryp_k2rr (address offset: 0x34) cryp_k3lr (address offset: 0x38) 1514131211109876543210 k1.17 b175 k1.18 b174 k1.19 b173 k1.20 b172 k1.21 b171 k1.22 b170 k1.23 b169 k1.24 b168 k1.25 b167 k1.26 b166 k1.27 b165 k1.28 b164 k1.29 b163 k1.30 b162 k1.31 b161 k1.32 b160 wwwwwwwwwwwwwwww 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 k1.33 b159 k1.34 b158 k1.35 b157 k1.36 b156 k1.37 b155 k1.38 b154 k1.39 b153 k1.40 b152 k1.41 b151 k1.42 b150 k1.43 b149 k1.44 b148 k1.45 b147 k1.46 b146 k1.47 b145 k1.48 b144 wwwwwwwwwwwwwwww 1514131211109876543210 k1.49 b143 k1.50 b142 k1.51 b141 k1.52 b140 k1.53 b139 k1.54 b138 k1.55 b137 k1.56 b136 k1.57 b135 k1.58 b134 k1.59 b133 k1.60 b132 k1.61 b131 k1.62 b130 k1.63 b129 k1.64 b128 wwwwwwwwwwwwwwww 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 k2.1 b127 k2.2 b126 k2.3 b125 k2.4 b124 k2.5 b123 k2.6 b122 k2.7 b121 k2.8 b120 k2.9 b119 k2.10 b118 k2.11 b117 k2.12 b116 k2.13 b115 k2.14 b114 k2.15 b113 k2.16 b112 wwwwwwwwwwwwwwww 1514131211109876543210 k2.17 b111 k2.18 b110 k2.19 b109 k2.20 b108 k2.21 b107 k2.22 b106 k2.23 b105 k2.24 b104 k2.25 b103 k2.26 b102 k2.27 b101 k2.28 b100 k2.29 b99 k2.30 b98 k2.31 b97 k2.32 b96 wwwwwwwwwwwwwwww 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 k2.33 b95 k2.34 b94 k2.35 b93 k2.36 b92 k2.37 b91 k2.38 b90 k2.39 b89 k2.40 b88 k2.41 b87 k2.42 b86 k2.43 b85 k2.44 b84 k2.45 b83 k2.46 b82 k2.47 b81 k2.48 b80 wwwwwwwwwwwwwwww 1514131211109876543210 k2.49 b79 k2.50 b78 k2.51 b77 k2.52 b76 k2.53 b75 k2.54 b74 k2.55 b73 k2.56 b72 k2.57 b71 k2.58 b70 k2.59 b69 k2.60 b68 k2.61 b67 k2.62 b66 k2.63 b65 k2.64 b64 wwwwwwwwwwwwwwww 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 k3.1 b63 k3.2 b62 k3.3 b61 k3.4 b60 k3.5 b59 k3.6 b58 k3.7 b57 k3.8 b56 k3.9 b55 k3.10 b54 k3.11 b53 k3.12 b52 k3.13 b51 k3.14 b50 k3.15 b49 k3.16 b48 wwwwwwwwwwwwwwww 1514131211109876543210 k3.17 b47 k3.18 b46 k3.19 b45 k3.20 b44 k3.21 b43 k3.22 b42 k3.23 b41 k3.24 b40 k3.25 b39 k3.26 b38 k3.27 b37 k3.28 b36 k3.29 b35 k3.30 b34 k3.31 b33 k3.32 b32 wwwwwwwwwwwwwwww RM0033 cryptographic processor (cryp) doc id 15403 rev 3 515/1317 cryp_k3rr (address offset: 0x3c) note: write accesses to these registers are disregarded when the cryptographic processor is busy (bit busy = 1 in the cryp_sr register). 19.6.10 cryp initialization vector registers (cryp_iv0...1(l/r)r) address offset: 0x40 to 0x4c reset value: 0x0000 0000 the cryp_iv0...1(l/r)r are the left-word and right-word registers for the initialization vector (64 bits for des/tdes and 128 bits fo r aes) and are used in the cbc (cipher block chaining) and counter (ctr) modes. after each computation round of the tdes or aes core, the cryp_iv0...1(l/r)r registers are updated as described in section : des and tdes cipher block chaining (des/tdes-cbc) mode on page 488 , section : aes cipher block chaining (aes-cbc) mode on page 492 and section : aes counter mode (aes-ctr) mode on page 494 . iv0 is the leftmost bit whereas iv63 (des, td es) or iv127 (aes) are the rightmost bits of the initialization vector. iv1(l/r)r is used only in the aes. cryp_iv0lr (address offset: 0x40) cryp_iv0rr (address offset: 0x44) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 k3.33 b31 k3.34 b30 k3.35 b29 k3.36 b28 k3.37 b27 k3.38 b26 k3.39 b25 k3.40 b24 k3.41 b23 k3.42 b22 k3.43 b21 k3.44 b20 k3.45 b19 k3.46 b18 k3.47 b17 k3.48 b16 wwwwwwwwwwwwwwww 1514131211109876543210 k3.49 b15 k3.50 b14 k3.51 b13 k3.52 b12 k3.53 b11 k3.54 b10 k3.55 b9 k3.56 b8 k3.57 b7 k3.58 b6 k3.59 b5 k3.60 b4 k3.61 b3 k3.62 b2 k3.63 b1 k3.64 b0 wwwwwwwwwwwwwwww 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 iv0 iv1 iv2 iv3 iv4 iv5 iv6 iv7 iv8 iv9 iv10 iv11 iv12 iv13 iv14 iv15 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 iv16 iv17 iv18 iv19 iv20 iv21 iv22 iv23 iv24 iv25 iv26 iv27 iv28 iv29 iv30 iv31 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 iv32 iv33 iv34 iv35 iv36 iv37 iv38 iv39 iv40 iv41 iv42 iv43 iv44 iv45 iv46 iv47 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 iv48 iv49 iv50 iv51 iv52 iv53 iv54 iv55 iv56 iv57 iv58 iv59 iv60 iv61 iv62 iv63 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw cryptographic processor (cryp) RM0033 516/1317 doc id 15403 rev 3 cryp_iv1lr (address offset: 0x48) cryp_iv1rr (address offset: 0x4c) note: in des/3des modes, only cryp_iv0(l/r) is used. note: write access to these registers are disregarded when the cryptographic processor is busy (bit busy = 1 in the cryp_sr register). 19.6.11 cryp register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 iv64 iv65 iv66 iv67 iv68 iv69 iv70 iv71 iv72 iv73 iv74 iv75 iv76 iv77 iv78 iv79 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 iv80 iv81 iv82 iv83 iv84 iv85 iv86 iv87 iv88 iv89 iv90 iv91 iv92 iv93 iv94 iv95 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 iv96 iv97 iv98 iv99 iv100 iv101 iv102 iv103 iv104 iv105 iv106 iv107 iv108 iv109 iv110 iv111 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 iv112 iv113 iv114 iv115 iv116 iv117 iv118 iv119 iv120 iv121 iv122 iv123 iv124 iv125 iv126 iv127 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw table 74. cryp register map and reset values offset register name reset value register size 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 cryp_cr 0x0000000 reserved crypen fflush reserved keysize datatype alomode algodir reserved 0x04 cryp_sr 0x0000003 reserved busy offu ofne ifnf ifem 0x08 cryp_dr 0x0000000 datain 0x0c cryp_dout 0x0000000 dataout 0x10 cryp_dmacr 0x0000000 reserved doen dien 0x14 cryp_imscr 0x0000000 reserved outim inim 0x18 cryp_risr 0x0000001 reserved outris inris 0x1c cryp_misr 0x0000000 reserved outmis in%is 0x20 cryp_k0lr 0x0000000 cryp_k0lr 0x24 cryp_k0rr 0x0000000 cryp_k0rr ... ... 0x38 cryp_k3lr 0x0000000 cryp_k3lr RM0033 cryptographic processor (cryp) doc id 15403 rev 3 517/1317 refer to table 1 on page 50 for the register boundary addresses. 0x3c cryp_k3rr 0x0000000 cryp_k3rr 0x40 cryp_iv0lr 0x0000000 cryp_iv0lr 0x44 cryp_iv0rr 0x0000000 cryp_iv0rr 0x48 cryp_iv1lr 0x0000000 cryp_iv1lr 0x4c cryp_iv1rr 0x0000000 cryp_iv1rr table 74. cryp register map and reset values (continued) offset register name reset value register size 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 random number generator (rng) RM0033 518/1317 doc id 15403 rev 3 20 random number generator (rng) 20.1 rng introduction the rng processor is a random number generator, based on a continuous analog noise, that provides a random 32-bit value to the host when read. the rng is expected to provide a success ratio of more than 85% to fips 140-2 tests for a sequence of 20 000 bits, measured on corner conditions by device characterization. 20.2 rng main features it delivers 32-bit random numbers, produced by an analog generator 40 periods of the pll48clk clock signal between two consecutive random numbers monitoring of the rng entropy to flag abnormal behavior (generation of stable values, or of a stable sequence of values) it can be disabled to reduce power-consumption 20.3 rng functional description figure 210 shows the rng block diagram. figure 210. block diagram the random number generator implements an a nalog circuit. this ci rcuit generates seeds that feed a linear feedback shift register (rng_lfsr) in order to produce 32-bit random numbers. the analog circuit is made of several ring os cillators whose outputs are xored to generate the seeds. the rng_lfsr is clocked by a dedicated clock (pll48clk) at a constant frequency, so that the quality of the random number is independent of the hclk frequency. the contents of the rng_lfsr are transferred into the data register (rng_dr) when a significant number of seeds have been introduced into the rng_lfsr. b i t ! ( " b u s 2 . ' ? $ 2 2 . ' ? # 2 2 . ' ? 3 2 3 t a t u s r e g i s t e r # o n t r o l r e g i s t e r f a u l t d e t e c t o r , & 3 2 ! n a l o g s e e d 2 . ' ? # , + # l o c k c h e c k e r d a t a r e g i s t e r 3 h i f t 2 e g i s t e r f e e d a , i n e a r & e e d b a c k a i RM0033 random number generator (rng) doc id 15403 rev 3 519/1317 in parallel, the analog seed and the dedicated pll48clk clock are monitored. status bits (in the rng_sr register) indicate when an abnormal sequence occurs on the seed or when the frequency of the pll48clk clock is too low. an interrupt can be generated when an error is detected. 20.3.1 operation to run the rng, follow the steps below: 1. enable the interrupt if needed (to do so, set the ie bit in the rng_cr register). an interrupt is generated when a random number is ready or when an error occurs. 2. enable the random number generation by setting the rngen bit in the rng_cr register. this activates the analog part, the rng_lfsr and the error detector. 3. at each interrupt, check that no error occurred (the seis and ceis bits should be ?0? in the rng_sr register) and that a random number is ready (the drdy bit is ?1? in the rng_sr register). the contents of the rng_dr register can then be read. as required by the fips pub (federal information processing standard publication) 140-2, the first random number generated after setting the rngen bit should not be used, but saved for comparison with the next generated random number. each subsequent generated random number has to be compared with the previously generated number. the test fails if any two compared numbers are equal (continuous random number generator test). 20.3.2 error management if the ceis bit is read as ?1? (clock error) in the case of a clock, the rng is no more able to generate random numbers because the pll48clk clock is not correct. check that the clock controller is correctly configured to provide the rng clock and clear the ceis bit. the rng can work when the cecs bit is ?0?. the clock error has no impact on the previously generated random numbers, and the rng_dr register contents can be used. if the seis bit is read as ?1? (seed error) in the case of a seed error, the generation of random numbers is interrupted for as long as the secs bit is ?1?. if a number is available in the rng_dr register, it must not be used because it may not have enough entropy. what you should do is clear the seis bit, then clear and set the rngen bit to reinitialize and restart the rng. 20.4 rng registers the rng is associated with a control register, a data register and a status register. random number generator (rng) RM0033 520/1317 doc id 15403 rev 3 20.4.1 rng control register (rng_cr) address offset: 0x00 reset value: 0x0000 0000 20.4.2 rng status register (rng_sr) address offset: 0x04 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ie rngen reserved rw rw bits 31:4 reserved, forced by hardware to 0. bit 3 ie: interrupt enable 0: rng interrupt is disabled 1: rng interrupt is enabled. an interrupt is pending as soon as drdy=1 or seis=1 or ceis=1 in the rng_sr register. bit 2 rngen: random number generator enable 0: random number generator is disabled 1: random number generator is enabled. bits 1:0 reserved, mu st be kept cleared. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 reserved seis ceis reserved secs cecs drdy rc_w0 rc_w0 r r r bits 31:3 reserved, forced by hardware to 0. bit 6 seis: seed error interrupt status this bit is set at the same time as secs, it is cleared by writing it to 0. 0: no faulty sequence detected 1: one of the following faulty sequences has been detected: ? more than 64 consecutive bits at the same value (0 or 1) ? more than 32 consecutive alternances of 0 and 1 (0101010101...01) an interrupt is pending if ie = 1 in the rng_cr register. bit 5 ceis: clock error interrupt status this bit is set at the same time as cecs, it is cleared by writing it to 0. 0: the pll48clk clock was correctly detected 1: the pll48clk was not correctly detected (f pll48clk < f hclk /16) an interrupt is pending if ie = 1 in the rng_cr register. bits 4:3 reserved, forced by hardware to 0. RM0033 random number generator (rng) doc id 15403 rev 3 521/1317 20.4.3 rng data register (rng_dr) address offset: 0x08 reset value: 0x0000 0000 the rng_dr register is a read-only register that delivers a 32-bit random value when read. after being read, this register delivers a new random value after a maximum time of 40 periods of the pll48clk clock. the software must check that the drdy bit is set before reading the rndata value. bit 2 secs: seed error current status 0: no faulty sequence has currently been detected . if the seis bit is set, this means that a faulty sequence was detected and the situation has been recovered. 1: one of the following faulty sequences has been detected: ? more than 64 consecutive bits at the same value (0 or 1) ? more than 32 consecutive alternances of 0 and 1 (0101010101...01) bit 1 cecs: clock error current status 0: the pll48clk clock has been correctly detected. if the ceis bit is set, this means that a clock error was detected and the situation has been recovered 1: the pll48clk was not correctly detected (f pll48clk < f hclk /16). bit 0 drdy: data ready 0: the rng_dr register is not yet valid, no random data is available 1: the rng_dr register contains valid random data note: an interrupt is pending if ie = 1 in the rng_cr register. once the rng_dr register has been read, this bit returns to 0 until a new valid value is computed. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rndata rrrrrrrrrrrrrrrr 1514131211109876543210 rndata rrrrrrrrrrrrrrrr bits 31:0 rndata: random data 32-bit random data. random number generator (rng) RM0033 522/1317 doc id 15403 rev 3 20.4.4 rng register map ta bl e 7 5 gives the rng register map and reset values. table 75. rng register map and reset map offset register name reset value register size 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 rng_cr 0x0000000 reserved ie rngen reserved 0x04 rng_sr 0x0000000 reserved seis ceis reserved secs cecs drdy 0x08 rng_dr 0x0000000 rndata[31:0] RM0033 hash processor (hash) doc id 15403 rev 3 523/1317 21 hash processor (hash) 21.1 hash introduction the hash processor is a fully compliant implementation of the secure hash algorithm (sha-1), the md5 (message-digest algorithm 5) hash algorithm and the hmac (keyed-hash message authentication code) algorithm suitable for a variety of applications. it computes a message digest (160 bits for the sha-1 algorithm, 128 bits for the md5 algorithm) for messages of up to (2 64 ? 1) bits, while hmac algorithms provide a way of authenticating messages by means of hash f unctions. hmac algorithms consist in calling the sha-1 or md5 hash function twice. 21.2 hash main features suitable for data authenticatio n applications, compliant with: ? fips pub 180-2 (federal information processing standards publication 180-2) ? secure hash standard specifications (sha-1) ? ietf rfc 1321 (internet engineering task force request for comments number 1321) specifications (md5) ahb slave peripheral 32-bit data words for input data, supporting word, half-word, byte and bit bit-string representations, with little-endian data representation only automatic swapping to comply with the big-endian sha1 computation standard with little-endian input bit-string representation automatic padding to complete the input bit string to fit modulo 512 (16 32 bits) message digest computing fast computation of sha-1 and md5 5 32-bit words (h0, h1, h2, h3 and h4) for output message digest, reload able to continue interrupted message digest computation corresponding 32-bit words of the digest from consecutive message blocks are added to each other to form the digest of the whole message automatic data flow control with support for direct memory access (dma) note: padding, as defined in the sha-1 algorithm, consists in adding a bit at bx1 followed by n bits at bx0 to get a total length congruent to 448 modulo 512. after this, the message is completed with a 64-bit integer which is the binary representation of the original message length. for this hash processor, the quanta for entering the message is a 32-bit word, so an additional information must be provided at the end of the message entry, which is the number of valid bits in the last 32-bit word entered. hash processor (hash) RM0033 524/1317 doc id 15403 rev 3 21.3 hash functional description figure 211 shows the block diagram of the hash processor. figure 211. block diagram the fips pub 180-2 standard and the ietf rfc 1321 publication specify the sha-1 and md5 secure hash algorithms, respectively, fo r computing a condensed representation of a message or data file. when a message of any length below 2 64 bits is provided on input, the sha-1 and md5 produce a 160-bit and 128-bit output string, respectively, called a message digest. the message digest can then be processed with a digital signature algorithm in order to generate or verify the signature for the message. signing the message digest rather than the message often improves the efficiency of the process because the message digest is usually much smaller in size than the message. the verifier of a digital signature has to use the same hash algorithm as the one used by the creator of the digital signature. the sha-1 and md5 are qualified as ?secure? because it is computationally infeasible to find a message that corresponds to a given message digest, or to find two different messages that produce the same message digest. any ch ange to a message in transit will, with very high probability, result in a diff erent message digest, and the signature will fail to verify. for more detail on the sha-1 algorithm, please refer to the fips pub 180-2 (federal information processing standards publication 180-2), 2002 august 1. the current implementation of this standard works with little-endian input data convention. for example, the c string ?abc? must be represented in memory as the 24-bit hexadecimal value 0x434241. a message or data file to be processed by the hash processor should be considered a bit string. the length of the message is the number of bits in the message (the empty message b i t ! ( " b u s ( a s h ( - ! # 3 ( ! - $ ( ! 3 ( ? $ ) . s w a p p i n g b i t ) . & ) & / ( ! 3 ( ? # 2 ( ! 3 ( ? ( ( ( ! 3 ( ? # 3 2 c o n t e x t d i g e s t ( ! 3 ( ? ) - 2 ( ! 3 ( ? 3 2 ) n t e r r u p t r e g i s t e r s # o n t r o l r e g i s t e r # o n t e x t s w a p p i n g - e s s a g e d i g e s t p r o c e s s o r c o r e ( ! 3 ( ? 3 4 2 3 t a r t r e g i s t e r ) . & ) & / f u l l w r i t e i n t o ( ! 3 ( ? $ ) . # o n t r o l a n d s t a t u s r e g i s t e r s $ a t a r e g i s t e r o r w r i t e $ # ! , b i t t o o r c o m p l e t e b l o c k o r $ # ! , w r i t t e n t o ) . b u f f e r t r a n s f e r r e d b y t h e $ - ! a i RM0033 hash processor (hash) doc id 15403 rev 3 525/1317 has length 0). you can consider that 32 bits of this bit string forms a 32-bit word. note that the fips pub 180-1 standard uses the convention that bit strings grow from left to right, and bits can be grouped as bytes (8 bits) or words (32 bits) (but some implementations also use half-words (16 bits), and implicitly, uses th e big-endian byte (half-word) ordering. this convention is mainly important for padding (see section 21.3.4: message padding on page 527 ). 21.3.1 duration of the processing the computation of an intermediate block of a message takes: 66 hclk clock cycles in sha-1 50 hclk clock cycles in md5 to which you must add the time needed to load the 16 words of the block into the processor (at least 16 clock cycles for a 512-bit block). the time needed to process the last block of a message (or of a key in hmac) can be longer because it includes the padding. this time depends on the length of the last block and the size of the key (in hmac mode). compared to the processing of an intermediate block, it can be increased by a factor of: 1 to 2.5 for a hash message around 2.5 for an hmac input-key 1 to 2.5 for an hmac message around 2.5 for an hmac output key in case of a short key 3.5 to 5 for an hmac output key in case of a long key 21.3.2 data type data are entered into the hash processor 32 bits (word) at a time, by writing them into the hash_din register. but the original bit-string can be organized in bytes, half-words or words, or even be represented as bits. as the system memory organization is little-endian and sha1 computation is big-endian, depending on the way the original bit string is grouped, a bit, byte, or half-word swapping operation is performed automatically by the hash processor. the kind of data to be proc essed is configured with the datatype bitfield in the hash control register (hash_cr). hash processor (hash) RM0033 526/1317 doc id 15403 rev 3 figure 212. bit, byte and half-word swapping the least significant bit of the message has to be at position 0 (right) in the first word entered into the hash processor, the 32nd bit of the bit string has to be at position 0 in the second word entered into the hash processor and so on. 21.3.3 message digest computing the hash sequentially processes blocks of 512 bits when computing the message digest. thus, each time 16 32-bit words (= 512 bits) have been written by the dma or the cpu, into the hash processor, the hash automatically starts computing the message digest. this operation is known as a partial digest computation. the message to be processed is entered into the peripheral by 32-bit words written into the hash_din register. the current contents of th e hash_din register are transferred to the input fifo (in fifo) each time the register is written with new data. hash_din and the input fifo form a fifo of a 17-word length (named the in buffer). " y t e " y t e " y t e " y t e b i t s b i t s b i t s b i t s ( ! 3 ( ? $ ) . b i t s t r i n g b i t b i t b i t b i t b i t " i t s w a p p i n g o p e r a t i o n b i t s t r i n g g r o w s i n t h i s d i r e c t i o n a s d e f i n e d b y & ) 0 3 0 5 " s t d b i t b i t b i t b i t b i t ( ! 3 ( ? $ ) . b i t s t r i n g " y t e s w a p p i n g o p e r a t i o n b i t s t r i n g g r o w s i n t h i s d i r e c t i o n a s d e f i n e d b y & ) 0 3 0 5 " s t d " y t e " y t e " y t e " y t e b i t s b i t s b i t s b i t s ( ! 3 ( ? $ ) . b i t s t r i n g ( a l f w o r d s w a p p i n g o p e r a t i o n b i t s t r i n g g r o w s i n t h i s d i r e c t i o n a s d e f i n e d b y & ) 0 3 0 5 " s t d ( a l f w o r d b i t s $ ! 4 ! 4 9 0 % b x $ ! 4 ! 4 9 0 % b x $ ! 4 ! 4 9 0 % b x ( a l f w o r d b i t s ( a l f w o r d b i t s ( a l f w o r d b i t s t - t t - p a d d i n g i s p e r f o r m e d o n t h i s s i d e o f t h e b i t s t r i n g a i RM0033 hash processor (hash) doc id 15403 rev 3 527/1317 the processing of a block can start only once the last value of the block has entered the in fifo. the peripheral must get the information as to whether the hash_din register contains the last bits of the message or not. two cases may occur: when the dma is not used: ? in case of a partial digest computation, this is done by writing an additional word into the hash_din register (actually the first word of the next block). then the software must wait until the processor is ready again (when dinis=1) before writing new data into hash_din. ? in case of a final digest computation (last block entered), this is done by writing the dcal bit to 1. when the dma is used: the contents of the hash_din register are interpreted automatically with the information sent by the dma controller. this process ?data entering + partial digest computation? continues until the last bits of the original message are written to the hash_din register. as the length (number of bits) of a message can be any integer value, the last word written into the hash processor may have a valid number of bits between 1 and 32. this number of valid bits in the last word, nblw, has to be written into the hash_str register, so that message padding is correctly performed before the final message digest computation. once this is done, writing into hash_str with bi t dcal = 1 starts the processing of the last entered block of message by the hash processor. this processing consists in: automatically performing the message padding operation: the purpose of this operation is to make the total length of a padded message a multiple of 512. the hash sequentially processes blocks of 512 bits when computing the message digest computing the final message digest when the dma is enabled, it provides the information to the hash processor when it is transferring the last data word. then the padding and digest computation are performed automatically as if dcal had been written to 1. 21.3.4 message padding message padding consists in appending a ?1? followed by m ?0?s followed by a 64-bit integer to the end of the original message to produce a padded message block of length 512. the ?1? is added to the last word written into the hash_din register at the bit position defined by the nblw bitfield, and the remaining upper bits are cleared (?0?s). example: let us assume that the original mess age is the ascii binary-coded form of ?abc?, of length l = 24: byte 0 byte 1 byte 2 byte 3 01100001 01100010 01100011 uuuuuuuu <-- 1st word written to hash_din --> nblw has to be loaded with the value 24: a ?1? is appended at bit location 24 in the bit string (starting counting from left to right in the above bit string), which corresponds to bit 31 in the hash_din register (little-endian convention): 01100001 01100010 01100011 1uuuuuuu since l = 24, the number of bits in the above bit string is 25, and 423 ?0?s are appended, making now 448. this gives (in hexadecimal, big-endian format): hash processor (hash) RM0033 528/1317 doc id 15403 rev 3 61626380 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 the l value, in two-word representation (that is 00000000 00000018) is appended. hence the final padded message in hexadecimal: 61626380 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000028 if the hash is programmed to use the little-endian byte input format, the above message has to be entered by doing the following steps: 1. 0xuu636261 is written into the hash_d in register (where ?u? means don?t care) 2. 0x18 is written into the hash_str register (the number of valid bits in the last word written into the hash_din register is 24, as the original message length is 24 bits) 3. 0x10 is written into the hash_str regist er to start the message padding and digest computation. when nblw 0x00, the message padding puts a ?1? into the hash_din register at the bit position defined by the nblw value, and inserts ?0?s at bit locations [31:(nblw+1)]. when nblw == 0x00, the message padding inserts one new word with value 0x0000 0001. then an all zero word (0x0000 0000) is added and the message length in a two-word representation, to get a block of 16 x 32-bit words. 4. the hash computing is performed, and the message digest is then available in the hash_hx registers (x = 0...4) for the sha-1 algorithm. for example: h0 = 0xa9993e36 h1 = 0x4706816a h2 = 0xba3e2571 h3 = 0x7850c26c h4 = 0x9cd0d89d 21.3.5 hash operation the hash function (sha-1, md5) is selected when the init bit is written to ?1? in the hash_cr register while the mode bit is at ?0? in hash_cr. the algorithm (sha-1 or md5) is selected at the same time (that is when the init bit is set) using the algo bit. the message can then be sent by writing it word by word into the hash_din register. when a block of 512 bits ?that is 16 words? has been written, a partial digest computation starts upon writing the first data of the next block. the hash processor remains busy for 66 cycles for the sha-1 algorithm or 50 cycles for the md5 algorithm. the process can then be repeated until the last word of the message. if dma transfers are used, refer to the procedure where the data are loaded by dma section. otherwise, if the message length is not an exact multiple of 512 bits, then the hash_str register has to be written to launch the computation of the final digest. once computed, the digest can be read from the hash_h0...hash_h4 registers (for the md5 algorithm, hash_h4 is not relevant). RM0033 hash processor (hash) doc id 15403 rev 3 529/1317 21.3.6 hmac operation the hmac algorithm is used for message authentication, by irreversibly binding the message being processed to a key chosen by the user. for hmac specifications, refer to ?hmac: keyed-hashing for message authentication, h. krawczyk, m. bellare, r. canetti, february 1997. basically, the algorithm consists of two nested hash operations: hmac(message) = hash[((key | pad) xor 0x5c) | hash(((key | pad) xor 0x36) | message)] where: pad is a sequence of zeroes needed to extend the key to the length of the underlying hash function data block (that is 512 bits for both the sha-1 and md5 hash algorithms) | represents the concatenation operator to compute the hmac, four different phases are required: 1. the block is initialized by writing the init bit to ?1? with the mode bit at ?1? and the algo bit set to the value corresponding to the desired algorithm . the lkey bit must also be set during this phase if the key being used is longer than 64 bytes (in this case, the hmac specifications specify that the hash of the key should be used in place of the real key). 2. the key (to be used for the inner hash function) is then given to the core. this operation follows the same mechanism as the one used to send the message in the hash operation (that is, by writing into ha sh_din and, finally, into hash_str). 3. once the last word has been entered and computation has started, the hash processor elaborates the key. it is then ready to accept the message text using the same mechanism as the one used to send the message in the hash operation. 4. after the first hash round, the hash processor returns ?ready? to indicate that it is ready to receive the key to be used for the outer hash function (normally, this key is the same as the one used for the inner hash function). when the last word of the key is entered and computation starts, the hmac result is made available in the hash_h0...hash_h4 registers. note: 1 the computation latency of the hmac primitive depends on the lengths of the keys and message. you could the hmac as two nested underlying hash functions with the same key length (long or short). 21.3.7 context swapping it is possible to interrupt a hash/hmac process to perform another processing with a higher priority, and to complete the interrupted process later on, when the higher-priority task is complete. to do so, the context of the interrupted task must be saved from the hash registers to memory, and then be restored from memory to the hash registers. the procedures where the data flow is controlled by software or by dma are described below. hash processor (hash) RM0033 530/1317 doc id 15403 rev 3 procedure where the data are loaded by software the context can be saved only when no block is currently being processed. that is, you must wait for dinis = 1 (the last block has been processed and the input fifo is empty) or nbw 0 (the fifo is not full and no processing is ongoing). context saving: store the contents of the following registers into memory: ? hash_imr ? hash_str ? hash_cr ? hash_csr0 to hash_csr50 context restoring: the context can be restored when the high-priority task is complete. please follow the order of the sequence below. a) write the following registers with the values saved in memory: hash_imr, hash_str and hash_cr b) initialize the hash processor by setting the init bit in the hash_cr register c) write the hash_csr0 to hash_csr50 registers with the values saved in memory you can now restart the processing from the point where it has been interrupted. procedure where the data are loaded by dma in this case it is not possible to predict if a dma transfer is in progress or if the process is ongoing. thus, you must stop the dma transfers, then wait until the hash is ready in order to interrupt the processing of a message. interrupting a processing: ? clear the dmae bit to disable the dma interface ? wait until the current dma transfer is complete (wait for dmaes = 0 in the hash_sr register). note that the block may or not have been totally transferred to the hash. ? disable the corresponding channel in the dma controller ? wait until the hash processor is ready (no bl ock is being processed), that is wait for dinis = 1 the context saving and context restoring phases are the same as above (see procedure where the data are loaded by software ). reconfigure the dma controller so that it transfers the end of the message. you can now restart the processing from the point where it was interrupted by setting the dmae bit. note: 1 if context swapping does not involve hmac operations, the hash_csr38 to hash_csr50 registers do not have to be saved and restored. 2 if context swapping occurs between two blocks (the last block was completely processed and the next block has not yet been pushed into the in fifo, nbw = 000 in the hash_cr register), the hash_csr22 to hash_csr37 registers do not have to be saved and restored. RM0033 hash processor (hash) doc id 15403 rev 3 531/1317 21.3.8 hash interrupt there are two individual maskable interrupt sources generated by the hash processor. they are connected to the same interrupt vector. you can enable or disable the interrupt sources individually by changing the mask bits in the hash_imr register. setting the appropriate mask bit to 1 enables the interrupt. the status of the individual interrupt sources can be read from the hash_sr register. figure 213. hash interrupt mapping diagram 21.4 hash registers the hash core is associated with several control and status registers and five message digest registers. all these registers are accessible through word accesses only, else an ahb error is generated. $ # ) 3 $ # ) - $ ) . ) 3 $ ) . ) - ( ! 3 ( i n t e r r u p t t o . 6 ) # a i hash processor (hash) RM0033 532/1317 doc id 15403 rev 3 21.4.1 hash control re gister (hash_cr) address offset: 0x00 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved lkey rw 1514131211109876543210 reserved dinne nbw algo mode datatype dmae init reserved r r r r r rw rw rw rw rw w bits 31:17 reserved, forced by hardware to 0. bit 16 lkey: long key selection this bit selects between short key ( 64 bytes) or long key (> 64 bytes) in hmac mode 0: short key ( 64 bytes) 1: long key (> 64 bytes) note: this selection is only ta ken into account when the init bit is set and mode = 1. changing this bit during a computation has no effect. bits 15:13 reserved, forced by hardware to 0. bit 12 dinne: din not empty this bit is set when the hash_din register ho lds valid data (that is after being written at least once). it is cleared when either the init bit (initialization) or the dcal bit (completion of the previous message processing) is written to 1. 0: no data are present in the data input buffer 1: the input buffer contains at least one word of data bits 11:8 nbw: number of words already pushed this bitfield reflects the number of words in the message that have already been pushed into the in fifo. nbw increments (+1) when a write access is performed to the hash_din register while dinne = 1. it goes to 0000 when the init bit is written to 1 or when a digest calculation starts (dcal written to 1 or dma end of transfer). if the dma is not used: 0000 and dinne=0: no word has been pushed into the din buffer (the buffer is empty, both the hash_din register and the in fifo are empty) 0000 and dinne=1: 1 word has been pushed into the din buffer (the hash_din register contains 1 word, the in fifo is empty) 0001: 2 words have been pushed into the din buffer (the hash_din register and the in fifo contain 1 word each) ... 1111: 16 words have been pushed into the din buffer if the dma is used, nbw is the exact number of words that have been pushed into the in fifo. RM0033 hash processor (hash) doc id 15403 rev 3 533/1317 bit 7 algo: algorithm selection this bit selects the sha-1 or the md5 algorithm: 0: sha-1 algorithm selected 1: md5 algorithm selected note: this selection is only take n into account when the init bi t is set. changing this bit during a computation has no effect. bit 6 mode: mode selection this bit selects the hash or hmac mode for the selected algorithm: 0: hash mode selected 1: hmac mode selected. lkey must be set if the key being used is longer than 64 bytes. note: this selection is only take n into account when the init bi t is set. changing this bit during a computation has no effect. bits 5:4 datatype: data type selection defines the format of the data entered into the hash_din register: 00: 32-bit data. the data written into hash_din are directly used by the hash processing, without reordering. 01: 16-bit data, or half-word. the data writ ten into hash_din are considered as 2 half- words, and are swapped before being used by the hash processing. 10: 8-bit data, or bytes. the data written into hash_din are considered as 4 bytes, and are swapped before being used by the hash processing. 11: bit data, or bit-string. the data written into hash_din are considered as 32 bits (1st bit of the sting at position 0), and are swapped be fore being used by the hash processing (1st bit of the string at position 31). bit 3 dmae: dma enable 0: dma transfers disabled 1: dma transfers enabled. a dma request is sent as soon as the hash core is ready to receive data. note: 1: this bit is cleared by hardware when the dma asserts the dma terminal count signal (while transferring the last data of the messa ge). this bit is not cleared when the init bit is written to 1. 2: if this bit is written to 0 while a dm a transfer has already been requested to the dma, dmae is cleared but the current tr ansfer is not aborted. instead, the dma interface remains internally enabled until the tran sfer is complete or init is written to 1. bit 2 init: initialize message digest calculation writing this bit to 1 resets the hash processor core, so that the hash is ready to compute the message digest of a new message. writing this bit to 0 has no effect. reading this bit always return 0. bit 1:0 reserved, must be kept cleared. hash processor (hash) RM0033 534/1317 doc id 15403 rev 3 21.4.2 hash data input register (hash_din) address offset: 0x04 reset value: 0x0000 0000 hash_din is the data input register. it is 32-bit wide. it is used to enter the message by blocks of 512 bits. when the hash_din register is written to, the value presented on the ahb databus is ?pushed? into the hash core and the register takes the new value presented on the ahb databus. the datatype bits must previously have been configured in the hash_cr register to get a correct message representation. when a block of 16 words has been written to the hash_din register, an intermediate digest calculation is launched: by writing new data into the hash_din register (the first word of the next block) if the dma is not used (intermediate digest calculation) automatically if the dma is used when the last block has been written to the ha sh_din register, the final digest calculation (including padding) is launched: by writing the dcal bit to 1 in the hash_s tr register (final digest calculation) automatically if the dma is used when a digest calculation (intermediate or final) is in progress, any new write access to the hash_din register is extended (by wait-state insertion on the ahb bus) until the hash calculation completes. when the hash_din register is read, the last wo rd written in this loca tion is accessed (zero after reset). . 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 datain rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 datain rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bit 31:0 datain: data input read = returns the current register content. write = the current register cont ent is pushed into the in fifo, and the register takes the new value presented on the ahb databus. RM0033 hash processor (hash) doc id 15403 rev 3 535/1317 21.4.3 hash start r egister (hash_str) address offset: 0x08 reset value: 0x0000 0000 the hash_str register has two functions: it is used to define the number of valid bits in the last word of the message entered in the hash processor (that is the number of valid least significant bits in the last data written into the hash_din register) it is used to start the processing of the last block in the message by writing the dcal bit to 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 reserved dcal reserved nblw w rwrwrwrwrw bits 31:9 reserved, forc ed by hardware to 0. bit 8 dcal: digest calculation writing this bit to 1 starts the message padding, using the previously written value of nblw, and starts the calculation of the final message digest with all data words written to the in fifo since the init bit was last written to 1. reading this bit returns 0. bits 7:5 reserved, forced by hardware to 0. bits 4:0 nblw: number of valid bits in the last word of the message when these bits are written and dcal is at ?0 ?, they take the value on the ahb databus: 0x00: all 32 bits of the last data written in the hash_din register are valid 0x01: only bit [0] of the last data wri tten in the hash_din register is valid 0x02: only bits [1:0] of the last data wr itten in the hash_din register are valid 0x03: only bits [2:0] of the last data wr itten in the hash_din register are valid ... 0x1f: only bits [30:0] of the last data written in the hash_din register are valid when these bits are written and dcal is at ?1?, the bitfield is not changed. reading them returns the la st value written to nblw. note: these bits must be configured before setting the dcal bit, else they are not taken into account. especially, it is not possible to configure nblw and set dcal at the same time. hash processor (hash) RM0033 536/1317 doc id 15403 rev 3 21.4.4 hash digest regi sters (hash_hr0...4) address offset: 0x0c to 0x1c reset value: 0x0000 0000 these registers contain the message digest result named as h0, h1, h2, h3 and h4, respectively, in the hash algorithm description, and as a, b, c and d, respectively, in the md5 algorithm description (note that in this case, the hash_h4 register is not used, and is read as zero). if a read access to one of these registers occurs while the hash core is calculating an intermediate digest or a final message digest (that is when the dcal bit has been written to 1), then the access on the ahb bus is extended until the completion of the hash calculation. hash_hr0 (address offset: 0x0c) hash_hr1 (address offset: 0x10) hash_hr2 (address offset: 0x14) hash_hr3 (address offset: 0x18) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 h0 rrrrrrrrrrrrrrrr 1514131211109876543210 h0 rrrrrrrrrrrrrrrr 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 h1 rrrrrrrrrrrrrrrr 1514131211109876543210 h1 rrrrrrrrrrrrrrrr 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 h2 rrrrrrrrrrrrrrrr 1514131211109876543210 h2 rrrrrrrrrrrrrrrr 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 h3 rrrrrrrrrrrrrrrr 1514131211109876543210 h3 rrrrrrrrrrrrrrrr RM0033 hash processor (hash) doc id 15403 rev 3 537/1317 hash_hr4 (address offset: 0x1c) note: when starting a digest computation for a new bit stream (by writing the init bit to 1), these registers assume their reset values. 21.4.5 hash interrupt enable register (hash_imr) address offset: 0x20 reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 h4 rrrrrrrrrrrrrrrr 1514131211109876543210 h4 rrrrrrrrrrrrrrrr 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 reserved dcie dinie rw rw bits 31:2 reserved, forced by hardware to 0. bit 1 dcie: digest calculation completion interrupt enable 0: digest calculation completion interrupt disabled 1: digest calculation completion interrupt enabled. bit 0 dinie: data input interrupt enable 0: data input interrupt disabled 1: data input interrupt enabled hash processor (hash) RM0033 538/1317 doc id 15403 rev 3 21.4.6 hash status r egister (hash_sr) address offset: 0x24 reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 reserved busy dmas dcis dinis rrrc_w0rc_w0 bits 31:4 reserved, forced by hardware to 0. bit 3 busy: busy bit 0: no block is currently being processed 1: the hash core is processing a block of data bit 2 dmas: dma status this bit provides information on the dma interface activity. it is set with dmae and cleared when dmae=0 and no dma transfer is ongoing. no interrupt is associated with this bit. 0: dma interface is disabled (dmae=0) and no transfer is ongoing 1: dma interface is enabled (dmae=1) or a transfer is ongoing bit 1 dcis: digest calculation completion interrupt status this bit is set by hardware when a digest becomes ready (the whole message has been processed). it is cleared by writing it to 0 or by writing the init bit to 1 in the hash_cr register. 0: no digest available in the hash_hx registers 1: digest calculation complete, a digest is ava ilable in the hash_hx registers. an interrupt is generated if the dcie bit is set in the hash_imr register. bit 0 dinis: data input interrupt status this bit is set by hardware when the input buffer is ready to get a new block (16 locations are free). it is cleared by writing it to 0 or by writing the hash_din register. 0: less than 16 locations are free in the input buffer 1: a new block can be entered into the input buff er. an interrupt is generated if the dinie bit is set in the hash_imr register. RM0033 hash processor (hash) doc id 15403 rev 3 539/1317 21.4.7 hash context swap regi sters (hash_csr0...50) address offset: 0x0f8 to 0x1c0 reset value: 0x0000 0000 these registers contain the complete internal register states of the hash processor, and are useful when a context swap has to be done because a high-priority task has to use the hash processor while it is already in use by another task. when such an event occurs, the hash_csrx registers have to be read and the read values have to be saved somewhere in the system memory space. then the hash processor can be used by the preemptive task, and when hash computation is finished, the saved context can be read from memory and written back into these hash_csrx registers. hash_csrx (address offset: 0x0f8 to 0x1c0) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 csx rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 csx rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw hash processor (hash) RM0033 540/1317 doc id 15403 rev 3 21.4.8 hash register map ta bl e 7 6 gives the summary hash register map and reset values. table 76. hash register map and reset values offset register name reset value register size 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 hash_cr reserved lkey reserved dinne nbw algo mode datatype dmae init reserved reset value 0 00000000000 0x04 hash_din datain reset value 00000000000000000000000000000000 0x08 hash_str reserved dcal reserved nblw reset value 0 00000 0x0c hash_hr0 h0 reset value 00000000000000000000000000000000 0x10 hash_hr1 h1 reset value 00000000000000000000000000000000 0x14 hash_hr2 h2 reset value 00000000000000000000000000000000 0x18 hash_hr3 h3 reset value 00000000000000000000000000000000 0x1c hash_hr4 h4 reset value 00000000000000000000000000000000 0x20 hash_imr reserved dcie dinie reset value 00000000000000000000000000000000 0x24 hash_sr reserved busy dmas dcis dinis reset value 0001 0xf8 hash_csr0 csr0 reset value 00000000000000000000000000000000 ... ... 0x1c0 hash_csr50 csr50 reset value 00000000000000000000000000000000 RM0033 real-time clock (rtc) doc id 15403 rev 3 541/1317 22 real-time clock (rtc) 22.1 introduction the real-time clock (rtc) is an independent bcd timer/counter. the rtc provides a time- of-day clock/calendar, two programmable alarm interrupts, and a periodic programmable wakeup flag with interrupt capability. the rtc also includes an automatic wakeup unit to manage low power modes. two 32-bit registers contain the seconds, minutes, hours (12- or 24-hour format), day (day of week), date (day of month), month, and year, expressed in binary coded decimal format (bcd). compensations for 28-, 29- (leap year), 30-, and 31-day months are performed automatically. daylight saving time compensation can also be performed. additional 32-bit registers contain the programmable alarm seconds, minutes, hours, day, and date. a digital calibration feature is available to co mpensate for any deviation in crystal oscillator accuracy. after power-on reset, all rtc registers are protected against possible parasitic write accesses. as long as the supply voltage remains in the operating range, the rtc never stops, regardless of the device status (run mode, low power mode or under reset). real-time clock (rtc) RM0033 542/1317 doc id 15403 rev 3 22.2 rtc main features the rtc unit main features are the following (see figure 214: rtc block diagram ): calendar with seconds, minutes, hours (12 or 24 format), day (day of week), date (day of month), month, and year. daylight saving compensation programmable by software. two programmable alarms with interrupt function. the alarms can be triggered by any combination of the calendar fields. automatic wakeup unit generating a periodic flag that triggers an automatic wakeup interrupt. reference clock detection: a more precise se cond source clock (50 or 60 hz) can be used to enhance the calendar precision. maskable interrupts/events: ?alarm a ?alarm b ? wakeup interrupt ? time-stamp ? tamper detection digital calibration circuit (periodic counter correction) ? 5 ppm accuracy time-stamp function for event saving (1 event) tamper detection: ? 1 tamper event on edge detection 20 backup registers (80 bytes). the backup registers are reset when a tamper detection event occurs. rtc alternate function outputs (rtc_afo): ? afo_calib: 512 hz clock output (with an lse frequency of 32.768 khz). it is routed to the device rtc_af1 pin. ? afo_alarm: alarm a or alarm b or wakeup (only one can be selected). it is routed to the device rtc_af1 pin. rtc alternate function inputs (rtc_afi): ? afi_tamper: tamper event detection. it is routed to the device rtc_af1 and rtc_af2 pins. ? afi_timestamp: timestamp event detection. it is routed to the device rtc_af1 and rtc_af2 pins. note: refer to section 6.3.15: selection of rtc_af1 and rtc_af2 alternate functions for more details on how to select rtc alternate functions (rtc_af1 and rtc_af2). RM0033 real-time clock (rtc) doc id 15403 rev 3 543/1317 figure 214. rtc block diagram 1. on stm32f20xx devices, the rtc_af1 and rtc_af2 alternat e functions are connected to pc13 and pi8, respectively. 22.3 rtc functional description 22.3.1 clock and prescalers the rtc clock source (rtcclk) is selected through the clock controller among the lse clock, the lsi oscillator clock, and the hse clock. for more information on the rtc clock source configuration, refer to section 5: reset and clock control (rcc) . a programmable prescaler stage generates a 1 hz clock which is used to update the calendar. to minimize power consumption, the prescaler is split into 2 programmable prescalers (see figure 214: rtc block diagram ): a 7-bit asynchronous prescaler configured through the prediv_a bits of the rtc_prer register. a 13-bit synchronous prescaler configured through the prediv_s bits of the rtc_prer register. note: when both prescalers are used, it is recommended to configure the asynchronous prescaler to a high value to minimize consumption. a i c c k ? a p r e d e f a u l t ( z c k ? s p r e d e f a u l t ( z ! & / ? # ! , ) " ( z 2 4 # ? 7 5 4 2 2 4 # # , + 7 5 4 & ( 3 % - ( z m a x , 3 % ( z , 3 ) ! s y n c h b i t p r e s c a l e r d e f a u l t 3 y n c h r o n o u s b i t p r e s c a l e r d e f a u l t # a l e n d a r 0 r e s c a l e r b i t w a k e u p a u t o r e l o a d t i m e r ! l a r m 2 4 # ? ! , 2 - ! 2 r e g i s t e r ! , 2 ! & ! & / ? ! , ! 2 - 2 4 # ? 0 2 % 2 2 4 # ? 0 2 % 2 3 h a d o w r e g i s t e r s 2 4 # ? 4 2 2 4 # ? $ 2 c k ! l a r m 2 4 # ? ! , 2 - " 2 r e g i s t e r ! , 2 " & " a c k u p r e g i s t e r s a n d 2 4 # t a m p e r c o n t r o l r e g i s t e r s ! & ) ? 4 ! - 0 % 2 4 i m e s t a m p r e g i s t e r s ! & ) ? 4 ) - % 3 4 ! - 0 4 i m e s t a m p f l a g / u t p u t c o n t r o l 4 ! - 0 % 4 3 % 2 4 # ? ! & 2 4 # ? ! & 2 4 # ? ! & / 2 4 # ? ! & ) 2 4 # ? ! & ) 7 5 # + 3 % , ; = 7 5 # + 3 % , ; = 0 e r i o d i c w a k e u p f l a g # o a r s e c a l i b r a t i o n 2 4 # ? ( z real-time clock (rtc) RM0033 544/1317 doc id 15403 rev 3 the asynchronous prescaler division factor is set to 128, and the synchronous division factor to 256, to obtain an internal clock frequency of 1 hz (ck_spre) with an lse frequency of 32.768 khz. the minimum division factor is 2 and the maximum division factor is 2 20 . this corresponds to a maximum input frequency of around 1 mhz. f ck_spre is given by the following formula: the ck_spre clock can be used either to update the calendar or as timebase for the 16-bit wakeup auto-reload timer. to obtain short timeout periods, the 16-bit wakeup auto-reload timer can also run with the rtcclk divided by the programmable 4-bit asynchronous prescaler (see section 22.3.4: periodic auto-wakeup for details). 22.3.2 real-time clock and calendar the rtc calendar time and date registers are accessed through shadow registers which are synchronized with pclk1 (apb1 clock): rtc_tr for the time rtc_dr for the date every two rtcclk periods, the current calendar value is copied into the shadow registers, and the rsf bit of rtc_isr register is set (see section 22.6.4 ). the copy is not performed in stop and standby mode. when exiting these modes, the shadow registers are updated after up to 2 rtcclk periods. when the application reads the calendar registers, it accesses the content of the shadow registers. when reading the rtc_tr or rtc_dr registers, the frequency of the apb clock (f apb ) must be at least 7 times the frequency of the rtc clock (f rtcclk ). the shadow registers are reset by system reset. 22.3.3 programmable alarms the rtc unit provides two programmable alarms, alarm a and alarm b. the programmable alarm functions are enabled through the alrae and alrbe bits in the rtc_cr register. the alraf and alrbf flags are set to 1 if the calendar seconds, minutes, hours, date or day match the values programmed in the alarm registers rtc_alrmar and rtc_alrmbr, respectively. each calendar field can be independently selected through the mskx bits of the rtc_alrmar and rtc_alrmbr registers. the alarm interrupts are enabled through the alraie and alrbe bits in the rtc_cr register. alarm a and alarm b (if enabled by bits osel[0:1] in rtc_cr register) can be routed to the afo_alarm output. afo_alarm polarity can be configured through bit pol the rtc_cr register. caution: if the seconds field is selected (msk0 bit reset in rtc_alrmar or rtc_alrmbr), the synchronous prescaler division factor set in the rtc_prer register must be at least 3 to ensure correct behavior. f ck_spre f rtcclk prediv_s 1 + () previd_a 1 + () ---------------------------------------------------------------------------------------------- = RM0033 real-time clock (rtc) doc id 15403 rev 3 545/1317 22.3.4 periodic auto-wakeup the periodic wakeup flag is generated by a 16-bit programmable auto-reload down-counter. the wakeup timer range can be extended to 17 bits. the wakeup function is enabled through the wute bit in the rtc_cr register. the wakeup timer clock input can be: rtc clock (rtcclk) divided by 2, 4, 8, or 16. when rtcclk is lse(32.768khz), this allows to configure the wakeup interrupt period from 122 s to 32 s, with a resolution down to 61s. ck_spre (usually 1 hz internal clock) when ck_spre frequency is 1hz, this allows to achieve a wakeup time from 1 s to around 36 hours with one-second resolution. this large programmable time range is divided in 2 parts: ? from 1s to 18 hours when wucksel [2:1] = 10 ? and from around 18h to 36h when wucksel[2:1] = 11. in this last case 2 16 is added to the 16-bit counter current valu e.when the initializ ation sequence is complete (see programming the wakeup timer on page 547 ), the timer starts counting down.when the wakeup function is enabled, the down-counting remains active in low power modes. in addition, when it reaches 0, the wutf flag is set in the rtc_isr register, and the wakeup counter is automatically reloaded with its reload value (rtc_wutr register value). the wutf flag must then be cleared by software. when the periodic wakeup interrupt is enabled by setting the wutie bit in the rtc_cr2 register, it can exit the device from low power modes. the periodic wakeup flag can be routed to the afo_alarm output provided it has been enabled through bits osel[0:1] of rtc_cr register. afo_alarm polarity can be configured through the pol bit in the rtc_cr register. system reset, as well as low power modes (sleep, stop and standby) have no influence on the wakeup timer. 22.3.5 rtc initialization and configuration rtc register access the rtc registers are 32-bit registers. the apb interface introduces 2 wait-states in rtc register accesses. rtc register write protection after power-on reset, all the rtc registers are write-protected. writing to the rtc registers is enabled by writing a key into the write protection register, rtc_wpr. the following steps are required to unlock the write protection on all the rtc registers except for rtc_isr[13:8], rtc_tafcr, and rtc_bkpxr. 1. write ?0xca? into the rtc_wpr register. 2. write ?0x53? into the rtc_wpr register. writing a wrong key reactivates the write protection. the protection mechanism is not affected by system reset. real-time clock (rtc) RM0033 546/1317 doc id 15403 rev 3 calendar initialization and configuration to program the initial time and date calendar values, including the time format and the prescaler configuration, the following sequence is required: 1. set init bit to 1 in the rtc_isr register to enter initialization mode. in this mode, the calendar counter is stopped and its value can be updated. 2. poll initf bit of in the rtc_isr register. the initialization phase mode is entered when initf is set to 1. it takes around 2 rtcclk clock cycles (due to clock synchronization). 3. to generate a 1 hz clock for the calendar counter, program first the synchronous prescaler factor in rtc_prer register, and then program the asynchronous prescaler factor. even if only one of the two fields needs to be changed, 2 separate write accesses must be performed to the tc_prer register. 4. load the initial time and date values in the shadow registers (rtc_tr and rtc_dr), and configure the time format (12 or 24 hours) through the fmt bit in the rtc_cr register. 5. exit the initialization mode by clearing the init bit. the actual calendar counter value is then automatically loaded and the counting restarts after 4 rtcclk clock cycles. when the initialization sequence is complete, the calendar starts counting. note: 1 after a system reset, the application can read the inits flag in the rtc_isr register to check if the calendar has been initialized or not. if this flag equals 0, the calendar has not been initialized since the year field is set at its power-on reset default value (0x00). 2 to read the calendar after initialization, the software must first check that the rsf flag is set in the rtc_isr register. daylight saving time the daylight saving time m anagement is performe d through bits sub1h, add1h, and bkp of the rtc_cr register. using sub1h or add1h, the software can subtract or add one hour to the calendar in one single operation without going through the initialization procedure. in addition, the software can use the bkp bit to memorize this operation. programming the alarm a similar procedure must be followed to program or update the programmable alarm (alarm a or alarm b): 1. clear alrae or alrbe in rtc_cr to disable alarm a or alarm b. 2. poll alrawf or alrbwf in rtc_isr until it is set to make sure the access to alarm registers is allowed. in medium density devices, this takes around 2 rtcclk clock cycles (due to clock synchronization). in high density devices, alrawf and alrbwf are always set, so this step can be skipped. 3. program the alarm a or alarm b re gisters (rtc_alrmar or rtc_alrmbr). 4. set alrae or alrbe in the rtc_cr register to enable alarm a or alarm b again. note: each change of the rtc_cr register is taken into account after around 2 rtcclk clock cycles due to clock synchronization. RM0033 real-time clock (rtc) doc id 15403 rev 3 547/1317 programming the wakeup timer the following sequence is required to configure or change the wakeup timer auto-reload value (wut[15:0] in rtc_wutr): 1. clear wute in rtc_cr to disable the wakeup timer. 2. poll wutwf until it is set in rtc_isr to make sure the access to wakeup auto-reload counter and to wucksel[2:0] bits is allowed. it takes around 2 rtcclk clock cycles (due to clock synchronization). 3. program the wakeup auto-reload value wut[15:0], and the wakeup clock selection (wucksel[2:0] bits in rtc_cr).set wute in rtc_cr to enable the timer again. the wakeup timer restarts down-counting. 22.3.6 reading the calendar to read the rtc calendar registers (rtc _tr and rtc_dr) properly, the apb1 clock frequency (f pclk1 ) must be equal to or greater than seven times the f rtcclk rtc clock frequency. this ensures a secure behavior of the synchronization mechanism. if the apb1 clock frequency is le ss than seven times the rtc clock frequency, the software must read the calendar time and date registers twice. if the second read of the rtc_tr gives the same result as the first read, this ensures that the data is correct. otherwise a third read access must be done. in any case the apb1 clock frequency must never be lower than the rtc clock frequency. the rsf bit is set in rtc_isr register each time the calendar registers are copied into the rtc_tr and rtc_dr shadow registers. the copy is performed every two rtcclk cycles. to ensure consistency between the 2 values, reading rtc_tr locks the values in the higher-order calendar shadow registers until rtc_dr is read. in case the software makes read accesses to the calendar in a time interval smaller than 2 rtcclk periods: rsf must be cleared by software after the first calendar read, and then the software must wait until rsf is set before reading again the rtc_tr and rtc_dr registers. after waking up from low power mode (stop or standby), rsf must be cleared by software. the software must then wait until it is se t again before reading the rtc_tr and rtc_dr registers. the rsf bit must be cleared after wakeup and not before entering low power mode. note: 1 after a system reset, the software must wait until rsf is set before reading the rtc_tr and rtc_dr registers. indeed, a system reset resets the shadow registers to their default values. 2 after an initializ ation (refer to calendar initialization an d configuration on page 546 ): the software must wait until rsf is set before reading the rtc_tr and rtc_dr registers. 22.3.7 resetting the rtc the calendar shadow registers (rtc_tr and rtc_dr) and the rtc status register (rtc_isr) are reset to their default values by all available system reset sources. on the contrary, the following registers are reset to their default values by a power-on reset and are not affected by a system reset: the rtc current calendar registers, the rtc control register (rtc_cr), the prescaler register (rtc_prer), the rtc calibration registers (rtc_calibr), the rtc timestamp registers (rtc_tstr and rtc_tsdr), the rtc tamper and alternate function configuration register (rtc_tafcr), the rtc backup real-time clock (rtc) RM0033 548/1317 doc id 15403 rev 3 registers (rtc_bkpxr), the wakeup timer regi ster (rtc_wutr), the alarm a and alarm b registers (rtc_alrmar and rtc_alrmbr). in addition, the rtc keeps on running under system reset if the reset source is different from the power-on reset one. when a power-on reset occurs, the rtc is stopped and all the rtc registers are set to their reset values. 22.3.8 rtc reference clock detection the reference clock (at 50 hz or 60 hz) should have a higher precision than the 32.768 khz lse clock. when the reference clock detection is enabled (refckon bit of rtc_cr set to 1), it is used to compensate for the imprecision of the calendar update frequency (1 hz). each 1 hz clock edge is compared to the nearest reference clock edge (if one is found within a given time window). in most cases, the two clock edges are properly aligned. when the 1 hz clock becomes misaligned due to the imprecision of the lse clock, the rtc shifts the 1 hz clock a bit so that future 1 hz clock edges are aligned. thanks to this mechanism, the calendar becomes as precise as the reference clock. if the reference clock halts, the calendar is updated continuously based solely on the lse clock. the rtc then waits for the reference clock using a detection window centered on the ck_spre edge. when the reference clock detection is enabled, prediv_a and prediv_s must be set to their default values: prediv_a = 0x007f previd_s = 0x00ff note: the reference clock detection is not available in standby mode. caution: the reference clock detection feature cannot be used in conjunction with the coarse digital calibration: rtc_calibr must be kept at 0x0000 0000 when refckon=1. 22.3.9 rtc coarse digital calibration the coarse digital calibration can be used to achieve a 5 ppm accuracy by adding (positive calibration) or masking (negative calibration) clock cycles at t he output of the asynchronous prescaler (ck_apre). positive and negative calibration are selected by setting the dcs bit in rtc_calibr register to ?0? and ?1?, respectively. when positive calibration is enabled (dcs = ?0?), 2 ck_apre cycles are added every minute (around 15360 ck_apre cycles) for 2xdc minutes. this causes the calendar to be updated sooner, thereby adjusting the effective rtc frequency to be a bit higher. when negative calibration is enabled (dcs = ?1?), 1 ck_apre cycle is removed every minute (around 15360 ck_apre cycles) for 2xdc minutes. this causes the calendar to be updated later, thereby adjusting the effective rtc frequency to be a bit lower. dc is configured through bits dc[4:0] of rtc_calibr register. this number ranges from 0 to 31 corresponding to a time interval (2xdc) ranging from 0 to 62. the coarse digital calibration can be configured only in initialization mode, and starts when the init bit is cleared. the full calibration cycl e lasts 64 minutes. the first 2xdc minutes of the 64 -minute cycle are modified as just described. RM0033 real-time clock (rtc) doc id 15403 rev 3 549/1317 negative calibration can be performed with a resolution of about 2 ppm while positive calibration can be performed with a resolution of about 4 ppm. the maximum calibration ranges from ? 63 ppm to 126 ppm. the calibration can be performed either on the lse or on the hse clock. caution: digital calibration may not work correctly if prediv_a < 6. case of rtcclk=32.768 khz and prediv_a+1=128 the following description assumes that ck_apre frequency is 256 hz obtained with an lse clock nominal frequency of 32.768 khz, and prediv_a set to 127 (default value). the ck_spre clock frequency is only modified during the first 2xdc minutes of the 64-minute cycle. for example, when dc equals 1, only the first 2 minutes are modified. this means that the first 2xdc minutes of each 64-minute cycle have, once per minute, one second either shortened by 256 or lengthened by 128 rtcclk cycles, given that each ck_apre cycle represents 128 rtcclk cycles (with prediv_a+1=128). therefore each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125829120 rtcclk cycles (64min x 60 s/min x 32768 cycles/s). this is equivalent to +4.069 ppm or-2.035 ppm per calibration step. as a result, the calibration resolution is +10.5 or ? 5.27 seconds per month, and the total calibration ranges from +5.45 to ? 2.72 minutes per month. in order to measure the clock deviation, a 512 hz clock is output for calibration.refer to section 22.3.12: calibration clock output . 22.3.10 time-stamp function time-stamp is enabled by setting the tse bit of rtc_cr register to 1. the calendar is saved in the time-stamp registers (rtc_tstr, rtc_tsdr) when a time- stamp event is detected on the pin to which the timestamp alternate function is mapped. when a time-stamp event occurs, the time-stamp flag bit (tsf) in rtc_isr register is set. by setting the tsie bit in the rtc_cr register, an interrupt is generated when a time-stamp event occurs. if a new time-stamp event is detected while the time-stamp flag (tsf) is already set, the time-stamp overflow flag (tsovf) flag is set and the time-stamp registers (rtc_tstr and rtc_tsdr) maintain the resu lts of the previous event. note: 1 tsf is set 2 ck_apre cycles after the time-stamp event occurs due to synchronization process. 2 there is no delay in the setting of tsovf. this means that if two time-stamp events are close together, tsovf can be seen as '1' while tsf is still '0'. as a consequence, it is recommended to poll tsovf only after tsf has been set. caution: if a time-stamp event occurs immediately after the tsf bit is supposed to be cleared, then both tsf and tsovf bits are set. to avoid masking a time-stamp event occurring at the same moment, the application must not write ?0? into tsf bit unle ss it has already read it to ?1?. real-time clock (rtc) RM0033 550/1317 doc id 15403 rev 3 timestamp alternate function the timestamp alternate function can be mapped to either rtc_af1 or rtc_af2 depending on the value of the tsinsel bit in the rtc_tafcr register (see section 22.6.13 on page 567 ). 22.3.11 tamper detection rtc backup registers the backup registers (rtc_bkpxr) are twenty 32-bit registers for storing 80bytes of user application data. they are implemented in the backup domain that remains powered-on by v bat when the v dd power is switched off. they are not reset by system reset, power-on reset, or when the device wakes up from standby mode. the backup registers are reset when a tamper detection event occurs (see section 22.6.14: rtc backup registers (rtc_bkpxr) and tamper detection initialization on page 550 . tamper detection initialization the tamper detection input is associated with a flag tamp1f in the rtc_isr2 register. the input can be enabled by setting the tamp1e bit to 1 in the rtc_tafcr register. a tamper detection event resets all backup registers (rtc_bkpxr). by setting the tampie bit in the rtc_tafcr register, an interrupt is generated when a tamper detection event occurs. edge detection on tamper inputs: tamper pins generate tamper detection events when either a rising edge is observed or an falling edge is observed dep ending on the corr esponding tampxtrg bit. the internal pull-up resistors on the tamper inputs are deactivated when edge detection is selected. caution: to avoid losing tamper detection events, the signal used for edge detection is logically anded with tampxe in order to detect a tamper detection event in case it occurs before the tamperx pin is enabled. when tampxtrg = 0: if the tamperx alternate function is already high before tamper detection is enabled (tampxe bit set to 1), a tamper event is detected as soon as tamperx is enabled, even if there was no rising edge on tamperx after tampxe was set. when tampxtrg = 1: if the tamperx alternate function is already low before tamper detection is enabled, a tamper event is detected as soon as tamperx is enabled (even if there was no falling edge on tamperx after tampxe was set. after a tamper event has been detected and cleared, the tamperx alternate function should be disabled and then re-enabled (tampxe set to 1) before re-programming the backup registers (rtc_bkpxr). this prevents the application from writing to the backup registers while the tamperx value still indicates a tamper detection. this is equivalent to a level detection on the tamperx alternate function. note: tamper detection is still active when v dd power is switched off. to avoid unwanted resetting of the backup registers, the pin to which the tamper alternate function is mapped should be externally tied to the correct level. RM0033 real-time clock (rtc) doc id 15403 rev 3 551/1317 tamper alternate function detection the tamper1 alternate function can be mapped either to rtc_af1(pc13) or rtc_af2 (pi8) depending on the value of tamp1insel bit in rtc_tafcr register (see section 22.6.13: rtc tamper and alternate function configuration register (rtc_tafcr) ). tampe bit must be cleared when tamp1insel is modified to avoid unwanted setting of tampf. 22.3.12 calibration clock output when the coe bit is set to 1 in the rtc_cr register, a reference clock is provided on the rtc_calib device output. if prediv_a = 0x7f, the rtc_calib frequency is f rtcclk /64. this corresponds to a calibration output at 512 hz for an rtcclk frequency at 32.768 khz. the rtc_calib output is not impacted by the calibration value programmed in rtc_calibr register. the rtc_calib duty cycle is irregular: there is a light jitter on falling edges. it is therefore recommended to use rising edges. calibration alternate function output when the coe bit in the rtc_cr register is set to 1, the calibration alternate function (afo_calib) is enabled on rtc_af1. 22.3.13 alarm output three functions can be selected on alar m output: alraf, alrbf and wutf. these functions reflect the contents of the corresponding flags in the rtc_isr register. the osel[1:0] control bits in the rtc_cr register are used to activate the alarm alternate function output (afo_alarm) in rtc_af1, and to select the function which is output on afo_alarm. the polarity of the output is determined by the pol control bit in rtc_cr so that the opposite of the selected flag bit is output when pol is set to 1. alarm alternate function output afo_alarm can be configured in output open drain or output push-pull using the control bit alarmouttype in the rtc_tafcr register. note: 1 once afo_alarm is enabled, it has priority over afo_calib (coe bit is don't care on rtc_af1 ). 2 when afo_calib or afo_alarm is selected, rtc_af1 is automatically configured in output alternate function. real-time clock (rtc) RM0033 552/1317 doc id 15403 rev 3 22.4 rtc and low power modes 22.5 rtc interrupts all rtc interrupts are connected to the exti controller. to enable the rtc alarm interrupt, the following sequence is required: 1. configure and enable the exti line 17 in interrupt mode and select the rising edge sensitivity. 2. configure and enable the rtc_alarm irq channel in the nvic. 3. configure the rtc to generate rtc alarms (alarm a or alarm b). to enable the rtc wakeup interrupt, the following sequence is required: 1. configure and enable the exti line 22 in interrupt mode and select the rising edge sensitivity. 2. configure and enable the rtc_wkup irq channel in the nvic. 3. configure the rtc to generate the rtc wakeup timer event. to enable the rtc tamper interrupt, the following sequence is required: 1. configure and enable the exti line 21 in interrupt mode and select the rising edge sensitivity. 2. configure and enable the tamp_stamp irq channel in the nvic. 3. configure the rtc to detect the rtc tamper event. to enable the rtc timestamp interrupt, the following sequence is required: 1. configure and enable the exti line 21 in interrupt mode and select the rising edge sensitivity. 2. configure and enable the tamp_stamp irq channel in the nvic. 3. configure the rtc to detect the rtc time-stamp event. table 77. effect of low power modes on rtc mode description sleep no effect rtc interrupts cause the device to exit the sleep mode. stop the rtc remains active when the rtc clock source is lse or lsi. rtc alarm, rtc tamper event, rtc time stamp event, and rtc wakeup cause the device to exit the stop mode. standby the rtc remains active when the rtc clock source is lse or lsi. rtc alarm, rtc tamper event, rtc time stamp event, and rt c wakeup cause the device to exit the standby mode. RM0033 real-time clock (rtc) doc id 15403 rev 3 553/1317 table 78. interrupt control bits interrupt event event flag enable control bit exit the sleep mode exit the stop mode exit the standby mode alarm a alraf alraie yes yes (1) 1. wakeup from stop and standby m odes is possible only when the rtc clock source is lse or lsi. yes (1) alarm b alrbf alrbie yes yes (1) yes (1) wakeup wutf wutie yes yes (1) yes (1) timestamp tsf tsie yes yes (1) yes (1) tamper1 detection tamp1f tampie yes yes (1) yes (1) real-time clock (rtc) RM0033 554/1317 doc id 15403 rev 3 22.6 rtc registers refer to section 1.1 of the reference manual for a list of abbreviations used in register descriptions. the peripheral registers can be accessed by words (32-bit). 22.6.1 rtc time register (rtc_tr) the rtc_tr is the calendar time shadow register. this register must be written in initialization mode only. refer to calendar initialization an d configuration on page 546 and reading the calendar on page 547 . address offset: 0x00 power-on reset value: 0x0000 0000 note: this register is write protected. the write access procedure is described in rtc register write protection on page 545 . 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved pm ht[1:0] hu[3:0] rw rw rw rw rw rw rw 1514131211109876543210 reserv ed mnt[2:0] mnu[3:0] reserv ed st[2:0] su[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31-24 reserved bit 23 reserved, always read as 0. bit 22 pm : am/pm notation 0: am or 24-hour format 1: pm bits 21:20 ht[1:0] : hour tens in bcd format bit 16:16 hu[3:0] : hour units in bcd format bit 15 reserved, always read as 0. bits 14:12 mnt[2:0] : minute tens in bcd format bit 11:8 mnu[3:0] : minute units in bcd format bit 7 reserved, always read as 0. bits 6:4 st[2:0] : second tens in bcd format bit 3:0 su[3:0] : second units in bcd format RM0033 real-time clock (rtc) doc id 15403 rev 3 555/1317 22.6.2 rtc date register (rtc_dr) the rtc_dr is the calendar date shadow register. this register must be written in initialization mode only. refer to calendar initialization an d configuration on page 546 and reading the calendar on page 547 . address offset: 0x04 power-on reset value: 0x0000 2101 note: this register is write protected. the write access procedure is described in rtc register write protection on page 545 . 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved yt[3:0] yu[3:0] rw rw rw rw rw rw rw rw 1514131211109876543210 wdu[2:0] mt mu[3:0] reserved dt[1:0] du[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31-24 reserved bits 23:20 yt[3:0] : year tens in bcd format bits 19:16 yu[3:0] : year units in bcd format bits 15:13 wdu[2:0] : week day units 000: forbidden 001: monday ... 111: sunday bit 12 mt : month tens in bcd format bits 11:8 mu : month units in bcd format bits 7:6 reserved, always read as 0. bits 5:4 dt[1:0] : date tens in bcd format bits 3:0 du[3:0] : date units in bcd format real-time clock (rtc) RM0033 556/1317 doc id 15403 rev 3 22.6.3 rtc control register (rtc_cr) address offset: 0x08 power-on value: 0x0000 0000 reset value: not affected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved coe osel[1:0] pol reserv- ed bkp sub1h add1h rw rw rw rw rw w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tsie wutie alrbie alraie tse wute alrbe alrae dce fmt reser ved refckon tsedge wucksel[2:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:24 reserved, always read as 0. bit 23 coe : calibration output enable this bit enables the afo_calib rtc output 0: calibration output disabled 1: calibration output enabled bits 22:21 osel[1:0] : output selection these bits are used to select the fl ag to be routed to afo_alarm rtc output 00: output disabled 01: alarm a output enabled 10: alarm b output enabled 11: wakeup output enabled bit 20 pol : output polarity this bit is used to configure the polarity of afo_alarm rtc output 0: the pin is high when alraf/alrbf/wutf is asserted (depending on osel[1:0]) 1: the pin is low when alraf/alrbf/wutf is asserted (depending on osel[1:0]). bit 19 reserved, always read as 0. bit 18 bkp : backup this bit can be written by the user to memorize whether the daylight saving time change has been performed or not. bit 17 sub1h : s ubtract 1 hour (winter time change) when this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. this bit is always read as 0. setting this bit has no effect when current hour is 0. 0: no effect 1: subtracts 1 hour to the current time. this can be used for winter time change. bit 16 add1h : add 1 hour (summer time change) when this bit is set outside initialization mode, 1 hour is added to the calendar time. this bit is always read as 0. 0: no effect 1: adds 1 hour to the current time. this can be used for summer time change bit 15 tsie : time-stamp interrupt enable 0: time-stamp interrupt disable 1: time-stamp interrupt enable RM0033 real-time clock (rtc) doc id 15403 rev 3 557/1317 bit 14 wutie : wakeup timer interrupt enable 0: wakeup timer interrupt disabled 1: wakeup timer interrupt enabled bit 13 alrbie : alarm b interrupt enable 0: alarm b interrupt disable 1: alarm b interrupt enable bit 12 alraie : alarm a interrupt enable 0: alarm a interrupt disabled 1: alarm a interrupt enabled bit 11 tse : time stamp enable 0: time stamp disable 1: time stamp enable bit 10 wute : wakeup timer enable 0: wakeup timer disabled 1: wakeup timer enabled bit 9 alrbe : alarm b enable 0: alarm b disabled 1: alarm b enabled bit 8 alrae: alarm a enable 0: alarm a disabled 1: alarm a enabled bit 7 dce: coarse digital calibration enable 0: digital calibration disabled 1: digital calibration enabled prediv_a must be 6 or greater bit 6 fmt : hour format 0: 24 hour/day format 1: am/pm hour format bit 5 reserved, always read as 0. bit 4 refckon : reference clock detection enable (50 or 60 hz) 0: reference clock detection disabled 1: reference clock detection enabled note: prediv_s must be 0x00ff. bit 3 tsedge : time-stamp event active edge 0: timestamp rising edge generates a time-stamp event 1: timestamp falling edge generates a time-stamp event tse must be reset when tsedge is changed to avoid unwanted tsf setting. bits 2:0 wucksel[2:0] : wakeup clock selection 000: rtc/16 clock is selected 001: rtc/8 clock is selected 010: rtc/4 clock is selected 011: rtc/2 clock is selected 10x: ck_spre (usually 1 hz) clock is selected 11x: ck_spre (usually 1 hz) clock is selected and 2 16 is added to the wut counter value (see note below) real-time clock (rtc) RM0033 558/1317 doc id 15403 rev 3 note: 1 wut = wakeup unit counter value. wut = (0x0000 to 0xffff) + 0x10000 added when wucksel[2:1 = 11]. 2 bits 7, 6 and 4 of this register can be written in initialization mode only (rtc_isr/initf = 1). 3 bits 2 to 0 of this register can be written only when rtc_cr wute bit = 0 and rtc_isr wutwf bit = 1. 4 it is recommended not to change the hour during the calendar hour increment as it could mask the incrementation of the calendar hour. 5 add1h and sub1h changes are effective in the next second. 6 this register is write protected. the write access procedure is described in rtc register write protection on page 545 . 22.6.4 rtc initialization and st atus register (rtc_isr) address offset: 0x0c reset value: 0x0000 0007 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 1514131211109876543210 res. res. ta m p 1f tsovf tsf wutf alrbf alraf init initf rsf inits res. wut wf alrb wf alra wf rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rw r rc_w0 r r r r bits 31:14 reserved bit 13 tamp1f : tamper detection flag this flag is set by hardware when a tamper detection event is detected. it is cleared by software writing 0. bit 12 tsovf : time-stamp overflow flag this flag is set by hardware when a time-s tamp event occurs while tsf is already set. this flag is cleared by software by writing 0. it is recommended to check and then clear tsovf only after clearing the tsf bit. otherwise, an overflow might not be noticed if a time- stamp event occurs immediately before the tsf bit is cleared. bit 11 tsf : time-stamp flag this flag is set by hardware wh en a time-stamp event occurs. this flag is cleared by software by writing 0. bit 10 wutf : wakeup timer flag this flag is set by hardware when the wakeup auto-reload counter reaches 0. this flag is cleared by software by writing 0. this flag must be cleared by software at least 1.5 rtcclk periods before wutf is set to 1 again. bit 9 alrbf : alarm b flag this flag is set by hardware when the time/date registers (rtc_tr and rtc_dr) match the alarm b register (rtc_alrmbr). this flag is cleared by software by writing 0. RM0033 real-time clock (rtc) doc id 15403 rev 3 559/1317 note: 1 the alraf, alrbf, wutf and tsf bits ar e cleared 2 apb clock cycles after programming them to 0. 2 this register is write protected (except for rtc_isr[13:8] bits). the write access procedure is described in rtc register write protection on page 545 . bit 8 alraf : alarm a flag this flag is set by hardware when the time/date registers (rtc_tr and rtc_dr) match the alarm a register (rtc_alrmar). this flag is cleared by software by writing 0. bit 7 init : initialization mode 0: free running mode 1: initialization mode used to program time and date register (rtc_tr and rtc_dr), and prescaler register (rtc_prer). counters are stopped and start counting from the new value when init is reset. bit 6 initf : initialization flag when this bit is set to 1, the rtc is in init ialization state, and the time, date and prescaler registers can be updated. 0: calendar registers update is not allowed 1: calendar registers update is allowed. bit 5 rsf : registers synchronization flag this bit is set by hardware each time the ca lendar registers are copied into the shadow registers (rtc_trx and rtc_drx). it is cleared either by software or by hardware in initialization mode. 0: calendar shadow registers not yet synchronized 1: calendar shadow registers synchronized bit 4 inits : initialization status flag this bit is set by hardware when the calendar year field is different from 0 (power-on reset state). 0: calendar has not been initialized 1: calendar has been initialized bit 3 reserved, always read as 0. bit 2 wutwf : wakeup timer write flag this bit is set by hardware when the wakeup timer values can be changed, after the wute bit has been set to 0 in rtc_cr. 0: wakeup timer configuration update not allowed 1: wakeup timer configuration update allowed bit 1 alrbwf : alarm b write flag this bit is set by hardware when alarm b values can be changed, after the alrbe bit has been set to 0 in rtc_cr. it is cleared by hardware in initialization mode. 0: alarm b update not allowed 1: alarm b update allowed. bit 0 alrawf : alarm a write flag this bit is set by hardware when alarm a values can be changed, after the alrae bit has been set to 0 in rtc_cr. it is cleared by hardware in initialization mode. 0: alarm a update not allowed 1: alarm a update allowed real-time clock (rtc) RM0033 560/1317 doc id 15403 rev 3 22.6.5 rtc prescaler re gister (rtc_prer) address offset: 0x10 power-on reset value: 0x007f 00ff system reset: not affected note: 1 this register must be writ ten in initialization mode only. th e initialization must be performed in two separate write accesses. refer to calendar initialization and configuration on page 546 2 this register is write protected. the write access procedure is described in rtc register write protection on page 545 . 22.6.6 rtc wakeup timer register (rtc_wutr) address offset: 0x14 power-on reset value: 0x0000 ffff system reset: not affected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved prediv_a[6:0] rw rw rw rw rw rw rw 1514131211109876543210 reserved prediv_s[12:0] rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:24 reserved bit 23 reserved, always read as 0. bits 22:16 prediv_a[6:0] : asynchronous prescaler factor this is the asynchronous division factor: ck_apre frequency = rtcclk frequency/(prediv_a+1) note: prediv_a [6:0]= 000000 is a prohibited value. bits 15:13 reserved, always read as 0. bits 12:0 prediv_s[12:0] : synchronous prescaler factor this is the synchronous division factor: ck_spre frequency = ck_apre frequency/(prediv_s+1) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 wut[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:16 reserved RM0033 real-time clock (rtc) doc id 15403 rev 3 561/1317 note: 1 this register can be written only when wutwf is set to 1 in rtc_isr. 2 this register is write protected. the write access procedure is described in rtc register write protection on page 545 . 22.6.7 rtc calibration re gister (rtc_calibr) address offset: 0x18 power-on reset value: 0x0000 0000 system reset: not affected bits 15:0 wut[15:0] : wakeup auto-reload value bits when the wakeup timer is enabled (wute set to 1), the wutf flag is set every (wut[15:0] + 1) ck_wut cycles. the ck_wut period is se lected through wucksel [2:0] bits of the rtc_cr register when wucksel[2] = 1, the wakeup timer bec omes 17-bits and wu cksel[1] effectively becomes wut[16] the most-significant bit to be reloaded into the timer. note: the first assertion of wutf occurs (wut+1 ) ck_wut cycles after wu te is set. setting wut[15:0] to 0x0000 with wucksel[2:0 ] =011 (rtcclk/2) is forbidden. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved dcs reserved dc[4:0] rw rw rw rw rw rw bits 31:8 reserved bit 7 dcs : digital calibration sign 0: positive calibration: calendar update frequency is increased 1: negative calibration: calendar update frequency is decreased bits 6:5 reserved, always read as 0. bits 4:0 dc[4:0] : digital calibration dcs = 0 (positive calibration) 00000: + 0 ppm 00001: + 4 ppm 00010: + 8 ppm .. 11111: + 126 ppm dcs = 1 (negative calibration) 00000: ? 0 ppm 00001: ? 2 ppm 00010: ? 4 ppm .. 11111: ? 63 ppm real-time clock (rtc) RM0033 562/1317 doc id 15403 rev 3 note: 1 this register can be written in init ialization mode only (r tc_isr/initf = ?1?). 2 this register is write protected. the write access procedure is described in rtc register write protection on page 545 . 22.6.8 rtc alarm a r egister (rtc_alrmar) address offset: 0x1c power-on reset value: 0x0000 0000 system reset: not affected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 msk4 wdsel dt[1:0] du[3:0] msk3 pm ht[1:0] hu[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 msk2 mnt[2:0] mnu[3:0] msk1 st[2:0] su[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bit 31 msk4 : alarm a date mask 0: alarm a set if the date/day match 1: date/day don?t care in alarm a comparison bit 30 wdsel : week day selection 0: du[3:0] repres ents the date units 1: du[3:0] represents the week day. dt[1:0] is don?t care. bits 29:28 dt[1:0] : date tens in bcd format. bits 27:24 du[3:0] : date units or day in bcd format. bit 23 msk3 : alarm a hours mask 0: alarm a set if the hours match 1: hours don?t care in alarm a comparison bit 22 pm: am/pm notation 0: am or 24-hour format 1: pm bits 21:20 ht[1:0] : hour tens in bcd format. bits 19:16 hu[3:0] : hour units in bcd format. bit 15 msk2 : alarm a minutes mask 0: alarm a set if the minutes match 1: minutes don?t care in alarm a comparison bits 14:12 mnt[2:0] : minute tens in bcd format. bits 11:8 mnu[3:0] : minute units in bcd format. bit 7 msk1 : alarm a seconds mask 0: alarm a set if the seconds match 1: seconds don?t care in alarm a comparison bits 6:4 st[2:0] : second tens in bcd format. bits 3:0 su[3:0] : second units in bcd format. RM0033 real-time clock (rtc) doc id 15403 rev 3 563/1317 note: 1 this register can be written only when alrawf is set to 1 in rtc_is r, or in initialization mode. 2 this register is write protected. the write access procedure is described in rtc register write protection on page 545 . 22.6.9 rtc alarm b r egister (rtc_alrmbr) address offset: 0x20 power-on reset value: 0x0000 0000 system reset: not affected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 msk4 wdsel dt[1:0] du[3:0] msk3 pm ht[1:0] hu[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 msk2 mnt[2:0] mnu[3:0] msk1 st[2:0] su[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bit 31 msk4 : alarm b date mask 0: alarm b set if the date and day match 1: date and day don?t care in alarm b comparison bit 30 wdsel : week day selection 0: du[3:0] represents the date units 1: du[3:0] represents the week day. dt[1:0] is don?t care. bits 29:28 dt[1:0] : date tens in bcd format bits 27:24 du[3:0] : date units or day in bcd format bit 23 msk3 : alarm b hours mask 0: alarm b set if the hours match 1: hours don?t care in alarm b comparison bit 22 pm: am/pm notation 0: am or 24-hour format 1: pm bits 21:20 ht[1:0] : hour tens in bcd format bits 19:16 hu[3:0] : hour units in bcd format bit 15 msk2 : alarm b minutes mask 0: alarm b set if the minutes match 1: minutes don?t care in alarm b comparison bits 14:12 mnt[2:0] : minute tens in bcd format bits 11:8 mnu[3:0] : minute units in bcd format bit 7 msk1 : alarm b seconds mask 0: alarm b set if the seconds match 1: seconds don?t care in alarm b comparison bits 6:4 st[2:0] : second tens in bcd format bits 3:0 su[3:0] : second units in bcd format real-time clock (rtc) RM0033 564/1317 doc id 15403 rev 3 note: 1 this register can be written only when alrbwf is set to 1 in rtc_is r, or in initialization mode. 2 this register is write protected. the write access procedure is described in rtc register write protection on page 545 . RM0033 real-time clock (rtc) doc id 15403 rev 3 565/1317 22.6.10 rtc write protect ion register (rtc_wpr) address offset: 0x24 reset value: 0x0000 0000 22.6.11 rtc time stamp ti me register (rtc_tstr) address offset: 0x30 power-on value: 0x0000 0000 system reset: not affected note: the content of this register is valid only wh en tsf is set to 1 in rt c_isr. it is cleared when tsf bit is reset. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 reserved key wwwwwwww bits 31:8 reserved, always read as 0. bits 7:0 key : write protection key this byte is written by software. reading this byte always returns 0x00. refer to rtc register write protection for a description of how to unlock rtc register write protection. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved pm ht[1:0] hu[3:0] rrrrrrr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserv- ed mnt[2:0] mnu[3:0] reserv- ed st[2:0] su[3:0] rrr rrrr rrrrr r r bits 31:23 reserved, always read as 0. bit 22 pm: am/pm notation 0: am or 24-hour format 1: pm bits 21:20 ht[1:0] : hour tens in bcd format. bits 19:16 hu[3:0] : hour units in bcd format. bit 15 reserved, always read as 0. bits 14:12 mnt[2:0] : minute tens in bcd format. bits 11:8 mnu[3:0] : minute units in bcd format. bit 7 reserved, always read as 0. bits 6:4 st[2:0] : second tens in bcd format. bits 3:0 su[3:0] : second units in bcd format. real-time clock (rtc) RM0033 566/1317 doc id 15403 rev 3 22.6.12 rtc time stamp date register (rtc_tsdr) address offset: 0x34 power-on value: 0x0000 0000 system reset: not affected note: the content of this register is valid only wh en tsf is set to 1 in rt c_isr. it is cleared when tsf bit is reset. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 wdu[1:0] mt mu[3:0] reserved dt[1:0] du[3:0] rrrrrrrr rrrrrr bits 31:16 reserved, always read as 0. bits 15:13 wdu[1:0] : week day units bit 12 mt : month tens in bcd format bits 11:8 mu[3:0] : month units in bcd format bits 7:6 reserved, always read as 0. bits 5:4 dt[1:0] : date tens in bcd format bit 3:0 du[3:0] : date units in bcd format RM0033 real-time clock (rtc) doc id 15403 rev 3 567/1317 22.6.13 rtc tamper and alternat e function configuration register (rtc_tafcr) address offset: 0x40 power-on value: 0x0000 0000 system reset: not affected 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved alarmout type tsin sel ta m p 1 insel rw rw rw 1514131211109876543 2 10 reserved ta m p i e ta m p 1 trg ta m p 1 e rw rw rw bit 31:19 reserved. always read as 0. bit 18 alarmouttype : afo_alarm output type 0: alarm_af0 is a push-pull output 1: alarm_af0 is an open-drain output bit 17 tsinsel : timestamp mapping 0: rtc_af1 used as timestamp 1: rtc_af2 used as timestamp bit 16 tamp1insel : tamper1 mapping 0: rtc_af1 used as tamper 1: rtc_af2 used as tamper note: tamp1e must be reset when tamp1insel is changed to avoid unwanted setting of ta m p 1 f. bit 15:3 reserved. always read as 0. bit 2 tampie : tamper interrupt enable 0: tamper interrupt disabled 1: tamper interrupt enabled bit 1 tamp1trg : active level for tamper 1 0: tamper1 rising edge triggers a tamper detection event. 1: tamper1 falling edge triggers a tamper detection event. bit 0 tamp1e : tamper 1 detection enable 0: tamper 1 detection disabled 1: tamper 1 detection enabled real-time clock (rtc) RM0033 568/1317 doc id 15403 rev 3 22.6.14 rtc backup registers (rtc_bkpxr) address offset: 0x50 to 0x9c power-on value: 0x0000 0000 system reset: not affected 22.6.15 rtc register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bkp[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 bkp[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw w rw rw bits 31:0 bkp[31:0] the application can write or read dat a to and from these registers. they are powered-on by v bat when v dd is switched off, so that they are not reset by system reset, and their contents remain valid when the device operates in low-power mode. this register is reset on a tamper detection event. or when the flash readout protection is disabled. table 79. rtc register map and reset values offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 rtc_tr reserved pm ht [1:0] hu[3:0] reserved mnt[2:0] mnu[3:0] reserved st[2:0] su[3:0] reset value 0000000 0000000 0000000 0x04 rtc_dr reserved yt[3:0] yu[3:0] wdu[2:0] mt mu[3:0] reserved dt [1:0] du[3:0] reset value 00100001 000001 0x08 rtc_cr reserved coe osel [1:0] pol reserved bkp sub1h add1h tsie wutie alrbie alraie tse wute alrbe alrae dce fmt reserved refckon tsedge wcksel [2:0] reset value 0000 0000000000000 00000 0x0c rtc_isr reserved ta m p 1 f tsovf tsf wutf alrbf alraf init initf rsf inits reserved wutwf alrbwf alrawf reset value 0000000000 111 0x10 rtc_prer reserved prediv_a[6:0] reserved prediv_s[12:0] reset value 1111111 0000011111111 0x14 rtc_wutr reserved wut[15:0] reset value 1111111111111111 0x18 rtc_calibr reserved dcs reserved dc[4:0] reset value 0 00000 0x1c rtc_alrmar msk4 wdsel dt [1:0] du[3:0] msk3 pm ht [1:0] hu[3:0] msk2 mnt[2:0] mnu[3:0] msk1 st[2:0] su[3:0] reset value 00000000000000000000000000000000 RM0033 real-time clock (rtc) doc id 15403 rev 3 569/1317 refer to table 1 on page 50 for the register boundary addresses. 0x20 rtc_alrmbr msk4 wdsel dt [1:0] du[3:0] msk3 pm ht [1:0] hu[3:0] msk2 mnt[2:0] mnu[3:0] msk2 st[2:0] su[3:0] reset value 00000000000000000000000000000000 0x24 rtc_wpr reserved key[7:0] reset value 00000000 0x30 rtc_tstr reserved pm ht[1:0] hu[3:0] reserved mnt[2:0] mnu[3:0] reserved st[2:0] su[3:0] reset value 0000000 0000000 0000000 0x34 rtc_tsdr reserved wdu[2:0] mt mu[3:0] reserved dt [1:0] du[3:0] reset value 00000000 000000 0x40 rtc_tafcr reserved alarmouttype tsinsel tamp1insel reserved ta m p i e ta m p 1 t r g ta m p 1 e reset value 000 000 0x50 to 0x9c rtc_bk0r bkp[31:0] reset value 00000000000000000000000000000000 to rtc_bk19r bkp[31:0] reset value 00000000000000000000000000000000 table 79. rtc register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 inter-integrated circuit (i 2 c) interface RM0033 570/1317 doc id 15403 rev 3 23 inter - integrated cir c uit (i 2 c) interface 23.1 i 2 c intr oduction i 2 c ( i nt er -in t e g r a t e d cir c uit ) b u s in te rf ace ser v es as an int e rf ace be tw ee n th e micr ocont r o ller an d th e se r i al i 2 c b u s . it pro v ides m u ltimas ter c a pability , and controls all i 2 c b u s - specific seq uen cing, pr ot ocol, ar bit r at ion a n d t i min g . i t su ppo r t s st an da rd a nd f a st spe ed mo de s . it is als o smb u s 2. 0 co mp a t ib le . it ma y be used f o r a v a r i ety of pur pos e s , inc l uding crc gener a tion and v e r i fication, smbus (s yste m m a n a g e m en t b u s ) an d pm bus (p o w er m a na ge m e n t b u s). depending on sp ecific de vic e implementation d m a capability c a n be a v ailab l e f o r reduced cpu o v er load. 23.2 i 2 c main f e atures p a r a llel-b u s/i 2 c pr ot ocol con v er t e r multimaster capability: t he same interf ac e can act as master or sla v e i 2 c ma st er f e at ur es: ? c lo c k ge ne r a t i on ? s t a r t an d st o p gen er a t io n i 2 c sla v e f e at ur es: ? p r o g r amma b l e i 2 c address detection ? d ual addressing capability to ac k n o w ledge 2 s l a v e addresses ? s top b i t de te ctio n ge ner at ion a nd de te ctio n of 7 - b i t/ 1 0 -b it a ddr essing a nd ge ne r a l call su pp o r ts dif f e r e n t co m m un ica t io n sp ee ds : ? s t a nda rd sp eed ( u p t o 10 0 khz) , ? f ast sp ee d (u p to 4 0 0 khz) sta t us f l ag s: ? t r a ns mit t e r /r ec eiv e r mo d e flag ? e n d - o f - byt e tr ansmission f l ag ?i 2 c b u sy fl a g er ro r flag s: ? a rbitr a tion lost condition f o r master mode ? a c kno wled g e m e nt f a ilur e af te r a d d r e s s/ da ta tr a n s m is sio n ? d et ec tion o f mis p la ce d sta r t or st op c o n d it ion ? o v e r r un /und er r un if clo c k str e t chin g is disab l e d 2 i n t e r r upt v e cto r s: ? 1 in te rr u p t f o r su cce s sf ul ad dr ess/ dat a com m u nicat i on ? 1 in te rr u pt f o r er ro r co nd itio n o p t i on al clo c k s t re tc hin g 1-b y te b u ff er with d m a capability RM0033 inter-integrated circuit (i 2 c) interface doc id 15403 rev 3 571/1317 conf igu r ab le pec ( p a c k e t err o r ch ec king ) ge ner at ion or v e r i f i ca tio n : ? p ec v a lu e can b e tr a n s m it te d a s las t b y te in tx m o de ? p ec er ro r ch ec king f o r last r e ceiv e d b yt e smbus 2.0 compatibility : ? 25 ms clo c k lo w t i me ou t de la y ? 10 ms mast er cum u lat i v e clo c k lo w e xte nd t i me ? 25 ms s l a v e cum u lati v e cloc k lo w e x tend time ? h a r d w ar e pec ge ner at ion / v e r i ficat i on wit h a c k con t r o l ? a d d r e ss resolu t i on pro t o col (arp) supp or t e d pmbus c o mpati b ility not e : s o m e of th e abo v e f e a t u r e s ma y n o t b e a v a ilab l e in cer t ain p r od uct s . th e user sh ould r e f e r t o t he p r od uct d a t a shee t, to i den tif y t h e sp ecific f eat ur es su pp or t ed b y t h e i 2 c interf ace imp l em ent at ion . 23.3 i 2 c functional description i n add it ion to r e ceiving an d tr a n smit ti ng dat a, th is int e r f a c e con v er t s it f r o m ser i a l t o par allel f o r m at and vice v e r s a . th e int e r r up ts ar e en ab led or disab l ed b y so ft w a re . t he int e r f ace is con nect e d t o th e i 2 c b u s b y a da ta p i n ( s d a ) a nd b y a cloc k pin (scl) . i t can be conn ect ed wit h a sta nda rd ( u p t o 10 0 khz) o r f a st ( up t o 40 0 khz) i 2 c b u s . 23.3.1 mode selection th e int e r f ace ca n op er a t e in o n e o f t h e f o u r f o llo wing mo des: sla v e tr an sm itt e r sla v e re ce iv er ma st er tr a n sm it te r ma st er rece iv e r by def au lt, it o per at es in sla v e mo de . th e int e r f a ce aut om at ically s witch es f r om sla v e t o ma ste r , af t e r it gen er a t e s a st ar t cond itio n an d fr om m a ste r t o sla v e , if an ar bit r a t io n loss or a stop gener ation oc curs , allo wing m u ltimas ter c a pability . comm uni cation fl o w in m a s t e r m o de , th e i 2 c int e r f ace init iat e s a da ta t r a n sf e r an d ge ner at es t h e clo c k sign al. a ser i a l dat a t r a n sf er a l w a ys beg ins with a sta r t con d it ion a n d end s wit h a st op co ndit i on . bo th st ar t a nd sto p cond it ions ar e gen er a t e d in ma st er mod e b y so f t w a re . i n sla v e mod e , t he int e r f ace is cap a b l e of re co gnizin g its o w n a d d r esses (7 o r 10 -bi t ) , an d t h e g e n e r a l call ad dr ess . t he ge ne r a l call add re ss de te ct io n ma y be en ab led o r disab l e d b y so ftw a r e . dat a an d ad dr esse s a r e t r an sf e r r ed as 8- bit b yt e s , msb f i r s t . t he f i rst b yte (s) f o llo wing t h e st ar t con d it ion con t a i n t he ad dr ess ( o n e in 7- bit m ode , tw o in 10 -b it mo de) . th e ad dr ess is alw a ys tr ansmitt e d in master mode . a 9t h cloc k pu lse f o llo ws th e 8 cloc k cycles of a b y t e t r an sf e r , du r i ng which t h e re ce iv e r m u st se nd a n ac k n o w led g e b i t to th e tr an sm itt e r . re f e r to fig u r e 215 . inter-integrated circuit (i 2 c) interface RM0033 572/1317 doc id 15403 rev 3 figu re 21 5. i 2 c b u s pr ot ocol ac kno wled ge ma y be ena b l e d or d i sab l ed b y sof t w ar e . th e i 2 c int e r f a c e add re sse s (d ua l a ddr essing 7 - bit / 10- bit and /o r ge ne r a l call add re ss) can be select ed b y so ft w a re . th e b l oc k d i ag r a m of th e i 2 c interf ac e is sho wn in figu re 2 1 6 . figu re 21 6. i 2 c b l oc k dia g ra m 1. smba is an optional signal in smbus mod e . this signal is not app licab l e if smbus is disabled. sc l sda 12 8 9 ms b ack stop start cond ition condition d a t a s hift regi s ter comp a r a tor own a ddre ss regi s ter c l oc k contr ol s t a t us regi s ter s control re gi s ter s control cloc k control d a t a control s cl logic d ua l a ddre ss regi s ter d a t a regi s ter pe c regi s ter interr u pt s pec c a lc u l a tion s mb a s da re gi s ter (ccr) ( s r1& s r2) (c r1&cr2 ) dma re qu e s t s & ack a i171 8 9 RM0033 inter-integrated circuit (i 2 c) interface doc id 15403 rev 3 573/1317 23.3.2 i 2 c sla ve mode by def au lt t h e i 2 c in te rf ace o per at es in slave mod e . to swit ch f r om de fa ult sla v e m ode to ma ste r mod e a st art cond itio n ge ner at ion i s ne ede d. th e pe r i phe r a l in put clo c k m u st be pr og r a mme d in t he i 2 c_cr2 re gist er in o r d e r t o g ene r a t e cor r e c t tim i ngs . th e per i phe r a l inp u t clo c k f r e que ncy m u st be at lea s t : 2 mhz in st an da rd mo de 4 mhz in f a st m ode as soo n as a sta r t cond itio n is de te ct e d , t h e ad dr ess is r e ceiv ed f r o m th e sd a lin e a n d sen t to th e sh ift re gis t e r . th en it is c o m p ar ed w i th th e ad d r e ss of th e int e r f a ce (o ar1 ) a n d with o a r2 (if e ndu al= 1 ) or the gener a l call address (if engc = 1). not e : i n 10 -b it ad dr essing mo de , t h e com par iso n includ es t h e hea der se que nce ( 111 10xx0) , wh er e xx de no te s th e t w o m o st sign ific an t bits o f t h e a d d r e ss . hea d er or a d dres s not ma tc h e d : th e int e r f a c e igno re s it a n d w a it s f o r a not he r st ar t condition. hea d er ma tc he d (10 - b i t mo de o n ly): th e int e r f a ce gen er a t e s a n ac kno wled ge pu lse if t he a c k b i t is se t an d w a its f o r t he 8- bit sla v e a ddr ess . ad dre ss mat c he d : t h e in te rf ace g ene r a t e s in sequ ence : an a c kn o wle dg e pu lse if th e a c k bit is s e t the a ddr bit is s e t b y hardw a re and an in terr upt is gener ated if the ite v fe n bit is set. i f endu al=1, t h e so ft w a re h a s t o r ead th e du alf bit to ch ec k wh ich sla v e add re ss ha s be en a c kn o w le dg ed. i n 1 0 -b it m ode , af te r r e ceiving th e ad dr ess seq uen ce th e sla v e is alw a ys in re ce iv er m ode . it will enter t r ansmitter mode on receiving a repeated s t ar t co ndition f o llo w e d b y the header seq uen ce wit h ma tch i ng ad dr ess b i ts and t h e least sig n if ica n t bit set (1 111 0xx1) . th e tra b i t in dicat e s wh et he r th e sla v e is in re ceiv er o r t r a n smit t e r mo de . sla v e transmitter f o llo win g t he ad dr ess r e cep t io n an d af te r clear i ng addr, t h e sla v e send s b yte s f r o m th e dr r e g i st er to t h e sd a lin e via t h e int e r nal shif t r e g i st er . th e sla v e st re tche s scl lo w u n t il addr is cle a r ed an d dr f illed wit h th e da ta t o be se nt (s ee fig u re 217 t r an sf er se que ncing ev1 ev3) . wh en th e a c kn o wle dg e pu lse is re ce iv ed : th e tx e b i t is se t b y h a r d w a re w i th an in te rr u p t if th e itevfen a n d the i t b u fen bit s ar e set . i f t x e is set and so me da ta w e r e no t wr itt e n in th e i2 c_dr r egist er b e f o r e t he en d of th e ne xt d a ta t r an sm issio n , t h e btf b i t is se t a n d the in te rf ac e w a its un til btf is c l ea re d b y a r e a d to i 2 c_ sr1 f o llo w ed b y a wr it e to th e i2 c_ dr r egist er , st re tchin g scl lo w . inter-integrated circuit (i 2 c) interface RM0033 574/1317 doc id 15403 rev 3 fi gu re 21 7. t r an sf e r sequ e nc e di a g ra m f o r sl a v e t r a n smi t t e r 1. th e ev 1 and ev3_1 events stretch scl lo w until the end of the corresponding so ftware sequen ce. 2. th e e v 3 event stretches scl low if the software seq uence is not comp leted be fore the end of th e next byte tra nsmission. sla v e re ceiver f o llo win g th e add re ss rece pt ion an d a f t e r cle a r i ng addr, t h e sla v e r e ceiv e s b y t e s fr om th e sd a lin e int o th e dr r egist er via t h e in te r n a l sh ift re giste r . af te r ea ch b yt e th e int e r f ace g ene r a t e s in sequ en ce : an a c kn o wle dg e pu lse if th e a c k bit is s e t the rxne b i t is se t b y ha rd w a r e an d an in te rr u p t is ge ner at ed if t h e it evf e n an d itbufen b i t is se t. i f rxne is se t an d th e da ta in th e dr re gist er is not re ad be f o re t h e end o f t h e n e xt d a t a r e cep t io n, t h e bt f bit is set a nd t h e in te rf ace w a its un til btf is cle a re d b y a r ead f r om t he i2c_dr register , stretching scl lo w (see fig u r e 218 t r an sf e r se qu encing ) . 7-b it s l ave tran s mitter 10-bit s lave tran s mitter le g end : s = s t a rt, s r = re pe a ted s t a rt, p= s top , a= acknowledge, na= non- a cknowledge , evx= event (with interr u pt if itevfen= 1 ) ev1: addr= 1 , cle a red b y re a ding s r1 followed b y re a ding s r2 ev 3 -1: txe=1, s hift reg i s ter empt y, d a t a regi s ter empty, write d a t a 1 in dr. ev 3 : txe=1, s hift regi s ter not empty, d a t a regi s ter empty, cle a red b y writing dr ev 3 -2: a f =1; af i s cle a red b y writ ing ? 0 ? in af b it of s r1 reg i s ter. s addr e ss ad a t a 1a d a t a 2a ... .. d a t a nn a p ev 1 e v 3 -1 e v 3 ev 3 ev 3 ev 3 -2 s he a der a a ddre ss a ev 1 s r he a de r a d a t a 1a .. .. d a t a nn a p ev1 e v 3 _1 ev 3 ev 3 ev 3 -2 a i1 8 209 RM0033 inter-integrated circuit (i 2 c) interface doc id 15403 rev 3 575/1317 fi gu re 21 8. t r an sf e r sequ e nc e di a g ra m f o r sl a v e r ece i ver 1. th e ev 1 event stretch e s scl low u n til t he end of the correspon ding softw are sequence. 2. th e e v 2 event stretches scl low if the software seq uence is not comp leted be fore the end of th e next byte reception. 3. after checking the sr1 register content, the use r should perform the comple te clearing sequence for each flag found set. th us, for addr a nd stopf flags, the follow ing sequen ce is required inside the i2c inter r upt r outine : read sr1 if (addr = = 1) { r e a d sr1; read sr2} if (stopf == 1) { r ead sr 1; w r ite cr 1} th e purpose is t o make sure that both ad dr and st opf fla gs are cleared if both are found set. closi ng sla ve comm unication af t e r t h e la st dat a b yte is t r an sf er re d a sto p cond itio n is g ene r a t e d b y th e mast er . t he in te rf ace de t e cts th is con d it ion a nd set s: th e s t opf b i t an d ge n e r a te s a n int e r r up t if t h e itevfen b i t is se t. th e st opf is clea re d b y a re ad o f t h e sr1 re gist er f o llo w ed b y a wr it e to th e cr1 r egist er (s ee fig u re 218 : t r a n sf er seq uen ce diag r a m f o r sla v e re ce iv e r ev4). 23.3.3 i 2 c master mode in m a s t e r m o de , th e i 2 c int e r f ace init iat e s a da ta t r a n sf e r an d ge ner at es t h e clo c k sign al. a ser i a l d a t a t r an sf er alw a ys be gins wit h a st ar t co ndit i on a n d e nds with a st op co ndit i on . ma ste r mod e is sele cte d as so on as th e st ar t con d it ion is gen er a t e d on t h e b u s with a st ar t bit. th e f o llo wing is th e re quir e d seq u e n ce in mast er m ode . pro g r a m t h e p e r i p her al inpu t cloc k in i2 c_cr2 re giste r in or de r t o ge ner a t e co rr ect tim i n g s conf igu r e t h e clo c k con t r o l re gist er s co n fig ur e the r i s e tim e re gis ter pro g r a m t h e i 2 c_ cr1 r egist er t o e nab le t h e p e r i ph er a l se t t h e st ar t bit in th e i2 c_ cr1 re g i ste r to g e n e r a te a sta r t co nd itio n th e pe r i phe r a l in put clo c k f r e q u ency m u st be a t lea st: 2 mhz in st an da rd mo de 4 mhz in f a st m ode 7-b it s lave r e ceiver 10-bit s lav e receiver le g end : s = s t a rt, s r = re pe a ted s t a rt, p= s top , a= acknowledge, evx= event (with interr u pt if itevfen= 1 ) ev1: addr= 1 , cle a red b y re a ding s r1 followed b y re a ding s r2 ev2: rxne=1 cle a red b y re a ding dr regi s ter. ev4: s topf=1, cle a red b y re a ding s r1 regi s ter followed b y writing to the c r 1 reg i s ter s addr e ss ad a t a 1a d a t a 2a .. .. . d a t a na p ev 1 e v 2 e v 2 e v2 ev 4 s he a der a a ddre ss ad a t a 1a .. .. . d a t a na p ev 1 e v 2 ev 2 ev4 a i1 8 20 8 inter-integrated circuit (i 2 c) interface RM0033 576/1317 doc id 15403 rev 3 star t condition se tt ing t h e st ar t b i t causes t he int e r f ace t o gen er a t e a st ar t co nd itio n an d to s wit ch t o m a st er m o de ( m / s l bit se t) wh en t h e busy b i t is c l ea re d. not e : i n mast er mod e , se tt ing t he st ar t bit cau s e s th e in t e rf a c e t o g ene r a t e a rest ar t con d it ion a t t he e nd of th e curr en t b y te t r a n sf e r . o n ce th e st ar t con d it ion is se nt : th e s b b i t is se t b y h a r d w a re a n d a n in te rr u p t is g e n e r at ed if th e itevfen b i t is s e t. th en t h e m a ste r w a its f o r a r ead o f t h e sr1 r egist er f o llo w e d b y a wr it e in t he dr r e g i st er with t h e sla v e ad dr es s ( s e e f i gur e 21 9 & f i gur e 22 0 t r an sf er se q u e n c i ng ev 5) . sla v e ad dress trans m ission then t h e sla v e ad dre s s is sen t t o t he sd a line via t h e in t e r n al sh if t re gist er . i n 10- bit add re ssin g mod e , send ing t h e h e a der se que nce causes t he f o llo wing e v e n t : ? t he add10 bit is set b y har dw a r e a n d a n int e r r upt is ge ne r a t e d if th e it evf e n bit is se t. the n t he ma st er w a it s f o r a re ad o f t he sr1 re giste r f o llo w e d b y a wr it e in th e dr re gist er wit h th e second a d d r e s s b yt e (see figu re 21 9 & figu re 22 0 t r ansf er sequ en cin g ) . ? t h e addr b i t is se t b y h a r d w a re a n d an in te rr u p t is g e n e r at ed if th e itevfen bit is se t. the n t he ma st er w a it s f o r a re ad o f t he sr1 re giste r f o llo w e d b y a r ead o f t h e sr2 re gist er ( s e e f i gu r e 21 9 & f i gu r e 22 0 t r ansf e r se que ncing ) . i n 7- bit a ddr essing m ode , one a d d r ess b yt e is sen t . as soo n as th e add re ss b y t e is sen t , ? t h e addr b i t is se t b y h a r d w a re a n d an in te rr u p t is g e n e r at ed if th e itevfen bit is se t. the n t he ma st er w a it s f o r a re ad o f t he sr1 re giste r f o llo w e d b y a r ead o f t h e sr2 re gist er ( s e e f i gu r e 21 9 & f i gu r e 22 0 t r ansf e r se que ncing ) . th e ma st er ca n de cid e to ent er t r an smit te r or re ce iv er mo de d epe nd ing o n th e lsb of th e sla v e add re ss se nt . i n 7- bit a ddr essing m ode , ? t o en te r t r a n smit te r mo de , a m a ste r send s t h e sla v e add re ss with l sb r e set . ? t o en te r receiv er mod e , a ma st er se nds th e sla v e a ddr ess wit h lsb set . i n 10- bit add re ssin g mod e , ? t o en te r t r a n smit te r mo de , a m a ste r send s t h e h ead er ( 1 1 110 xx0 ) an d th en t h e sla v e ad dr ess , ( w her e xx de no te s t he t w o m o st signi fican t bit s of t h e a d d r e s s). ? t o en te r receiv er mod e , a ma st er se nds th e he ade r ( 111 10xx0) a n d t h e n t he sla v e ad dr ess . th en it sh ou ld se nd a r e p eat ed st ar t co nd itio n f o llo w e d b y th e hea der (1 111 0xx1), (whe re xx den ot es th e tw o most sig n if ica n t bit s of t he add re ss) . t h e t r a b i t in dic a t e s wh et he r th e m a ste r is in r e c e iv e r or t r an sm itt e r m o d e . RM0033 inter-integrated circuit (i 2 c) interface doc id 15403 rev 3 577/1317 master transm itter f o llo win g t he ad dr ess t r a n smissio n an d af te r clear in g addr, t h e mast er sen d s b yte s f r o m th e dr r e gist er to t h e sd a lin e via th e in te r n al sh ift r e gist er . th e ma st er w a it s u n t il t h e fir st da ta b yte is wr itten into i2c_dr (s ee figu re 2 1 9 t r ansf e r seq uen cing ev8_ 1 ). wh en th e a c kn o wle dg e pu lse is re ce iv ed : the txe bit is set b y ha rd w a r e and an int e r r up t is gen er a t e d if t h e i t evfen and itbufen b i ts a r e se t. i f txe is set a nd a da ta b yte w a s n o t wr it t en in t he dr re gist er b e f o re t h e e n d o f t he last d a t a tr an sm iss i on , btf is se t an d th e int e r f a ce w a it s until btf is cleared b y a wr ite to i2c_d r , str e t ch i ng sc l lo w . closing t h e comm unica tion af t e r th e la st b yte is wr it t e n to t he dr r egi st er , t he st o p bit is set b y so ft w a re to ge ner at e a st op con d it ion ( see fig u r e 219 t r an sf er se que ncing ev8 _2) . th e int e r f ace aut o m at ically g oes ba c k t o sla v e mo de ( m / s l bit clea re d) . not e : s t o p con d it ion sho u ld b e pr og r a mmed dur in g ev8_2 e v ent , wh en eit h er txe or btf is se t. f i g u re 2 1 9 . t r a n s f er se q u e n ce d i a g ra m f o r ma st er tran s m it te r 1. th e ev5, ev 6 , ev 9 , ev 8 _1 and ev8_2 events st retch scl low until t he end of the corresponding software sequ ence. 2. th e ev8 even t stretches scl low if the softw are sequence is no t complete be fore the e nd of the next byte transmission. 7-bit ma s ter tran s mitter 10-bit ma s ter tran s mitter le g e nd: s = s t a rt, s r = repe a ted s t a rt, p= s top, a= acknowled ge, e v x= even t (with interr u pt if itevfen = 1) ev 5 : s b=1 , cle a red b y re a ding s r1 regi s ter foll owed b y writing dr regi s t er with addre ss . ev 6 : addr=1, cle a red b y r e a ding s r1 regi s ter followed b y re a ding s r2. ev 8 _1 : txe=1, s hift regi s ter empty, d a t a regi s ter empty, write d a t a 1 in dr. ev 8 : txe=1, s hift regi s ter not empty, d a t a regi s ter empty, cle a red b y writing dr regi s ter . ev 8 _2 : txe=1, btf = 1, progr a m s top re qu e s t. txe a nd btf a re cle a red b y h a rdw a re b y the s top condition ev 9 : add10=1, cle a red b y re a ding s r1 regi s ter followed b y writing dr regi s ter. s ad dre ss ad a t a 1a d a t a 2a .. .. . d a t a na p e v 5 e v6 ev 8 _1 e v 8 ev 8 ev 8 ev 8 _2 s he a der a a ddre ss ad a t a 1a . ... . d a t a na p e v 5 e v9 ev6 e v 8 _1 e v 8 ev 8 ev 8 _2 a i1 8 210 inter-integrated circuit (i 2 c) interface RM0033 578/1317 doc id 15403 rev 3 master recei ver f o llo win g t he ad dr ess t r a n smissio n an d af te r clear in g addr, t h e i 2 c in te rf ac e en te rs ma ste r receiv er mod e . in th is mo de t h e in te rf ace r e ceiv es b y t e s fr om t h e sd a lin e int o t he dr r e g i st er via t h e int e r n al shif t r egist er . af t e r e a ch b y t e t he in te rf ace ge ne r a t e s in sequence: 1. an a c kn o wle dg e pu lse if th e a c k bit is set 2 . the rxne b i t is se t an d an in te rr u p t is ge ner a t ed if t h e itevfen and itb u fen b i ts ar e set ( s ee fig u r e 220 t r an sf er se que ncing ev7 ). i f t h e rxne b i t is set an d th e da ta in t h e dr re giste r is n o t re ad be f o re t h e end o f t h e la st da ta re ce pt ion , th e bt f b i t is se t b y h a r d w a re an d th e in te rf ac e w a it s un til bt f is cle a r e d b y a r e a d in th e dr r egist er , st re tchin g scl lo w . closing t h e comm unica tion the m a s t e r s e n d s a na ck f o r th e las t b y te r e c e iv e d fr om t h e sla v e . afte r re ce ivin g t h is na ck, t he sla v e r e le ases th e co nt ro l o f t h e scl an d sd a line s . th en t h e m a ste r can sen d a st op /rest a r t co ndit i on . 1 . t o g ene r a t e t he n ona c k n o wle d g e pulse a f t e r th e last r e ceiv ed dat a b y t e , t h e a c k bit m u st be c l ea re d jus t a f t e r re a d in g th e se co nd la st da ta b y te (a ft er se co nd la st rxn e eve n t ) . 2 . i n or der to gen er a t e th e st op/ resta r t con d it ion , sof t w ar e m u st set t he st op/ s t a r t bit af t e r r e a d ing t h e se co nd la st dat a b y te ( a f t e r t h e seco nd last rxne e v ent ). 3. in c a s e a sing le b y te h a s to b e re ce iv ed , th e ac kn o wle dg e d i sab l e is m a de d u r in g ev6 (before addr flag is cleared) and the stop condition generation is made after ev6. after the stop condition generation, the interface goes automatically back to slave mode (m/sl bit cleared). RM0033 inter-integrated circuit (i 2 c) interface doc id 15403 rev 3 579/1317 fi gu re 22 0. t r an sf e r sequ e nc e di a g ra m f o r mas t e r rec e i ver 1. if a sin gle b y te is received, it is na. 2. th e ev 5 , ev 6 and ev9 events stretch sc l low until the en d of the correspo nding softw are sequence. 3. th e e v 7 event stretches scl low if the software seq uence is not comp leted be fore the end of th e next byte reception. 4. th e ev 7 _1 sof t ware sequen ce must be completed befo r e the ack pu lse of the current byte transfer. the p r o c e dur es de scr i be d be lo w ar e re comme n d ed if t h e ev7 - 1 sof t w ar e sequ en ce is no t com p let e d b e f o r e t he a c k p u lse of th e cu rr en t b y t e t r an sf e r . th ese pr oced ur es m u st be f o llo w ed t o mak e su re : the a c k bit is set lo w on t i me b e f o r e th e en d of t h e last da ta rece pt ion t h e s t op bit is s e t h i gh a fte r th e las t d a t a re ce pt ion wit ho u t r e c e p t io n of supp leme nt ar y d a t a . fo r 2-b y t e re cep ti on: w a it until addr = 1 (scl s t retc hed lo w until the add r flag is cleared) set a c k lo w , set pos high clear ad dr flag w a it until btf = 1 (data 1 in dr , data2 in sh if t re giste r , scl st re tche d lo w un til a da ta 1 is r e a d ) se t s t op hig h read d a t a 1 & 2 fo r n >2 -b yt e rec e pt ion, f r o m n- 2 dat a rec e pt ion w a it un t il btf = 1 (d at a n-2 in dr, da t a n- 1 in shif t r egist er , scl st ret che d lo w un ti l da ta n- 2 is r ead ) set a c k lo w read d a t a n-2 w a it until btf = 1 (data n-1 in dr, data n in shift regis t er , s cl stretched lo w until a da ta n- 1 is r ead ) se t s t op hig h re a d da ta n - 1 & n 23.3.4 err o r conditions th e f o llo wing ar e t h e e r r o r con d it ion s which ma y cause comm unication to f a il. bus er r o r (be rr) t h is er ro r oc cu rs whe n th e i 2 c in te rf ace de te ct s an e xt e r nal st op or sta r t cond itio n du r i ng a n add re ss or a dat a t r an sf er . in t h is case: th e berr b i t is se t a n d an in te rr u p t is ge ne r a t e d if th e iterre n b i t is se t in sla v e mod e : d a t a ar e discar ded a n d t h e lin es are rele ased b y h a r d w a re : ? i n c a s e o f a mis p la ce d sta r t, th e sla v e c o n sid er s it is a re sta r t an d w a its f o r an add re ss , or a st o p co ndit i o n ? i n c a s e o f a mis p la ce d sto p , t h e sla v e be h a v e s lik e f o r a sto p co nd itio n an d th e lines ar e re lease d b y har dw are i n mast er m ode : t he lin es a r e n o t r e le ased a nd t h e st at e of th e cu rr en t t r an sm ission is n o t a ff e cte d . i t is up t o th e s o f tw a r e to a b o r t or n o t th e cu rr en t t r an sm issio n inter-integrated circuit (i 2 c) interface RM0033 580/1317 doc id 15403 rev 3 ac kno w ledg e failure (af) th is e r r o r o c cur s wh en t he int e rf ace de te ct s a non ac kno wled ge b i t. in t h is case: th e af b i t is se t a n d an in te rr u p t is ge ne r a ted if th e iterr e n b i t is se t a tr ans m itter w h ic h receiv es a na ck m u st reset the comm unication: ? i f sla v e: line s ar e r e lea s e d b y ha rd w a r e ? i f mast er : a st op or re pea te d sta r t cond it ion m u st b e ge ner at ed b y sof t w ar e arbitration l o st (arlo) t h is er ro r oc cu rs whe n th e i 2 c in te rf ace de te ct s an ar bit r a t io n lost con d it ion . i n th is case , t he arlo b i t is set b y ha rd w a r e (a nd a n int e r r upt is g ene r a t e d if t he i t erren bit is set) t he i 2 c i n t e r f a ce goe s a u t o ma ticall y ba c k t o sla v e m ode ( t he m/ sl bi t is clea re d) . whe n t he i 2 c loses t h e a r b i tr a t ion, it is no t ab le t o a c kno wledg e its sla v e add re ss in th e sa me t r an sf er , b u t it ca n ac kno wledg e it a f t e r a re pea t ed st ar t f r o m th e winnin g mast er . lin es a r e re le as ed b y h a r d w a re overrun/unde rrun e r r o r (o vr) an o v er r u n e r r o r can occu r in sla v e m ode wh en cloc k st r e t c h i ng is disab l ed a nd t h e i 2 c in te rf ace is recei v in g dat a . th e int e r f a c e h a s rece iv e d a b y t e ( r xne=1 ) an d t he da t a in dr h a s n o t bee n re ad, be f o re t h e n e xt b yte is re ce iv ed b y t h e in t e rf ace . i n t h is ca se , the last receiv ed b yte is lost. i n ca se o f ov er r u n e r r o r , sof t w ar e sh ould clea r t he rxne b i t an d th e tr a n smit t e r shou ld r e - t r a n sm i t th e last r e ce iv e d b yt e . und e r r un er r o r can o c cur in sla v e mo de whe n cloc k st re tchin g is d i sa b l ed an d t he i 2 c in te rf ace is tr a n smit ti ng da ta . th e int e r f ace has no t up da te d th e dr with t h e ne xt b yt e (txe= 1 ), bef ore the cloc k c o mes f o r the ne xt b yt e . in this c a se , the s a me b y te in the dr register will be s e nt again the user sh ou ld ma k e sur e t hat da ta re ce iv ed o n t h e r e ceiv e r side dur in g a n un der r u n er ro r ar e discar ded a n d t h a t t h e n e xt b yte s ar e wr itt e n wit h in th e clo c k lo w time specified in the i 2 c b u s st an da r d . f o r the first b yte to be tr ansm itted, the dr m u st be wr itten a fter addr is cleared and bef o re th e firs t sc l r i sing e d g e . if n o t po ss ib le , th e r e ceiv er m u st disc ar d th e firs t d a t a. RM0033 inter-integrated circuit (i 2 c) interface doc id 15403 rev 3 581/1317 23.3.5 sd a/scl line contr o l i f cloc k st re t c h i ng is e n a b le d: ? t r a n s m i tt er mod e : i f t x e=1 an d btf=1: th e int e r f ace hold s t h e clo c k line lo w bef or e t r an sm ission t o w a it f o r th e micro c o n t r o ller t o wr ite th e b yt e in t he dat a re giste r ( bot h b u f f er a nd shif t r egist er a r e e m pt y). ? r e c e i v e r mo de : i f rxne=1 an d btf=1: th e int e r f a c e hold s t h e cloc k line lo w af te r rece pt ion t o w a it f o r t h e micr ocon tr olle r to r e a d t he b y t e in t h e dat a reg i st er (b ot h b u ff er and sh ift re giste r ar e f u ll) . i f cloc k st re t c h i ng is d i sab l ed in sla v e mod e : ? o v e r r un er ro r in case of rxne=1 a nd n o re ad of dr ha s be en d one b e f o r e t he ne xt b yt e is r e ceiv ed . th e la st re ce iv e d b yte is los t . ? u n der r u n er ro r in case txe=1 and n o wr ite in to dr has be en do ne b e f o r e th e ne xt b yte m u st be tr ansmitted. th e same b yte will be sent again. ? w r i te collision not managed. 23.3.6 smbus intr oducti on th e syst em ma na gem ent bus ( s mbus) is a tw o- wir e int e rf ace t h r oug h wh ich v a r i ou s de vic e s ca n c o m m u n ic ate wit h ea ch ot he r an d with th e re st o f t h e sy ste m . it is b a s e d o n i 2 c pr inciples of oper a tion. smbus pro vides a control b u s f o r syst em and po w e r management relat e d t a s ks . a sys tem ma y use smbus to pass me ssag es to a n d f r o m de vices inst ead o f t o g g ling individu al cont r o l line s . th e syst em ma na gem ent bus sp ecifica t io n re f e rs to t h r e e t ype s of de vices . a sl a v e is a d e vice th at is re ce ivin g or resp ond ing t o a comm and . a master is a de vice t hat issu es com m an ds , ge ne r a t e s t he clo c ks , and t e r m inat es t h e t r an sf er . a host is a specializ ed mast er th at p r o vid e s t h e m a in in te rf ac e to th e sys tem ' s cpu . a ho st m u st b e a m a s t e r-s la v e a n d m u st su ppo r t t h e smbu s ho st no tif y p r o t o col. o n ly o n e h o st is allo w e d in a syst em. simi larities be tween smbus an d i 2 c 2 wire b u s pr ot ocol (1 clk, 1 da ta ) + smbu s aler t line op t i ona l ma st er -sla v e co mm un ica t ion, mast er p r o vide s cloc k multi mas t er c a pability smbus dat a f o r m at sim ilar t o i 2 c 7- bit add re ssin g f o r m a t ( figu re 2 1 5 ). diff erence s between smbus and i 2 c th e f o llo wing t a b l e de scr i b e s t h e d i f f e r e n ces b e t w e en smbu s an d i 2 c. t a b l e 80 . s mbus v s . i 2 c smbus i 2 c max. spee d 100 khz m ax. spe ed 40 0 kh z min. cl oc k spe ed 10 khz n o mini m u m cloc k sp eed 35 ms clo c k lo w timeo u t n o timeou t log ic l e v e ls are fi x e d l o g ic le v e ls are v dd depe nde nt inter-integrated circuit (i 2 c) interface RM0033 582/1317 doc id 15403 rev 3 smbus applic ation us a g e wit h syst em ma nag eme n t bu s , a de vice ca n pr o v id e ma n u f a ctu r e r inf o r m at ion , t e ll t he syst e m wha t it s m ode l/p a r t n u mbe r is , sa v e it s st at e f o r a suspe nd e v e n t , r epo r t dif f er en t t y pes of err o r s , a c ce pt co nt ro l p a r a met e r s , a nd r e t u r n its st at u s . smbu s pr o v id es a co nt ro l b u s f o r syst em a nd po w e r ma na gem ent re lat e d t a sks . de vice identific a tion an y d e vice th at e x ist s o n t he syst em m ana gem ent bus a s a sla v e has a un iqu e add re ss calle d t he sla v e ad dr ess . f o r t h e list o f r e ser v ed sla v e a d d r e s ses , re f e r t o t he smbus spec ification v e r . 2.0 ( h t t p : //s mb us .o rg /s pe cs/ ). bus p r otoco l s t h e sm bu s sp ec ifica t io n su pp or ts u p to 9 b u s pr ot oc ols . f o r mo re d e t a ils of th es e p r o t o c o l s a nd smbus ad dr ess t y p e s , re f e r t o smbus sp ecifica t io n v e r . 2 . 0 ( h ttp :/ /sm b u s .o rg /sp e cs/ ). th ese pr ot ocols shou ld be im plem ent ed b y th e user sof t w ar e . ad dress res o lution p r otoco l (arp) smbu s sla v e a d d r ess co nf lict s ca n be r e solv ed b y dynam ica lly a s sign ing a n e w un ique a ddr ess t o e a ch sla v e de vice . the add r e s s resolut i o n prot o c o l ( a rp) has th e f o llo wing a t t r ib ut es: add r ess assig n me nt uses t h e st an dar d smbu s ph ysical la y e r ar bit r at io n mecha n ism assig ned a d d r esses re main con s t a nt while de vice po w e r is a p p lied; ad dre s s re t ent ion t h ro ug h de vice po w e r lo ss is a l so a llo w e d no add it iona l sm bu s p a c k e t o v erh e a d is in cu rr ed af t e r a d d r e s s assig n me nt . ( i . e . subseq ue nt a c ce sses to a s sig ned sla v e a d d r e s s e s ha v e th e sa me o v er he ad a s accesse s t o f i x e d ad dr ess de vice s . ) an y smbus mast er ca n en um er a t e t h e b u s unique de vice identifie r (udid) i n or de r t o pr o v id e a mecha n ism to iso l at e ea ch d e vice f o r t he pu r p ose of add re ss a s sign men t , ea ch d e vice m u st imp l eme n t a uniq ue d e vice id en tif i er (udid) . for the details on 128 bit udid and more information on arp, refer to smbus specification ver. 2.0 ( http://smbus.org/specs/ ). diff e ren t ad dress type s (reser v ed, dyna mi c etc.) 7 -b it, 10-bi t an d g ene r a l cal l sl a v e ad dress type s diff e ren t b u s protocol s (quic k comman d , process call etc.) n o b u s pr ot oco l s t a b l e 80 . s mbus v s . i 2 c (c ontin ue d) smbus i 2 c RM0033 inter-integrated circuit (i 2 c) interface doc id 15403 rev 3 583/1317 smbus aler t m ode smbu s aler t is an o p t i on al sig n a l wit h an in te rr u p t li ne f o r d e vice s t h a t w a nt t o t r ad e t heir ability to master f o r a pin. sm ba is a wired-and s i gnal just as the scl and sd a signals are . smba is u sed in con j unct i on wit h t he smbu s g ene r a l call add r ess . messag e s in v o k ed wit h th e smb u s ar e 2 b yt e s lon g . a sla v e-o n ly d e vice can sig nal t h e ho st t h r o u gh smba th at it w a n t s t o ta lk b y set t i ng al er t b i t in i 2 c_cr1 re gist er . th e ho st pr ocesse s t h e in te rr u p t and sim u lt an eo usly a c cesses all smba de vices th ro ug h th e ale r t re sp on se ad dr es s (kno wn as ara ha ving a v a lue 00 01 100x). only the de vice(s ) w h ic h pulled sm ba lo w w ill ac k n o wledge the a l er t response ad dre ss . th is st at us is ide n t i fie d using smbal er t st at us fla g in i 2 c_sr1 re giste r . th e h o st pe rf or ms a mod i fie d re ceiv e byt e o per at ion. the 7 bit d e vice add re ss pr o v id ed b y t h e sla v e t r ansmit de vice is pla ced in t h e 7 mo st signi f i can t b i ts of t he b yte . the eigh th bit ca n be a z e r o or o n e . if more than one de v i ce pul ls smba lo w , the highest pr ior i ty (lo w es t addres s) de v ice will win com m u nicat i on r i ght s via st and ar d ar bit r at ion d u r i n g th e sla v e a ddr ess t r a n sf e r . af te r a c kn o w le dg ing t h e sla v e a ddr ess th e de vice m u st di se nga ge it s smba pull- do wn. i f t h e host still sees smba lo w when the message tr ansf e r is complete , it kno w s to read the a r a a gain . a ho st wh ich doe s no t im plem ent th e smba sig nal ma y pe r i od ica lly access t h e ara. f o r mo re d e t a ils on smbus aler t m ode , ref e r to sm bus spe cificat ion v e r . 2. 0 ( h ttp :/ /sm b u s .o rg /sp e cs/ ). timeout err o r th er e ar e dif f ere n ces in t he t i ming spe cificat ion s b e t w ee n i 2 c an d smbus . smbu s de fi nes a clo c k lo w tim eou t, ti meout of 35 ms . also sm bus spe cifie s tl o w : sext as the cum u lativ e cloc k lo w e xtend time f o r a sla v e de vice . smbus specifies tlo w : m ext as th e cu m u lativ e c l oc k lo w e x ten d tim e f o r a ma st er d e v i ce . f o r m o r e de ta ils o n th es e tim e o u t s , r e f e r to sm bu s s p e cif icat ion v e r . 2. 0 ( h ttp :/ /sm b u s .o rg /sp e c s/ ). th e sta t u s f l ag t i meo u t o r tlo w er ro r in i 2 c_sr1 sho w s t he st at us o f t h is f e at ur e . ho w to use the interface in smbus m ode t o s witc h fro m i 2 c mo de t o smbus mod e , t he f o llo wing seq uen ce sh ould be pe rf or med . se t t h e sm bu s bit in th e i2c _ c r 1 re g i s t e r conf igu r e t h e sm btype a nd enarp bit s in t h e i2 c_ cr1 r e g i st er as r e q u ir ed f o r t h e ap plicat ion i f y o u w a n t t o conf igu r e t h e de vice as a mast er , f o llo w th e sta r t con d it ion g ene r a t i on pr oc ed u r e in sect ion 2 3. 3. 3: i 2 c ma st er mod e . otherw ise , f o llo w the sequenc e in se ct ion 2 3. 3. 2: i 2 c sla v e mod e . t h e a p p lica t io n ha s to co nt ro l th e v a r i ou s sm bu s pr ot oco l s b y sof t w a re . smb d e vice def a ult address ac kno wledged if ena r p=1 and smbtype=0 smb h o st header ac kno w ledg ed if enarp=1 and smbtype=1 smb a l er t response address ac kno wledg ed if smbaler t=1 inter-integrated circuit (i 2 c) interface RM0033 584/1317 doc id 15403 rev 3 23.3.7 dma requests dma re que sts (whe n ena b l ed) are gen er a t e d on ly f o r d a t a tr ansf e r . dma r equ ests ar e g ene r a t e d b y da ta re giste r be co ming emp t y in tr ansmission a nd dat a regist er b e comi ng f u ll in r e cep t io n. t he dma req u e s t m u st be se r v ed b e f o r e t he en d of th e cu rr en t b y t e t r a n sf e r . when t h e n u mb er o f da ta tr a n sf ers which ha s be en p r og r a mm ed f o r t h e cor r e s p o n d ing dma chan ne l is re ache d, t h e dma cont r o ller se nd s an en d of t r an sf er eo t sign al t o th e i 2 c int e r f a c e and g e n e r a te s a t r a n sf er com p let e int e rr up t if ena b l ed: ma st er tr a n smit te r : in th e int e r r upt ro ut ine a f t e r th e eo t int e r r upt , disab l e dma re qu ests th en w a it f o r a btf e v en t be f o re p r o g r a m m ing t h e st op co ndit i on . ma st er rece iv e r ? w h e n t h e n u m ber of b y te s t o be r e ceiv e d is eq ual t o or g r ea t e r th an t w o , t h e dma co nt ro ller se nds a har dw a r e sig n a l , eo t _1, cor r e s p ond ing to th e last b u t one da ta b y te ( n um b e r _ o f _ b y t es ? 1 ) . if , in th e i2 c_ cr2 re g i ste r , th e last b i t is s e t, i 2 c aut om at ica lly sen d s a na ck a f te r t he ne xt b y t e f o llo wing eo t_ 1. the u s e r can gen er a t e a st op co ndit i on in th e dm a t r ansf e r co mple te in te rr u p t rou t ine if ena b l e d. ? w h e n a sing le b y t e m u st b e re ce iv ed: t he na ck m u st b e pr og r a mme d dur in g ev6 e v en t, i.e . pr og r a m a c k=0 wh en addr=1, be f o re clea r i ng addr f l ag. the n t he user can prog r a m the st op condition eith er after c l ear i ng a ddr flag, or in the d m a t r ansf er complete int e r r up t ro ut ine . t r ansmi ssion us ing dma dma mod e can be e n a b le d f o r t r an sm issio n b y se tt in g th e dm aen bit in th e i 2 c_cr2 regis t er . data will be loaded from a memor y area conf igured using the dma per i pher al (ref er t o t h e dma spe c if icat ion ) t o t h e i 2 c_dr re gist er wh en e v er t he t x e b i t is se t. t o ma p a dm a cha nne l f o r i 2 c t r a n smissio n , per f o r m th e f o llo wing seq uen ce . her e x is t he cha nne l n u mb er . 1 . set th e i2 c_ dr r egist er a ddr ess in th e dm a_cp arx register . the da ta will be mo v e d to t h is ad d r e ss fro m th e m e m o r y af te r ea ch txe e v e n t . 2. set the memor y address in the dma_cmarx regis t er . th e data will be loaded into i2 c_ dr fr om t h is m e m o r y af ter e a c h tx e e v e n t. 3. configure the total n u mber of b y te s to be tr ans f erred in the dma_cndtr x re gist er . after eac h tx e e v ent, th is v a lue will be decremented. 4 . conf igu r e t h e ch ann el pr io r i ty using t h e pl [ 0 : 1 ] b i ts in t he dma_ccrx re gist er 5 . set th e di r bit a nd, in t he dma_ccrx re gist er , con f ig ur e int e r r up ts af te r ha lf t r an sf e r or f u ll t r a n sf e r de pen din g on a pplicat ion req u ir eme n t s . 6. ac tiv a te the channel b y s e tting the en bit in the dma_ccrx r egist er . whe n t he n u m ber of d a t a t r an sf er s which h a s b een pro g r a m m ed in t h e dm a con t r o lle r r e g i st er s is r e a c h ed, t h e dm a co nt ro ller se nds a n end of t r a n sf e r eo t/ eo t_ 1 sign al t o t h e i 2 c in t e rf a c e and th e dma gen er a t e s a n in te rr u p t , if en ab led, on th e dma ch an nel in te rr u p t v e ctor . no te : d o n o t en a b le th e itb u fen b i t in th e i2 c_ cr2 register if dma is us ed f o r tr a n sm iss i on . RM0033 inter-integrated circuit (i 2 c) interface doc id 15403 rev 3 585/1317 rece ption usi ng dma dma m ode can be ena b l ed f o r r e cep t io n b y set t i ng th e dmaen bit in t he i2 c_ cr2 re gist er . data will be loaded from the i2 c_dr register to a memor y ar ea configured us ing the dma p e r i ph er a l (r ef er t o t h e dm a spe c if icat ion ) whe n e v e r a da ta b yt e is r e cei v e d . t o ma p a dma cha nne l f o r i 2 c re ce pt ion , pe rf or m th e f o llo wing seq uen ce . he re x is t h e cha n n e l n u mb er . 1 . set t he i2 c_ dr r e g i st er ad dr ess in dma_cp arx regis t er . the data will be mo v e d from t h is a d d r ess to t h e m e mo r y af te r ea ch rxne e v ent . 2. set the memor y address in the dma_c m ar x register . the data w ill be loaded from the i2 c_ dr re gis t e r t o th is m e mo r y a r e a af te r e a ch rxn e e v en t. 3. configure the total n u mber of b y tes to be tr ans f erred in the dma_cndtr x register . after eac h rxn e e v ent, th is v a lue will be decremented. 4 . conf igu r e t h e ch ann el pr io r i ty using t h e pl [ 0 : 1 ] b i ts in t he dma_ccrx re gist er 5. reset the d i r bit and config ure interr upts in the dma_ccrx register after half tr ans f er or f u ll t r a n sf e r de pen din g on a pplicat ion req u ir eme n t s . 6. ac tiv a te the channel b y s e tting the en bit in the dma_ccrx register . whe n t he n u m ber of d a t a t r an sf er s which h a s b een pro g r a m m ed in t h e dm a con t r o lle r r e g i st er s is r e a c h ed, t h e dm a co nt ro ller se nds a n end of t r a n sf e r eo t/ eo t_ 1 sign al t o t h e i 2 c in te rf ace an d dma g e n e r a te s an in t e rr upt , if en ab led, on t h e dma chan ne l in te rr u p t ve ct o r . no te : d o n o t en a b le th e itb u fen b i t in th e i2 c_ cr2 register if dma is us ed f o r re ce pt ion . 23.3.8 p a c k et err o r c hec king a pec calculator has been im plemented to impro v e the relia bility of comm unication. the pec is calculated b y using the c(x ) = x 8 + x 2 + x + 1 crc- 8 po lynom ial se r i ally on ea ch bit . pec c a lc ulation is enab led b y s e tting the en pec bit in the i2c_cr1 regis t er . pec is a crc- 8 ca lcu l at ed o n all me ssag e b y t e s includ ing ad dr esses a nd r/ w bit s . ? i n tr an sm iss i on : set th e pec tr an sf er b i t in th e i2 c_ cr1 r e g i st er a fte r th e tx e e v ent corresponding to the last b yte . the p ec will be tr ansf e rred after the las t t r an sm itte d b y te . ? i n r e cep t io n: se t t he pec b i t in t h e i 2 c_ cr1 r egist er a f t e r th e rxne e v en t co rr espo ndin g to th e last b yte so t h a t t he r e ceiv er se nds a na ck if t h e n e xt r e ceiv ed b y te is no t e q u a l to t h e in te r n a lly ca lcu l a t e d p e c . in ca se o f m a ste r - r e c e iv er , a na ck mu s t f o llo w the pec whate v er the c h ec k result. the pec m u s t be set b e f o r e t he a c k o f t he crc r e cept ion in sla v e mo de . i t m u st be set wh en the a c k is set lo w in master mode . a pecerr er ro r f l ag /in t e r r u pt is also a v ailab l e in t h e i 2 c_ sr1 r e g i st er . i f dma and pec ca lcu l at ion a r e b o t h en ab led: - ? i n tr an sm iss i on : whe n th e i 2 c in te rf ace r e ceiv es an eo t sign al fr om t h e dma c o ntroller , it automatically se nd s a pe c a fte r th e las t b y te . ? i n re ce pt ion : w h e n th e i 2 c in te rf ace r e ceiv es an eo t_ 1 signa l f r om t he dma c o ntroller , it will automatic a lly cons ider th e ne xt b yte as a pec and will check it. a dm a r equ est is gen er a t e d af t e r pec r e cep t ion. t o allo w in te r m e d ia te pec tr a n s f e r s , a c o n t r o l bit is a v ailab l e in the i2c_cr2 register (l ast b i t ) to det er mine if it is really the last dma tr ansf er or not. if it is the last dma re qu est f o r a mast er r e cei v e r , a na ck is au to mat i cally sent a f t e r t he la st r e ceiv e d b y t e . pec calcula t io n is cor r up te d b y an a r b i tr at ion lo ss . inter-integrated circuit (i 2 c) interface RM0033 586/1317 doc id 15403 rev 3 23.4 i 2 c interrupts th e t a b l e be lo w giv e s t he list o f i 2 c int er r up t r equ est s . t not e : 1 sb , addr, add10, st o p f , btf , rxne an d txe ar e log i cally o r ed on t h e sa me int e r r up t cha nne l. 2 berr , ar lo , af , o v r, pecerr , timeout an d smbaler t a r e lo gically ored o n th e sam e int e r r upt chan nel. t a b l e 81 . i 2 c int e rr upt re que st s interrupt e v ent e vent fla g enab le contr o l bit sta r t bit se nt (master) s b itevfen address sent (ma s ter) or address ma tch ed (sla v e ) a ddr 10-b i t he ader sent (ma ste r) add10 st op r e ce i v ed ( s la v e ) s t o pf data b yte t r ansf e r finished bt f recei v e b u ff er not empty r xne itevfen and itb u fen t r ansmit b u ff er empty t xe bus error berr iterren arbitr atio n loss (master) arl o ac kn o wle dge f a i l ure a f ov e r r un/und e rr un o v r pec err o r pecerr ti me out/tlo w error t imeout sm bus aler t s m bale r t RM0033 inter-integrated circuit (i 2 c) interface doc id 15403 rev 3 587/1317 figu re 22 1. i 2 c int e rr upt map p ing dia g ram addr sb add10 rxne txe btf it_event arlo berr af ovr pecerr timeout smbalert iterren it_error itevfen itbufen stopf inter-integrated circuit (i 2 c) interface RM0033 588/1317 doc id 15403 rev 3 23.5 i 2 c deb u g mode whe n t he micro c ont r o ller ent er s t h e d e b u g m ode ( c or t e x-m3 co re h a lt ed) , t h e sm b u s t i me out eit h e r co nt in ue s t o w o r k n o r m a lly o r sto p s , dep en ding o n t he dbg_ i2 cx_ s m b us_ti m eo ut con f ig ur a t io n bit s in th e dbg m odu le . f o r mor e de t a ils , re f e r to se ctio n 3 2 . 1 6 . 2 : de b u g su pp o r t f o r tim e rs , w a tc hd og , bx can a n d i 2 c o n pa g e 12 92 . 23.6 i 2 c registe r s ref e r to se ct ion 1 . 1 on p age 4 6 f o r a list o f ab b r e v ia t i ons used in r e g i st er descr ipt i on s . th e pe r i phe r a l r egist er s can b e accesse d b y ha lf- w o r d s ( 16- bit ) o r w o rds (3 2- bit ) . 23.6.1 i 2 c contr o l register 1 (i2c_cr1) ad dre s s of f s e t : 0x00 re se t v a lu e: 0x 00 0 0 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 65432 10 sw r st res . a l er t pec p o s a ck st op st ar t no stretch eng c enpec enarp smb type res . smb u s p e r w rw r w rw r w rw rw rw rw r w rw rw rw rw bit 15 swrst : softw a re reset w hen se t, the i2c is und er reset state . be f o re re se tting th is bi t, mak e su re th e i2c l i nes a r e rel eased a nd th e b u s is free . 0: i 2 c p e r i phe r a l n o t un der reset 1: i 2 c p e r i phe r a l u nder reset state n o te: t h i s bi t ca n b e use d in case the b u sy bit is se t to ?1 when no sto p con d ition has been detected on the b u s . bit 1 4 r e ser v ed, f o rced b y hardw a r e to 0. bit 13 al er t : smbus aler t this bit is se t and cl eared b y softw a r e , and cl eared b y ha rdw a re whe n pe= 0. 0: rele ases smba pin h i gh. aler t r e spon se ad dress head er f o llo w e d b y na ck. 1: dr iv e s smba p i n lo w . aler t re sponse add r ess h eade r f o llo w ed b y a c k. bit 12 pec : p a c k e t er ror chec k i ng this bit is se t an d cl eared b y softw are , an d cl eared b y h a rdw a re whe n pec i s tr an sf erred or b y a st ar t or sto p conditi on or when pe= 0. 0: no pec tr ansf er 1: pec tr a n sf er (in tx or rx mo de) n o te: pec ca lcula t i on is corr upted b y an a r b i tr ation l o ss . RM0033 inter-integrated circuit (i 2 c) interface doc id 15403 rev 3 589/1317 bit 11 pos : ac kno w l edge /pec p o siti on (f or data recep t io n) this bit is se t and cl eared b y softw a r e and clea red b y hardw a r e w hen pe=0 . 0: a c k bit controls th e (n)a ck of the curren t b yte bei ng receiv e d in the shift reg i ste r . the pec bit indicates that current b y te in shift regist er is a pec . 1: a c k bit controls th e (n)a ck of the ne xt b yte wh ich will b e re ceiv ed in th e sh ift regi ster . the pec bit i ndica te s that th e n e xt b yte i n th e sh ift regi ster is a pec n o te: t h e pos bit must b e u sed onl y in 2 - b yte rece ption con f ig ur a t i on in master mod e . it m u st be config ured bef ore data recep t io n star ts , as descr ib ed in the 2-b y te recep t i on proce dure recommend ed in section : ma ster recei v er on pag e 578 . bit 10 ac k : ac kno w l edge e nab le this bit is se t and cl eared b y softw a r e and clea red b y hardw a r e w hen pe=0 . 0: no ac kno w l edge re tu r n e d 1: ac kn o wled ge retur ned after a b yte i s recei v ed (matched ad dress or d a ta) bit 9 st op : stop g ene r a tion the bit is se t an d cl eared b y softw are , cl ea red b y hardw a r e w hen a stop cond iti on is de te cted , set b y h a rdw a re wh en a ti me out error i s de te cte d . in master mode: 0: no sto p gene r a tio n . 1: stop gene r a tio n a f ter the current b yte tr a n sf er or after the current star t co ndi ti on is se nt. in sl a v e mo de : 0: no sto p gene r a tio n . 1: rele ase th e scl and sd a lin es a f ter th e current b yte tr a n sf er . n o te: w h en th e st op , st ar t or pec bit i s set, the softw are m u st n o t p e rf or m an y wr i t e access to i2c_ cr1 bef ore th is b i t i s clea red b y hardw a r e . othe rw ise th ere is a r i sk o f setti ng a second st op , st ar t or pec req uest. bit 8 st ar t : star t gene r a tio n this bit is se t and cl eared b y softw a r e and cl ea red b y hardw a r e w hen star t is sent or pe= 0. in master mode: 0: no sta r t gener a t i o n 1: repe ated sta r t gen er a t i o n in sl a v e mo de : 0: no sta r t gener a t i o n 1: sta r t gen er a t io n when the b u s i s free bit 7 no str e t c h : cloc k stre tchi ng disa b l e (sla v e mo de) this bit is used to di sa b l e cloc k stretchin g i n sla v e mo de when addr or btf fla g i s set, until it is reset b y softw a re . 0: cloc k stre tchi ng ena b l e d 1: cloc k stre tchi ng disa b l ed bit 6 engc : gen e r a l ca ll ena b l e 0: ge neral call di sa b l e d . add r ess 0 0h is na ck e d . 1: ge neral call en ab le d. ad dress 0 0h is a c k e d . bit 5 enpec: pec enab le 0: pec ca lcula t io n disab l ed 1: pec ca lcula t io n ena b l ed inter-integrated circuit (i 2 c) interface RM0033 590/1317 doc id 15403 rev 3 23.6.2 i 2 c contr o l register 2 (i2c_cr2) ad dre s s of f s e t : 0x04 re se t v a lu e: 0x 00 0 0 bit 4 enarp : arp enab le 0: arp disab l e 1: arp e nab le smbus de vi ce def a u lt a ddress recogn iz ed if smbtype= 0 smbus host address re cogniz ed if smbtype=1 bit 3 smbtype : smbu s t ype 0: sm bus de vice 1: sm bus host bit 2 r eser v ed, f o rced b y hardw a r e to 0. bit 1 smb u s : smbus m o de 0: i 2 c mode 1: sm bus mode bit 0 pe : p e r i pheral en ab le 0: p e r i phe r a l d i sab l e 1: p e r i phe r a l e nab l e : the corresp ondi ng ios are selected as al ter n a t e functio n s d epe ndin g on smbus bit. n o te: i f th is bit i s rese t whil e a comm uni cation is on go ing, th e per i pheral is disab led a t th e end o f the current comm uni cation, when b a c k to idle state . all bit resets d ue to pe= 0 occur at the en d o f the comm un ication . in ma ster mode , thi s b i t m u st not be reset bef o r e the e nd of the comm u n icatio n. 1 5 1 4 1 3 1 2 1 1 1 0 987 654321 0 reser v e d l ast dma en it b u f en i t evt en ite r r en reser v ed f r eq [5 :0] rw r w r w rw rw rw r w rw rw rw rw bi ts 15:13 rese r v ed , f o rced b y h a rdw a re to 0. bit 12 la st : dm a last t r ansf e r 0: ne xt d m a eo t is n o t the la st transf e r 1: ne xt d m a eo t is the la st tr an sf er note: t his b i t i s u s ed in ma ster recei v er mode to p e r m it the ge neration o f a na ck on the l a st rec e iv ed data. bit 11 dmaen : d m a requ ests en ab le 0: dma requ ests disa b l ed 1: dma requ est en ab le d when txe=1 or rxne =1 bit 10 it b u f e n : buff er interr up t en ab le 0: txe = 1 o r rxne = 1 do es n o t g enerate an y i n terr up t. 1:txe = 1 or r x ne = 1 generates event interrupt (whatever the state of dmaen) RM0033 inter-integrated circuit (i 2 c) interface doc id 15403 rev 3 591/1317 bit 9 itevten : ev ent interr u p t en ab l e 0: ev e n t in te rr upt disab l ed 1: ev e n t in te rr upt enab led th is i n terr upt is g ene r a ted wh en: ?sb = 1 (m as ter) ? a ddr = 1 (master/sl a v e ) ? a dd1 0= 1 (maste r ) ?st o pf = 1 (sl a v e ) ? b tf = 1 with no txe or rxne e v e n t ?txe e v ent to 1 if it b u f e n = 1 ? r xne e v ent to 1 i f i t bufen = 1 bit 8 iterren : erro r in te rr upt enab le 0: error interr upt disab l ed 1: error interr upt enab led th is i n terr upt is g ene r a ted wh en: ?b e r r = 1 ?a r l o = 1 ?a f = 1 ?o v r = 1 ? p ec err = 1 ?t i m e o u t = 1 ?s m b a l e r t = 1 bits 7: 6 r e ser v e d, f o rce d b y ha rd w a re to 0 . bits 5:0 freq[5:0] : p e r i phe r a l clo c k freque ncy th e p e r i p heral cloc k freq uency m u st be config u r e d using the in put apb cloc k frequency (i2 c per i phe r a l con nected to apb). the mini m u m allo w e d freq uency is 2 m hz, th e ma x i m u m fre quen cy is limited b y the maximum apb freq uen c y (30 m hz ) a nd an in tr i n sic limitation o f 46 mhz. 0b0 0000 0: no t al lo w ed 0b0 0000 1: no t al lo w ed 0b0 0001 0: 2 mhz .. . 0b0 1111 0: 3 0 mhz high e r tha n 0b0 1111 0: no t al lo w e d inter-integrated circuit (i 2 c) interface RM0033 592/1317 doc id 15403 rev 3 23.6.3 i 2 c own ad dress regi ster 1 (i2c_o ar1) ad dre s s of f s e t : 0x08 re se t v a lu e: 0x 00 0 0 23.6.4 i 2 c own ad dress regi ster 2 (i2c_o ar2) ad dre s s of f s e t : 0x0c re se t v a lu e: 0x 00 0 0 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6543 21 0 ad d mode reser v ed add[9 : 8 ] add[7:1] add0 rw rw rw rw r w rw rw rw rw rw rw bi t 15 addmode ad dressin g mo de (sla v e mode ) 0: 7 - bit sla v e add ress (1 0-bit addre s s no t ac kno w l edg ed) 1: 1 0 -bit sla v e ad dress (7-bit addre s s no t ac kno w l edg ed) bi t 14 shou ld alw a ys b e k ept a t 1 b y softw a re . bi ts 13:10 rese r v ed , f o rce d b y h a rdw a re to 0. bits 9:8 add[9 : 8] : interf ace ad dress 7-bit add ressing mode : do n?t ca re 10-b i t ad dressing mod e : b i ts9 : 8 o f add ress bits 7:1 add[7 : 1] : interf ace ad dress bits 7 : 1 o f ad dress bit 0 add0 : interf ace ad dress 7-bit add ressing mode : do n?t ca re 10-b i t ad dressing mod e : b i t 0 of addre s s 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 54321 0 re s e r v ed a d d2 [7:1] e ndu al rw rw rw rw rw rw rw rw bits 15:8 r eser v ed, f o rced b y hard w a r e to 0. bits 7:1 add2[7:1 ] : in te rf ace add ress b i ts 7:1 of a ddress in du al add ressing mod e bit 0 en du a l : d ual ad dressing mod e enab le 0 : on ly o a r1 is recogn iz ed in 7-b i t ad dressing mod e 1: both oar1 and oar2 are recognized in 7-bit addressing mode RM0033 inter-integrated circuit (i 2 c) interface doc id 15403 rev 3 593/1317 23.6.5 i 2 c data register (i2c_dr) ad dre s s of f s e t : 0x10 re se t v a lu e: 0x 00 0 0 23.6.6 i 2 c status register 1 (i2c_sr1) ad dre ss of f s e t : 0x14 re se t v a lu e: 0x 00 0 0 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 54321 0 re s e r v ed dr[7: 0] rw rw rw rw r w r w rw r w bits 15: 8 res e r v ed, f o r c ed b y hardw a re to 0. bits 7:0 d r [ 7: 0] 8- bi t da t a reg i ste r byte rece iv ed or to be transmitted to the b u s . ? t r a n s mi tter mo de: byte tr an smi s si on sta r ts aut omatical ly w hen a b y te is wr itte n in th e dr re gister . a con t i n u ous transmit stream can be ma in ta ined if th e n e xt data to be tr a n smitted is p u t in d r o n ce th e transmissio n i s star ted (txe= 1 ) ? r e c e i v e r mode : rece iv ed b y te is copie d in to dr (rxne=1). a con t i n u ous transmit strea m ca n be main tai ned if dr is re ad bef ore th e ne xt data b y te is re ceiv e d (r xn e=1). no te: i n sla v e mo de , the ad dress is n o t co pied i n to d r. no te: w r i te coll ision i s no t mana ged (dr can be wr itten i f txe= 0). no te: i f a n arlo e v en t occurs on a c k pu lse , the recei v ed b yte is not co pie d i n to dr and so ca nno t be rea d . 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 54321 0 smb al er t ti me out res . pe c er r o v r a f a rlo b err t xe rxne re s . st opf a dd10 b tf a d dr sb r c _ w 0 r c_ w 0 r c_ w 0 r c _ w 0 r c_ w 0 r c _ w 0 r c_ w 0 r r rrrr r bit 15 smb a ler t : sm bus aler t in smbus host mode: 0: no smbaler t 1: smbaler t e v ent o ccurred on pi n in smbus sl a v e mode : 0: no smbaler t respo n se add re ss he ade r 1: smbaler t respon se a ddress hea der to smbaler t lo w re ce iv ed ? clea r e d b y so ftw a re wr itin g 0, or b y hard w a r e when pe= 0. bit 14 ti meout : timeou t or tlo w e r ro r 0: no timeou t error 1: scl remai ned lo w f o r 2 5 ms (ti m e out) or ma ster cum u lativ e clo c k lo w e xtend time mo re tha n 10 ms (tlo w:me xt) or sl a v e cumulativ e cl oc k l o w e xtend time more th an 25 ms (tlo w:se xt) ? w he n se t in sla v e mod e : sla v e resets the comm u n ication a nd lin es a r e re lease d b y ha rdw a re ? w he n se t in master mo de: stop con d ition se nt b y ha rd w a re ? clea r e d b y so ftw a re wr itin g 0, or b y hard w a r e when pe= 0. note: t his functiona lity i s a v aila b l e o n ly in smbu s mod e . inter-integrated circuit (i 2 c) interface RM0033 594/1317 doc id 15403 rev 3 bit 13 reser v ed , f o rced b y ha rdw a re to 0 . bit 12 pecerr : pec error in r e ception 0: no pec error : recei v er re tu r n s a c k a f ter pec rece ption (if a c k=1 ) 1: pec error : receiv er retur n s na ck after pec rece pti on (wha te v e r a c k) ?cle ared b y softw a re wr iti ng 0, o r b y ha rdw a re whe n pe= 0 . ?note: w hen the rece iv ed cr c i s wron g, pecerr is no t set i n sl a v e mode i f th e pec con t ro l b i t i s no t set b e f o re the en d of the crc rece pti on. ne v e r t h e le ss , re adin g th e pec v a lue de te r m in es w hether the receiv ed crc is r i gh t or wrong . bit 11 ov r : ov err u n / u nderr u n 0: no o v e r r un/und err u n 1: ov err u n o r un derr u n ?set b y ha rdw a re in sla v e mo de whe n nostretch = 1 an d: ?in rece ption whe n a ne w b y te is re ceiv ed (in cludi ng a c k pulse ) an d the dr regi ster has not b een rea d y e t. ne w receiv ed b yte is l o st. ?in tr a n smission wh en a ne w b yte shou ld be sen t and the dr reg i ste r h a s n o t be en wr i t ten y e t. the same b yte is s e nt twice . ?cle ared b y softw a re wr iti ng 0, o r b y ha rdw a re whe n pe= 0 . note: if th e dr wr ite occurs v e r y close to scl r i si ng e dge , the sen t d a ta is u n specifie d an d a hold timing error occurs bit 10 af : ac kn o wle dge f ai l ure 0: no ac kn o wled ge f a i lure 1: ac kno w l edge f a ilu re ?set b y ha rdw a re whe n no ac kno wl edge is retur ned . ?cle ared b y softw a re wr iti ng 0, o r b y ha rdw a re whe n pe= 0 . bi t 9 arlo : arbi t r a t i o n l o st (ma st er mo de ) 0: no arbi trati on lo st detected 1: arbitr a t i on lost detected se t b y hard w are when the in te rf ace loses t he arbi tration of th e b u s to an other maste r ?cle ared b y softw a re wr iti ng 0, o r b y ha rdw a re whe n pe= 0 . after an arlo e v e n t the in terf a ce s witche s ba c k au to ma ti ca lly to sl a v e mode (m/ sl =0). note: i n smb u s , the a r bitr atio n on the data in sl a v e mode o ccu rs o n ly dur i ng the data ph ase , o r the ac kno w ledg e transmission (n ot on the ad dress ac kno wledge). bi t 8 berr : bus error 0: no mispl a ced star t or sto p condi ti on 1: mispl a ced star t or sto p co ndi ti on ?set b y ha rdw a re w hen th e in te rf ace de te cts a n sd a r i sing or f a l ling edg e wh ile sc l is h i gh, o c cu rr ing in a n on-v a l id posi t i on dur i ng a b yte transf e r . ?cle ared b y softw a re wr iti ng 0, o r b y ha rdw a re whe n pe= 0 . bi t 7 tx e : data regi ster empty (tr a nsmitters) 0: da ta reg iste r no t empty 1 : da t a re gist er e m pt y ?set wh en dr is empty i n tr a n smission . txe is not se t du r i ng ad dress pha se . ?cle ared b y softw a re wr iti ng to the dr reg i ster o r b y ha rd w a re afte r a star t or a sto p co nd i t i o n or w h e n pe= 0 . txe is n o t set if ei th er a na ck is re ceiv e d , or if ne x t b yte to be tr ansmit ted is pec (pe c = 1 ) note: t xe i s no t clea red b y wr iting the first da ta be ing tr a n smitted , or b y wr iting d a ta when btf is set, as in both cases t he data regi ster is sti ll empty . RM0033 inter-integrated circuit (i 2 c) interface doc id 15403 rev 3 595/1317 bi t 6 rxne : data re gister not empty (recei v ers) 0 : da t a re gist er e m pt y 1: da ta reg iste r no t empty ?set wh en da ta reg i ste r is no t empty i n re ceiv e r mod e . rxne is n o t set dur i ng add ress p hase . ?cle ared b y softw a re rea d in g o r wr iti ng the dr register or b y h a rdw a re wh en pe=0. rxne i s no t set i n case of arl o e v ent. note: r xne is not cleare d b y re adin g data when bt f is set, as th e data register is stil l ful l . bi t 5 r eser v e d , f o rced b y ha rdw a re to 0 . bi t 4 st opf : s t op detection (sla v e mode) 0: no stop cond ition de te cted 1: stop cond ition de te cted ?set b y ha rdw a re whe n a stop con d ition is de te cte d o n th e b u s b y the sla v e afte r a n ac kno w l e dg e (i f a c k= 1) . ?cle ared b y softw a re rea d in g the sr1 reg i ster f o llo w e d b y a wr i t e in the cr1 re gister , or b y hardw a re when pe=0 note: t he st opf bi t is not se t after a n a ck reception . it is recommend ed to perf o r m the co mp lete clear ing seq uence (read sr1 then wri t e cr1) afte r the st opf is set. ref e r to fi gure 2 1 8 : t r an sf er sequence dia g ram f o r sla v e receiv er o n page 5 7 5 . bi t 3 add1 0 : 10 -bit h ead er se nt (master mo de) 0: no add1 0 e v ent o ccurred. 1: master has sent first a ddress b yte (h ead er). ?set b y ha rdw a re whe n the master has s ent th e first b yte i n 1 0 -bit add ress mod e . ?cle ared b y softw a re rea d in g the sr1 reg i ster f o llo w e d b y a wr i t e in the dr reg i ste r of th e seco nd add ress b yte , o r b y ha rdw a re whe n pe= 0 . note: a dd1 0 bit is n o t set afte r a na ck rece ption bi t 2 btf : byte transf e r fini sh ed 0: dat a b yte tr ansf e r not done 1: da ta b yte tr ansf e r su cce eded ?set b y ha rdw a re whe n nostretch = 0 an d: ?in rece pti on whe n a ne w b yte is re ceiv e d (i nclud i ng a c k pu lse) and dr ha s n o t be en read y e t (rxne=1). ?in tr an smi ssion whe n a ne w b yte shoul d be sent and dr ha s no t be en wr itten y e t (txe=1). ? c l e ar ed b y s o f t w a re b y e i th er a re ad or w r i t e in t h e dr reg i ste r or b y h a rd w a re a f t e r a star t or a sto p co ndi tio n in tr ansmissio n or w hen pe=0 . note: t he btf bit i s n o t set after a na c k rece pti o n the btf bit i s n o t set if ne xt b yte to be tr an smitted is th e pec (tra=1 in i2c_ sr2 reg i ster a nd pec=1 in i2c_ cr1 regi ste r ) inter-integrated circuit (i 2 c) interface RM0033 596/1317 doc id 15403 rev 3 bi t 1 addr : address sent (ma s ter mode )/matched (sla v e mo de) thi s bi t is clea re d b y so ftw a re read ing sr1 reg i ste r f o llo w ed rea d ing sr2 , or b y hardw are when pe= 0. ad dr ess matc hed (sla ve) 0: add r e ss mismatched o r no t recei v ed. 1: re ce iv ed a ddress match ed. ?set b y ha rdw a re as soon as the receiv ed sla v e a ddress match ed with the o a r regi ste r s con t e n t o r a ge neral call or a smbu s de vice de f aul t addre s s or smbu s ho st or smbu s ale r t is recogn iz ed. (wh en en ab le d depe ndi ng on config ur a t io n). note: i n sla v e mod e , it is re co mme nded to pe rf or m the comple te cle a r i n g se que nce (r ead sr1 then re ad sr2) after addr is set. ref e r to figu re 218: t r ansf e r seq uence d iag r a m f o r sla v e re ceiv e r on p age 57 5 . ad dr ess se nt (ma s ter) 0: no en d of a ddress transmissio n 1: end o f add re ss tr ansmission ?f or 10-bi t ad dressing , the bit is se t afte r the a c k o f th e 2nd b yte . ?f or 7-bit add re ssing, th e b i t i s set after the a c k of the b yte . note: a ddr i s no t set a f ter a na ck recep t i o n bi t 0 sb : star t bit (master mode) 0: no star t con d ition 1: star t cond ition g enerated. ?set wh en a sta r t cond ition ge nerated. ?cle ared b y softw a re b y rea d ing the sr1 reg i ste r f o llo w ed b y wr itin g the d r re gister , or b y hardw a re when pe=0 RM0033 inter-integrated circuit (i 2 c) interface doc id 15403 rev 3 597/1317 23.6.7 i 2 c status register 2 (i2c_sr2) ad dre s s of f s e t : 0x18 re se t v a lu e: 0x 00 0 0 no te : r e a d i ng i 2 c _ sr 2 aft e r r e a d i ng i2 c_ sr1 cle a r s th e addr fla g , e v en if th e addr fla g w a s set af t e r r e a d ing i2 c_sr1. co nsequ en tly , i 2 c_sr2 m u st be r e a d on ly whe n addr is f o und set in i2 c_sr1 or whe n t he st opf bit is clea re d. 1 5 14 13 12 1 1 1 0 9 8 7 6 5 4 3 2 1 0 p e c [7 :0 ] d u a l f smb host smb d e fa u l t gen cal l re s . tra b usy m sl r r r r rrrr r r r r r r r bits 15: 8 pec[7:0] p a c k e t error chec king register th is re gister co ntains the inter nal pec whe n enpec=1. bit 7 du alf : d ual flag (sla v e mo de) 0: r e ceiv e d addre s s matched wi th o a r1 1: r e ceiv e d addre s s matched wi th o a r2 ? cle ared b y ha rd w a re afte r a stop cond iti on or repe ate d sta r t condi ti on, o r wh en pe=0 . bit 6 smbhost : smbus host head er (sl a v e mode ) 0: n o smbus host addre s s 1: smbus host address receiv ed when s m btype =1 and enarp=1. ? cle ared b y ha rd w a re afte r a stop cond iti on or repe ate d sta r t condi ti on, o r wh en pe=0 . bit 5 smbdef a ul t : smbus de vice def a u lt addre s s (sla v e mo de) 0: n o smbus de vice def a ult addre s s 1: smbus de vice def a ult a ddress recei v ed whe n en arp=1 ? cle ared b y ha rd w a re afte r a stop cond iti on or repe ate d sta r t condi ti on, o r wh en pe=0 . bit 4 gencall : gene r a l cal l addre s s (sla v e mo de) 0 : no ge ne r al ca l l 1: gene r a l c a ll addre s s recei v ed whe n engc= 1 ? cle ared b y ha rd w a re afte r a stop cond iti on or repe ated sta r t condi ti on, o r wh en pe=0 . bi t 3 r es er v e d , f o r ced b y ha rd w a re to 0 . bit 2 tra : t r ansm it ter/receiv er 0: da ta b yte s recei v ed 1: da ta b yte s t r an smi t t e d th is b i t is set depe nding on the r/w bit o f the add ress b yte , at the en d o f total add ress pha se . it is also clea red b y hardw are a f ter detection o f sto p co nditio n (st o pf=1 ), repe ated sta r t cond iti on, loss of b u s a r b i tr ation (arl o= 1), or whe n pe= 0 . bit 1 bu s y : bus b u sy 0: n o co mmuni ca ti on on the b u s 1: c o mm uni cation on goin g on th e b u s ? s et b y h a rdw a re on d e tecti on of sd a or scl lo w ? cle ared b y hardw a r e o n detection o f a sto p co ndi tio n . it ind i cates a co mmunica ti on in progress on the b u s . this in f o r m a t i on is stil l upda te d when th e interf ace i s di sab l e d (pe= 0). inter-integrated circuit (i 2 c) interface RM0033 598/1317 doc id 15403 rev 3 23.6.8 i 2 c cloc k contr o l register (i2c_ccr) ad dre s s of f s e t : 0x1c re se t v a lu e: 0x 00 0 0 not e : 1 t o use th e i 2 c at 40 0 khz (in f a st mod e ) , th e pclk1 fr eq ue ncy (i 2c p e r i ph er a l inp u t cloc k) m u st be a m u lt ip le of 1 0 mhz. 2 t h e ccr re giste r m u st b e conf igu r e d on ly when th e i2 c is disab l ed ( pe = 0). bit 0 msl : m a st er/sla v e 0: sl a v e mode 1: master mode ? s et b y h a rdw a re as soon a s the in te rf ace is i n ma ste r mode (sb= 1). ? cle ared b y ha rd w a re afte r de te ctin g a stop co nditio n o n th e b u s or a l o ss o f arbitration (arl o= 1), o r b y hard w are when pe= 0. 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 54321 0 f/s duty reser v e d ccr[1 1 :0] rw rw r w rw r w rw rw rw rw rw r w r w rw r w bit 15 f/s : i2c m a ster mode selection 0: sta ndard mod e i2c 1: f a st mode i2c bit 14 du t y : f a st mo de du ty cycl e 0: f a st mode t lo w /t hi gh = 2 1: f a st mode t lo w /t hi gh = 1 6 /9 (se e ccr) bits 13 :1 2 r eser v ed, f o rced b y hardw a r e to 0. bits 11:0 c cr[11:0]: clock control register in fast/standard mode (master mode) controls the scl clock in master mode. standard mode or smbus : t hi gh = ccr * t pcl k 1 t lo w = cc r * t pclk1 fast mode : if duty = 0: t hi gh = ccr * t pcl k 1 t lo w = 2 * ccr * t pclk1 if duty = 1: (to re ach 400 khz) t hi gh = 9 * ccr * t pcl k 1 t lo w = 1 6 * c cr * t pclk1 f o r in stan ce: in stand ard mode , to ge nerate a 1 00 khz sc l freq uency: if freq r = 08, t pcl k 1 = 125 n s so ccr mu st be programme d with 0x28 (0x28 < = > 4 0d x 125 ns = 50 00 ns .) n o te : 1 . the mini m u m all o w e d v a lue i s 0x0 4 , e xcept in f ast d u ty mode whe r e th e minimum a llo w ed v a lue is 0x01 2. 3. 4. the s e timin g s a r e w i thout fi lte r s . 5. the ccr reg i ster must be con f i gured o n ly when the i 2 c is d i sa b l ed ( pe = 0 ) . RM0033 inter-integrated circuit (i 2 c) interface doc id 15403 rev 3 599/1317 23.6.9 i 2 c trise register (i2c_trise) ad dre s s of f s e t : 0x20 re se t v a lu e: 0x 00 0 2 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 54321 0 reser v e d tri se[ 5: 0] rw rw r w r w rw r w bits 15: 6 reser v ed, f o rc ed b y ha rd w a re to 0 . bits 5:0 tr is e[5: 0] : maxim u m r i se time in f a st/stan dard mode (master mo de) th ese bits m u st b e prog r a mmed wi th the maximum scl r i se time gi v en in the i 2 c b u s speci f ica t i on, i n cremented b y 1. f o r instance : in stand ard mo de , the maximum a llo w ed scl r i se time is 100 0 n s . if , i n the i2c_ cr2 reg i ster , the v a lue o f freq[5 :0] bi ts i s e qua l to 0x08 and t pcl k 1 = 12 5 ns theref o r e th e trise[5 : 0] bits must b e p r og r a mmed wi th 09 h. (100 0 ns / 125 n s = 8 + 1 ) t h e f i l t er v a l u e ca n al so b e a d d e d to t r ise[ 5: 0] . if the re sult is no t a n integ e r , trise[5:0] m u st be prog r a mmed with the i n te ger p a r t , in order to r e spect the t hi gh par a meter . note: trise[5:0] must be configured only when the i2c is disabled (pe = 0). inter-integrated circuit (i 2 c) interface RM0033 600/1317 doc id 15403 rev 3 23.6.10 i 2 c register map th e t a b l e be lo w pr o v id es th e i 2 c re giste r ma p and rese t v a lu es . ref e r to t a b l e 1 on p age 50 f o r t h e r e g i st er bou nd ar y ad dr esse s t a b l e . t ab l e 82. i 2 c re gi st er map an d res e t v a l u e s offset registe r 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 i2c_cr1 reser v ed swrs t reserved alert pec pos ack stop start nostretch engc enpec enarp smbtype reserved smbus pe r e s e t v a l u e 0 00 00 0 0 00000 00 0x04 i2c_cr2 reser v ed las t dma e n it b u fe n i t evten iterre n reser v ed f r eq [5 :0] r e s e t v a l u e 0 00 0 0 000000 0x08 i2 c _ o ar1 reser v ed a ddmode reserved add[9 : 8] a dd[7:1] add0 reset v a lu e 0 0 0 00000000 0x 0c i2 c _ o ar2 re se r v e d a dd2 [7 :1 ] endu a l reset v a lu e 00000000 0x10 i2c_dr re se r v e d dr[7:0] reset v a lu e 00000000 0x14 i2 c_ s r 1 reser v ed smbalert timeout reserved pecerr ovr af arlo berr txe rxne reserved stopf add10 btf addr sb r e s e t v a l u e 0 0 0 00 0 0 00 00000 0x18 i2 c_ s r 2 reser v ed pe c [ 7: 0 ] dualf smbhost smbdefault gencall reserved tra busy msl r e s e t v a l u e 0000 00 0 0 0000 000 0x 1c i2c_ccr reser v ed f/s duty reser v ed ccr[11:0] r e s e t v a l u e 0 0 00 0 0 00000000 0x20 i2 c_ tris e re se r v e d tris e[5:0] reset va lu e 000010 RM0033 universal synchronous asynchronous receiver transmitter (usart) doc id 15403 rev 3 601/1317 24 universal synchronous asynchronous receiver transmitter (usart) 24.1 usart introduction the universal synchronous asynchronous receiver transmitter (usart) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard nrz asynchronous serial data format. the u sart offers a very wide range of baud rates using a fractional baud rate generator. it supports synchronous one-way communication and half-duplex single wire communication. it also supports the lin (local interconnection network), smartcard protocol and irda (infrared data association) sir endec specifications, and modem operations (cts/rts). it allows mult iprocessor communication. high speed data communication is possible by using the dma for multibuffer configuration. 24.2 usart main features full duplex, asynchronous communications nrz standard format (mark/space) configurable oversampli ng method by 16 or by 8 to gi ve flexibility be tween speed and clock tolerance fractional baud rate generator systems ? a common programmable transmit and receive baud rate of up to 7.5 mbit/s when the apb frequency is 60 mhz and oversampling is by 8 programmable data word length (8 or 9 bits) configurable stop bits - support for 1 or 2 stop bits lin master synchronous break send ca pability and lin slav e break detection capability ? 13-bit break generation and 10/11 bit break detection when usart is hardware configured for lin transmitter clock output for synchronous transmission irda sir encoder decoder ? support for 3/16 bit duration for normal mode smartcard emulation capability ? the smartcard interface supports the asynchronous protocol smartcards as defined in the iso 7816-3 standards ? 0.5, 1.5 stop bits for smartcard operation single-wire half-duplex communication configurable multibuffer communication using dma (direct memory access) ? buffering of received/transmitted bytes in reserved sram using centralized dma separate enable bits for transmitter and receiver universal synchronous asynchronous receiver transmitter (usart) RM0033 602/1317 doc id 15403 rev 3 transfer detection flags: ? receive buffer full ? transmit buffer empty ? end of transmission flags parity control: ? transmits parity bit ? checks parity of received data byte four error detection flags: ? overrun error ? noise detection ?frame error ? parity error ten interrupt sources with flags: ? cts changes ? lin break detection ? transmit data register empty ? transmission complete ? receive data register full ? idle line received ? overrun error ? framing error ? noise error ? parity error multiprocessor communication - enter into mute mode if address match does not occur wake up from mute mode (by idle line detection or address mark detection) two receiver wakeup modes: address bit (msb, 9 th bit), idle line 24.3 usart functional description the interface is externally connected to another device by three pins (see figure 222 ). any usart bidirectional communication requires a minimum of two pins: receive data in (rx) and transmit data out (tx): rx: receive data input is the serial data input. oversampling techniques are used for data recovery by discriminating between valid incoming data and noise. tx: transmit data output. when the transmitter is disabled, the output pin returns to its i/o port configuration. when the transmitter is enabled and nothing is to be transmitted, the tx pin is at high level. in single-wire and smartcard modes, this i/o is used to transmit and receive the data (at usart level, data are then received on sw_rx). RM0033 universal synchronous asynchronous receiver transmitter (usart) doc id 15403 rev 3 603/1317 through these pins, serial data is transmitted and received in normal usart mode as frames comprising: an idle line prior to transmission or reception a start bit a data word (8 or 9 bits) least significant bit first 0.5,1, 1.5, 2 stop bits indicating that the frame is complete this interface uses a fractional baud rate generator - with a 12-bit mantissa and 4-bit fraction a status register (usart_sr) data register (usart_dr) a baud rate register (usart_brr) - 12-bit mantissa and 4-bit fraction. a guardtime register (usart_gtpr) in case of smartcard mode. refer to section 24.6: usart registers on page 638 for the definitions of each bit. the following pin is required to interface in synchronous mode: sclk: transmitter clock output. this pin outputs the transmitter data clock for synchronous transmission corresponding to spi master mode (no clock pulses on start bit and stop bit, and a software option to send a clock pulse on the last data bit). in parallel data can be received synchronously on rx. this can be used to control peripherals that have shift registers (e.g. lcd drivers). the clock phase and polarity are software programmable. in smartcard mode, sclk can provide the clock to the smartcard. the following pins are required to interface in irda mode: irda_rdi: receive data input is the data input in irda mode. irda_tdo: transmit data output in irda mode. the following pins are required in hardware flow control mode: ncts: clear to send blocks the data transmission at the end of the current transfer when high nrts: request to send indicates that the usart is ready to receive a data (when low). universal synchronous asynchronous receiver transmitter (usart) RM0033 604/1317 doc id 15403 rev 3 figure 222. usart block diagram w a ke u p u nit receiver control s r tr a n s mit control txetc rxneidleore nf fe u s art control interr u pt cr1 m wake receive d a t a regi s ter (rdr) receive s hift regi s ter re a d tr a n s mit d a t a regi s ter (tdr) tr a n s mit s hift regi s ter write s w_rx tx (d a t a regi s ter) dr tr a n s mitter clock receiver clock receiver r a te tr a n s mitter r a te f pclkx(x=1,2) control control / [ 8 x (2 - over 8 )] convention a l bau d r a te gener a tor s bk rwu re te idle rxne tcie txeie cr1 ue pce p s peie pe pwdata irlp s cen iren dmar dmat u s art addre ss cr2 cr 3 irda s ir endec b lock line cken cpol cpha lbcl s clk control s clk cr2 gt s top[1:0] nack div_m a nti ssa 15 0 re u s art_brr / u s artdiv te hd (cpu or dma) (cpu or dma) prdata h a rdw a re flow controller ct s lbd rx irda_out irda_in nrt s nct s gtpr p s c ie ie div_fr a ction 4 u s artdiv = div_m a nti ssa + (div_fr a ction / 8 (2 ? over 8 )) s ampling cr1 over 8 divider a i16099 RM0033 universal synchronous asynchronous receiver transmitter (usart) doc id 15403 rev 3 605/1317 24.3.1 usart character description word length may be selected as being either 8 or 9 bits by programming the m bit in the usart_cr1 register (see figure 223 ). the tx pin is in low state during the start bit. it is in high state during the stop bit. an idle character is interpreted as an entire frame of ?1?s followed by the start bit of the next frame which contains data (the number of ?1? ?s will include the number of stop bits). a break character is interpreted on receiving ?0?s for a frame period. at the end of the break frame the transmitter inserts either 1 or 2 stop bits (logic ?1? bit) to acknowledge the start bit. transmission and reception are driven by a common baud rate generator, the clock for each is generated when the enable bit is set respectively for the transmitter and receiver. the details of each block is given below. figure 223. word length programming bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit8 start bit stop bit next start bit idle frame bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit idle frame start bit 9-bit word length (m bit is set), 1 stop bit 8-bit word length (m bit is reset), 1 stop bit possible parity bit possible parity bit break frame start bit stop bit data frame break frame start bit stop bit data frame next data frame next data frame start bit **** ** lbcl bit controls last data clock pulse clock clock ** lbcl bit controls last data clock pulse ** ** universal synchronous asynchronous receiver transmitter (usart) RM0033 606/1317 doc id 15403 rev 3 24.3.2 transmitter the transmitter can send data words of either 8 or 9 bits depending on the m bit status. when the transmit enable bit (te) is set, the data in the transmit shift register is output on the tx pin and the corresponding clock pulses are output on the sclk pin. character transmission during an usart transmission, data shifts out leas t significant bit first on the tx pin. in this mode, the usart_dr register consists of a buffer (tdr) between the internal bus and the transmit shift register (see figure 222 ). every character is preceded by a start bit which is a logic level low for one bit period. the character is terminated by a configurable number of stop bits. the following stop bits are supported by usart: 0.5, 1, 1.5 and 2 stop bits. note: 1 the te bit should not be reset during transmission of data. resetting the te bit during the transmission will corrupt the data on the tx pin as the baud rate counters will get frozen. the current data being transmitted will be lost. 2 an idle frame will be sent a fter the te bit is enabled. configurable stop bits the number of stop bits to be transmitted with every character can be programmed in control register 2, bits 13,12. 1. 1 stop bit : this is the default value of number of stop bits. 2. 2 stop bits : this will be supported by normal usart, single-wire and modem modes. 3. 0.5 stop bit : to be used when receiving data in smartcard mode. 4. 1.5 stop bits : to be used when transmitting and receiving data in smartcard mode. an idle frame transmission will include the stop bits. a break transmission will be 10 low bits followe d by the configured number of stop bits (when m = 0) and 11 low bits followed by the configured number of stop bits (when m = 1). it is not possible to transmit long breaks (break of length greater than 10/11 low bits). RM0033 universal synchronous asynchronous receiver transmitter (usart) doc id 15403 rev 3 607/1317 figure 224. configurable stop bits procedure: 1. enable the usart by writing the ue bit in usart_cr1 register to 1. 2. program the m bit in usart_cr1 to define the word length. 3. program the number of stop bits in usart_cr2. 4. select dma enable (dmat) in usart_cr3 if multi buffer communication is to take place. configure the dma register as explained in multibuffer communication. 5. select the desired baud rate using the usart_brr register. 6. set the te bit in usart_cr1 to send an idle frame as first transmission. 7. write the data to send in the usart_dr register (this clears the txe bit). repeat this for each data to be transmitted in case of single buffer. 8. after writing the last data into the usart_ dr register, wait until tc=1. this indicates that the transmission of the last frame is complete. this is required for instance when the usart is disabled or enters the halt mode to avoid corrupting the last transmission. single byte communication clearing the txe bit is always performed by a write to the data register. the txe bit is set by hardware and it indicates: the data has been moved from tdr to the shift register and the data transmission has started. the tdr register is empty. the next data can be written in the usart_dr register without overwriting the previous data. this flag generates an interrupt if the txeie bit is set. bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit 8-bit word length (m bit is reset) possible parity bit data frame next data frame **** ** lbcl bit controls last data clock pulse clock ** bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit 2 stop bits next start bit possible parity bit data frame next data frame bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit next start bit possible parity bit data frame next data frame 1/2 stop bit bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit next start bit possible parity bit data frame next data frame 1 1/2 stop bits a) 1 stop bit b) 1 1/2 stop bits c) 2 stop bits d) 1/2 stop bit universal synchronous asynchronous receiver transmitter (usart) RM0033 608/1317 doc id 15403 rev 3 when a transmission is taking place, a write instruction to the usart_dr register stores the data in the tdr register and which is copied in the shift register at the end of the current transmission. when no transmission is taking place, a write instruction to the usart_dr register places the data directly in the shift register, the data transmission starts, and the txe bit is immediately set. if a frame is transmitted (after the stop bit) and the txe bit is set, the tc bit goes high. an interrupt is generated if the tcie bit is set in the usart_cr1 register. after writing the last data into the usart_dr re gister, it is mandatory to wait for tc=1 before disabling the usart or causing the microcontroller to enter the low power mode (see figure 225: tc/txe behavior when transmitting ). the tc bit is cleared by the following software sequence: 1. a read from the usart_sr register 2. a write to the usart_dr register note: the tc bit can also be cleared by writing a ?0 to it. this clearing sequence is recommended only for multibuffer communication. figure 225. tc/txe behavior when transmitting break characters setting the sbk bit transmits a break character. the break frame length depends on the m bit (see figure 223 ). if the sbk bit is set to ?1 a break character is sent on the tx line after comp leting the current character transmission. this bit is reset by ha rdware when the break character is completed (during the stop bit of the break character). the usart inserts a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. note: if the software resets the sbk bit before the commencem ent of break tr ansmission, the break character will not be tran smitted. for two consecutive breaks, the sbk bit should be set after the stop bit of the previous break. idle characters setting the te bit drives the usart to send an idle frame before the first data frame. tx line u s art_dr fr a me 1 txe fl a g f2 tc fl a g f 3 fr a me 2 software waits until txe=1 and writes f2 into dr software waits until txe=1 and writes f3 into dr tc is not set because txe=0 software waits until tc=1 fr a me 3 tc is set because txe=1 s et b y h a rdw a re cle a red b y s oftw a re s et b y h a rdw a re cle a red b y s oftw a re s et b y h a rdw a re s et idle pre a m b le b y h a rdw a re f1 software enables the usart tc is not set because txe=0 software waits until txe=1 and writes f1 into dr a i17121 b RM0033 universal synchronous asynchronous receiver transmitter (usart) doc id 15403 rev 3 609/1317 24.3.3 receiver the usart can receive data words of either 8 or 9 bits depending on the m bit in the usart_cr1 register. start bit detection the start bit detection sequence is the same when oversampling by 16 or by 8. in the usart, the start bit is detected when a specific sequence of samples is recognized. this sequence is: 1 1 1 0 x 0 x 0 x 0 0 0 0. figure 226. start bit detection when oversampling by 16 or 8 note: if the sequence is not complete, the start bit detection aborts and the receiver returns to the idle state (no flag is set) where it waits for a falling edge. the start bit is confirmed (rxne flag set, interrupt generated if rxneie=1) if the 3 sampled bits are at 0 (first sampling on the 3rd, 5th and 7th bits finds the 3 bits at 0 and second sampling on the 8th, 9th and 10th bits also finds the 3 bits at 0). the start bit is validated (rxne flag set, interrupt generated if rxneie=1) but the ne noise flag is set if, for both samplings, at least 2 out of the 3 sampled bits are at 0 (sampling on the 3rd, 5th and 7th bits and sampling on the 8th, 9th and 10th bits). if this condition is not met, the start detection aborts and the receiver returns to the idle state (no flag is set). if, for one of the samplings (sampling on the 3rd, 5th and 7th bits or sampling on the 8th, 9th and 10th bits), 2 out of the 3 bits are found at 0, the start bit is validated but the ne noise flag bit is set. character reception during an usart reception, data shifts in least si gnificant bit first through the rx pin. in this mode, the usart_dr register consists of a bu ffer (rdr) between the internal bus and the received shift register. rx line sampled values idle start bit rx state real sample clock ideal sample clock 0 10x0x0000xxxxxx conditions to validate the start bit at least 2 bits out of 3 at 0 at least 2 bits out of 3 at 0 falling edge detection 1 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 x x x x x x x x 9 10 111213141516 6/16 7/16 one-bit time 7/16 x ai15471 universal synchronous asynchronous receiver transmitter (usart) RM0033 610/1317 doc id 15403 rev 3 procedure: 1. enable the usart by writing the ue bit in usart_cr1 register to 1. 2. program the m bit in usart_cr1 to define the word length. 3. program the number of stop bits in usart_cr2. 4. select dma enable (dmar) in usart_cr3 if multibuffer communication is to take place. configure the dma register as explained in multibuffer communication. step 3 5. select the desired baud rate using the baud rate register usart_brr 6. set the re bit usart_cr1. this enables the receiver which begins searching for a start bit. when a character is received the rxne bit is set. it indicates that the content of the shift register is transferred to the rdr. in other words, data has been received and can be read (as well as its associated error flags). an interrupt is generated if the rxneie bit is set. the error flags can be set if a frame error, noise or an overrun error has been detected during reception. in multibuffer, rxne is set after every byte received and is cleared by the dma read to the data register. in single buffer mode, clearing the rxne bit is performed by a software read to the usart_dr register. the rxne flag can also be cleared by writing a zero to it. the rxne bit must be cleared before the end of the reception of the next character to avoid an overrun error. note: the re bit should not be reset while rece iving data. if the re bit is disabled during reception, the reception of t he current byte will be aborted. break character when a break character is received, the usart handles it as a framing error. idle character when an idle frame is detected, there is the same procedure as a data received character plus an interrupt if the idleie bit is set. overrun error an overrun error occurs when a character is received when rxne has not been reset. data can not be transferred from the shift register to the rdr register until the rxne bit is cleared. the rxne flag is set after every byte received. an overrun error occurs if rxne flag is set when the next data is received or the previous dma request has not been serviced. when an overrun error occurs: the ore bit is set. the rdr content will not be lost. the previous data is available when a read to usart_dr is performed. the shift register will be overwritten. after th at point, any data received during overrun is lost. RM0033 universal synchronous asynchronous receiver transmitter (usart) doc id 15403 rev 3 611/1317 an interrupt is generated if either the rxneie bit is set or both the eie and dmar bits are set. the ore bit is reset by a read to the usart_sr register followed by a usart_dr register read operation. note: the ore bit, when set, indicates that at least 1 data has been lost. there are two possibilities: if rxne=1, then the last valid data is stored in the receive register rdr and can be read, if rxne=0, then it means that the last valid data has already been read and thus there is nothing to be read in the rdr. this case can occur when the last valid data is read in the rdr at the same time as the new (and lost) data is received. it may also occur when the new data is received during the reading sequence (between the usart_sr register read access and the usart_dr read access). selecting the proper oversampling method the receiver implements different user-configurable oversampling techniques (except in synchronous mode) for data recovery by discriminating between valid incoming data and noise. the oversampling method can be selected by programming the over8 bit in the usart_cr1 register and can be either 16 or 8 times the baud rate clock ( figure 227 and figure 228 ). depending on the application: select oversampling by 8 (over8=1) to achieve higher speed (up to f pclk /8). in this case the maximum receiver tolerance to clock deviation is reduced (refer to section 24.3.5: usart receiver?s tolerance to clock deviation on page 621 ) select oversampling by 16 (over8=0) to increase the tolerance of the receiver to clock deviations. in this case, the maxi mum speed is limited to maximum f pclk /16 programming the onebit bit in the usart_cr3 register selects the method used to evaluate the logic level. there are two options: the majority vote of the three samples in the center of the received bit. in this case, when the 3 samples used for the majority vote are not equal, the nf bit is set a single sample in the center of the received bit depending on the application: ? select the three samples? majority vote method (onebit=0) when operating in a noisy environment and reject the data when a noise is detected (refer to figure 83 ) because this indicates that a glitch occurred during the sampling. ? select the single sample method (onebit=1) when the line is noise-free to increase the receiver?s tolerance to clock deviations (see section 24.3.5: usart receiver?s tolerance to clock deviation on page 621 ). in this case the nf bit will never be set. when noise is detected in a frame: the nf bit is set at the rising edge of the rxne bit. the invalid data is transferred from the shift register to the usart_dr register. no interrupt is generated in case of single byte communication. however this bit rises at the same time as the rxne bit which itself generates an interrupt. in case of multibuffer communication an interrupt will be issued if the eie bit is set in the usart_cr3 register. universal synchronous asynchronous receiver transmitter (usart) RM0033 612/1317 doc id 15403 rev 3 the nf bit is reset by a usart_sr register read operation followed by a usart_dr register read operation. note: oversampling by 8 is not available in the smartcard, irda and lin modes. in those modes, the over8 bit is forced to ?0 by hardware. figure 227. data sampling when oversampling by 16 figure 228. data sampling when oversampling by 8 framing error a framing error is detected when: the stop bit is not recognized on reception at the expected time, following either a de- synchronization or excessive noise. table 83. noise detection from sampled data sampled value ne status received bit value 000 0 0 001 1 0 010 1 0 011 1 1 100 1 0 101 1 1 110 1 1 111 0 1 rx line sample clock 1234567891011 12 13 14 15 16 sampled values one bit time 6/16 7/16 7/16 rx line one bit time 3/8 3/8 12345678 2/8 sample clock(x8) sampled values RM0033 universal synchronous asynchronous receiver transmitter (usart) doc id 15403 rev 3 613/1317 when the framing error is detected: the fe bit is set by hardware the invalid data is transferred from the shift register to the usart_dr register. no interrupt is generated in case of single byte communication. however this bit rises at the same time as the rxne bit which itself generates an interrupt. in case of multibuffer communication an interrupt will be issued if the eie bit is set in the usart_cr3 register. the fe bit is reset by a usart_sr register read operation followed by a usart_dr register read operation. configurable stop bits during reception the number of stop bits to be received can be configured through the control bits of control register 2 - it can be either 1 or 2 in normal mode and 0.5 or 1.5 in smartcard mode. 1. 0.5 stop bit (reception in smartcard mode) : no sampling is done for 0.5 stop bit. as a consequence, no framing error and no break frame can be detected when 0.5 stop bit is selected. 2. 1 stop bit : sampling for 1 stop bit is done on the 8th, 9th and 10th samples. 3. 1.5 stop bits (smartcard mode) : when transmitting in smartcard mode, the device must check that the data is correctly sent. thus the receiver block must be enabled (re =1 in the usart_cr1 register) and the stop bit is checked to test if the smartcard has detected a parity error. in the event of a parity error, the smartcard forces the data signal low during the sampling - nack signal-, which is flagged as a framing error. then, the fe flag is set with the rxne at the end of the 1.5 stop bit. sampling for 1.5 stop bits is done on the 16th, 17th and 18th samples (1 baud clock period after the beginning of the stop bit). the 1.5 stop bit can be decomposed into 2 parts: one 0.5 baud clock period during which nothing happens, followed by 1 normal stop bit period during which sampling occurs halfway through. refer to section 24.3.11: smartcard on page 629 for more details. 4. 2 stop bits : sampling for 2 stop bits is done on the 8th, 9th and 10th samples of the first stop bit. if a framing error is detected during the first stop bit the framing error flag will be set. the second stop bit is not checke d for framing error. the rxne flag will be set at the end of the first stop bit. 24.3.4 fractional baud rate generation the baud rate for the receiver and transmitter (rx and tx) are both set to the same value as programmed in the mantissa and fraction values of usartdiv. equation 1: baud rate for standard usart (spi mode included) equation 2: baud rate in smartcard, lin and irda modes tx/rx baud f ck 8 2 over8 ? () usartdiv ---------------------------------------------------------------------------------- - = tx/rx baud f ck 16 usartdiv --------------------------------------------- = universal synchronous asynchronous receiver transmitter (usart) RM0033 614/1317 doc id 15403 rev 3 usartdiv is an unsigned fixed point number that is coded on the usart_brr register. when over8=0, the fractional part is coded on 4 bits and programmed by the div_fraction[3:0] bits in the usart_brr register when over8=1, the fractional part is coded on 3 bits and programmed by the div_fraction[2:0] bits in the usart_brr register, and bit div_fraction[3] must be kept cleared. note: the baud counters are updated to the new value in the baud registers after a write operation to usart_brr. hence the baud rate register value should not be changed during communication. how to derive usartdiv from usart_brr register values when over8=0 example 1 : if div_mantissa = 0d27 and div_fraction = 0d12 (usart_brr = 0x1bc), then mantissa (usartdiv) = 0d27 fraction (usartdiv) = 12/16 = 0d0.75 therefore usartdiv = 0d27.75 example 2 : to program usartdiv = 0d25.62 this leads to: div_fraction = 16*0d0.62 = 0d9.92 the nearest real number is 0d10 = 0xa div_mantissa = mantissa (0d25.620) = 0d25 = 0x19 then, usart_brr = 0x19a hence usartdiv = 0d25.625 example 3 : to program usartdiv = 0d50.99 this leads to: div_fraction = 16*0d0.99 = 0d15.84 the nearest real number is 0d16 = 0x10 => overflow of div_frac[3:0] => carry must be added up to the mantissa div_mantissa = mantissa (0d50.990 + carry) = 0d51 = 0x33 then, usart_brr = 0x330 hence usartdiv = 0d51.000 how to derive usartdiv from usart_brr register values when over8=1 example 1: if div_mantissa = 0x27 and div_fraction[2:0]= 0d6 (usart_brr = 0x1b6), then mantissa (usartdiv) = 0d27 fraction (usartdiv) = 6/8 = 0d0.75 therefore usartdiv = 0d27.75 RM0033 universal synchronous asynchronous receiver transmitter (usart) doc id 15403 rev 3 615/1317 example 2 : to program usartdiv = 0d25.62 this leads to: div_fraction = 8*0d0.62 = 0d4.96 the nearest real number is 0d5 = 0x5 div_mantissa = mantissa (0d25.620) = 0d25 = 0x19 then, usart_brr = 0x195 => usartdiv = 0d25.625 example 3 : to program usartdiv = 0d50.99 this leads to: div_fraction = 8*0d0.99 = 0d7.92 the nearest real number is 0d8 = 0x8 => overflow of the div_frac[2:0] => carry must be added up to the mantissa div_mantissa = mantissa (0d50.990 + carry) = 0d51 = 0x33 then, usart_brr = 0x0330 => usartdiv = 0d51.000 table 84. error calculation for programmed baud rates at f pclk = 8 mhz or f pclk = 12 mhz), oversampling by 16 (1) oversampling by 16 (over8=0) baud rate f pclk = 8 mhz f pclk = 12 mhz s.no desired actual value programmed in the baud rate register % error = (calculated - desired) b.rate / desired b.rate actual value programmed in the baud rate register % error 1 1.2 kbps 1.2 kbps 416.6875 0 1.2 kbps 625 0 2 2.4 kbps 2.4 kbps 208.3125 0.01 2.4 kbps 312.5 0 3 9.6 kbps 9.604 kbps 52.0625 0.04 9.6 kbps 78.125 0 4 19.2 kbps 19.185 kbps 26.0625 0.08 19.2 kbps 39.0625 0 5 38.4 kbps 38.462 kbps 13 0.16 38.339 kbps 19.5625 0.16 6 57.6 kbps 57.554 kbps 8.6875 0.08 57.692 kbps 13 0.16 7 115.2 kbps 115.942 kbps 4.3125 0.64 115.385 kbps 6.5 0.16 8 230.4 kbps 228.571 kbps 2.1875 0.79 230.769 kbps 3.25 0.16 9 460.8 kbps 470.588 kbps 1.0625 2.12 461.538 kbps 1.625 0.16 10 921.6 kbps na na na na na na 11 2 mbps na na na na na na 12 3 mbps na na na na na na 1. the lower the cpu clock the lower the accuracy for a particul ar baud rate. the upper limit of the achievable baud rate can be fixed with these data. universal synchronous asynchronous receiver transmitter (usart) RM0033 616/1317 doc id 15403 rev 3 table 85. error calculation for programmed baud rates at f pclk = 8 mhz or f pclk =12 mhz), oversampling by 8 (1) oversampling by 8 (over8 = 1) baud rate f pclk = 8 mhz f pclk = 12 mhz s.no desired actual value programmed in the baud rate register % error = (calculated - desired) b.rate / desired b.rate actual value programmed in the baud rate register % error 1 1.2 kbps 1.2 kbps 833.375 0 1.2 kbps 1250 0 2 2.4 kbps 2.4 kbps 416.625 0.01 2.4 kbps 625 0 3 9.6 kbps 9.604 kbps 104.125 0.04 9.6 kbps 156.25 0 4 19.2 kbps 19.185 kbps 52. 125 0.08 19.2 kbps 78.125 0 5 38.4 kbps 38.462 kbps 26 0.16 38.339 kbps 39.125 0.16 6 57.6 kbps 57.554 kbps 17.37 5 0.08 57.692 kbps 26 0.16 7 115.2 kbps 115.942 kbps 8.625 0.64 115.385 kbps 13 0.16 8 230.4 kbps 228.571 kbps 4.375 0.79 230.769 kbps 6.5 0.16 9 460.8 kbps 470.588 kbps 2.125 2.12 461.538 kbps 3.25 0.16 10 921.6 kbps 888.889 kbps 1.125 3.55 923.077 kbps 1.625 0.16 11 2 mbps na na na na na na 12 3 mbps na na na na na na 1. the lower the cpu clock the lower the accuracy for a particular baud rate. the upper limit of the achievable baud rate can be fixed with these data. table 86. error calculation for programmed baud rates at f pclk = 16 mhz or f pclk = 24 mhz), oversampling by 16 (1) oversampling by 16 (over8 = 0) baud rate f pclk = 16 mhz f pclk = 24 mhz s.no desired actual value programmed in the baud rate register % error = (calculated - desired) b.rate / desired b.rate actual value programmed in the baud rate register % error 1 1.2 kbps 1.2 kbps 833.3125 0 1.2 1250 0 2 2.4 kbps 2.4 kbps 416.6875 0 2.4 625 0 3 9.6 kbps 9.598 kbps 104.1875 0.02 9.6 156.25 0 4 19.2 kbps 19.208 kbps 52.0625 0.04 19.2 78.125 0 5 38.4 kbps 38.369 kbps 26. 0625 0.08 38.4 39.0625 0 6 57.6 kbps 57.554 kbps 17. 375 0.08 57.554 26.0625 0.08 7 115.2 kbps 115.108 kbps 8.6875 0.08 115.385 13 0.16 RM0033 universal synchronous asynchronous receiver transmitter (usart) doc id 15403 rev 3 617/1317 8 230.4 kbps 231.884 kbps 4.3125 0.64 230.769 6.5 0.16 9 460.8 kbps 457.143 kbps 2.1875 0.79 461.538 3.25 0.16 10 921.6 kbps 941.176 kbps 1.0625 2.12 923.077 1.625 0.16 11 2 mbps na na na na na na 12 3 mbps na na na na na na 1. the lower the cpu clock the lower the accuracy for a parti cular baud rate. the upper limit of the achievable baud rate can be fixed with these data. table 86. error calculation for programmed baud rates at f pclk = 16 mhz or f pclk = 24 mhz), oversampling by 16 (1) (continued) oversampling by 16 (over8 = 0) baud rate f pclk = 16 mhz f pclk = 24 mhz s.no desired actual value programmed in the baud rate register % error = (calculated - desired) b.rate / desired b.rate actual value programmed in the baud rate register % error table 87. error calculation for programmed baud rates at f pclk = 16 mhz or f pclk = 24 mhz), oversampling by 8 (1) oversampling by 8 (over8=1) baud rate f pclk = 16 mhz f pclk = 24 mhz s.no desired actual value programmed in the baud rate register % error = (calculated - desired) b.rate / desired b.rate actual value programmed in the baud rate register % error 1 1.2 kbps 1.2 kbps 1666.625 0 1.2 kbps 2500 0 2 2.4 kbps 2.4 kbps 833.375 0 2.4 kbps 1250 0 3 9.6 kbps 9.598 kbps 208.375 0.02 9.6 kbps 312.5 0 4 19.2 kbps 19.208 kbps 10 4.125 0.04 19.2 kbps 156.25 0 5 38.4 kbps 38.369 kbps 52. 125 0.08 38.4 kbps 78.125 0 6 57.6 kbps 57.554 kbps 34.7 5 0.08 57.554 kbps 52.125 0.08 7 115.2 kbps 115.108 kbps 17.375 0.08 115.385 kbps 26 0.16 8 230.4 kbps 231.884 kbps 8.625 0.64 230.769 kbps 13 0.16 9 460.8 kbps 457.143 kbps 4.375 0.79 461.538 kbps 6.5 0.16 10 921.6 kbps 941.176 kbps 2.125 2.12 923.077 kbps 3.25 0.16 11 2 mbps 2000 kbps 1 0 2000 kbps 1.5 0 12 3 mbps na na na 3000 kbps 1 0 1. the lower the cpu clock the lower the accuracy for a partic ular baud rate. the upper limit of the achievable baud rate can be fixed with these data. universal synchronous asynchronous receiver transmitter (usart) RM0033 618/1317 doc id 15403 rev 3 table 88. error calculation for programmed baud rates at f pclk = 8 mhz or f pclk = 16 mhz), oversampling by 16 (1) oversampling by 16 (over8=0) baud rate f pclk = 8 mhz f pclk = 16 mhz s.no desired actual value programmed in the baud rate register % error = (calculated - desired)b.rate /desired b.rate actual value programmed in the baud rate register % error 1. 2.4 kbps 2.400 kbps 208.3125 0.00% 2.400 kbps 416.6875 0.00% 2. 9.6 kbps 9.604 kbps 52.0625 0.04% 9.598 kbps 104.1875 0.02% 3. 19.2 kbps 19.185 kbps 26.0625 0.08% 19.208 kbps 52.0625 0.04% 4. 57.6 kbps 57.554 kbps 8.6875 0.08% 57.554 kbps 17.3750 0.08% 5. 115.2 kbps 115.942 kbps 4.3125 0.64% 115.108 kbps 8.6875 0.08% 6. 230.4 kbps 228.571 kbps 2.1875 0.79% 231.884 kbps 4.3125 0.64% 7. 460.8 kbps 470.588 kbps 1.0625 2.12% 457.143 kbps 2.1875 0.79% 8. 896 kbps na na na 888.889 kbps 1.1250 0.79% 9. 921.6 kbps na na na 941.176 kbps 1.0625 2.12% 10. 1.792 mbps na na na na na na 11. 1.8432 mbps na na na na na na 12. 3.584 mbps na na na na na na 13. 3.6864 mbps na na na na na na 14. 7.168 mbps na na na na na na 15. 7.3728 mbps na na na na na na 1. the lower the cpu clock the lower the accuracy for a particu lar baud rate. the upper limit of the achievable baud rate can be fixed with these data. table 89. error calculation for programmed baud rates at f pclk = 8 mhz or f pclk = 16 mhz), oversampling by 8 (1) oversampling by 8 (over8=1) baud rate f pclk = 8 mhz f pclk = 16 mhz s.no desired actual value programmed in the baud rate register % error = (calculated - desired)b.rate /desired b.rate actual value programmed in the baud rate register % error 1. 2.4 kbps 2.400 kbps 416.625 0.01% 2. 400 kbps 833.375 0.00% 2. 9.6 kbps 9.604 kbps 104.125 0.04% 9. 598 kbps 208.375 0.02% 3. 19.2 kbps 19.185 kbps 52.125 0.08% 19.208 kbps 104.125 0.04% 4. 57.6 kbps 57.557 kbps 17.375 0.08% 57.554 kbps 34.750 0.08% 5. 115.2 kbps 115.942 kbps 8.625 0.64% 115.108 kbps 17.375 0.08% 6. 230.4 kbps 228.571 kbps 4.375 0.79% 231.884 kbps 8.625 0.64% 7. 460.8 kbps 470.588 kbps 2.125 2.12% 457.143 kbps 4.375 0.79% RM0033 universal synchronous asynchronous receiver transmitter (usart) doc id 15403 rev 3 619/1317 8. 896 kbps 888.889 kbps 1.125 0.79% 888.889 kbps 2.250 0.79% 9. 921.6 kbps 888.889 kbps 1.125 3.55% 941.176 kbps 2.125 2.12% 10. 1.792 mbps na na na 1.7777 mbps 1.125 0.79% 11. 1.8432 mbps na na na 1.7777 mbps 1.125 3.55% 12. 3.584 mbps na na na na na na 13. 3.6864 mbps na na na na na na 14. 7.168 mbps na na na na na na 15. 7.3728 mbps na na na na na na 1. the lower the cpu clock the lower the accuracy for a particu lar baud rate. the upper limit of the achievable baud rate can be fixed with these data. table 89. error calculation for programmed baud rates at f pclk = 8 mhz or f pclk = 16 mhz), oversampling by 8 (1) (continued) oversampling by 8 (over8=1) baud rate f pclk = 8 mhz f pclk = 16 mhz s.no desired actual value programmed in the baud rate register % error = (calculated - desired)b.rate /desired b.rate actual value programmed in the baud rate register % error table 90. error calculation for programmed baud rates at f pclk = 30 mhz or f pclk = 60 mhz), oversampling by 16 (1)(2) oversampling by 16 (over8=0) baud rate f pclk = 30 mhz f pclk = 60 mhz s.no desired actual value programmed in the baud rate register % error = (calculated - desired)b.rate /desired b.rate actual value programmed in the baud rate register % error 1. 2.4 kbps 2.400 kbps 781.2500 0.00% 2.400 kbps 1562.5000 0.00% 2. 9.6 kbps 9.600 kbps 195.3125 0.00% 9.600 kbps 390.6250 0.00% 3. 19.2 kbps 19.194 kbps 97.6875 0.03% 19.200 kbps 195.3125 0.00% 4. 57.6 kbps 57.582kbps 32.5625 0.03% 57.582 kbps 65.1250 0.03% 5. 115.2 kbps 115.385 kbps 16.2500 0.16% 115.163 kbps 32.5625 0.03% 6. 230.4 kbps 230.769 kbps 8.1250 0.16% 230.769kbps 16.2500 0.16% 7. 460.8 kbps 461.538 kbps 4.0625 0.16% 461.538 kbps 8.1250 0.16% 8. 896 kbps 909.091 kbps 2.0625 1.46% 895.522 kbps 4.1875 0.05% 9. 921.6 kbps 909.091 kbps 2.0625 1.36% 923.077 kbps 4.0625 0.16% 10. 1.792 mbps 1.1764 mbps 1.0625 1.52% 1.8182 mbps 2.0625 1.36% 11. 1.8432 mbps 1.8750 mbps 1.0000 1.73% 1.8182 mbps 2.0625 1.52% 12. 3.584 mbps na na na 3.2594 mbps 1.0625 1.52% 13. 3.6864 mbps na na na 3.7500 mbps 1.0000 1.73% universal synchronous asynchronous receiver transmitter (usart) RM0033 620/1317 doc id 15403 rev 3 14. 7.168 mbps na na na na na na 15. 7.3728 mbps na na na na na na 1. the lower the cpu clock the lower the accuracy for a particu lar baud rate. the upper limit of the achievable baud rate can be fixed with these data. 2. only usart1 and usart6 are clocked with pclk2 (60 mhz max). other usarts are clocked with pclk1 (30 mhz max). table 91. error calculation for programmed baud rates at f pclk = 30 mhz or f pclk = 60 mhz), oversampling by 8 (1) (2) oversampling by 8 (over8=1) baud rate f pclk = 30 mhz f pclk =60 mhz s.no desired actual value programmed in the baud rate register % error = (calculated - desired)b.rate /desired b.rate actual value programmed in the baud rate register % error 1. 2.4 kbps 2.400 kbps 1562.5000 0.00% 2.400 kbps 3125.0000 0.00% 2. 9.6 kbps 9.600 kbps 390.6250 0.00% 9.600 kbps 781.2500 0.00% 3. 19.2 kbps 19.194 kbps 195.3750 0.03% 19.200 kbps 390.6250 0.00% 4. 57.6 kbps 57.582 kbps 65.1250 0.16% 57.582 kbps 130.2500 0.03% 5. 115.2 kbps 115.385 kbps 32.5000 0.16% 115.163 kbps 65.1250 0.03% 6. 230.4 kbps 230.769 kbps 16.2500 0.16% 230.769 kbps 32.5000 0.16% 7. 460.8 kbps 461.538 kbps 8.1250 0.16% 461.538 kbps 16.2500 0.16% 8. 896 kbps 909.091 kbps 4.1250 1.46% 895.522 kbps 8.3750 0.05% 9. 921.6 kbps 909.091 kbps 4.1250 1.36% 923.077 kbps 8.1250 0.16% 10. 1.792 mbps 1.7647 mbps 2.1250 1.52% 1.8182 mbps 4.1250 1.46% 11. 1.8432 mbps 1.8750 mbps 2.0000 1.73% 1.8182 mbps 4.1250 1.36% 12. 3.584 mbps 3.7500 mbps 1.0000 4.63% 3.5294 mbps 2.1250 1.52% 13. 3.6864 mbps 3.7500 mbps 1.0000 1.73% 3.7500 mbps 2.0000 1.73% 14. 7.168 mbps na na na 7.5000 mbps 1.0000 4.63% 15. 7.3728 mbps na na na 7.5000 mbps 1.0000 1.73% 1. the lower the cpu clock the lower the accuracy for a particu lar baud rate. the upper limit of the achievable baud rate can be fixed with these data. 2. only usart1 and usart6 are clocked with pclk2 (60 mhz max). other usarts are clocked with pclk1 (30 mhz max). table 90. error calculation for programmed baud rates at f pclk = 30 mhz or f pclk = 60 mhz), oversampling by 16 (1)(2) (continued) oversampling by 16 (over8=0) baud rate f pclk = 30 mhz f pclk = 60 mhz s.no desired actual value programmed in the baud rate register % error = (calculated - desired)b.rate /desired b.rate actual value programmed in the baud rate register % error RM0033 universal synchronous asynchronous receiver transmitter (usart) doc id 15403 rev 3 621/1317 24.3.5 usart receiver?s tole rance to clock deviation the usart?s asynchronous receiver works correc tly only if the total clock system deviation is smaller than the usart receiver?s tolerance. the causes which contribute to the total deviation are: dtra: deviation due to the transmitter error (which also includes the deviation of the transmitter?s lo cal oscillator) dquant: error due to the baud rate quantization of the receiver drec: deviation of the receiver?s local oscillator dtcl: deviation due to the tr ansmission line (generally due to the transceivers which can introduce an asymmetry between the low-to-high transition timing and the high-to- low transition timing) dtra + dquant + drec + dtcl < usart receiver?s tolerance the usart receiver?s tolerance to properly receive data is equal to the maximum tolerated deviation and depends on the following choices: 10- or 11-bit character length defined by the m bit in the usart_cr1 register oversampling by 8 or 16 defined by the over8 bit in the usart_cr1 register use of fractional baud rate or not use of 1 bit or 3 bits to sample the data, depending on the value of the onebit bit in the usart_cr3 register table 93. usart receiver?s tolerance when div_fraction is different from 0 note: the figures specified in ta b l e and ta bl e 9 3 may slightly differ in the special case when the received frames contain some idle frames of exactly 10-bit times when m=0 (11-bit times when m=1). 24.3.6 multiprocessor communication there is a possibility of perfor ming multiprocessor communic ation with the usart (several usarts connected in a network). for instance one of the usarts can be the master, its tx output is connected to the rx input of the other usart. the others are slaves, their respective tx outputs are logically anded together and connected to the rx input of the master. table 92. usart receiver?s tolerance when div fraction is 0 m bit over8 bit = 0 over8 bit = 1 onebit=0 onebit=1 onebit=0 onebit=1 0 3.75% 4.375% 2.50% 3.75% 1 3.41% 3.97% 2.27% 3.41% m bit over8 bit = 0 over8 bit = 1 onebit=0 onebit=1 onebit=0 onebit=1 0 3.33% 3.88% 2% 3% 1 3.03% 3.53% 1.82% 2.73% universal synchronous asynchronous receiver transmitter (usart) RM0033 622/1317 doc id 15403 rev 3 in multiprocessor configurations it is often desirable that only the intended message recipient should actively receive the full message contents, thus reducing redundant usart service overhead for all non addressed receivers. the non addressed devices may be placed in mute mode by means of the muting function. in mute mode: none of the reception status bits can be set. all the receive interrupts are inhibited. the rwu bit in usart_cr1 register is set to 1. rwu can be controlled automatically by hardware or written by the software under certain conditions. the usart can enter or exit from mute mode using one of two methods, depending on the wake bit in the usart_cr1 register: idle line detection if the wake bit is reset, address mark detection if the wake bit is set. idle line detection (wake=0) the usart enters mute mode when the rwu bit is written to 1. it wakes up when an idle frame is detected. then the rwu bit is cleared by hardware but the idle bit is not set in the usart_sr register. rwu can also be written to 0 by software. an example of mute mode behavior using idle line detection is given in figure 229 . figure 229. mute mode using idle line detection address mark detection (wake=1) in this mode, bytes are recognized as addresses if their msb is a ?1 else they are considered as data. in an address byte, the address of the targeted receiver is put on the 4 lsb. this 4-bit word is compared by the receiver with its own address which is programmed in the add bits in th e usart_cr2 register. the usart enters mute mode when an addr ess character is received which does not match its programmed address. in this case, the rwu bit is set by hardware. the rxne flag is not set for this address byte and no interrupt nor dma request is issued as the usart would have entered mute mode. it exits from mute mode when an address character is received which matches the programmed address. then the rwu bit is cleared and subsequent bytes are received normally. the rxne bit is set for the address character since the rwu bit has been cleared. the rwu bit can be written to as 0 or 1 when the receiver buffer contains no data (rxne=0 in the usart_sr register). otherwise the write attempt is ignored. rwu written to 1 data 1 idle rx data 2 data 3 data 4 data 6 data 5 rwu mute mode normal mode idle frame detected rxne rxne RM0033 universal synchronous asynchronous receiver transmitter (usart) doc id 15403 rev 3 623/1317 an example of mute mode behavior using address mark detection is given in figure 230 . figure 230. mute mode using address mark detection 24.3.7 parity control parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the pce bit in the usart_cr1 register. depending on the frame length defined by the m bit, the possible usart frame formats are as listed in ta bl e 9 4 . table 94. frame formats even parity the parity bit is calculated to obtain an even number of ?1s? inside the frame made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. e.g.: data=00110101; 4 bits set => parity bit will be 0 if even parity is selected (ps bit in usart_cr1 = 0). odd parity the parity bit is calculated to obtain an odd number of ?1s? inside the frame made of the 7 or 8 lsb bits (depending on whether m is equal to 0 or 1) and the parity bit. e.g.: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (ps bit in usart_cr1 = 1). parity checking in reception if the parity check fails, the pe flag is set in the usart_sr register and an interrupt is generated if peie is set in the usart_cr1 register. the pe flag is cleared by a software sequence (a read from the status register followed by a read or write access to the usart_dr data register). rwu written to 1 idle rx addr=0 rwu mute mode normal mode matching address rxne rxne (rxne was cleared) data 2 data 3 data 4 data 5 data 1 idle addr=1 addr=2 mute mode in this example, the current address of the receiver is 1 (programmed in the usart_cr2 register) nonmatching address nonmatching address rxne m bit pce bit usart frame (1) 1. legends: sb: start bit, stb: stop bit, pb: parity bit. 0 0 | sb | 8 bit data | stb | 0 1 | sb | 7-bit data | pb | stb | 1 0 | sb | 9-bit data | stb | 1 1 | sb | 8-bit data pb | stb | universal synchronous asynchronous receiver transmitter (usart) RM0033 624/1317 doc id 15403 rev 3 note: in case of wakeup by an address mark: the msb bit of the data is taken into account to identify an address but not the parity bit. and the receiver does not check the parity of the address data (pe is not set in case of a parity error). parity generation in transmission if the pce bit is set in usart_cr1, then the msb bit of the data written in the data register is transmitted but is changed by the parity bit (even number of ?1s? if even parity is selected (ps=0) or an odd number of ?1s? if odd parity is selected (ps=1)). note: the software routine that manages the transmission can activate the software sequence which clears the pe flag (a read from the status register followed by a read or write access to the data register). when operating in half-duplex mode, depending on the software, this can cause the pe flag to be unexpectedly cleared. 24.3.8 lin (local interconnection network) mode the lin mode is selected by setting the linen bit in the usart_cr2 register. in lin mode, the following bits must be kept cleared: clken in the usart_cr2 register, stop[1:0], scen, hdsel and iren in the usart_cr3 register. lin transmission the same procedure explained in section 24.3.2 has to be applied for lin master transmission than for normal usart transmission with the following differences: clear the m bit to configure 8-bit word length. set the linen bit to enter lin mode. in this case, setting the sbk bit sends 13 ?0 bits as a break character. then a bit of value ?1 is sent to allow the next start detection. lin reception a break detection circuit is implemented on the usart interface. the detection is totally independent from the normal usart receiver. a break can be detected whenever it occurs, during idle state or during a frame. when the receiver is enabled (re=1 in usart_cr1), the circuit looks at the rx input for a start signal. the method for detecting start bits is the same when searching break characters or data. after a start bit has been detected, the circuit samples the next bits exactly like for the data (on the 8th, 9th and 10th samples). if 10 (when the lbdl = 0 in usart_cr2) or 11 (when lbdl=1 in usart_cr2) consecutive bits are detected as ?0, and are followed by a delimiter character, the lbd flag is set in usart_sr. if the lbdie bit=1, an interrupt is generated. before validating the break, the delimiter is checked for as it signifies that the rx line has returned to a high level. if a ?1 is sampled before the 10 or 11 have occurred, the break detection circuit cancels the current detection and searches for a start bit again. if the lin mode is disabled (linen=0), the receiver continues working as normal usart, without taking into account the break detection. if the lin mode is enabled (linen=1), as soon as a framing error occurs (i.e. stop bit detected at ?0, which will be the case for any br eak frame), the receiver stops until the break detection circuit receives either a ?1, if the break word was not complete, or a delimiter character if a break has been detected. RM0033 universal synchronous asynchronous receiver transmitter (usart) doc id 15403 rev 3 625/1317 the behavior of the break detector state machine and the break flag is shown on the figure 231: break detection in lin mode (11-bit break length - lbdl bit is set) on page 625 . examples of break frames are given on figure 232: break detection in lin mode vs. framing error detection on page 626 . figure 231. break detection in lin mode (11-bit break length - lbdl bit is set) case 1: break signal not long enough => break discarded, lbd is not set break frame rx line break state machine capture strobe 0 bit1 bit2 bit3 bit4 bi t5 bit6 bit7 bit8 bit9 idle idle read samples bit0 0000000001 bit10 break frame rx line break state machine capture strobe 0 bit1 bit2 bit3 bit4 bi t5 bit6 bit7 bit8 bit9 idle idle read samples bit0 0000000000 b10 case 2: break signal just long enough => break detected, lbd is set lbd break frame rx line break state machine capture strobe 0 bit1 bit2 bit3 bit4 bi t5 bit6 bit7 bit8 bit9 idle idle read samples bit0 0000000000 bit10 case 3: break signal long enough => break detected, lbd is set wait delimiter lbd delimiter is immediate universal synchronous asynchronous receiver transmitter (usart) RM0033 626/1317 doc id 15403 rev 3 figure 232. break detection in lin mode vs. framing error detection 24.3.9 usart synchronous mode the synchronous mode is select ed by writing the clken bit in the usart_cr2 register to 1. in synchronous mode, the following bits must be kept cleared: linen bit in the usart_cr2 register, scen, hdsel and iren bits in the usart_cr3 register. the usart allows the user to control a bidirectional synchronous serial communications in master mode. the sclk pin is the output of the usart transmitter clock. no clock pulses are sent to the sclk pin during start bit and stop bit. depending on the state of the lbcl bit in the usart_cr2 register clock pulses will or will not be generated during the last valid data bit (address mark). the cpol bit in the usart_cr2 register allows the user to select the clock polarity, and the cpha bit in the usar t_cr2 register allows the user to select the phase of the external clock (see figure 233 , figure 234 & figure 235 ). during the idle state, preamble and send break, the external sclk clock is not activated. in synchronous mode the usart transmitter works exactly like in asynchronous mode. but as sclk is synchronized with tx (according to cpol and cpha), the data on tx is synchronous. in this mode the usart receiver works in a different manner compared to the asynchronous mode. if re=1, the data is sampled on sclk (rising or falling edge, depending on cpol and cpha), without any oversampling. a setup and a hold time must be respected (which depends on the baud rate: 1/16 bit time). note: 1 the sclk pin works in conjunction with the tx pin. thus, the clock is provided only if the transmitter is enabled (te=1) and a data is being transmitted (the data register usart_dr has been written). this means that it is not possible to receive a synchronous data without transmitting data. 2 the lbcl, cpol and cpha bits have to be selected when both the transmitter and the receiver are disabled (te=re=0) to ensure that the clock pulses function correctly. these bits should not be changed while the transmitter or the receiver is enabled. case 1: break occurring after an idle idle data2 (0x55) data 1 data 3 (header) in these examples, we suppose that lbdl=1 (11-bit break length), m=0 (8-bit data) rx line rxne / fe lbd 1 data time 1 data time case 1: break occurring while a data is being received data 2 data2 (0x55) data 1 data 3 (header) rx line rxne / fe lbd 1 data time 1 data time break break RM0033 universal synchronous asynchronous receiver transmitter (usart) doc id 15403 rev 3 627/1317 3 it is advised that te and re are set in the same instruction in order to minimize the setup and the hold time of the receiver. 4 the usart supports master mode only: it cannot receive or send data related to an input clock (sclk is always an output). figure 233. usart example of synchronous transmission figure 234. usart data clock timing diagram (m=0) rx tx sclk usart data out data in synchronous device clock (e.g. slave spi) m=0 (8 data bits) clock (cpol=0, cpha=1) clock (cpol=1, cpha=0) clock (cpol=1, cpha=1) start lsb msb stop * lbcl bit controls last data clock pulse start idle or preceding transmission data on tx stop clock (cpol=0, cpha=0) 01 234 56 7 * * * * idle or next transmission * capture strobe lsb msb data on rx 01 234 56 7 (from master) (from slave) universal synchronous asynchronous receiver transmitter (usart) RM0033 628/1317 doc id 15403 rev 3 figure 235. usart data clock timing diagram (m=1) figure 236. rx data setup/hold time note: the function of sclk is different in smartcard mode. refer to the smartcard mode chapter for more details. 24.3.10 single-wire half-duplex communication the single-wire half-duplex mode is selected by setting the hdsel bit in the usart_cr3 register. in this mode, the following bits must be kept cleared: linen and clken bits in the usart_cr2 register, scen and iren bits in the usart_cr3 register. the usart can be configured to follow a single-wire half-duplex protocol where the tx and rx lines are internally connected. the selection between half- and full-duplex communication is made with a control bit ?half duplex sel? (hdsel in usart_cr3). as soon as hdsel is written to 1: the tx and rx lines are internally connected the rx pin is no longer used the tx pin is always released when no data is transmitted. thus, it acts as a standard i/o in idle or in reception. it means that the i/o must be configured so that tx is configured as floating input (or output high open-drain) when not driven by the usart. idle or next m=1 (9 data bits) clock (cpol=0, cpha=1) clock (cpol=1, cpha=0) clock (cpol=1, cpha=1) start lsb msb stop * lbcl bit controls last data clock pulse start idle or preceding transmission data on tx stop clock (cpol=0, cpha=0) 01 234 56 7 * * * * 8 transmission capture strobe lsb msb data on rx 01 234 56 7 (from slave) (from master) * 8 valid data bit t setup t hold sclk (capture strobe on sclk rising edge in this example) data on rx (from slave) t setup = t hold 1/16 bit time RM0033 universal synchronous asynchronous receiver transmitter (usart) doc id 15403 rev 3 629/1317 apart from this, the communications are similar to what is done in normal usart mode. the conflicts on the line must be managed by the software (by the use of a centralized arbiter, for instance). in particular, the transmission is never blocked by hardware and continue to occur as soon as a data is written in the data register while the te bit is set. 24.3.11 smartcard the smartcard mode is selected by setting the scen bit in the usart_cr3 register. in smartcard mode, the following bits must be kept cleared: linen bit in the usart_cr2 register, hdsel and iren bits in the usart_cr3 register. moreover, the clken bit may be set in order to provide a clock to the smartcard. the smartcard interface is designed to support asynchronous protocol smartcards as defined in the iso 7816-3 standard. the usart should be configured as: 8 bits plus parity: where m=1 and pce=1 in the usart_cr1 register 1.5 stop bits when transmitting and receiving: where stop=11 in the usart_cr2 register. note: it is also possible to choose 0.5 stop bit for receiving but it is recommended to use 1.5 stop bits for both transmitting and receiving to avoid switching between the two configurations. figure 237 shows examples of what can be seen on the data line with and without parity error. figure 237. iso 7816-3 asynchronous protocol when connected to a smartcard, the tx output of the usart drives a bidirectional line that the smartcard also drives into. to do so, sw_rx must be connected on the same i/o than tx at product level. the transmitter output enable tx_en is asserted during the transmission of the start bit and the data byte, and is deasserted during the stop bit (weak pull up), so that the receive can drive the line in case of a parity error. if tx_en is not used, tx is driven at high level during the stop bit: thus the receiver can drive the line as long as tx is configured in open-drain. smartcard is a single wire half duplex communication protocol. transmission of data from the transmit shift register is guaranteed to be delayed by a minimum of 1/2 baud clock. in normal operation a full transm it shift register will start shifting on the next baud clock edge. in smartcard mode this transmission is further delayed by a guaranteed 1/2 baud clock. s 0 1 23 5 4 67 p start bit guard time s 0 1 23 5 4 67 p start bit line pulled low by receiver during stop in case of parity error guard time without parity error with parity error universal synchronous asynchronous receiver transmitter (usart) RM0033 630/1317 doc id 15403 rev 3 if a parity error is detected during reception of a frame programmed with a 0.5 or 1.5 stop bit period, the transmit line is pulled low for a baud clock period after the completion of the receive frame. this is to indicate to the smartcard that the data transmitted to usart has not been correctl y received. this nack signal (pulling transmit line low for 1 baud clock) will caus e a framing error on the transmitter side (configured with 1.5 stop bits). the applicat ion can handle re-sending of data according to the protocol. a parity error is ?nack?ed by the receiver if the nack control bit is set, otherwise a nack is not transmitted. the assertion of the tc flag can be delayed by programming the guard time register. in normal operation, tc is asserted when the transmit shift register is empty and no further transmit requests are outstanding. in smartcard mode an empty transmit shift register triggers the guard time counter to count up to the programmed value in the guard time register. tc is forced low during this time. when the guard time counter reaches the programmed value tc is asserted high. the de-assertion of tc flag is unaffected by smartcard mode. if a framing error is detected on the transmitter end (due to a nack from the receiver), the nack will not be detected as a start bit by the receive block of the transmitter. according to the iso protocol, the duration of the received nack can be 1 or 2 baud clock periods. on the receiver side, if a parity error is detected and a nack is transmitted the receiver will not detect the nack as a start bit. note: 1 a break character is not si gnificant in smartcard mode. a 0x 00 data with a framing error will be treated as data and not as a break. 2 no idle frame is transmitted when toggling the te bit. the idle frame (as defined for the other configurations) is not defined by the iso protocol. figure 238 details how the nack signal is sampled by the usart. in this example the usart is transmitting a data and is configured with 1.5 stop bits. the receiver part of the usart is enabled in order to check the integrity of the data and the nack signal. figure 238. parity error detection using the 1.5 stop bits the usart can provide a clock to the smartcard through the sclk output. in smartcard mode, sclk is not associated to the communicat ion but is simply derived from the internal peripheral input clock through a 5-bit prescaler. the division ratio is configured in the prescaler register usart_gtpr. sclk frequency can be programmed from f ck /2 to f ck /62, where f ck is the peripheral input clock. 1 bit time 1.5 bit time 0.5 bit time 1 bit time sampling at 8th, 9th, 10th sampling at 8th, 9th, 10th sampling at 8th, 9th, 10th sampling at 16th, 17th, 18th bit 7 parity bit 1.5 stop bit RM0033 universal synchronous asynchronous receiver transmitter (usart) doc id 15403 rev 3 631/1317 24.3.12 irda sir endec block the irda mode is selected by setting the iren bit in the usart_cr3 register. in irda mode, the following bits must be kept cleared: linen, stop and clken bits in the usart_cr2 register, scen and hdsel bits in the usart_cr3 register. the irda sir physical layer specifies use of a return to zero, inverted (rzi) modulation scheme that represents logic 0 as an infrared light pulse (see figure 239 ). the sir transmit encoder modulates the non return to zero (nrz) transmit bit stream output from usart. the output pulse stream is transmitted to an external output driver and infrared led. usart supports only bit rates up to 115.2kbps for the sir endec. in normal mode the transmitted pulse width is specified as 3/16 of a bit period. the sir receive decoder demodulates the return-to-zero bit stream from the infrared detector and outputs the received nrz serial bit stream to usart. the decoder input is normally high (marking state) in the idle state. the transmit encoder output has the opposite polarity to the decoder input. a start bit is detected when the decoder input is low. irda is a half duplex communication protocol. if the transmitter is busy (i.e. the usart is sending data to the irda encoder), any da ta on the irda receive line will be ignored by the irda decoder and if the receiver is busy (usart is receiving decoded data from the usart), data on the tx from the us art to irda will not be encoded by irda. while receiving data, transmission should be avoided as the data to be transmitted could be corrupted. a ?0 is transmitted as a high pulse and a ?1 is transmitted as a ?0. the width of the pulse is specified as 3/16th of the selected bit period in normal mode (see figure 240 ). the sir decoder converts the irda compliant receive signal into a bit stream for usart. the sir receive logic interprets a high state as a logic one and low pulses as logic zeros. the transmit encoder output has the opposite polarity to the decoder input. the sir output is in low state when idle. the irda specification requires the acceptance of pulses greater than 1.41 us. the acceptable pulse width is programmable. glitch detection logic on the receiver end filters out pulses of width less than 2 psc periods (psc is the prescaler value programmed in the irda low-power baud register, usart_gtpr). pulses of width less than 1 psc period are always rejected, but those of width greater than one and less than two periods may be accepted or re jected, those greater than 2 periods will be accepted as a pulse. the irda encoder/decoder doesn?t work when psc=0. the receiver can communicate with a low-power transmitter. in irda mode, the stop bits in the usart_cr2 register must be configured to ?1 stop bit?. universal synchronous asynchronous receiver transmitter (usart) RM0033 632/1317 doc id 15403 rev 3 irda low-power mode transmitter : in low-power mode the pulse width is not maintained at 3/16 of the bit period. instead, the width of the pulse is 3 times the low-power baud rate which can be a minimum of 1.42 mhz. generally this value is 1.8432 mhz (1.42 mhz < psc< 2.12 mhz). a low-power mode programmable divisor divides the s ystem clock to achieve this value. receiver : receiving in low-power mode is similar to receiving in normal mode. for glitch detection the usart should discard pulses of duration shorter than 1/psc. a valid low is accepted only if its duration is greater than 2 periods of the irda low-power baud clock (psc value in usart_gtpr). note: 1 a pulse of width less than two and greater than one psc period(s) may or may not be rejected. 2 the receiver set up time should be managed by software. the irda physical layer specification specifies a minimum of 10 ms delay between transmission and reception (irda is a half duplex protocol). figure 239. irda sir endec- block diagram figure 240. irda data modulation (3/16) -normal mode usart sir transmit encoder sir receive decoder or usart_tx irda_out irda_in usart_rx tx rx siren tx irda_out irda_in rx start bit 0 1 0 1 0 0 1 1 0 1 3/16 stop bit bit period 0 1 0 1 0 0 1 1 01 RM0033 universal synchronous asynchronous receiver transmitter (usart) doc id 15403 rev 3 633/1317 24.3.13 continuous communication using dma the usart is capable of continuous communication using the dma. the dma requests for rx buffer and tx buffer are generated independently. note: you should refer to product specs for ava ilability of the dma cont roller. if dma is not available in the product, you should use the usart as explained in section 24.3.2 or 24.3.3 . in the usart_sr register, you can clear the txe/ rxne flags to achieve continuous communication. transmission using dma dma mode can be enabled for transmission by setting dmat bit in the usart_cr3 register. data is loaded from a sram area configured using the dma peripheral (refer to the dma specification) to the usart_dr register whenever the txe bit is set. to map a dma channel for usart transmission, use the following procedure (x denotes the channel number): 1. write the usart_dr register address in the dma control register to configure it as the destination of the transfer. the data will be moved to this address from memory after each txe event. 2. write the memory address in the dma control register to configure it as the source of the transfer. the data will be loaded into the usart_dr register from this memory area after each txe event. 3. configure the total number of bytes to be transferred to the dma control register. 4. configure the channel priority in the dma register 5. configure dma interrupt generation after half/ full transfer as required by the application. 6. clear the tc bit in the sr register by writing 0 to it. 7. activate the channel in the dma register. when the number of data transfers programmed in the dma controller is reached, the dma controller generates an interrupt on the dma channel interrupt vector. in transmission mode, once the dma has written all the data to be transmitted (the tcif flag is set in the dma_isr register), the tc flag can be monitored to make sure that the usart communication is complete. this is required to avoid corrupting the last transmission before disabling the usart or entering the stop mode. the software must wait until tc=1. the tc flag remains cleared during all data transfers and it is set by hardware at the last frame?s end of transmission. universal synchronous asynchronous receiver transmitter (usart) RM0033 634/1317 doc id 15403 rev 3 figure 241. transmission using dma reception using dma dma mode can be enabled for reception by setting the dmar bit in usart_cr3 register. data is loaded from the usart_dr register to a sram area configured using the dma peripheral (refer to the dma specification) whenever a data byte is received. to map a dma channel for usart reception, use the following procedure: 1. write the usart_dr register address in the dma control register to configure it as the source of the transfer. the data will be moved from this address to the memory after each rxne event. 2. write the memory address in the dma control register to configure it as the destination of the transfer. the data will be loaded fr om usart_dr to this me mory area after each rxne event. 3. configure the total number of bytes to be transferred in the dma control register. 4. configure the channel priority in the dma control register 5. configure interrupt generation after half/ full transfer as required by the application. 6. activate the channel in the dma control register. when the number of data transfers programmed in the dma controller is reached, the dma controller generates an interrupt on the dma channel interrupt vector. the dmar bit should be cleared by software in the usart_cr3 register during the interrupt subroutine. note: if dma is used for reception, do not enable the rxneie bit. 4 8 l i n e 5 3 ! 2 4 ? $ 2 & r a m e 4 8 % f l a g & 4 # f l a g & & r a m e software waits until tc=1 & r a m e s e t b y h a r d w a r e c l e a r e d b y $ - ! r e a d s e t b y h a r d w a r e c l e a r e d b y $ - ! r e a d s e t b y h a r d w a r e s e t ) d l e p r e a m b l e b y h a r d w a r e & software configures the dma to send 3 data and enables the usart $ - ! r e q u e s t i g n o r e d b y t h e $ - ! $ - ! w r i t e s f l a g $ - ! 4 # ) & s e t b y h a r d w a r e c l e a r b y s o f t w a r e 5 3 ! 2 4 ? $ 2 b e c a u s e $ - ! t r a n s f e r i s c o m p l e t e dma writes f1 into usart_dr dma writes f2 into usart_dr dma writes f3 into usart_dr. the dma transfer is complete (tcif=1 in dma_isr) 4 r a n s f e r c o m p l e t e a i b RM0033 universal synchronous asynchronous receiver transmitter (usart) doc id 15403 rev 3 635/1317 figure 242. reception using dma error flagging and interrupt generation in multibuffer communication in case of multibuffer communication if any error occurs during the transaction the error flag will be asserted after the current byte. an interr upt will be generated if the interrupt enable flag is set. for framing error, overrun error and noise flag which are asserted with rxne in case of single byte reception, there will be separate error flag interrupt enable bit (eie bit in the usart_cr3 register), which if set will issu e an interrupt after the current byte with either of these errors. 24.3.14 hardware flow control it is possible to control the serial data flow between 2 devices by using the ncts input and the nrts output. the figure 243 shows how to connect 2 devices in this mode: figure 243. hardware flow control between 2 usarts rts and cts flow control can be enabled independently by writing respectively rtse and ctse bits to 1 (in the usart_cr3 register). 4 8 l i n e 5 3 ! 2 4 ? $ 2 & r a m e 2 8 . % f l a g & & & r a m e & r a m e s e t b y h a r d w a r e c l e a r e d b y $ - ! r e a d & software configures the dma to receive 3 data blocks and enables the usart $ - ! r e q u e s t $ - ! r e a d s 5 3 ! 2 4 ? $ 2 $ - ! 4 # ) & f l a g s e t b y h a r d w a r e c l e a r e d b y s o f t w a r e dma reads f1 from usart_dr 4 r a n s f e r c o m p l e t e dma reads f2 from usart_dr dma reads f3 from usart_dr the dma transfer is complete (tcif=1 in dma_isr) a i b usart 1 rx circuit tx circuit usart 2 tx circuit rx circuit rx tx tx rx ncts nrts nrts ncts universal synchronous asynchronous receiver transmitter (usart) RM0033 636/1317 doc id 15403 rev 3 rts flow control if the rts flow control is enabled (rtse=1), then nrts is asserted (tied low) as long as the usart receiver is ready to rece ive a new data. when the receive register is full, nrts is deasserted, indicating that the transmission is expected to stop at the end of the current frame. figure 244 shows an example of communication with rts flow control enabled. figure 244. rts flow control cts flow control if the cts flow control is enabled (ctse=1), then the transmitter checks the ncts input before transmitting the next frame. if ncts is asserted (tied low), then the next data is transmitted (assuming that a data is to be transmitted, in other words, if txe=0), else the transmission does not occur. when ncts is deasserted during a transmission, the current transmission is completed before the transmitter stops. when ctse=1, the ctsif status bit is automatically set by hardware as soon as the ncts input toggles. it indicates when the receiver becomes ready or not ready for communication. an interrupt is generated if the ctsie bit in the usart_cr3 register is set. the figure below shows an example of communication with cts flow control enabled. figure 245. cts flow control note: special behavior of break frames: when the cts flow is enabled, the transmitter does not check the ncts input state to send a break. start bit stop bit data 1 idle start bit stop bit data 2 rx nrts rxne data 1 read rxne data 2 can now be transmitted start bit stop bit data 2 idle start bit data 3 tx ncts cts transmission of data 3 data 1 stop bit is delayed until ncts = 0 cts data 2 data 3 empty empty transmit data register tdr writing data 3 in tdr RM0033 universal synchronous asynchronous receiver transmitter (usart) doc id 15403 rev 3 637/1317 24.4 usart interrupts the usart interrupt events are connected to the same interrupt vector (see figure 246 ). during transmission: transmissi on complete, clear to send or transmit data register empty interrupt. while receiving: idle line detection, overrun error, receive data register not empty, parity error, lin break detection, noise flag (only in multi buffer communication) and framing error (only in mult i buffer communication). these events generate an interrupt if the corresponding enable control bit is set. figure 246. usart interrupt mapping diagram table 95. usart interrupt requests interrupt event event flag enable control bit transmit data register empty txe txeie cts flag cts ctsie transmission complete tc tcie received data ready to be read rxne rxneie overrun error detected ore idle line detected idle idleie parity error pe peie break flag lbd lbdie noise flag, overrun error and framing error in multibuffer communication nf or ore or fe eie tc tcie txe txeie idle idleie rxneie ore rxneie rxne pe peie fe ne ore eie dmar usart lbd lbdie cts ctsie interrupt universal synchronous asynchronous receiver transmitter (usart) RM0033 638/1317 doc id 15403 rev 3 24.5 usart mode configuration 24.6 usart registers refer to section 1.1 on page 46 for a list of abbreviations used in register descriptions. 24.6.1 status register (usart_sr) address offset: 0x00 reset value: 0x00c0 table 96. usart mode configuration (1) 1. x = supported; na = not applicable. usart modes usart1 usart2 usart3 uart4 uart5 usart6 asynchronous mode xxxxxx hardware flow control x x x na na x multibuffer communication (dma)xxxxxx multiprocessor communication xxxxxx synchronous x x x na na x smartcard x x x na na x half-duplex (single-wire mode) xxxxxx irda xxxxxx lin xxxxxx 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 reserved cts lbd txe tc rxne idle ore nf fe pe rc_w0rc_w0rrc_w0rc_w0rrrrr bits 31:10 reserved, forced by hardware to 0. bit 9 cts : cts flag this bit is set by hardware when the ncts input toggles, if the ctse bit is set. it is cleared by software (by writing it to 0). an interr upt is generated if ctsie=1 in the usart_cr3 register. 0: no change occurred on the ncts status line 1: a change occurred on the ncts status line note: this bit is not available for uart4 & uart5. bit 8 lbd : lin break detection flag this bit is set by hardware when the lin break is detected. it is cleared by software (by writing it to 0). an interrupt is generat ed if lbdie = 1 in the usart_cr2 register. 0: lin break not detected 1: lin break detected note: an interrupt is generated when lbd=1 if lbdie=1 RM0033 universal synchronous asynchronous receiver transmitter (usart) doc id 15403 rev 3 639/1317 bit 7 txe : transmit data register empty this bit is set by hardware when the content of the tdr register has been transferred into the shift register. an interrupt is generated if the txeie bit =1 in the usart_cr1 register. it is cleared by a write to the usart_dr register. 0: data is not transferred to the shift register 1: data is transferred to the shift register) note: this bit is used during single buffer transmission. bit 6 tc : transmission complete this bit is set by hardware if the transmission of a frame containing data is complete and if txe is set. an interrupt is generated if tcie=1 in the usart_cr1 register. it is cleared by a software sequence (a read from the usart_sr register followed by a write to the usart_dr register). the tc bit can also be cleared by writing a '0' to it. this clearing sequence is recommended only for multibuffer communication. 0: transmission is not complete 1: transmission is complete bit 5 rxne : read data register not empty this bit is set by hardware when the content of the rdr shift register has been transferred to the usart_dr register. an interrupt is generated if rxneie=1 in the usart_cr1 register. it is cleared by a read to the usart_dr register. the rxne flag can also be cleared by writing a zero to it. this clearing sequence is recommended only for multibuffer communication. 0: data is not received 1: received data is ready to be read. bit 4 idle : idle line detected this bit is set by hardware when an idle line is detected. an interrupt is generated if the idleie=1 in the usart_cr1 register. it is cl eared by a software sequence (an read to the usart_sr register followed by a read to the usart_dr register). 0: no idle line is detected 1: idle line is detected note: the idle bit will not be set again until the rxne bit has been set itself (i.e. a new idle line occurs). bit 3 ore : overrun error this bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the rdr register while rxne=1. an interrupt is generated if rxneie=1 in the usart_cr1 register. it is cleared by a software sequence (an read to the usart_sr register followed by a read to the usart_dr register). 0: no overrun error 1: overrun error is detected note: when this bit is set, the rdr register content will not be lost but the shift register will be overwritten. an interrupt is generated on ore flag in case of multi buffer communication if the eie bit is set. universal synchronous asynchronous receiver transmitter (usart) RM0033 640/1317 doc id 15403 rev 3 24.6.2 data register (usart_dr) address offset: 0x04 reset value: undefined bit 2 nf : noise detected flag this bit is set by hardware when noise is detected on a received frame. it is cleared by a software sequence (an read to the usart_sr register followed by a read to the usart_dr register). 0: no noise is detected 1: noise is detected note: this bit does not generate interrupt as it appears at the same time as the rxne bit which itself generates an interrupting interrup t is generated on nf flag in case of multi buffer communication if the eie bit is set. note: when the line is noise-free, the nf flag can be disabled by programming the onebit bit to 1 to increase the usart tolerance to deviations (refer to section 24.3.5: usart receiver?s tolerance to clock deviation on page 621 ). bit 1 fe : framing error this bit is set by hardware when a de-synchr onization, excessive noise or a break character is detected. it is cleared by a software sequence (an read to the usart_sr register followed by a read to the usart_dr register). 0: no framing error is detected 1: framing error or break character is detected note: this bit does not generate interrupt as it appears at the same time as the rxne bit which itself generates an interrupt. if the word currently being transferred causes both frame error and overrun error, it will be transferred and only the ore bit will be set. an interrupt is generated on fe flag in case of multi buffer communication if the eie bit is set. bit 0 pe : parity error this bit is set by hardware when a parity error occurs in receiver mode . it is cleared by a software sequence (a read from the status regi ster followed by a read or write access to the usart_dr data register). the software must wait for the rxne flag to be set before clearing the pe bit. an interrupt is generated if peie = 1 in the usart_cr1 register. 0: no parity error 1: parity error 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 reserved dr[8:0] rw rw rw rw rw rw rw rw rw RM0033 universal synchronous asynchronous receiver transmitter (usart) doc id 15403 rev 3 641/1317 24.6.3 baud rate r egister (usart_brr) note: the baud counters stop counting if the te or re bits are disabled respectively. address offset: 0x08 reset value: 0x0000 24.6.4 control register 1 (usart_cr1) address offset: 0x0c reset value: 0x0000 bits 31:9 reserved, forced by hardware to 0. bits 8:0 dr[8:0] : data value contains the received or transmitted data charac ter, depending on whether it is read from or written to. the data register performs a double function (read and write) since it is composed of two registers, one for transmission (tdr) and one for reception (rdr) the tdr register provides the parallel inte rface between the internal bus and the output shift register (see figure 1). the rdr register provides the parallel interface between the input shift register and the internal bus. when transmitting with the parity enabled (pce bi t set to 1 in the usart_cr1 register), the value written in the msb (bit 7 or bit 8 dependi ng on the data length) has no effect because it is replaced by the parity. when receiving with the parity enabled, the value read in the msb bit is the received parity bit. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 div_mantissa[11:0] div_fraction[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:16 reserved, forced by hardware to 0. bits 15:4 div_mantissa[11:0] : mantissa of usartdiv these 12 bits define the mantissa of the usart divider (usartdiv) bits 3:0 div_fraction[3:0] : fraction of usartdiv these 4 bits define the fraction of the usart divider (usartdiv). when over8=1, the div_fraction3 bit is not consid ered and must be kept cleared. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 over8 reserved ue m wake pce ps peie txeie tcie rxneie idleie te re rwu sbk rw res. rw rw rw rw rw rw rw rw rw rw rw rw rw rw universal synchronous asynchronous receiver transmitter (usart) RM0033 642/1317 doc id 15403 rev 3 bits 31:16 reserved, forced by hardware to 0. bit 15 over8 : oversampling mode 0: oversampling by 16 1: oversampling by 8 note: oversampling by 8 is not available in the smartcard, irda and lin modes: when scen=1,iren=1 or linen=1 then over8 is forced to ?0 by hardware. bit 14 reserved, forced by hardware to 0. bit 13 ue : usart enable when this bit is cleared the usart prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption. this bit is set and cleared by software. 0: usart prescaler and outputs disabled 1: usart enabled bit 12 m : word length this bit determines the word length. it is set or cleared by software. 0: 1 start bit, 8 data bits, n stop bit 1: 1 start bit, 9 data bits, n stop bit note: the m bit must not be modified during a data transfer (both transmission and reception) bit 11 wake : wakeup method this bit determines the usart wakeup method, it is set or cleared by software. 0: idle line 1: address mark bit 10 pce : parity control enable this bit selects the hardware parity control (generation and detection). when the parity control is enabled, the computed parity is inserted at the msb position (9th bit if m=1; 8th bit if m=0) and parity is checked on the received data. this bit is set and cleared by software. once it is set, pce is active after the current byte (in reception and in transmission). 0: parity control disabled 1: parity control enabled bit 9 ps : parity selection this bit selects the odd or even parity when the parity generation/detection is enabled (pce bit set). it is set and cleared by software. the parity will be selected after the current byte. 0: even parity 1: odd parity bit 8 peie : pe interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an usart interrupt is generated whenever pe=1 in the usart_sr register bit 7 txeie : txe interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an usart interrupt is generated whenever txe=1 in the usart_sr register bit 6 tcie : transmission comple te interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an usart interrupt is generated whenever tc=1 in the usart_sr register RM0033 universal synchronous asynchronous receiver transmitter (usart) doc id 15403 rev 3 643/1317 bit 5 rxneie : rxne interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an usart interrupt is generated whenever ore=1 or rxne=1 in the usart_sr register bit 4 idleie : idle interrupt enable this bit is set and cleared by software. 0: interrupt is inhibited 1: an usart interrupt is generated whenever idle=1 in the usart_sr register bit 3 te : transmitter enable this bit enables the transmitter. it is set and cleared by software. 0: transmitter is disabled 1: transmitter is enabled note: 1: during transmission, a ?0? pulse on the te bit (?0? followed by ?1?) sends a preamble (idle line) after the current word, except in smartcard mode. 2: when te is set there is a 1 bit-time delay before the transmission starts. bit 2 re : receiver enable this bit enables the receiver. it is set and cleared by software. 0: receiver is disabled 1: receiver is enabled and begins searching for a start bit bit 1 rwu : receiver wakeup this bit determines if the usart is in mute m ode or not. it is set and cleared by software and can be cleared by hardware when a wakeup sequence is recognized. 0: receiver in active mode 1: receiver in mute mode note: 1: before selecting mute mode (by setting the rwu bit) the usart must first receive a data byte, otherwise it cannot function in mute mode with wakeup by idle line detection. 2: in address mark detection wakeup conf iguration (wake bit=1) the rwu bit cannot be modified by software while the rxne bit is set. bit 0 sbk : send break this bit set is used to send break characters. it can be set and cleared by software. it should be set by software, and will be reset by hardware during the stop bit of break. 0: no break character is transmitted 1: break character will be transmitted universal synchronous asynchronous receiver transmitter (usart) RM0033 644/1317 doc id 15403 rev 3 24.6.5 control register 2 (usart_cr2) address offset: 0x10 reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 res. linen stop[1:0] clken cpol cpha lbcl res. lbdie lbdl res. add[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:15 reserved, forced by hardware to 0. bit 14 linen : lin mode enable this bit is set and cleared by software. 0: lin mode disabled 1: lin mode enabled the lin mode enables the capability to send lin synch breaks (13 low bits) using the sbk bit in the usart_cr1 register, and to detect lin sync breaks. bits 13:12 stop : stop bits these bits are used for programming the stop bits. 00: 1 stop bit 01: 0.5 stop bit 10: 2 stop bits 11: 1.5 stop bit note: the 0.5 stop bit and 1.5 stop bit are not available for uart4 & uart5. bit 11 clken : clock enable this bit allows the user to enable the sclk pin. 0: sclk pin disabled 1: sclk pin enabled this bit is not available for uart4 & uart5. bit 10 cpol : clock polarity this bit allows the user to select the polarity of the clock output on the sclk pin in synchronous mode. it works in conjunction with the cpha bi t to produce the desired clock/data relationship 0: steady low value on sclk pin outside transmission window. 1: steady high value on sclk pin outside transmission window. this bit is not available for uart4 & uart5. bit 9 cpha : clock phase this bit allows the user to select the phase of the clock output on the sclk pin in synchronous mode. it works in conjunction with the cpol bit to produce the desired clock/data relationship (see figures 234 to 235 ) 0: the first clock transition is the first data capture edge 1: the second clock transition is the first data capture edge note: this bit is not available for uart4 & uart5. RM0033 universal synchronous asynchronous receiver transmitter (usart) doc id 15403 rev 3 645/1317 note: these 3 bits (cpol, cpha, lbcl) should not be written while the transmitter is enabled. 24.6.6 control register 3 (usart_cr3) address offset: 0x14 reset value: 0x0000 bit 8 lbcl : last bit clock pulse this bit allows the user to select whether the clock pulse associated with the last data bit transmitted (msb) has to be output on the sclk pin in synchronous mode. 0: the clock pulse of the last data bit is not output to the sclk pin 1: the clock pulse of the last dat a bit is output to the sclk pin note: 1: the last bit is the 8th or 9th data bit tr ansmitted depending on the 8 or 9 bit format selected by the m bit in the usart_cr1 register. 2: this bit is not available for uart4 & uart5. bit 7 reserved, forced by hardware to 0. bit 6 lbdie : lin break detection interrupt enable break interrupt mask (break detection using break delimiter). 0: interrupt is inhibited 1: an interrupt is generated whenev er lbd=1 in the usart_sr register bit 5 lbdl : lin break detection length this bit is for selection between 11 bit or 10 bit break detection. 0: 10-bit break detection 1: 11-bit break detection bit 4 reserved, forced by hardware to 0. bits 3:0 add[3:0] : address of the usart node this bit-field gives the address of the usart node. this is used in multiprocessor communication during mute mode, for wake up with address mark detection. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved onebit ctsie ctse rtse dmat dmar scen nack hdsel irlp iren eie rw rw rw rw rw rw rw rw rw rw rw rw bits 31:12 reserved, forced by hardware to 0. bit 11 onebit : one sample bit method enable this bit allows the user to select the sample method. when the one sample bit method is selected the noise detection flag (nf) is disabled. 0: three sample bit method 1: one sample bit method bit 10 ctsie : cts interrupt enable 0: interrupt is inhibited 1: an interrupt is generated whenever cts=1 in the usart_sr register note: this bit is not available for uart4 & uart5. universal synchronous asynchronous receiver transmitter (usart) RM0033 646/1317 doc id 15403 rev 3 bit 9 ctse : cts enable 0: cts hardware flow control disabled 1: cts mode enabled, data is only transmitted when the ncts input is asserted (tied to 0). if the ncts input is deasserted while a data is being transmitted, then the transmission is completed before stopping. if a data is written into the data register while ncts is asserted, the transmission is postponed until ncts is asserted. note: this bit is not available for uart4 & uart5. bit 8 rtse : rts enable 0: rts hardware flow control disabled 1: rts interrupt enabled, data is only requeste d when there is space in the receive buffer. the transmission of data is expected to cease after the current character has been transmitted. the nrts output is asserted (tied to 0) when a data can be received. note: this bit is not available for uart4 & uart5. bit 7 dmat : dma enable transmitter this bit is set/reset by software 1: dma mode is enabled for transmission. 0: dma mode is disabled for transmission. note: this bit is not available for uart5. bit 6 dmar : dma enable receiver this bit is set/reset by software 1: dma mode is enabled for reception 0: dma mode is disabled for reception note: this bit is not available for uart5. bit 5 scen : smartcard mode enable this bit is used for enabling smartcard mode. 0: smartcard mode disabled 1: smartcard mode enabled note: this bit is not available for uart4 & uart5. bit 4 nack : smartcard nack enable 0: nack transmission in case of parity error is disabled 1: nack transmission during parity error is enabled note: this bit is not available for uart4 & uart5. bit 3 hdsel : half-duplex selection selection of single-wire half-duplex mode 0: half duplex mode is not selected 1: half duplex mode is selected RM0033 universal synchronous asynchronous receiver transmitter (usart) doc id 15403 rev 3 647/1317 bit 2 irlp : irda low-power this bit is used for selecting between normal and low-power irda modes 0: normal mode 1: low-power mode bit 1 iren : irda mode enable this bit is set and cleared by software. 0: irda disabled 1: irda enabled bit 0 eie : error interrupt enable error interrupt enable bit is required to enable interrupt generation in case of a framing error, overrun error or noise flag (fe=1 or ore=1 or nf=1 in the usart_sr register) in case of multi buffer communication (dmar=1 in the usart_cr3 register). 0: interrupt is inhibited 1: an interrupt is generated whenever dmar=1 in the usart_cr3 register and fe=1 or ore=1 or nf=1 in the usart_sr register. universal synchronous asynchronous receiver transmitter (usart) RM0033 648/1317 doc id 15403 rev 3 24.6.7 guard time and prescal er register (usart_gtpr) address offset: 0x18 reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 gt[7:0] psc[7:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:16 reserved, forced by hardware to 0. bits 15:8 gt[7:0] : guard time value this bit-field gives the guard time value in terms of number of baud clocks. this is used in smartcard mode. the transmission complete flag is set after this guard time value. note: this bit is not available for uart4 & uart5. bits 7:0 psc[7:0] : prescaler value ? in irda low-power mode: psc[7:0] = irda low-power baud rate used for programming the prescaler for dividi ng the system clock to achieve the low-power frequency: the source clock is divided by the value given in the register (8 significant bits): 00000000: reserved - do not program this value 00000001: divides the source clock by 1 00000010: divides the source clock by 2 ... ? in normal irda mode: psc must be set to 00000001. ? in smartcard mode: psc[4:0] : prescaler value used for programming the prescaler for dividi ng the system clock to provide the smartcard clock. the value given in the register (5 significant bits ) is multiplied by 2 to give the division factor of the source clock frequency: 00000: reserved - do not program this value 00001: divides the source clock by 2 00010: divides the source clock by 4 00011: divides the source clock by 6 ... note: 1: bits [7:5] have no effe ct if smartcard mode is used. 2: this bit is not available for uart4 & uart5. RM0033 universal synchronous asynchronous receiver transmitter (usart) doc id 15403 rev 3 649/1317 24.6.8 usart register map the table below gives the usart register map and reset values. refer to table 1 on page 50 for the register boundary addresses. table 97. usart register map and reset values offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 usart_sr reserved cts lbd txe tc rxne idle ore nf fe pe reset value 0011000000 0x04 usart_dr reserved dr[8:0] reset value 000000000 0x08 usart_brr reserved div_mantissa[15:4] div_fraction [3:0] reset value 0000000000000000 0x0c usart_cr1 reserved over8 reserved ue m wake pce ps peie txeie tcie rxneie idleie te re rwu sbk reset value 0 00000000000000 0x10 usart_cr2 reserved linen stop [1:0] clken cpol cpha lbcl reserved lbdie lbdl reserved add[3:0] reset value 0000000 00 0000 0x14 usart_cr3 reserved onebit ctsie ctse rtse dmat dmar scen nack hdsel irlp iren eie reset value 000000000000 0x18 usart_gtpr reserved gt[7:0] psc[7:0] reset value 0000000000000000 serial peripheral interface (spi) RM0033 650/1317 doc id 15403 rev 3 25 serial peripheral interface (spi) th is sect ion a pplie s t o t he who l e stm32 f 20 x a nd stm3 2f2 1 x f a mily , unle s s ot he rwise spec ified. 25.1 spi intr oduction the spi interf ac e giv e s the fle x ibility to get either the spi protocol or the i 2 s au dio pro t ocol. by de f a ult , it is th e spi fu nctio n t h a t is sele ct ed . i t is p o ssib l e to s wit ch t he in te rf ace f r om spi to i 2 s b y sof t w a r e .th e se r i al p e r i ph er a l int e rf ace (spi) a llo ws h a lf / fu ll-d u p l e x , synchr on ou s , ser i a l co mm unica tio n wit h e x t e r n a l d e vice s . t he int e rf ace can be co nf igur ed a s t h e m a ste r a nd in th is case it pr o v ides t he com m u nicat i on clo c k (sck) t o t he e x t e r n a l sla v e d e vice . the in te rf ace is also ca pa b l e o f op er a t i ng in m u lt ima s t e r co nf igu r at ion . i t m a y b e used f o r a v a r i et y o f p u r p oses , includ ing simp le x synch r on ou s t r an sf er s o n tw o lin es wit h a po ssib le bid i re ct io nal da ta line or re liab l e co mm un ica t ion using crc ch ec king. th e i 2 s is also a s y nc hr on o u s , se r i al c o m m u n i c a t i o n int e r f a c e wit h a 3 - pin pro t ocol. i t ca n a ddr ess f o u r dif f er en t au dio st and ar ds in clu d in g th e i 2 s phillips standard, the msb- and l s b- just ifie d st an dar ds a nd th e pcm st and ar d. i t ca n o per at e in sla v e or ma st er mo de wit h ha lf- d u p l e x co m m un ica tio n. m a s ter c l oc k ma y be p r o v ide d b y th e int e r f a c e to a n e x ter n al slav e co mpo nen t whe n th e i 2 s is co nf igur ed a s t h e com m unicat i o n mast er . w a rning: sin ce so me spi1 a nd spi3 / i2s3 p i ns m a y be ma ppe d o n to some p i n s use d b y t h e jt a g in te rfa ce ( s pi 1_ nss ont o jt di , spi3_nss/i2s3_ws onto jtdi an d spi3_ sck/i2 s3_ck ont o jtdo ), y ou ma y ei th er: ? map spi/i2s ont o ot her pins ? di sa b l e t h e jt a g and u se t h e swd i n te rfa c e pr io r t o con f igur ing t h e pins list e d as spi i/os ( w h e n deb u g g ing t h e app l ica t ion) or ? disa b l e bo th jt a g /swd inte rfa c e s (f or s t an dalone a p pl ic at ions) . for mor e information on the configuration of the jtag/swd interface pins, please refer to section 6.3.2: i/o pin multiplexer and mapping . RM0033 serial periphe ral interface (spi) doc id 15403 rev 3 651/1317 25.2 spi and i 2 s main f eatures 25.2.1 spi f eatures f u ll- d up le x sy nch r on ou s tr an sf er s o n th re e line s simple x synchr ono us tr a n sf er s on t w o lines wit h o r with out a bid i re ct ion a l da ta lin e 8- o r 16 -b it t r an sf e r fr ame f o r m at select ion m a s t e r o r sla v e op er a t io n multimaster mode capability 8 ma st er mod e bau d r a t e p r escale rs (f pclk /2 m a x. ) sla v e m ode fr eq uen cy (f pclk /2 m a x) f a ste r comm un icat ion f o r b o t h ma st er and sla v e nss man age men t b y h a r d w a re or sof t w ar e f o r b o t h m a ste r and sla v e : dyna mic chan ge of mast er /sla v e ope r a t i on s pro g r a m m ab le cloc k pola r ity an d pha se pr og r a mm a b le d a t a or de r with m sb- firs t o r lsb- fir st sh iftin g dedicated tr ansmission a nd reception flags with interr upt capability spi b u s b u s y s t at us fla g spi ti mode hardw a re crc f eature f o r reliab l e c o mm unic ation: ? c rc v a lu e ca n be t r a n sm i tte d as la st b yte in tx mo d e ? a uto m at ic c rc er ro r c h e c kin g f o r la st re ce iv e d b yt e mas t er mode f a ult, o v err u n and crc error flags with interr upt c a pability 1-b y te tr ans m is sion and reception b u ff er with dma capability: tx and rx reques t s serial peripheral interface (spi) RM0033 652/1317 doc id 15403 rev 3 25.2.2 i 2 s f eatures simple x communication (only tr ansmit ter or receiv er) m a s t e r o r sla v e op er a t io ns 8- bit pr og r a mmab l e lin ea r pr escaler to re ach accur a te a u d i o samp le fr eq uen cies (f ro m 8 k h z t o 96 kh z) da ta f o r m at m a y be 1 6 - b i t, 24 -b it or 3 2 - b it p a c k e t f r a m e is f i x e d t o 16 -b it (1 6- bit d a t a fr am e ) o r 32 - b it (1 6- b i t, 2 4 - b i t, 32 -b it da ta fr a m e) b y a u d i o ch an ne l pro g r a m m ab le cloc k pola r ity (st e a d y st at e) unde rr u n fla g in sla v e t r a n smissio n mo de an d ov er r u n f l a g in re ce pt ion mo de ( m ast e r an d sla v e) 16 -b it re gist er f o r tr a n smission an d re cept ion wit h on e da ta r e g i st er f o r bo th cha n n e l sides sup por t e d i 2 s pr ot oco l s: ?i 2 s phillips standard ? m sb-justified standa rd (left-justified) ? l sb-ju st if ied st and ar d (r ig ht -ju s t i f i ed ) ? p cm st and ar d ( w it h sho r t an d lo ng f r am e syn c h r o n izat ion on 1 6 -b it ch ann el f r ame o r 16 - b it da ta f r a m e e x te nd ed t o 32 -b it c h a n n e l fr a m e) data direction is alw a ys msb first dma capability f o r tr ans m is sion and reception (16-bit w i de) master clock may be output to drive an external audio component. ratio is fixed at 256 f s (where f s is the audio sampling frequency) RM0033 serial periphe ral interface (spi) doc id 15403 rev 3 653/1317 25.3 spi functi onal description 25.3.1 general description th e b l oc k d i ag r a m of th e spi is sho w n in fig u r e 247 . figu re 24 7. spi b l oc k dia g ra m usually , t h e spi is conn ect ed t o e xt e r n al de vices th ro ugh 4 pins: m i so : m a ste r in / sla v e o u t d a t a . th is p i n ca n b e us ed to t r a n sm i t d a t a in sla v e mo d e an d re ce iv e dat a in m a ste r mo de . m o s i: ma ste r ou t / sla v e in d a t a . this pin c a n b e us ed to t r an sm it d a t a in m a st er mo de an d re ce iv e da ta in sla v e mod e . sck: ser i al cloc k ou tp ut f o r spi mast er s a nd inp u t f o r spi sla v e s . nss : sla v e select. this is an optional pin to sele ct a sla v e de vice . this pin act s a s a ?chip selec t ? to let the spi master comm unic at e with sla v es individ ually and to a v oid cont en t i on on t h e dat a lin es . sla v e nss in put s ca n be dr iv e n b y sta n d a rd i o p o r t s on t he ma st er de vice . th e nss pin m a y a l so be use d as a n ou tp ut if en ab led ( s so e b i t ) an d dr iv en lo w if t h e spi i s in ma st er co nf igu r at ion . i n th is ma nn er , a ll nss pins fr om de vices conn ecte d t o th e mast er nss pin see a lo w le v e l an d be co me sla v e s whe n t h e y ar e con f ig ur ed in nss h a r d w a re mo de . wh en conf ig ure d in ma st er mod e wit h nss con f ig ur ed as an in put (m st r=1 a nd ssoe=0) a n d if nss is p u lled l o w , t h e spi en te rs th e mast er m ode f a ult st at e: th e mstr b i t is aut om at ically clea re d an d th e de vice is co nf igu r ed i n sla v e mo de ( r ef e r to se ctio n 25. 3. 1 0 : er ro r f l ags on p age 6 7 4 ). mosi miso baud rate generator sck master control logic communication control spe br2 br1 br0 mstr cpol cpha br[2:0] rxne lsb bidi mode bidi oe ssm ssi bsy ovr mod rxne txe err txe 00 dff 0 ssoe crc en 0 rx only crc next crc err 0 1 nss ie f first spi_cr1 spi_cr2 spi_sr txdm aen rxdm aen ie ie address and data bus read rx buffer shift register lsb first tx buffer write ai14744 serial peripheral interface (spi) RM0033 654/1317 doc id 15403 rev 3 a ba sic e x amp l e of int e r c o nne ctio ns b e t w e en a sing le mast er a n d a sing le sla v e is illus t r a ted in figu re 2 4 8 . fi gu re 24 8. si ngl e mas t e r / s i n g le sl a v e ap pli c ati o n 1. here, the nss pin is configured as an input. th e mo si pin s ar e conn ect ed t o g e t her and t h e miso p i ns ar e co nne cte d to ge th er . i n t h is w a y d a t a is t r an sf e r r ed ser i a lly be t w ee n mast er a n d sla v e (mo st signif i cant bit fir s t) . the comm unication is alw a y s initiated b y th e mast er . whe n t he ma st er de vice t r ansmit s d a t a to a sla v e de vice via t he mo si pin , t h e sla v e de vice r e spon ds via t h e miso p i n. this imp lies fu ll-d uple x com m u nicat i on wit h bo th dat a ou t a nd da t a in synch r on iz ed wit h t he sam e clo c k sign al (which is pr o v id ed b y t h e ma ste r de vice via t he sck p i n) . sla v e select (nss) pin mana g e ment th er e ar e tw o nss mo de s: sof t w ar e nss mo de: th is mo de is ena b l ed b y set t i ng t h e ssm bit in th e spi_ c r1 re gist er ( s e e f i gu r e 24 9 ) . i n th is m o de , th e e x te r n a l nss pin is fr ee f o r ot he r a p p lica t io n us es an d th e int e r n al nss s i gn al le v e l is dr iv en b y wr iting to the ssi bit in t he spi _cr1 r e g i st er . har d w a re nss m ode : t h e r e a r e t w o cases: ? n ss ou t put is en ab led: whe n t he st m32 f 20 x a nd st m32 f 21 x a r e ope r a t e s a s a mast er a nd t he nss o u t p u t is e nab le d th ro ugh t h e sso e b i t in t h e spi _cr2 r e gist er , th e nss pin is d r iv en lo w an d a ll th e nss pin s o f de vice s co nn ec te d to th e mast er nss pin see a lo w le v e l an d beco m e sla v e s when th e y ar e co nf igu r e d in nss ha rdw a r e mod e . when a n spi w a nt s t o br oad ca st a me ssag e , it h a s t o p u ll n ss lo w to inf o r m all others that there is no w a mast er f o r th e b u s . i f i t f a ils t o p u ll nss lo w , th is me an s t hat t her e is a not h e r ma st e r co mm un ica t ing, and a ha rd f a ult er ro r oc cu rs . ? nss output is disabled: the mu ltimaster capability is allowed. 8-bit shift register spi clock generator 8-bit shift register miso mosi mosi miso sck sck slave master nss (1) nss (1) v dd msbit lsbit msbit lsbit not used if nss is managed by software ai14745 RM0033 serial periphe ral interface (spi) doc id 15403 rev 3 655/1317 fi gu re 24 9. har d war e / s of tw are s l a v e se le ct ma na g e ment cloc k ph ase an d c l oc k pola r ity f o ur p o ssib l e t i min g re lat i on sh ips ma y be chose n b y so f t w a re , using t h e cpol a n d cpha bit s in th e spi _cr 1 re gis t e r . t h e cpo l (clo ck po la rity ) bit co nt ro ls t h e st ea d y st at e va lue o f th e c l oc k wh en n o d a t a is be in g t r a n s fer re d . t h is bit af fec ts b o th ma st er an d slav e m o de s. if cpol is res e t, the sck pin has a lo w - le v e l id le st at e . i f c p ol is se t, th e sck p i n ha s a high-le v e l idle s t ate . if the cpha (clock phase) bit is s e t, the se cond edge on the s c k pin (f alling edge i f the cpo l bit is r e set , r i s i ng e d g e if the c p ol b i t is se t) is th e msb i t ca p t u r e st ro be . da ta a r e lat ch e d o n th e occ u r r e n ce of th e se co nd c l oc k tr an sit i on . i f t h e c p ha b i t is r e s e t, th e fir st edge on the sck pin (f a lling edge if cpol bit is s e t, r i sing ed ge if c p ol bit is reset) is the msbit ca pt ur e str obe . da t a ar e lat c h e d o n th e occur r en ce of t h e f i r s t cloc k t r a n sitio n . th e co mbin at ion o f t he cpo l (cloc k pola r it y) a nd cpha (clock pha se ) bit s sele ct s t h e d a t a ca pt ur e clo c k e d g e . fig u r e 25 0 , sh o w s an spi tr a n s f e r w i th th e f o ur co m b in at ion s of th e cpha an d cpo l bit s . th e diag r a m ma y b e in t e r p re te d as a mast er or sla v e t i min g diag r a m wh er e t h e sck pin , t he mi so p i n, t h e m o si p i n ar e dir e ct ly conn ect ed be tw ee n th e mast er a n d t h e sla v e de vice . not e : 1 pr io r to ch ang ing t h e cpol /cpha b i ts t he spi m u st be disab l e d b y re se tt in g th e spe b i t. 2 m a ste r an d sla v e m u st b e pr og r a mme d wit h t h e sam e tim i ng mo de . 3 t h e idle st at e of sck m u st cor r e spon d to t h e pola r it y select ed in t h e spi _cr1 re gist er ( b y pulling up sck if c pol=1 or pulling do wn sc k if cpol= 0 ). 4 t he da ta f r a m e f o r m a t (8 - or 1 6 - b it ) is se lec t e d th ro ug h th e df f bit in spi_ c r 1 re gis t er , a nd de t e r m ines th e da ta le ng th d u r i ng tr a n smission/ r e cept ion . 1 0 nss internal ssm bit ssi bit nss external pin ai14746 serial peripheral interface (spi) RM0033 656/1317 doc id 15403 rev 3 figu re 25 0. dat a c l o c k t i ming d i a g ram 1. th ese timings a r e shown w i th the lsb f irst b i t reset in the s p i_c r 1 re gister. data frame f o rmat dat a can b e sh if te d out eit h e r msb-f i r s t or l s b- f i rst d epe nd ing on th e v a lue o f t h e lsb f i r st b i t in t h e spi _c r1 re gis t er . ea ch d a t a fr ame is 8 or 1 6 bit s lo ng d epe nd ing on t h e siz e of t h e dat a pr og r a mme d using t h e dff b i t in t h e spi _cr1 re giste r . th e se lect ed da ta f r a m e f o r m at is ap plicab le f o r tr an sm iss i on a n d /o r re ce pt ion . 25.3.2 configuring t he spi in sla v e mode i n t he sla v e co nf igur at ion , t he ser i a l cloc k is r e ceiv ed on t he sck p i n f r om t h e m a st er de vic e . th e v a lu e se t in t h e br [2 :0] b i ts in t h e sp i_ cr1 re g i ste r , do e s n o t a f f e ct th e da ta tr an sf er r a te . not e : i t is re co mme nde d to ena b l e t h e spi sla v e b e f o r e th e mast er sen d s th e clo c k. i f no t , u nde sir e d d a t a t r an sm ission m i gh t occur . t he da ta r e g i ste r of th e sla v e ne ed s t o be r e a d y b e f o r e th e fi rst e dge o f t h e com m u nicat i on clo c k or bef or e t h e e nd of t he on goin g com m u nicat i on . i t is man dat o r y t o h a v e t h e p o la r i ty of t h e co mm un ica t io n cloc k set t o th e st ead y st at e v a lue b e f o r e t he sla v e a n d t h e m a ste r ar e en ab led . f o llo w th e pr oc ed u r e b e lo w to co n f ig ur e th e s p i in sla v e m o d e : # 0 / , # 0 / , - 3 " i t , 3 " i t - 3 " i t , 3 " i t - ) 3 / - / 3 ) . 3 3 t o s l a v e # a p t u r e s t r o b e # 0 ( ! # 0 / , # 0 / , - 3 " i t , 3 " i t - 3 " i t , 3 " i t - ) 3 / - / 3 ) . 3 3 t o s l a v e # a p t u r e s t r o b e # 0 ( ! o r b i t s d e p e n d i n g o n t h e $ a t a f r a m e f o r m a t b i t s e e $ & & i n 3 0 ) ? # 2 o r b i t s d e p e n d i n g o n t h e $ a t a f r a m e f o r m a t b i t s e e $ & & i n 3 0 ) ? # 2 a i b RM0033 serial periphe ral interface (spi) doc id 15403 rev 3 657/1317 pr ocedure 1 . set th e df f bit t o de f i ne 8- or 1 6 -b it d a t a fr ame f o r m at 2 . sele ct th e cpo l an d cpha bit s t o de fin e on e of t h e f o ur r e la tio n ships be tw een th e da ta t r ansf e r an d t h e se r i al cloc k ( s e e f i gur e 25 0 ) . f o r co rr ect dat a tr a n sf er , th e cpol an d cpha bit s m u st be co nf igur ed in th e sam e w a y in t h e sla v e de vice and t he mast er de vice . t h is st ep is not re quir e d wh en t he ti mod e is sele ct ed th ro ugh t h e frf b i t o f t he spi _cr2 r e g i st er . 3 . the f r a m e f o r m a t (m sb- f irst or l sb-f i rst d epe nd ing on t he v a lu e o f t he lsbfi r st b i t in t he spi _cr1 r e g i st er ) m u st be t h e sam e as t h e mast er d e vice . this st ep is no t r equ ire d when t h e ti mo de is se lect ed. 4. in h a r d w a re m o de ( r e f e r t o sla v e select (nss) pin m ana gem ent on p age 6 5 4 ), th e nss p i n must b e co nn ec te d to a lo w le v e l signa l dur in g t he comp let e b y t e t r an sm it sequ en ce . in nss sof t w a r e mod e , set t he ssm bit an d clea r t he ssi bit in t he spi _cr1 re gist er . th is st ep is not re quir e d whe n t he ti mod e is sele ct ed . 5 . set th e frf bit in t h e spi _ cr2 re gist er t o select th e ti m ode p r o t o c o l f o r ser i al comm u n icat ions . 6 . clear th e mstr bit a nd set th e spe bi t (b ot h in t he spi _cr1 reg i ste r ) t o a s sign t h e pin s t o alt e r nat e f u n c t i on s . i n t h is co nf igur at ion t h e m o si p i n is a d a t a inpu t a nd t h e mi so pi n is a da t a out pu t. t r ansmit sequen c e th e da ta b yt e is pa r a lle l-lo ade d int o t h e tx b u f f e r du r i ng a wr it e cycle . th e tr a n smit seq uen ce b egin s wh en t he sla v e de vice re ce iv es t he clo c k signa l an d th e m o st sign ifica n t b i t of t he da ta on it s mo si pin . th e re main ing b i ts (t he 7 b i t s in 8- bit dat a f r am e f o r m a t, an d th e 15 b i ts in 16 -b it da ta fr a m e f o r m at ) ar e loa d e d in to th e sh ift- re gis t e r . t h e txe fla g in th e spi_ s r re gis t er is se t o n th e tr an sf er o f d a t a fr om t h e tx buf f er t o the s h if t re gis t e r a n d an in te rr u p t is ge ne r a t e d if th e t xeie bit in th e spi_ cr2 r e g i ste r is s e t . rece ive se quence f o r th e re ce iv e r , w h e n da ta t r a n sf e r is co m p le te : t h e d a t a in s h if t r e g i st er is tr an sf er re d to rx buf f e r an d th e rxne fla g ( spi_ s r register) is set an in te rr u p t is g e n e r a te d if t h e rxn e ie bit is s e t in th e spi_ cr2 r e g i st er . afte r th e las t s a m p ling clo c k ed ge t h e rx ne b i t is se t, a co p y o f th e d a t a b yte r e c e iv e d in th e sh ift r e gist er is mo v e d t o the r x b u ff er . wh e n th e s p i_ dr r e gist er is re ad , th e spi p e r i ph er a l r e t u r n s th is b u f f ere d v a lu e . clea r ing o f t he rxne bit is p e r f o r me d b y re adin g t he spi _dr r egist er . spi ti p r otoco l in sla v e mode i n sla v e m ode , th e spi int e r f ace is com pat ib le with t h e t i pr ot oco l . th e frf b i t o f t he spi _cr2 re giste r can be used t o conf igu r e t h e sla v e spi ser i a l com m unicat i on s t o be compliant with this protocol. th e clo c k pola r it y and ph ase ar e f o r ced to con f o r m to t he ti pr ot ocol re quir e m ent s wha t e v e r th e v a lu e s se t in th e s p i_ cr1 r e g i ste r . nss ma n a g e m e nt is als o s p e cif ic to t h e ti pr ot oc ol which ma k e s th e co nf igu r at ion o f nss m ana gem ent t h ro ug h th e spi_ c r1 a nd spi _cr2 r e g i st er s ( s u ch as ssm, ssi, sso e ) t r an sp ar ent f o r t he u s e r . serial peripheral interface (spi) RM0033 658/1317 doc id 15403 rev 3 i n sla v e m ode ( fig u re 251 : ti m ode - sla v e mo de , sing le tr ansf e r a nd fig u r e 252 : ti mod e - sla v e mod e , con t in u ous tr ansf e r ), th e spi ba ud r a te p r e s ca ler is used t o cont ro l th e mom ent whe n th e mi so pin st at e chan ges t o hiz . an y b aud r a t e ca n be u s e d t hus allo wing t o deter m ine this moment with optima l fle x ibility . ho w e v e r , the baud r a te is gener ally set to the e x te r n al m a st er clo c k ba ud r a te . t h e t i m e f o r th e m iso sig n a l t o be co me h i z (t release ) d epe nd s o n in te r n a l re syn c h r o n izat ion s a nd on t h e ba ud r a t e v a lue se t in th ro ug h br[2 :0 ] of spi _cr1 re giste r . i t is g i v en b y t h e f o r m ula : no te : t his f e at ur e is n o t a v a ila b l e f o r mo to ro la spi co mmun i ca tio n s (frf b i t se t to 0 ) . t o de te ct t i fr a m e er ror s in sla v e tr a n smit t e r only m ode b y using th e er ro r in te rr u p t ( e rri e = 1) , t he spi m u st be con f ig ur ed in 2- line u n id ire c t i on al mod e b y set t in g bi di mo de an d bidioe to 1 in the sp i_cr1 regi ster . when bidimode is s e t to 0, o v r is se t t o 1 b e cause t h e d a t a re gist er is ne v e r re ad a nd er ro r int e rr up t a r e a l w a ys g ene r a t e d, while wh en bi dimo de is se t t o 1, dat a ar e no t r e ceiv e d and o v r is ne v e r set . figu re 25 1. ti mode - sla v e mode , single t rans f er figu re 25 2. ti mode - sla v e mo de , con t in uous t ra n sf e r t b aud_ rate 2 ------------- -------- - 4t pc l k + t release t b aud_ rate 2 ------------- -------- - 6t pc l k + << a i - 3 " ) . - / 3 ) i n p u t . 3 3 i n p u t 3 # + i n p u t t r i g g e r e d g e s a m p l i n g e d g e t r i g g e r e d g e s a m p l i n g e d g e t r i g g e r e d g e s a m p l i n g e d g e $ / . 4 # ! 2 % , 3 " ) . $ / . 4 # ! 2 % - ) 3 / o u t p u t o r - 3 " / 5 4 , 3 " / 5 4 t 2 e l e a s e a i - 3 " ) . - / 3 ) i n p u t . 3 3 i n p u t 3 # + i n p u t t r i g g e r s a m p l i n g t r i g g e r s a m p l i n g t r i g g e r s a m p l i n g $ / . 4 # ! 2 % , 3 " ) . $ / . 4 # ! 2 % - ) 3 / o u t p u t o r - 3 " / 5 4 , 3 " / 5 4 - 3 " ) . , 3 " ) . - 3 " / 5 4 , 3 " / 5 4 & 2 ! - % & 2 ! - % RM0033 serial periphe ral interface (spi) doc id 15403 rev 3 659/1317 25.3.3 configuring the spi in master mode in th e m a s t er c o n f ig ur a t io n, th e se r i al cloc k is ge ne r a t e d o n th e sck pin . pr ocedure 1. se lec t t h e br [2 :0] b i ts to de fin e th e se r i al cloc k b a u d r a t e ( se e spi_ cr1 r e g i st er ). 2 . sele ct th e cpo l an d cpha bit s t o de fin e on e of t h e f o ur r e la tio n ships be tw een th e da ta t r a n sf e r an d t he ser i a l cloc k (see f i gur e 25 0 ). this step is not required when the ti m ode is select ed . 3 . set th e df f bit t o de f i ne 8- or 1 6 -b it d a t a fr ame f o r m at 4. co n f ig ur e the l sbf ir st bit in th e spi_ cr1 r e gist er to d e f in e t h e f r a m e f o r m a t. th is ste p is n o t r e q u ir ed when th e ti m ode is se lect ed. 5 . i f t he nss p i n is r equ ire d in inp u t m ode , in ha rd w a r e mod e , conn ect t h e nss pin t o a hig h - l e v el signa l dur in g th e comp let e b y t e t r an sm it sequ en ce . in nss so ft w a re mo de , set t h e ssm a nd ssi b i ts in th e spi_ c r1 r e g i st er . if th e nss pin is re qu ire d in out p u t mo de , t h e ssoe bit on ly shou ld be set . this st ep is no t r equ ire d wh en t h e t i mo de is selected. 6 . set th e frf bit in spi _cr2 to se lect t h e ti pr ot ocol f o r ser i a l co mm un ica t io ns . 7. the mstr and spe bits must be set (the y remain set only if the nss pin is connected t o a hig h -le v el si gna l). i n t h is co nf igur at ion t h e m o si p i n is a d a t a out p u t a nd t h e mi so p i n is a d a t a inpu t. t r ansmit sequen c e th e t r an smi t sequ en ce b egin s whe n a b y t e is wr it t en in t h e t x buf f er . th e da ta b y t e is pa r a lle l-lo ade d int o t h e shif t r e g i st e r (f ro m th e int e r n a l b u s) d u r i ng th e fir st b i t t r an sm ission and t h e n shif te d ou t ser i all y t o th e mosi pin msb f i rst o r lsb fir st d epe nd ing on t h e l sbfi r st bit in th e spi_ c r1 r egist er . t he txe fla g is set on t he t r an sf e r o f d a t a f r o m th e tx buf f er t o t h e sh if t r egist er and an in te rr u p t is g e n e r a te d if th e txei e b i t in the spi_cr2 register is set. rece ive se quence f o r th e re ce iv e r , w h e n da ta t r a n sf e r is co m p le te : the dat a in t h e shif t r e g i ste r is t r an sf e r r ed t o t he rx bu ff er and t h e rxne fla g is set an in te rr u p t is ge ne r a t e d if th e rxne ie b i t is se t in the sp i_ cr2 re g i ste r at t h e la st sa m p lin g clo c k e d g e th e rxne bit is se t, a c o p y of th e da ta b y te re ce iv e d in the sh ift re gis t er is m o v e d t o th e rx b u f f e r . w h e n th e spi_ dr re gis t er is re a d , th e spi p e r i ph er a l r e t u r n s th is b u f f ere d v a lu e . clear ing the rxne bit is perf o r m ed b y r ead ing t h e spi _dr r e g i st er . a co n t in u o u s t r an sm it s t re a m ca n be m a inta in ed if th e ne xt da ta t o be tr a n s m itte d is p u t in t h e t x b u f f e r on ce th e tr ansmission is st ar t e d . not e t hat txe fla g sh ou ld be ?1 b e f o r e an y at te mp t to wr ite t h e tx b u f f e r is m a d e . not e : i n t he nss h a r d w a re mo de , t h e sla v e's nss inp u t is con t r o lle d b y th e nss pin or a not he r g p io p i n th at has to be cont r o lled b y so ft w a re . serial peripheral interface (spi) RM0033 660/1317 doc id 15403 rev 3 spi ti p r otoco l in mas t er mode in m a s t e r m o de , th e spi int e r f a c e is com p at ib le wit h t h e t i pr ot oc ol. t h e f r f b i t of th e spi _cr2 re giste r can be used t o conf igu r e t h e mast er spi ser i a l co mm un ica t io ns t o b e compliant with this protocol. th e clo c k pola r it y and ph ase ar e f o r c ed to con f o r m to t he ti pr ot ocol re quir e m ent s wha t e v e r th e v a lu e s se t in th e s p i_ cr1 r e g i ste r . nss ma n a g e m e nt is als o s p e c if ic to t h e ti pr ot oc ol which ma k e s th e co nf igu r at ion o f nss m ana gem ent t h ro ug h th e spi_ c r1 a nd spi _cr2 registers (ssm, ssi, ssoe) t r a n spar en t f o r t h e user . fig u r e 25 3: ti mo de - m a ste r m ode , sing le t r a n sf e r an d figu re 2 54: t i m ode - mast er mo de , co nt in uo us tr a n s f e r ) sho w th e spi mast er co mm unica tio n w a v e f o r m s when th e ti m ode is sele ct e d in mast er m ode . figu re 25 3. ti mode - ma st er mode , s i n g le tra n sf er figure 254. ti mode - master mode, continuous transfer a i - 3 " ) . - / 3 ) i n p u t . 3 3 o u t p u t 3 # + o u t p u t t r i g g e r e d g e s a m p l i n g e d g e t r i g g e r e d g e s a m p l i n g e d g e t r i g g e r e d g e s a m p l i n g e d g e $ / . 4 # ! 2 % , 3 " ) . $ / . 4 # ! 2 % - ) 3 / o u t p u t o r - 3 " / 5 4 , 3 " / 5 4 a i - 3 " / 5 4 - / 3 ) o u t p u t . 3 3 o u t p u t 3 # + o u t p u t t r i g g e r s a m p l i n g t r i g g e r s a m p l i n g t r i g g e r s a m p l i n g $ / . 4 # ! 2 % , 3 " / 5 4 $ / . 4 # ! 2 % - ) 3 / i n t p u t o r - 3 " ) . , 3 " ) . - 3 " / 5 4 , 3 " / 5 4 - 3 " ) . , 3 " ) . & 2 ! - % & 2 ! - % RM0033 serial periphe ral interface (spi) doc id 15403 rev 3 661/1317 25.3.4 configuring the spi f o r simple x comm unication th e spi is ca pab le o f op er a t in g in simple x mo de in 2 con f ig ur a t io ns . 1 cloc k and 1 b i dir e ct iona l d a t a wire 1 cloc k and 1 d a t a wire ( r e c e i v e - only or t r a n smit -o nly) 1 c lo c k and 1 bidirectiona l data wire (bidimode=1) th is mo de is en ab led b y set t i ng t h e bi dimo de bit in th e spi_ cr1 r e gist er . in t h is m o d e sck is used f o r th e cloc k a n d mo si in ma ste r or m i so in sla v e mod e is u s e d f o r da t a com m u nicat i on . th e t r an sf er d i re ctio n (i np ut /o ut pu t) is select ed b y t h e bi di oe bit in t h e spi _cr1 re giste r . when th is bit is 1 , t he da t a line is out pu t o t h e rwise it is inp u t . 1 c l o c k and 1 unidirection a l data wire (bidimode=0) i n t h is mod e , t h e a ppl ica t io n can u s e t h e spi eit h e r in t r a n smit -o nly m ode or in re ce iv e - o n ly mo de . t r ansmit-only mode is similar to full-duple x m ode (bi d im ode=0 , rxonl y =0): t h e da ta ar e tr a n smit t ed on th e tr a n smit p i n ( m o s i i n ma ste r mod e o r miso in sla v e mo de) a nd t he r e ceiv e pin ( m i s o in ma st er mod e or m o si in sla v e mod e ) can b e used a s a ge ner al- pur po se i o . in t h is ca se , th e ap plicat ion ju st ne eds to igno re t h e rx b u ff er (if t he da ta reg i ste r is r e a d , it doe s n o t co nt ain t he r e ceiv ed v a lue ) . i n r e ceiv e - o n ly mo de , t h e a pplica t io n ca n d i sab l e th e spi out pu t f unct i on b y set t in g th e rxo n l y b i t in t h e spi _cr 2 re gis t e r . i n th is ca se , it fre e s t h e tr a n s m it io p i n (m o s i in ma st er mod e or mi so in sla v e mod e ), so it can b e used f o r o t her pur po se s . t o st ar t th e co mm un ica t io n in r e ceiv e- on ly mo de , con f ig ur e an d ena b l e th e spi: in master mode , the comm unication star ts immediately and stops when the spe bit is clear ed a nd t h e cur r e n t re ce pt ion st ops . th ere i s no n eed to r e a d th e bsy f l ag in t h is mo de . i t is alw a ys se t whe n an spi com m unicat i o n is on go ing. i n sla v e mo de , t h e spi co nt in ue s t o re ce iv e as l ong a s t h e nss is pu lled d o wn ( o r t h e ssi b i t is cle a r e d in ns s so ft w a re m o de ) an d th e sck is r u nn in g. 25.3.5 data transmission and recepti on pr ocedures rx a nd tx b u ff er s i n r e cept ion , d a t a ar e re ce iv ed an d t hen st or ed in to a n int e r nal rx b u f f er while in t r a n smissio n , d a t a ar e f i rst st or ed int o a n int e r n al tx b u ff er bef or e be ing t r a n smit te d. a re ad a c cess o f t h e spi _dr r e g i st er re tu r n s th e rx b u f f ere d v a lu e wh er eas a wr ite a c ce ss t o t he spi _dr st ore s t h e wr it t en da ta i n t o th e tx b u ff er . serial peripheral interface (spi) RM0033 662/1317 doc id 15403 rev 3 star t sequenc e in ma ster mode i n fu ll-d uple x ( b idi m ode=0 an d rxo n l y =0) ? t he seq uen ce beg ins wh en da t a ar e wr it t e n in to t h e spi _ dr reg i ste r (t x b u f f e r ) . ? t he d a t a ar e th en p a r a llel load ed f r om t he tx b u ff er int o t he 8- bit sh ift re gist er dur in g th e f i rst b i t t r an sm ission and t h e n shif te d ou t ser i a lly t o th e mosi pin . ? a t t he same t i me , th e re ce iv ed da ta on t he mi so pin is shif te d in ser i a lly t o th e 8- bit shif t reg i ste r an d th en p a r a llel load ed in to t h e spi _ dr reg i ste r (rx b u ff er ). i n unid i re ct io nal r e ceiv e- on ly mo de ( b i d i m ode=0 and rxonl y =1) ? t he seq uen ce beg ins as soo n as spe=1 ? o nly th e re ce iv er is activ a te d and t h e r e ceiv e d da ta o n th e mi so p i n ar e shif te d in s e r i a lly t o th e 8- bit sh ift re gis t e r a n d th en par a llel loaded into the spi_dr regis t er (rx b u f f er ). in b i d i re ctio na l m o de , wh e n tr an sm itt i ng ( b idi m o d e= 1 an d bidi oe= 1 ) ? t he seq uen ce beg ins wh en da t a ar e wr it t e n in to t h e spi _ dr reg i ste r (t x b u f f e r ) . ? t he d a t a ar e th en p a r a llel load ed f r om t he tx b u ff er int o t he 8- bit sh ift re gist er dur in g th e f i rst b i t t r an sm ission and t h e n shif te d ou t ser i a lly t o th e mosi pin . ? n o d a t a ar e re ce iv ed. i n bidir e ct ion a l mod e , when r e ceivin g (bi d i m o d e=1 a nd bi di oe=0) ? t he seq uen ce beg ins as soo n as spe=1 an d bi di oe=0. ? the r e ceiv ed dat a on th e mosi pin ar e shif t ed in ser i a lly t o th e 8- bit sh ift re giste r and t h e n pa r a lle l lo ad ed int o t h e spi _dr r e g i st er (rx b u f f er ). ? t h e tr a n sm itt e r is no t ac tiv a te d a n d no d a t a ar e sh ifte d ou t ser i a lly to th e mo si pin. star t sequenc e in sl a v e mode i n fu ll-d uple x mo de ( b idi m ode=0 an d rxo n l y =0) ? t he se qu ence beg ins when t he sla v e d e vice r e ceiv es t h e cloc k signa l an d t h e f i rst bit o f t h e d a t a on it s m o si p i n. t he 7 r e ma ining bit s ar e loa d e d int o th e shif t r e gist er . ? a t t h e sam e t i me , t h e da ta a r e p a r alle l lo ad e d fr om th e tx b u f f er in to th e 8- bit s h ift r e gist er d u r i n g th e fir st b i t tr an sm iss i on , a n d th en sh ift e d o u t se r i ally to t h e m i so pin. the sof t w ar e m u st h a v e wr it t en t h e d a t a to b e sent be f o re t h e spi mast er de vice init iat e s th e t r an sf er . i n unid i re ct io nal r e ceiv e- on ly mo de ( b i d i m ode=0 and rxonl y =1) ? t he se qu ence beg ins when t he sla v e d e vice r e ceiv es t h e cloc k signa l an d t h e f i rst bit o f t h e d a t a on it s m o si p i n. t he 7 r e ma ining bit s ar e loa d e d int o th e shif t r e gist er . ? t h e tr a n sm itt e r is no t ac tiv a te d a n d no d a t a ar e sh ifte d ou t ser i a lly to th e mi so pin. in b i d i re ctio na l m o de , wh e n tr an sm itt i ng ( b idi m o d e= 1 an d bidi oe= 1 ) ? t he se qu ence beg ins when t he sla v e d e vice r e ceiv es t h e cloc k signa l an d t h e f i rst bit in t h e tx b u f f er is tr ansmit t ed on th e mi so pin. ? t he d a t a ar e th en p a r a llel load ed f r om t he tx b u ff er int o t he 8- bit sh ift re gist er dur in g th e f i rst b i t t r an sm ission and t h e n shif te d ou t ser i a lly t o th e mi so pin . th e s o f tw a r e m u s t h a v e w r itte n th e da ta to b e se nt b e f o r e th e s p i m a ste r de vice initiates the tr ansf e r . ? n o d a t a ar e re ce iv ed. RM0033 serial periphe ral interface (spi) doc id 15403 rev 3 663/1317 i n bidir e ct ion a l mod e , when r e ceivin g (bi d i m o d e=1 a nd bi di oe=0) ? t he se qu ence beg ins when t he sla v e d e vice r e ceiv es t h e cloc k signa l an d t h e f i rst b i t of th e da ta o n its mi so pin . ? t he r e ceiv ed dat a on th e mi so pin ar e shif t ed in ser i a lly t o th e 8- bit sh ift re giste r and t h e n pa r a lle l lo ad ed int o t h e spi _dr r e g i st er (rx b u f f er ). ? t h e tr a n sm itt e r is no t ac tiv a te d a n d no d a t a ar e sh ifte d ou t ser i a lly to th e mi so pin. handling data tra n smiss i on and rec e ption t h e txe f l ag (t x b u ff e r e m pty ) is se t wh en th e d a t a a r e t r an sf e r re d fr om th e t x b u ff er t o th e sh ift re gis t er . i t in dic a t e s th at th e int e r n al tx b u ff e r is r e ad y t o be lo ad e d with th e n e xt d a t a . an in te rr u p t can be ge ne r a t e d if th e txeie bit in t he spi _cr2 r e g i st e r is set . clea r ing t h e t xe b i t is pe r f o r m e d b y w r iting t o th e spi_ dr re gis t er . no te : t he so ft w a re must e n s u r e th at th e tx e fla g is s e t to 1 b e f o r e at tem p tin g to wr ite t o th e tx b u f f er . o t h e r w ise , it o v erwr it es th e da ta p r e v io usly wr it te n t o th e tx b u ff er . th e rxne f l ag ( r x b u ff er not emp t y) is set o n t he last sa mplin g clo c k e dge , wh en t h e d a t a a r e t r an sf e r r ed f r o m th e shif t r egist er t o t h e rx b u f f er . i t i ndicat e s t hat dat a a r e r ead y t o be r e a d fr om t h e spi _dr r e g i st er . an int e r r upt ca n be g ene r a t e d if t he rxnei e bit in t h e spi_cr2 register is set. clear ing the r x ne bit is pe rf or m ed b y r e a d ing t h e spi _ dr re gis t e r . f o r so me co nf igu r at ion s , t he bsy fla g ca n b e u s e d dur in g t h e la st d a t a tr a n sf er t o w a it un til th e co mp le tion o f th e t r an sf e r . ful l-duple x trans m it and re ceive p r oce dure in ma ster or sla ve mode (bidimode=0 and rxonl y =0) th e sof t w a r e has to f o llo w t h is p r o c e d u r e t o t r an smi t an d re ce iv e dat a ( s e e f i gu r e 25 5 a nd fig u r e 25 6 ): 1. enab le the spi b y setting the spe bit to 1. 2. wr it e th e fir st d a t a ite m t o be tr an sm itt e d into th e spi_ d r r e g i st er ( t h i s clea r s t h e tx e f l ag) . 3 . w a it un t il txe=1 an d wr ite t h e se co nd d a t a it em t o be tr a n s m it te d. the n w a it un til rxne=1 an d re ad t he spi _dr t o ge t t he f i rst r e ceiv e d da ta it em ( t h i s clea rs th e rxne bit ) . repe at th is op er a t io n f o r e a ch dat a it em t o be t r a n smit te d/ re ceiv ed u n t il t h e n?1 receiv ed data. 4. w a it until rxne =1 and r ead t h e last r e ceiv ed d a t a . 5 . w a it un t il txe=1 an d t hen w a it u n t il bsy=0 be f o re d i sab ling t h e spi . th is p r oce dur e ca n also be imp l eme n t e d u s in g ded icat ed int e r r up t subr ou tin e s la un ch ed at e a ch r i sing ed ge s of th e rxne or t x e f l ag . serial peripheral interface (spi) RM0033 664/1317 doc id 15403 rev 3 figu re 25 5. txe/rxne/bsy be ha vior in mas t er / f u ll- duple x mode (b idi m o d e= 0 and rxo n l y =0 ) i n th e cas e of c ont in uo us tr ans f er s figure 256. txe/rxne/bsy behavior in slave / full-duplex mode (bidimode=0, rxonly=0) in the case of continuous transfers mi s o/mo s i (in) tx bu ff er data1 = 0xa1 txe fl a g 0xf2 b s y fl a g 0xf 3 s oftw a re write s 0xf1 into s pi_dr s oftw a re w a it s u ntil txe=1 a nd write s 0xf2 into s pi_dr s oftw a re w a it s u ntil rxne=1 a nd re a d s 0xa1 from s pi_dr s et b y h a rdw a re cle a re d b y s oftw a re s et b y h a rdw a re cle a red b y s oftw a re s et b y h a rdw a re s et b y h a rdw a re s ck data 2 = 0xa2 data 3 = 0xa 3 re s et b y h a rdw a re ex a mple in m as t er mode wit h cpol =1, cpha=1 0xf1 rxne fl a g (wri te s pi _d r) rx bu ffer s et b y h a rdw a re mi s o/mo s i (o u t) data1 = 0xf1 data2 = 0xf2 data 3 = 0xf 3 (r e a d s pi _d r) 0xa1 0xa2 0xa 3 s oftw a re w a it s u ntil txe=1 a nd write s 0xf 3 into s pi_dr s oftw a re w a it s u ntil rxne=1 a nd re a d s 0xa2 from s pi_ dr s oftw a re w a it s u ntil rxne=1 a nd re a d s 0xa 3 from s pi_dr b 0 b 1 b 2 b3 b 4 b 5 b 6 b 7 b 0 b 1 b 2 b3 b 4 b 5 b 6 b 7 b 0 b 1 b 2 b3 b 4 b 5 b 6 b 7 b 0 b 1 b 2 b3 b 4 b 5 b 6 b 7 b 0 b 1 b 2 b3 b 4 b 5 b 6 b 7 b 0 b 1 b 2 b3 b 4 b 5 b 6 b 7 cle a re d b y s oftw a re a i17 3 4 3 0xf1 s et b y cle a red b y s oftw a re mi s o/mo s i (in) tx bu ff er data 1 = 0xa1 txe fl a g 0xf2 b s y fl a g 0xf 3 software writes 0xf1 into spi_dr software waits until txe=1 and writes 0xf2 into spi_dr software waits until rxne=1 and reads 0xa1 from spi_dr s et b y h a rdw a re cle a re d b y s oftw a re s et b y h a rdw a re cle a re d b y s oftw a re s et b y h a rdw a re s ck data 2 = 0xa2 data 3 = 0xa 3 re s et b y h a rdw a re ex a mple in s l a ve m ode with cp ol=1, cpha=1 rxn e fl a g (wri te t o s pi _d r) rx bu ffer s et b y h a rdw a re mi s o/mo s i (o u t) data 1 = 0xf1 data 2 = 0xf2 d a ta 3 = 0xf 3 (r e a d from s pi _d r) 0xa1 0xa2 0xa 3 software waits until txe=1 and writes 0xf3 into spi_dr software waits until rxne=1 and reads 0xa2 from spi_ dr software waits until rxne=1 and reads 0xa3 from spi_dr b 0 b 1 b 2 b3 b 4 b 5 b 6 b 7 b 0 b 1 b 2 b3 b 4 b 5 b 6 b 7 b 0 b 1 b 2 b3 b 4 b 5 b 6 b 7 b 0 b 1 b 2 b3 b 4 b 5 b 6 b 7 b 0 b 1 b 2 b3 b 4 b 5 b 6 b 7 b 0 b 1 b 2 b3 b 4 b 5 b 6 b 7 cle a red b y s oftw a re a i17 3 44 RM0033 serial periphe ral interface (spi) doc id 15403 rev 3 665/1317 t r ansmi t-onl y pr ocedure (bidimode=0 rxonl y =0) in this mode , the pr ocedure can be reduc ed as descr i bed belo w and the bsy bit can be u s e d to w a it unt il th e comp let i on o f t he t r an sm ission (see fig u r e 25 7 and f i gur e 25 8 ). 1. enab le the spi b y setting the spe bit to 1. 2 . wr ite t h e fir st da ta it e m t o sen d int o t he spi _dr r egist er ( t his clea rs th e txe bit ) . 3 . w a it un t il txe=1 an d wr ite t h e ne xt d a t a it em t o be t r an smitt e d. rep e a t t h is st ep f o r e a c h da ta ite m to b e tr a n sm it ted . 4. after wr iting the last data it em int o t h e spi _dr re giste r , w a it until txe=1, then w a it until bsy=0, this indicates that the tr ansmi ssion of the last data is complete . th is p r oce dur e ca n be al so imp l eme n t e d u s in g ded icat ed int e r r up t subr ou tin e s la un ch ed at e a ch r i sing ed ge o f t he txe fl ag. note: 1 dur i ng discontin uous comm unications , t here is a 2 apb cloc k per i od dela y betw een the wr ite oper ation to spi_dr and the bsy bit setting. as a co nsequence , in tr ansmit-only mode , it is mandator y to w a it first until txe is set and then until bsy is cleared after w r iting th e las t d a t a . 2 a fte r tr a n s m it tin g t w o d a t a ite m s in tr a n s m it -o nly m o d e , th e o v r f l ag is se t in t h e spi _sr re gis t e r s i nc e the r e ceiv ed d a t a ar e ne v e r r e a d . fi gu re 25 7. txe/ bsy be ha vi or in m ast er t r ans m it -o nl y mode ( b idimode=0 and rxonl y =0) in the c ase o f con t in uous tra n sf e r s 0xf1 tx bu ffer t xe f l a g 0xf2 b s y f l a g 0xf 3 sof t ware writes 0 xf1 into sp i _ d r so ftware waits unt il txe= 1 an d writes 0xf2 into spi_dr s et b y h a rdw a re cle a red b y s oftw a re s et b y h a rdw a re cle a red b y s oftw a re s et b y h a rdw a re s et b y h a rdw a re s ck re s et b y h a rdw a re ex a mple in m as t er mode wit h cpol =1, cpha=1 (wri te t o s pi _d r) mi s o/ mo s i (o u t) data 1 = 0xf1 data 2 = 0xf2 d a ta 3 = 0xf 3 sof t ware w a its u n til txe=1 and writes 0xf3 into spi_dr software waits until bsy=0 software wa it s un ti l t x e= 1 b 0 b 1 b 2 b3 b 4 b 5 b 6 b 7 b 0 b 1 b 2 b3 b 4 b 5 b 6 b 7 b 0 b 1 b 2 b3 b 4 b 5 b 6 b 7 a i17 3 45 serial peripheral interface (spi) RM0033 666/1317 doc id 15403 rev 3 fi gu re 25 8. txe/ bsy i n sla v e tra n smi t - onl y mode ( b i d im ode=0 and rxonl y =0) i n th e cas e of c ont in uo us tr ans f er s bidirect ional trans m it pr o cedure (bidimode=1 and bidioe=1) i n t h is mod e , t h e pro c edu re is similar t o th e p r oce dur e in t r ansmit - only mo de e x cep t t h a t t h e bi dimo de an d bidi oe bit s bo th h a v e t o be set in th e spi _ cr2 re gist er b e f o re e n a b lin g th e spi. unidirec tional rece ive-onl y pr oce dure (bidimode=0 and rxonl y =1) i n t h is m ode , th e pr oced ur e ca n be r e d u ced as de scr i be d be lo w ( s e e figu re 2 5 9 ): 1 . set th e rxo n l y bit i n th e spi_ c r2 r egist er . 2. enab le the spi b y setting the spe bit to 1: a) in m a ste r mo de , t h is imme diat ely act i v a t e s t h e g e n e r a tio n of t h e sck cloc k, an d data are ser i ally receiv ed unt il the sp i is disab l ed (spe=0). b) in sla v e m ode , da t a ar e r e ceiv e d whe n t he spi ma st er de vice dr iv es nss lo w a n d g e n e r at es th e sck cloc k . 3 . w a it un t il rxne=1 a nd r ead t h e spi _ dr re giste r t o get t he re ceiv ed d a t a (t his clear s t he rxne bit ) . repe at th is op er a t i on f o r e a ch da ta it em t o be rece iv e d . th is p r oce dur e ca n also be imp l eme n t e d u s in g ded icat ed int e r r up t subr ou tin e s la un ch ed at e a ch r i sing ed ge o f t he rxne f l ag . not e : i f it is req u ir ed t o d i sa b l e th e spi a f t e r th e last tr a n sf er , f o ll o w t he r e comm end at ion d e scr ibed in section 25.3.8: disabling the spi on page 671 . 0xf1 tx bu ffer txe fl a g 0xf2 b s y fl a g 0xf 3 software writes 0xf1 into spi_dr software waits until txe=1 and writes 0xf2 into spi_dr s et b y h a rdw a re cle a red b y s oftw a re s et b y h a rdw a re cl e a re d b y s oftw a re s et b y h a rdw a re s et b y h a rdw a re s ck re s et b y h a rdw a re ex a mple in s l a ve mode with cpol =1, cpha =1 (wri te t o s pi _d r) mi s o/ mo s i (o u t) data 1 = 0xf1 data 2 = 0xf2 data 3 = 0xf 3 software waits until txe=1 and writes 0xf3 into spi_dr software waits until bsy=0 soft w a re wait s un til t x e=1 b 0 b 1 b 2 b3 b 4 b 5 b 6 b 7 b 0 b 1 b 2 b3 b 4 b 5 b 6 b 7 b 0 b 1 b 2 b3 b 4 b 5 b 6 b 7 a i17 3 46 RM0033 serial periphe ral interface (spi) doc id 15403 rev 3 667/1317 figu re 25 9. rxne be ha vior in rec e ive- onl y mode (b idi r m o de =0 and r x on l y = 1 ) in the ca s e of c ont in uo us tr ans f er s bidirect ional rece ive pr ocedure (bidimode=1 an d bidi oe=0) i n t h is m ode , th e pr oced ur e is similar to t h e re ce iv e- only mod e pr oced ure e xce pt t h at t h e bi dimo de b i t ha s t o be set an d th e bidi oe bit cle a r ed in t h e spi _cr2 re giste r be f o re e nab lin g th e spi. contin uo us and d i scontin u ous transf er s wh en tr a n sm i ttin g da ta in m a s t e r m o de , if th e so ftw a r e is f a st e n o u g h t o de te ct ea ch r i sin g ed g e of t xe ( o r t xe in te rr u p t ) an d to im m e d i at ely wr ite t o the s p i_ dr r e gist er b e f o r e th e o ngo ing d a t a t r an sf e r is co mple te , t he com m unicat i o n is sa id t o be co nt in uo us . in th is case , t h e r e is no d i scon tin u it y in t h e g ene r a t i on o f t h e spi clo c k be t w ee n ea ch d a t a it em an d th e bsy bit is ne v e r cleared betw een each data tr ansf er . o n th e cont r a r y , if t h e sof t w ar e is n o t f a st en oug h, t h is can le ad t o so me di scon tin u it ies in t h e com m unicat i o n . i n t h is ca se , th e bsy b i t is clea re d be tw een e a ch da ta tr a n smission (s ee fig u re 260 ). i n m a ste r r e ceiv e- on ly m ode (rxonl y=1 ) , t he co mm unica tio n is alw a ys con t in u ous a nd t h e bsy flag is alw a ys read at 1. i n sla v e m ode , th e co nt in uit y o f t h e com m unicat i o n is de cided b y th e spi mast er d e vice . i n an y case , e v en if the communication is cont in uous , the bsy flag goes lo w betw een each tr an sf er f o r a m i nim u m d u r a tion o f on e spi clo c k cy cle (s ee figu re 2 5 8 ). mi s o/ mo s i (in) data 1 = 0xa1 software waits until rxne=1 and reads 0xa1 from spi_dr s ck data 2 = 0xa2 data 3 = 0xa 3 ex a mple with cpol =1, cpha = 1 , rxon l y =1 rxn e fl a g rx bu ffer s et b y h a rdw a re (r e a d from s pi _d r) 0xa1 0xa2 0xa 3 software waits until rxne=1 and reads 0xa2 from spi_dr software waits until rxne=1 and reads 0xa3 from spi_dr b 0 b 1 b 2 b3 b 4 b 5 b 6 b 7 b 0 b 1 b 2 b3 b 4 b 5 b 6 b 7 b 0 b 1 b 2 b3 b 4 b 5 b 6 b 7 cle a re d b y s oftw a re a i17 3 47 serial peripheral interface (spi) RM0033 668/1317 doc id 15403 rev 3 figu re 26 0. txe/bsy be ha vior wh en tr ans m it ti ng ( b idirmode=0 a nd rxonl y =0 ) in t h e c ase of dis c ont in u ous t r ans f er s 25.3.6 crc calculation a cr c c a lculator has been implemented f o r comm unication reliability . separ a te crc calcula t ors ar e imple m en t ed f o r t r a n smit te d dat a a nd r e ceiv ed d a t a . the crc is ca lcu l at ed u s in g a pro g r a m m ab le po lyn o mia l ser i ally o n each bit . i t is calcu l at ed on t h e sam p ling cloc k e dge d e f i ne d b y t he cpha an d cpo l bit s in t h e spi _ cr1 re gist er . not e : t h i s spi o f f e rs t w o kin d s of crc calcula t io n sta nda rd wh ich d epe nd d i re ct ly o n t he da ta f r a m e f o r m at se lecte d f o r th e t r ansmission a n d / o r r e cept io n: 8 - b i t d a t a ( c r8) an d 16 -bit da ta (c rc16). crc calculation is enab led b y s e tting the crcen bit in the spi _cr1 re giste r . th is act i on resets the crc regis t ers (spi_r xcrcr and spi_txc rcr). in full duple x or tr ansmitter on ly m o d e , wh en the tr an sf er s ar e m a n a g e d b y th e so ft w a r e (c pu m o de ) , it is n e c e s s ar y to wr ite the bit c rcne xt immediatel y after the last data to be tr ansf erred is wr itten to the spi_ dr. at th e en d of th is last d a t a tr an sf er , th e spi_ t xcrc r v a lue is tr ans m itted. in r e ceiv e on ly mo de a nd whe n th e tr ansf e r s ar e ma nag ed b y sof t w ar e ( c pu mod e ) , it is n e cessar y t o wr it e t h e crcnext bit af te r t he secon d last d a t a ha s be en r e ceiv ed . th e crc is receiv ed just after the last data rec e ption and the crc chec k is then perf or med. at th e end o f d a t a an d crc t r a n sf ers , t he crcerr f l ag in th e spi_ s r re gist er is se t if cor r up tio n occur s du r i ng t h e t r a n sf e r . if d a ta ar e p r e se n t in th e tx b u ff e r , th e cr c v a lu e is tr an sm itt e d on ly af ter t h e tr an sm iss i on o f t he d a t a b yt e . dur i n g crc tr a n smission, th e crc ca lculat or is s w it che d of f a nd t he r e g i st er v a lue r e ma ins uncha ng ed. note: p lease ref e r to the pr oduct specifications f o r a v ailability of this f e ature . mo s i ( o u t) tx bu ffer data 1 = 0xf1 txe fl a g 0xf1 b s y fl a g 0xf2 so f t wa re wri t e s 0 x f1 into sp i_dr software waits until txe=1 but is late to write 0xf2 into spi_dr sof t ware waits until txe= 1 but is late t o write 0xf3 i n to spi_dr s ck 3 f x 0 = 3 a t a d 2 f x 0 = 2 a t a d ex a mple with cpol=1, cpha=1 0xf 3 software waits until txe=1 software waits until bsy=0 (write to s pi_dr) b 0 b 1 b 2 b3 b 4 b 5 b 6 b 7 b 0 b 1 b 2 b3 b 4 b 5 b 6 b 7 b 0 b 1 b 2 b3 b 4 b 5 b 6 b 7 a i17 3 4 8 RM0033 serial periphe ral interface (spi) doc id 15403 rev 3 669/1317 spi comm unication using the crc is possi b l e through the f o llo w i ng procedure: 1. prog r a m the cpol, cpha , lsbfirs t, br, ssm , ssi a n d m s tr v a lu es . 2. pr og r a m th e po lyn o m i a l in th e spi_ crc pr r e gist er . 3. enab le the crc calculation b y setting the crc en bit in the spi_c r1 register . this also clears the sp i_rxcrc r and s p i_tx crcr registers . 4. enab le the spi b y setting th e spe bit in the spi_cr1 register . 5. st ar t th e co mmun i ca tio n an d su sta i n th e com m u n i cat i on u n t il a ll b u t on e b yt e or h a lf- w o rd h a v e b een tr a n smit t ed or rece iv e d . ? i n f u ll du ple x or tr ansmit t e r - on ly mo de , wh en t h e t r an sf e r s are man age d b y s o f t w a r e , whe n wr itin g th e la st b yte o r ha lf w o r d to th e tx b u f f e r , se t t h e c rcn ext bit in the s p i_cr1 register to indicate that the c rc will be transmitted af te r t he t r a n smissio n of th e last b y t e . ? i n r e ceiv e r on ly mo de , set t he bit crcnext ju st af t e r t h e rece pt ion of t he secon d to la st da ta to p r e par e t h e spi to e n t e r in crc phase a t t he e nd o f t he r e cep t io n of the last data. crc calculation is froz en dur i ng the crc tr ans f er . 6 . aft e r th e t r an sf er of t h e la st b y t e or half w o rd , t he spi e n t e r s t he crc t r an sf er and chec k p hase . in f u ll d uple x mod e or r e ceiv er -o nly mo de , th e r e ceiv e d crc is com par ed to the s p i_rxcrc r v a lue . if the v a lue does not matc h, the crc err flag in spi_sr is set a n d a n int e r r upt can be g e n e r a te d wh en t h e errie bit in t he spi_ c r2 r e g i st er is set. note: when the spi is in sla v e mode , be careful to enab le crc c a lculation only when the c l oc k is stab le , that is , when the cloc k is in the stead y st at e . i f n o t, a wr on g crc ca lcu l a t ion ma y be done . in f a ct, the crc is s e nsitiv e to the sck s la v e input c loc k as soon as crc en is set, a nd t h is , wh at e v e r th e v a lu e of t h e spe bit . wit h high b i tr a t e f r equ encie s , be car e f u l wh en t r an sm itt i ng t h e crc . as th e n u mbe r of u s e d cpu cyc les has to be as lo w as possib le in the c rc tr ansf er phase , it is f o rbidden to call sof t w ar e f unct i on s in t he crc t r an sm ission se que nce t o a v o i d er ro rs i n th e last d a t a an d crc r e cept io n. i n f a ct , crcnext bit h a s t o b e wr it t e n b e f o r e th e en d of t h e tr an sm iss i on /r ec ep tio n of th e las t d a t a . f o r h i gh bit r a t e fr equ en cie s , it is a d vise d t o u s e t he dma m ode t o a v oid t h e de g r ad at ion of t h e spi sp eed p e r f o r ma nce du e to cpu acce sse s imp a ctin g t he spi b and wid t h . whe n t he stm3 2f2 0 x a n d stm 32f 21x ar e co nf igu r e d as sla v es and t h e nss har dw ar e mo de is used , t he nss p i n ne eds to b e k e p t lo w b e t w e en t h e d a t a pha se and t h e crc p hase . whe n t he spi is co nf igur ed in sla v e mo de with th e crc f e at ur e ena b l ed, crc ca lcu l at ion t a k e s p l ace e v en if a hig h le v e l is a p p lied on th e nss pin . th is ma y ha pp en f o r e x a m ple in case of a m u lt isla v e e n vir onm ent wher e t he comm u n icat ion m a ste r ad dr esse s sla v e s alt e r n ate l y . be tw een a sla v e de se lect ion ( h igh le v e l on nss) an d a ne w sla v e se lect ion ( l o w le v e l o n nss), th e crc v a lue sho u ld b e cl ear ed o n bot h ma ste r an d sla v e side s in or de r t o r e synchr oniz e th e mast er a n d sla v e f o r t heir resp ectiv e crc calcula t io n. t o c l ea r th e crc , f o llo w th e pr oc ed ur e be lo w: 1. disab le s p i (spe = 0) 2. clear the c rcen bit 3. se t t h e c rcen bit 4. enab le the spi (spe = 1) serial peripheral interface (spi) RM0033 670/1317 doc id 15403 rev 3 25.3.7 status flags th re e st at us f l ag s a r e pr o v id ed f o r th e a pplica t io n t o co mple te ly mon i to r t h e sta t e of t h e spi bu s. tx b u ff er empty fla g (txe) whe n it is se t, th is f l ag in dicat e s th at th e tx b u f f er is emp t y an d th e ne xt da ta t o be t r a n smit te d ca n be lo ade d int o t h e b u f f er . t he txe fla g is clea re d wh en wr it ing t o t he spi_dr register . rx b u ff er not e m pty (rxne) whe n set , t h is f l a g indica te s t hat t her e ar e v a lid r e ceiv ed dat a in t h e rx b u ff er . it is clear ed when spi_d r is read. bu s y f l ag this bsy flag is set and cleared b y hardw a re (wr i ting to this flag has no eff e ct). the b sy fla g ind i ca te s t h e st at e of th e co mm u n i ca tion la y e r o f th e s p i. when bsy is set, it indicates th at the spi is b u sy comm unicating. there is one e xception in ma ste r mod e / b i dir e ctio na l r e ceiv e mo de ( m str=1 and bdm=1 a nd bdoe=0) whe r e t h e bsy flag is k e pt lo w dur ing reception. th e bsy f l ag is u s e f u l t o de te ct th e end o f a t r ansf e r if th e so ft w a re w a nt s t o disab l e th e spi a nd en t e r halt mod e (o r disab l e t h e p e r i ph er a l clo c k) . th is a v oid s cor r upt in g th e last tr an sf er . f o r t h is , th e p r oce d u r e de sc r i be d be lo w m u s t b e str i c t ly re sp ect e d . the bsy flag is also useful to a v oid wr ite c o llis i ons in a m u ltimaster system. th e bsy fla g is se t wh en a t r a n sf er st a r t s , wit h t h e e x cep t ion of ma st er m ode / bid i re ct io nal r e ceiv e mo de ( m str=1 and bdm=1 a nd bdoe=0). it is c l ea re d: when a tr a n sf er is fin i sh ed ( e xcept in mast er m ode if t he comm u n icat ion is co nt in uo us) when t h e spi is d i sa b l e d when a mast er mo de f a u l t occur s ( m odf=1) whe n comm un icat ion is n o t co nt in uo us , th e bsy f l ag is lo w be tw ee n each com m u nicat i on . whe n comm un icat ion is co nt in uou s: in master mode , the bsy flag is k e pt hi gh dur i ng all the tr ansf ers in sla v e m ode , th e bsy f l ag g oes lo w f o r o n e spi clo c k cycle b e t w ee n ea ch t r a n sf e r note: do not use the bsy flag to handle each data tran smission or reception. it is better to use the txe and rxne flags instead. RM0033 serial periphe ral interface (spi) doc id 15403 rev 3 671/1317 25.3.8 disab ling the spi whe n a t r an sf er is t e r m inat ed , t h e a p p lica t io n can sto p th e comm u n icat ion b y d i sa b ling t he spi per i pher al. this is done b y clear i ng the spe bit. f o r some co nf igur at ions , disa b lin g th e spi an d en te r i ng t h e halt mod e while a t r an sf e r is ongoing can cause the cu rrent tr ansf er to be corr upted and/or the bsy flag might become unreliab l e . t o a v oi d an y o f t hose e f f e ct s , it is r e comm end ed t o r e spect t h e f o llo win g pr oced ure wh en d i sa b lin g t he spi : in master or sla v e full-dup le x mode (bi d imode=0, rxonl y = 0 ) 1. w a it until rxne =1 to receiv e the last data 2. w a it until txe=1 3. then w a it until bsy=0 4 . disa b le t he spi ( s pe=0) an d, e v e n t uall y , ent e r t h e ha lt mod e ( o r disab l e t h e pe r i ph er a l cloc k) in master or sla v e unidirec t ional trans m it-onl y mode (bidimode=0, rxonl y =0) or bidirectiona l transm it mode (bidimode=1, bidioe=1) afte r th e las t d a t a is w r itte n int o the s p i_ dr r e gist er : 1. w a it until txe=1 2. then w a it until bsy=0 3 . disa b le t he spi ( s pe=0) an d, e v e n t uall y , ent e r t h e ha lt mod e ( o r disab l e t h e pe r i ph er a l cloc k) in master uni directional re ceive-o n l y mode (mstr=1, bidimode=0, rxonl y =1) or bidirectiona l receive mode (mstr=1, bidimode=1, bidioe=0) this ca se m u st be m a n a g e d in a pa r t ic ula r w a y to en su re t h a t th e s p i d o e s no t init ia te a ne w tr a n sf er . t h e se qu en ce be lo w is v a lid only f o r sp i motorola configur ation (frf bit s e t to 0) : 1 . w a it f o r t h e se co nd t o last o c cu rr ence o f rxne=1 (n ?1 ) 2 . the n w a it f o r o ne spi cloc k cycle ( u sing a sof t w ar e loo p ) b e f o r e disab ling t h e spi (spe=0) 3. t h en w a it f o r th e las t rx ne=1 bef o re enter i ng the halt mode (or disab ling the pe r i phe r a l cloc k) whe n th e spi is co nf igur ed in t i mo de ( b it frf set t o 1) , t h e f o llo win g pr ocedu re h a s t o b e r e spe c t e d t o a v oid g ene r a t i ng an un de sir e d p u lse on nss wh en t he spi is disab l ed : 1. w a it f o r th e s e c o n d to la st oc cur r e n ce of rxn e = 1 (n -1 ). 2. disab le the sp i (spe = 0) in the f o llo wing windo w fr ame using a softw are loop: ? a f t e r a t le ast on e spi cloc k cycle , ? b e f ore t h e beg inn i ng of th e lsb da ta t r a n sf e r . note: i n master bidirectional receiv e mode (m str=1 and bd m=1 and bdoe=0), the bsy flag is k e pt lo w dur ing t r an sf er s . serial peripheral interface (spi) RM0033 672/1317 doc id 15403 rev 3 in sla ve rece ive-onl y m ode (mstr=0 , bidimode=0 , rxonl y =1) or bid i re ctional re ceive m ode (mstr= 0, bidimode=1 , bidoe=0) 1. y o u can disab l e the spi (wr i te spe=1) at an y time: the cu rrent tr ansf er w ill complete b e f o r e th e spi is e f f e ctiv ely dis a b l ed 2. then, if y o u w a nt to enter the halt mode , y ou m u st fi rst w a it until bsy = 0 bef o re en te r i ng t h e halt mod e (o r disa b lin g th e pe r i phe r a l cloc k) . 25.3.9 spi comm u nication using dma (direct memor y ad dressing) t o o per at e a t it s maxim u m spe ed, t h e spi n eed s t o b e f e d wit h th e dat a f o r t r an smission an d the data rec e iv ed on the rx b u ff er should be read to a v oid o v err un. t o f a cilitate the tr ansf ers , the spi f e atures a dma capab ility implementing a s i mple r equest/ac k n o w ledge protocol. a dma a c ce ss is r equ est ed when th e ena b l e bit in t h e spi _ cr2 r egist er is ena b l ed. se par a t e re que st s m u st be issued to t h e t x an d rx b u f f e r s (see f i gur e 26 1 an d fig u r e 26 2 ): in t r a n s m i ssio n , a dm a re qu es t is iss u e d ea ch tim e txe is se t to 1. the d m a th en wr ite s t o t he spi _dr r egist er ( t his clea rs th e txe fla g ) . i n r e cep t io n, a dma r e q uest is issued e a ch t i me rxne is set t o 1. th e dma th en re ad s t he spi _dr r egist er ( t his clea rs th e rxne f l ag) . whe n t he spi is used on ly t o t r an sm it da ta , it is po ssib le t o en ab le on ly t he spi tx dma cha nne l. i n t h is ca se , th e o v r fla g is set be ca use th e da ta r e ceiv e d ar e no t re ad . whe n t he spi is used on ly t o r e ceiv e da ta , it is po ssib le t o en ab le only t he spi rx dma cha nne l. i n t r an smission mo de , whe n th e dma h a s wr it te n all th e da ta t o be t r an sm itt e d ( f lag tci f is set in the dma_isr register), the bsy flag can be monitor ed to ensure that the spi com m u nicat i on is co mple t e . this is re qu ired t o a v oid cor r upt in g th e last t r an sm ission b e f o r e d i sa b lin g t he spi o r en te r i ng t h e st op m ode . the sof t w ar e m u st f i r s t w a it unt il txe=1 and then until bsy=0. note: d ur ing discontin uous comm unications , there is a 2 apb cl oc k per i od dela y betw een the wr ite oper ation to spi_dr and the bsy bit setting. as a cons equence , it is mandator y to w a it first until txe=1 and then unt il bsy=0 after wr iting the last data. RM0033 serial periphe ral interface (spi) doc id 15403 rev 3 673/1317 fi gu re 26 1. t r an smi ssi on us in g dm a figu re 26 2. rec e pt ion using dma 0xf1 tx bu ffer txe fl a g 0xf2 b s y fl a g 0xf 3 s et b y h a rdw a re cle a r b y dma wri t e s et b y h a rdw a re cle a red b y d ma wr it e s et b y h a rdw a re s et b y h a rdw a re s ck re s et ex a mple with cpol =1, cpha = 1 (write to s pi_dr ) mi s o /mo s i (o u t) data 1 = 0xf1 da ta 2 = 0xf2 data 3 = 0xf 3 sof tware configures the dma spi tx channel to send 3 data items and enables the spi dma write s to s pi _d r dma re qu e s t ignored b y the dma b ec aus e dma tcif fl a g s et b y h a rdw a re cle a r b y s oftw a re d ma writes data1 into spi_dr b y h a rdw a re dma writes data2 into spi_dr dma writes data3 into sp i _d r softwa re wa its un til bsy=0 (dma tr a n s fe r comp lete) dm a transfer is co mp le te (tcif=1 i n dma_ isr) software waits un til txe=1 dma tr a n s fe r i s compl e te b 0 b 1 b 2 b3 b 4 b 5 b 6 b 7 b 0 b 1 b 2 b3 b 4 b 5 b 6 b 7 b 0 b 1 b 2 b3 b 4 b 5 b 6 b 7 a i17 3 49 mi s o/ mo s i (in) data 1 = 0xa1 sof t war e co nf ig ur es the dm a s p i rx ch an ne l to re ceive 3 d a ta items a nd en ab le s th e s pi s ck data 2 = 0xa 2 da t a 3 = 0xa 3 ex a mple with cpol =1, cpha = 1 rxne fl a g rx bu ffer s et b y h a rdw a re (re a d from s pi_dr) 0xa1 0xa2 0xa 3 dma re qu e s t dma re ad s da ta3 from spi _ dr fl a g dma tcif s et b y h a rdw a re cle a r b y s oftw a re dma re a d from s pi _dr th e dma tra n sf er is complete (tcif=1 in dma_isr) dma reads data2 from sp i _ dr dma reads data 1 fr om sp i_dr (dma tr a n s fer comp lete) b 0 b 1 b 2 b3 b 4 b 5 b 6 b 7 b 0 b 1 b 2 b3 b 4 b 5 b 6 b 7 b 0 b 1 b 2 b3 b 4 b 5 b 6 b 7 cle a r b y dma r e a d a i17 3 50 serial peripheral interface (spi) RM0033 674/1317 doc id 15403 rev 3 dma capability with crc when spi comm unication is enab l ed wit h crc comm unication and dma mode , the t r a n smissio n and rece pt ion of t he crc at th e en d of com m unicat i o n ar e aut om at ic t h a t is without us ing the bit c rcne xt . af ter the crc rec e ption, the crc m u st be read in the spi _dr r e g i st er to clea r t he rxne f l ag . at th e end o f d a t a an d crc t r a n sf ers , t he crcerr f l ag in spi _ sr is set if cor r upt io n oc cu rs du r i ng t h e t r a n sf e r . 25.3.10 err o r fla g s master mode fault (modf) ma ste r mod e f ault occurs when t h e mast er d e vice h a s its nss pin p u lle d lo w (in nss h a r d w a re mo de) or ssi b i t lo w (in nss sof t w ar e mo de) , t h is au to mat i cally se ts th e modf b i t. mast er m ode f a u l t a f f e ct s t h e spi p e r i p her al in th e f o llo wing w a ys: th e m o df b i t is se t a n d an spi in te rr u p t is g e n e r at ed if th e erri e b i t is se t. the spe bit is clea re d. th is b l oc ks all out pu t f r o m th e de vice a nd disa b l e s t he spi interf ace . t h e m s t r bit is c l ea re d , t h u s f o r cin g th e de vice in to sla v e m o d e . use th e f o llo wing sof t w ar e se qu ence t o clear th e modf bit : 1. m a k e a r e a d o r w r ite ac ce ss to th e spi_ s r r e gist er wh ile th e m o df bit is s e t . 2. t h en wr it e to th e spi_ cr1 r e g i st er . t o a v oi d an y m u ltiple s l a v e conflicts in a sys tem compr i sing se v e r a l mcus , the nss pin m u st be pulled high dur i ng the modf bit clea r i ng sequence . the spe and mstr bits can b e re st or ed t o t h e i r or ig inal st at e af te r t h is cle a r i ng se que nce . as a se cu r i t y , h a r d w a re d oes not allo w th e se tt in g of t h e spe an d mstr b i t s while t h e modf bit is s e t. i n a sla v e d e vice th e modf b i t cann ot be set . ho w e v e r , in a m u lt ima ste r conf igu r at ion , t h e de vic e ca n b e in sla v e m o de with th is m o d f b i t se t. i n t h is c a s e , th e m o df bit in d i cat e s th at t h e r e m i ght ha v e bee n a m u lt ima s t e r co nf lict f o r syst e m con t r o l. an int e r r up t ro ut ine can be u s e d to reco v e r cle anly fr om t h is sta t e b y p e r f o r min g a re set o r re t u r n ing t o a de f a ult st at e . overrun cond ition an o v e r r u n co nd itio n oc cur s whe n th e m a st er d e v i ce h a s se nt d a ta b yte s an d th e sla v e d e vice has not clear ed t h e rxne b i t r e sult ing f r om t he pr e viou s d a t a b yt e t r ansmit t e d . wh en a n o v e r r u n co nd itio n occ u r s: t he o v r bit is set and an int e r r up t is gen er a t e d if t h e errie bit is set . in this cas e , the rec e iv er b u ff er contents will not be updated with th e ne w l y rec e iv ed data fr om t h e m a s t e r d e vice . a r e ad fr om the s p i_ dr r e gist er r e t u r n s th is b yte . all oth e r sub s e q u ent ly t r a n smit te d b y t e s ar e lost . clea r ing t he o v r bit is d o n e b y a r ead f r o m th e spi _dr r egist er f o llo w ed b y a rea d acce ss t o t he spi _sr r e g i st er . RM0033 serial periphe ral interface (spi) doc id 15403 rev 3 675/1317 crc err o r th is f l ag is used t o v e r i f y th e v a lidit y o f t h e v a lue r e ceiv ed wh en t he crcen bit in t h e spi_cr1 register is set. the crc err flag in th e spi_ s r re gist er is se t if th e v a lue r e ceiv e d in th e shif t r egist er d oes no t ma tch t h e r e ceiv er spi _ rxcrcr v a lue . ti mode frame f o rm at err o r a ti m ode f r a m e f o r m at e r r o r is de te ct e d wh en a n nss pu lse o c cu rs d u r i n g an o ngo ing com m u nicat i on wh en t h e spi is act i ng in sla v e m ode and con f igur ed t o con f o r m t o th e ti m o d e pr ot oc ol. wh en t h is er ro r oc cu rs , t h e t i f r f e fla g is se t in the sp i_ sr r e g i st er . t h e spi is no t disab l ed when an er ro r o ccu rs , t h e nss pul se is ign o re d, a nd th e spi w a its f o r t he n e xt nss p u lse be f o re st ar t i ng a n e w tr ansf e r . t he da ta ma y be cor r upt ed sin c e t h e err o r de te ct ion m a y r e su lt in the lo st o f two d a t a b yte s . th e ti frfe fla g is clea re d wh en spi _sr r e g i st er is r ead . i f t h e b i t erri e is set , a n in te rr u p t is ge ner at ed on th e nss er ro r de te ct io n. i n t h is ca se , th e spi shou ld be d i sa b l ed b e cause d a t a con s ist e n c y is no m o r e gu ar a n t eed and co mm un ica t ions shou ld b e re init iat e d b y th e ma ste r wh en t h e sla v e spi is r e - e n a b le d. fi gu re 26 3. ti mode f r ame f o r m at e r r o r d e te ct io n 25.3.11 spi interrupts a i - 3 " ) . - / 3 ) i n p u t . 3 3 o u t p u t 3 # + o u t p u t t r i g g e r s a m p l i n g t r i g g e r s a m p l i n g t r i g g e r s a m p l i n g $ / . 4 # ! 2 % - ) 3 / o u t p u t o r - 3 " / 5 4 , 3 " / 5 4 - 3 " ) . , 3 " ) . - 3 " / 5 4 , 3 " / 5 4 t r i g g e r s a m p l i n g t r i g g e r s a m p l i n g t r i g g e r s a m p l i n g t r i g g e r s a m p l i n g , 3 " ) . $ / . 4 # ! 2 % 4 ) & 2 & % t a b l e 98 . spi int e rr upt r e que st s inter r upt e v ent e vent fla g enab le contr o l bit t r ansmit b u ff er empty flag txe t xeie recei v e b u ff er not empty flag rxne rxneie maste r mod e f ault e v ent modf errie ov e r r un error o vr crc error fl ag crcerr ti frame f o r m a t error t ifrfe e rrie serial peripheral interface (spi) RM0033 676/1317 doc id 15403 rev 3 25.4 i 2 s functi onal description 25.4.1 i 2 s g e neral description th e b l oc k d i ag r a m of th e i 2 s is sho w n in fig u r e 264 . figu re 26 4. i 2 s b l oc k dia g ra m th e spi cou l d fu nctio n as an a udio i 2 s int e r f a c e wh en t he i 2 s capability is enab led (b y se ttin g th e i2 smo d bit in th e spi_ i 2 s cf gr r e g i ste r ) . th is inte r f ac e us es alm o st th e sam e pins, flags and interrupts as the spi. tx buffer shift register 16-bit communication rx buffer 16-bit mosi/ sd master control logic miso spi baud rate generator ck i2smod lsb first lsb first spe br2 br1 br0 mstr cpol cpha bidi mode bidi oe crc en crc next dff rx only ssm ssi address and data bus control nss /ws bsy ovr modf crc err ch side txe rxne i 2 s clock generator mck i2s_ c k i2s mod i2se ch datlen len ckpol i2scfg i2sstd mckoe odd i2sdiv[7:0] [1:0] [1:0] [1:0] udr i2sxclk ai14748 RM0033 serial periphe ral interface (spi) doc id 15403 rev 3 677/1317 th e i 2 s sha r es t h re e commo n pin s wit h th e spi: sd: ser i a l dat a ( m ap ped on t he mo si pin ) t o tr ansmit or r e ceiv e t h e t w o t i me- mu ltip lexed d a t a ch an nels (in simp le x m ode only) . ws: w o r d select ( m a ppe d on t h e nss pin) is t he da t a co nt ro l sig nal ou tp ut in mast er mo de an d inp u t in sla v e mod e . ck: ser i a l cloc k (m app ed o n th e sck pin ) is t h e se r i al cloc k o u t p u t in ma st er mod e an d se r i al cloc k i npu t in sla v e mod e . an a ddit i on al pin cou l d be u s e d when a mast er cloc k out p u t is ne ede d f o r some e x t e r n a l audio de vices: mck: ma st e r clo c k ( m ap pe d se pa r a t e ly) is used, wh en t h e i 2 s is con f ig ur ed in ma st er m o d e ( a n d wh en th e m c k o e bit in th e spi_ i 2 spr re gis t e r is se t) , t o ou tp ut th is ad dit i on al clo c k g ene r a t e d a t a p r e c o n f i gur ed f r equ en cy r a t e eq ua l t o 25 6 f s , wh er e f s is t h e a u d i o sa mplin g f r eq ue ncy . th e i 2 s u ses its o w n c l oc k ge n e r a to r t o pr od u ce th e co mm u n i cat i on c l oc k wh en it is s e t in ma ste r mod e . th is cloc k gen er a t o r is a l so th e sour ce of t h e m a ste r cloc k out pu t . t w o a ddit i on al re gist er s ar e a v ailab l e in i 2 s m ode . one is link e d t o th e clo c k g ene r a t o r con f ig ur a t io n spi_ i 2 spr an d t he ot he r on e is a g e n e r i c i 2 s co nf igur at ion r egi st er spi _i 2scfgr (a udi o st an dar d, sl a v e/ ma st e r mod e , da ta f o r m a t , pac k e t f r a m e , cloc k po la r i ty , e t c. ). t h e spi _c r1 re gis t e r a n d all c rc re gis t e r s ar e no t u s e d in th e i 2 s m ode . lik e wise , th e ssoe bit in t he spi_ c r2 r e g i st er and th e modf an d crcerr bit s in th e spi _ sr ar e no t us ed . th e i 2 s use s t he same spi re giste r f o r d a t a tr ansf e r ( spi_ d r) in 16- bit wid e mod e . 25.4.2 suppor ted audio pr otocols th e t h r ee- line b u s ha s t o han dle o n ly a u d i o dat a g ene r a lly tim e - m ult i ple x e d on t w o cha nne ls: t he r i g h t cha n n e l an d th e lef t cha n n e l. ho w e v e r t h e r e is on ly on e 16 -b it r egist er f o r t h e t r a n smissio n or t h e re ce pt ion. so , it is up t o t h e sof t w ar e t o wr ite in to t h e dat a r egist er th e ad eq u a t e v a lu e co rr es po nd in g to th e co ns ide r e d ch an n e l s i de , o r t o re ad t h e d a t a fro m t h e d a t a re gist er a nd t o ide n t i fy th e cor r esp ond ing cha nne l b y ch ec king t h e chside bit in t h e spi_ s r re giste r . ch ann el l e f t is alw a ys se nt f i rst f o llo w e d b y t he ch ann el r i ght ( c hsi d e h a s n o mea n in g f o r t he pcm pr ot ocol) . f o ur d a t a an d pa c k e t f r a m es ar e a v a ilab l e . dat a ma y be sen t wit h a f o r m a t o f : 16 -b it da ta p a c k e d in 16 -b it f r ame 16 -b it da ta p a c k e d in 32 -b it f r ame 24 -b it da ta p a c k e d in 32 -b it f r ame 32 -b it da ta p a c k e d in 32 -b it f r ame whe n u s in g 1 6 - b it da ta e xt e n ded on 32 -b it p a c k e t, t h e f i rst 16 bit s (msb) ar e t h e sign ifican t b i ts , t he 1 6 -b it l s b is f o rced t o 0 wit hou t a n y ne ed f o r so ft w a re a c t i on or dma re que st (o nly o ne r ead /wr i t e op er a t io n) . th e 24 -b it an d 32 -bit da ta f r a m es nee d t w o cpu r ead o r wr it e ope r a t i on s t o / f r o m t h e spi _dr o r t w o dma ope r a t i on s if th e dm a is pr ef er red f o r th e ap plicat ion . f o r 24 -b it da ta f r a m e spe c if ically , t h e 8 non sig n if icant b i ts a r e e xte nde d t o 32 b i t s wit h 0 - b i ts ( b y h a r d w a re) . fo r all d a t a fo rm at s an d commu n icat ion st an dar ds, t h e m o st sign ifican t b i t is a lways sen t f i rst (msb fi rst) . th e i 2 s int e rf ace supp or t s f o u r au dio sta n d a rd s , co nf igur ab le using t h e i 2 sst d [ 1 : 0 ] an d pcmsync bits in the spi_i2sc f gr register . serial peripheral interface (spi) RM0033 678/1317 doc id 15403 rev 3 i 2 s phillips standar d f o r t h is st an da rd, t he ws sig nal is used t o ind i ca te w h ich c h a n n e l is b e i ng tr a n s m itte d. it is ac tiv a te d on e ck c l oc k cyc le be f o re t h e fir s t bit (m sb) is a v a ilab l e . figu re 26 5. i 2 s ph il l i p s pr o t oc ol w a vef or ms (1 6/ 32- bi t f ull ac cura c y , cpol = 0 ) data are latched on the f a lling edge of ck (f or the tr ans m itter) and are read on the r i sing e dge ( f or t h e r e ceiv e r ) . th e ws sign al is al so la tche d on t h e f a lling ed ge o f ck. figu re 26 6. i 2 s phi lli ps s t a n d a r d wa ve f o rm s (2 4- bi t fram e w i t h cpo l = 0) th is mo de n eed s t w o wr it e or rea d op er a t io ns t o /f ro m th e spi_ d r. i n tr ansmission mo de : if 0 x 8 eaa3 3 ha s t o be sen t ( 24- bit ) : ms b ls b msb ck ws sd cha nnel left channel right may be 16 -bit, 32-bit tran smiss i on reception ck ws sd channel le ft 32-bit channel right ms b lsb 8-bit remain ing 0 forced 24-bit d ata t r an smi ssion reception RM0033 serial periphe ral interface (spi) doc id 15403 rev 3 679/1317 fi gu re 26 7. t r an smi t t i n g 0x8 eaa33 i n re ce pt ion mo de : if data 0x8eaa33 is receiv ed: fi gu re 26 8. rec e i v i ng 0x 8eaa33 figu re 26 9. i 2 s ph il l i p s st anda r d ( 16- bi t e x t e n d ed t o 3 2 - b i t pac k et f r ame w i t h cpol = 0 ) whe n 16 -bi t da ta f r a m e e xt e n ded t o 32 -b it cha nne l f r a m e is se lecte d du r i ng t h e i 2 s con f ig ur a t io n ph ase , on ly o ne access t o spi _dr is r e q u ir ed. the 16 r e ma ining b i ts ar e f o r ced b y ha rd w a r e t o 0x00 00 t o e xt end t h e dat a t o 32 -b it f o r m at . i f t h e dat a t o t r an sm it or th e re ceiv ed d a t a ar e 0x76 a3 (0 x76a3 000 0 e xt end ed t o 32 -b it) , t h e o per at ion sho w n in fig u re 270 is re qui red . 0x8eaa 0x33xx only the 8 msbs are sent to complete the 24 bits first wr ite to data r egister second write to data register 8 lsb bits have no meaning and could be anything 0x8eaa 0x3300 only the 8msb are right f i rst read from data register second read from data register the 8 lsb will always be 00 ck ws sd channel left 32-bit channel right msb lsb 16-bit remaining 16-bit data 0 forced transmission reception serial peripheral interface (spi) RM0033 680/1317 doc id 15403 rev 3 fi gu re 27 0. ex ampl e f o r tr a n s m is sio n , ea ch t i me a n m sb is wr itte n to spi _d r, the txe fla g is se t an d its int e r r up t, if allo wed , is g e n e r ate d to lo ad s p i_ dr w i th th e ne w v a lu e to se nd . th is tak e s p l ace e v en i f 0x00 00 h a v e n o t y e t b een sen t b e cause it is do ne b y h a r d w a re . f o r r e cept io n, t h e rxne f l ag is set a n d it s in te rr u p t , if allo w e d, is ge ner at ed whe n th e fir s t 16 msb half-w ord is receiv ed. i n t h is w a y , mor e t i me is p r o v ide d be tw een tw o wr it e o r re ad o per at ions , which pr e v en ts u nde rr u n or o v e r r u n co ndit i on s ( d e pen ding on t he d i rect ion o f t h e d a t a tr ansf e r ) . msb j u stified s t andar d f o r t h is s t a n d a r d , th e ws sig n a l is g e n e r a te d a t th e sa m e t i me as t h e firs t da ta bit , wh ich is th e msb i t. figu re 27 1. m s b j u st if ied 16 -bit o r 3 2 - b it fu ll-a cc urac y le ngt h with cpol = 0 data are latched on the falling edge of ck (for transmitter) and are re ad on the rising edge (for the receiver). 0x76a3 only one access to spi_dr msb lsb msb ck ws sd channel left channel right may be 16-bit, 32-bit transmission reception RM0033 serial periphe ral interface (spi) doc id 15403 rev 3 681/1317 figure 2 7 2 . ms b j u s t i f ie d 2 4 - b it fra m e le ngt h wi th cp ol = 0 fi gu re 27 3. m s b j u st if i e d 16 -bi t e x ten d ed t o 32- bi t pa c k et f r ame w i t h cpol = 0 lsb just ified sta ndar d th is st and ar d is simila r t o th e msb j u stif ied st an dar d ( no dif f er ence f o r th e 16- bit an d 32- bit full-accur a c y f r ame f o r m ats). fi gu re 27 4. l s b j u st if i e d 16 -bi t or 3 2 - b i t fu ll -a cc urac y wi th cpol = 0 ck ws sd channel left 32-bit channel right msb lsb 8-bit remaining 0 forced 24-bit data transmission reception ck ws sd channel left 32-bit channel right msb lsb 16-bit remaining 0 forced 16-bit data transmission reception msb l sb msb ck ws sd chan nel left channel right may be 16-bit, 3 2 -bit transmissio n reception serial peripheral interface (spi) RM0033 682/1317 doc id 15403 rev 3 figure 2 7 5 . ls b j u s t i f ie d 2 4 - b it fra m e le ngt h wi th cp ol = 0 i n tr ansmission mo de : i f da ta 0 x 347 8ae ha v e to b e t r ansmit t e d , t w o wr it e ope r a t i on s t o t he spi _dr r egist er ar e re qu ired fr om sof t w ar e or b y dma. the o per at ion s ar e sho w n belo w . fi gu re 27 6. o p er ati o n s requ ir ed to t r an smi t 0x 347 8ae i n re ce pt ion mo de : if d a t a 0x3 4 7 8 ae a r e r e ceiv ed , t w o s u cc es siv e re a d op er a t io ns fr om spi_ dr ar e re qu ired on ea ch rxne e v ent . figure 277. operations required to receive 0x3478ae ck ws sd channel left 32-bit channel right msb lsb 24-bit remaining 0 f o r c e d 8-bit data transmission reception 0xxx34 0x78ae f i rst write to dat a regist er secon d write to da ta register only the 8 lsb bits of the half-word are sig nifica nt. whatever the 8 ms bs a field of 0x00 is forced instea d conditioned by txe = ?1? con d itioned by t x e = ?1? 0x0034 0x78ae first read from da ta register second read from d a ta reg i ster only the 8 lsb b i ts of the ha lf-word are significant. what ever the 8 msbs, a field of 0x00 is forced instead condit i oned by r x n e = ?1? condition ed by rxne = ?1? RM0033 serial periphe ral interface (spi) doc id 15403 rev 3 683/1317 fi gu re 27 8. l s b j u st if i e d 16 -bi t e x ten d ed t o 32- bi t pa c k et f r ame w i t h cpol = 0 whe n 16 -bi t da ta f r a m e e xt e n ded t o 32 -b it cha nne l f r a m e is se lecte d du r i ng t h e i 2 s con f ig ur a t io n ph ase , on ly o ne access t o spi _dr is req u ir ed. the 16 r e ma ining b i ts ar e f o rce d b y h a r d w a re to 0x 00 00 to e x te nd th e d a t a t o 3 2 - b it f o r m a t. in th is ca se it co rr es po n d s t o t he h a lf -w ord msb . if th e da ta to t r a n sm i t o r th e re ce iv ed d a t a ar e 0x 76 a3 (0 x0 0 0 0 7 6 a3 e xt e n d e d to 3 2 - b it), th e op er a t io n sh o w n in fig u r e 279 is required. fi gu re 27 9. ex ampl e in tr a n s m is sio n mo d e , w h e n tx e is ass e r t ed , th e ap plic at ion h a s to wr it e th e da ta to b e tr an sm itt e d ( i n th is c a se 0 x7 6 a 3 ) . th e 0x 00 0 fie l d is tr a n s m itte d firs t ( e x t e n s i on o n 32 -b it) . txe is a s se r t ed aga in as so on as t he ef f e ct iv e dat a ( 0 x76a3 ) is sen t o n sd . in re ce p tio n m o de , rx ne is as se r te d as so on a s th e s i gn ific an t h a l f-wo rd is re ce iv ed ( a n d n o t t h e 0x000 0 f i eld) . i n th is w a y , mo re t i me is pr o v id ed be tw een t w o wr it e o r re ad ope r a t i on s t o p r e v ent u n d e rr un o r o v err un cond it ions . pcm s t andar d f o r t h e pcm st a nda rd , t her e is n o ne ed t o use chan ne l-side in f o r m a t io n. the t w o pcm mo de s ( s h o r t a nd lon g f r ame ) ar e a v ailab l e a nd con f ig ur a b le u s in g t he pcmsync bit in spi _i 2scfgr. ck ws sd chan nel left 32-bit channel right ms b lsb 16-bit remaining 0 f o r c e d 16-bit data tran smissio n reception 0x 76a3 only one access to spi_dr serial peripheral interface (spi) RM0033 684/1317 doc id 15403 rev 3 fi gu re 28 0. pcm st and a r d w a vef o rms (1 6- bit ) f o r lon g f r ame synchr o n i za tio n , th e ws sign al asse r t io n t i me is f i x ed 1 3 bit s in ma ste r mo de . f o r shor t f r ame synchroniz a t ion , the w s sy nc hronization signal is only one cycle long. fi gu re 28 1. pcm st and a r d w a vef o rms (1 6- bit e x te nde d to 32 -bi t p a c ket fra m e) no te : f or b o th m o de s (m a ste r an d sla v e ) an d f o r bo th sy nc hr on iza t io ns (s ho r t an d lon g ) , th e n u mbe r of bi ts b e t w e en tw o co nsecut iv e piece s o f da ta (a nd s o two sy nc hr on iza t io n sig n a l s) n eed s t o be specif ied ( d a t l e n an d chlen b i t s in th e spi_ i 2 s cf gr r e g i st er ) e v e n i n sla v e mo de . 25.4.3 cloc k g enerator th e i 2 s bit r a t e det er mine s t h e d a t a f l o w on th e i 2 s da ta lin e an d th e i 2 s cloc k sig nal fr eq ue n cy . i 2 s b i t r at e = n u mbe r of bit s p e r cha nne l n u m ber o f cha nne ls sa mplin g au dio f r e que ncy f o r a 1 6 -b it a udio , lef t a nd r i g h t cha nne l, t h e i 2 s bit r at e is ca lcu l at ed a s f o llo ws: i 2 s bit r a t e = 16 2 f s msb lsb msb ck ws sd 16-bit ws up to 13-bit sh ort frame long frame ms b ck ws sd 16- bit ws up to 13-bit short frame lon g frame ls b RM0033 serial periphe ral interface (spi) doc id 15403 rev 3 685/1317 it will be: i 2 s bit r a t e = 32 x 2 x f s if th e pa c k e t le ng th is 32-bit wide . figu re 28 2. a udio sa mplin g f r e quen c y def i nit i on whe n t he ma st er mod e is con f ig ur ed, a sp ecif ic act i on n eed s t o be t a k en t o pr ope r l y p r o g r a m t h e lin ear divide r in or der to co mm unica te wit h t he de sir e d a u d i o fr eq uen cy . figu re 28 3. i 2 s c l oc k g e ner a t or ar c hi t ec tu re 1. where x could be 2 or 3. fig u r e 28 2 pr esent s th e co mm un ica t io n cloc k a r chit e c t u r e . t o a c h i e v e h i gh- qu alit y a udio pe rf or m a n ce , t h e i 2 s xcl k c l oc k so u r ce ca n be e i t her t h e pll i 2 s o u t put ( t hr oug h r divisi on f a ct or ) or a n e xt e r n al cloc k ( m a ppe d to i2 s_cki n pin). th e au dio samp ling f r equ ency ma y be 96 khz, 48 khz, 44 .1 khz, 32 khz, 22 .0 5 khz, 1 6 khz, 1 1 . 025 khz o r 8 khz (o r an y ot her v a lue wit hin t h is r a n g e ) . i n o r de r t o re ach t he d e sire d fr eq uen cy , t h e lin ea r divide r ne eds t o be pr og r a mme d accor d ing t o t h e f o r m ulas belo w: whe n t he ma st er clo c k is gen er a t e d (m ck o e in th e spi _ i2 spr re gist er is se t) : f s = i2 sxcl k / [( 16 *2) * (( 2*i2 sdi v )+ odd ) *8 )] wh en th e ch an n e l fr am e is 16 -b it wide f s = i2 sxcl k / [( 32 *2) * (( 2*i2 sdi v )+ odd ) *4 )] wh en th e ch an n e l fr am e is 32 -b it wide whe n t he ma st er clo c k is disab l ed ( m ck oe bit cle a r ed) : f s = i2 sxcl k / [( 16 *2) * (( 2*i2 sdi v )+ odd ) ) ] wh e n th e cha n n e l f r a m e is 1 6 - b it wid e f s = i2 sxcl k / [( 32 *2) * (( 2*i2 sdi v )+ odd ) ) ] wh e n th e cha n n e l f r a m e is 3 2 - b it wid e ta b l e 9 9 pr o vides e xamp l e pr ecision v a lu es f o r dif f er ent clo c k con f ig ur atio ns . not e : o th er con f ig ur a t ions ar e possib l e th at allo w o p t i m u m cloc k p r e c isio n. 16-bit or 32-bit left channel 16-bit or 32-bit right channel sampling point sampling point 3 2 -bits or 64-b i ts f s f s : audio sampling frequency 8-bit di vider + linear ck odd i2sd iv[7:0] i2sxclk chl e n i2sm o d reshaping stage d ivider by 4 div2 1 0 m cko e mckoe mck 0 1 serial peripheral interface (spi) RM0033 686/1317 doc id 15403 rev 3 25.4.4 i 2 s master mode th e i 2 s can be co nf igur ed in m a ste r m ode . th is mea n s th at t he se r i al cloc k is g ene r a t e d on t h e ck p i n as w e ll as t h e w o r d select sign al ws . mast er cloc k (mck) ma y be o u t put or no t, th an ks to th e m c k o e bit in th e spi_ i 2 spr re gis t e r . t a b l e 99. a udio f r equ e nc y pr ecis i on ( f or pllm vco = 1 m hz or 2 m hz) (1) master cl o ck ta r g e t f s (hz ) da ta fo r m a t plli2sn p lli2sr i2sdiv i2s o dd real f s (hz) err o r di sab l e d 8 000 1 6 -bit 19 2 2 18 7 1 80 00 0.00 00% 3 2 -bit 19 2 3 62 1 8 0 0 0 0 .0000% 160 00 1 6 -bit 19 2 3 62 1 1600 0 0 .00 00% 3 2 -bit 25 6 2 62 1 1600 0 0 .00 00% 320 00 1 6 -bit 25 6 2 62 1 3200 0 0 .00 00% 3 2 -bit 25 6 5 12 1 3200 0 0 .00 00% 480 00 1 6 -bit 19 2 5 12 1 4800 0 0 .00 00% 3 2 -bit 38 4 5 12 1 4800 0 0 .00 00% 960 00 1 6 -bit 38 4 5 12 1 9600 0 0 .00 00% 3 2 -bit 42 4 3 11 1 9 601 4.4921 9 0 .01 51% 220 50 1 6 -bit 29 0 3 68 1 2 204 9.8769 5 0 .00 06% 3 2 -bit 30 2 2 53 1 2 205 0.2343 8 0 .00 11% 441 00 1 6 -bit 30 2 2 53 1 4 410 0.4687 5 0 .00 11% 3 2 -bit 42 9 4 19 0 4 409 9.5078 1 0 .00 11% 19 2000 1 6 -bit 42 4 3 11 1 1 920 28.984 4 0 .01 51% 3 2 -bit 25 8 3 3 1 1 919 64.281 3 0 .01 86% enab led 8 000 do n't care 25 6 5 12 1 8 0 0 0 0 .0000% 16000 do n't care 21 3 2 13 0 1 6000.6005 9 0 .0038% 32000 do n't care 21 3 2 6 1 3 2001.2011 7 0 .0038% 48000 do n't care 25 8 3 3 1 4 7991.0703 1 0 .0186% 96000 do n't care 34 4 2 3 1 9 5982.1406 3 0 .0186% 22050 do n't care 42 9 4 9 1 2 2049.7539 1 0 .0011% 44100 do n't care 27 1 2 6 0 4 4108.0742 2 0 .0183% 1. th is table gives only exampl e value s for dif f erent clock configu r ations. othe r config urations allowing optimum clock precision are possible. RM0033 serial periphe ral interface (spi) doc id 15403 rev 3 687/1317 pr ocedure 1. se lec t t h e i 2 sd iv[7 :0 ] b i ts in th e spi_ i 2 spr re gis t er t o de fin e th e s e r i a l c l o c k ba u d r a t e t o r each t h e p r op er a u d i o sa mple f r equ en cy . th e odd b i t in t h e spi _i 2spr re gist er a l so h a s to b e de fin ed. 2 . sele ct th e ckpo l bit to d e f i ne t h e st ea dy le v e l f o r t he comm u n icat ion cloc k. se t t h e mck o e bit in t h e spi_ i 2spr re giste r if t h e ma st er cloc k mck ne ed s t o be pr o vid ed t o t he e xt e r nal d a c/ adc au dio comp one nt (t he i 2 sdi v a nd odd v a lue s sho u ld be comp ut ed d epe ndin g on t h e st at e of th e mck o u t p u t , f o r mo re d e t a ils ref e r to sect ion 2 5 . 4 . 3: cloc k ge ner at or ). 3. se t th e i 2 sm o d b i t in spi _i 2sc f g r to ac tiv a te the i 2 s fu nct i ona litie s and choo se t h e i 2 s st and ar d th ro ugh th e i 2 sstd[1 : 0 ] a nd pcmsync bit s , th e da ta leng th th ro ugh t h e d a t l en [1 :0] b i ts an d th e n u m b er o f b i ts pe r ch an n e l b y c o n f ig ur in g th e chl en bit . sele ct also t he i 2 s m a s t er m o de a n d d i re ct ion ( t r a ns m i tte r or re ce iv er ) th ro ug h th e i2 scfg [1 :0 ] b i ts in th e spi_ i 2 s cfgr re g i ste r . 4. if needed, s e lect all th e potential interr uption sour ces and the dma capabilities b y wr itin g t he spi_ c r2 r e g i st er . 5. t h e i 2 se b i t in spi _i2 s cf g r r e gist er m u st be s e t . ws and ck ar e co nf igu r e d in out p u t m ode . mck is also an o u t put , if t he mck o e b i t in spi_i2spr is set. t r ansmi ssion s e quence th e t r an smi s sion seq u e n ce be gins wh en a h a lf -w or d is wr it te n int o t he tx b u ff e r . assume dly , th e f i rst d a t a wr it t e n in to t h e tx b u f f er cor r e spon d to t h e ch ann el le ft da ta . wh en d a t a ar e tr an sf er re d fr om t h e t x b u f f e r t o th e s h if t r e g i st er , t xe is se t a n d da ta co rr es po nd in g to th e ch an ne l r i gh t h a v e t o be wr it te n into t h e t x b u ff e r . th e chs ide flag in dicat e s wh ich ch ann el is t o be t r a n smit te d. it has a me anin g wh en t h e t x e f l ag is se t b e cause t h e chside fla g is u pda t ed when txe g oes hig h . a f u ll fr a m e h a s t o be co nside r ed a s a l e f t cha nne l dat a t r an sm ission f o llo w e d b y a rig h t cha nne l dat a t r an sm issio n . i t is no t po ssib le t o ha v e a pa r t ial f r am e wh er e on ly t he le ft cha nne l is sent . th e da ta h a lf -w or d is p a r a llel load ed in to t h e 16- bit sh ift re gist er d u r i ng t h e fir s t bit tr an sm iss i on , an d th en s h ift e d o u t, s e r i a lly , to t h e m o si/sd p i n, m sb fir st . th e txe fla g is se t a fte r ea ch tr a n s f er fr om t h e tx b u ff er to th e sh ift r e g i st er an d an in te rr u p t is g e n e r at ed if t h e t x ei e bit in th e spi _ cr2 r egist er is se t . f o r mo re d e t a ils abo ut t h e wr it e op er a t ions dep en ding o n t he i 2 s st and ar d mod e select ed, re f e r to sect ion 2 5. 4. 2: supp or t ed au dio p r o t o c o l s ). t o ensur e a con t in u ous au dio da ta tr a n smission, it is man dat or y t o wr it e th e spi_ d r wi th t h e n e xt d a t a to tr a n smit b e f o r e t he en d of th e curr en t t r an sm issio n . t o s witc h off the i 2 s , b y clear i ng i2se, it is mandator y to w a it f o r txe = 1 and bsy = 0. rece ption se quence th e o per at ing m ode is th e same as f o r t h e t r ansmission mod e e xcep t f o r t he p o int 3 (r ef er to th e pr oc ed ur e d e sc r i be d in se ct ion 2 5. 4. 4: i 2 s mast er m ode ), wh er e t he conf ig ur a t io n sho u ld set th e mast er r e cep t io n mo de t h r oug h t he i 2 scfg[ 1 : 0 ] bit s . wh at e v e r th e da ta o r c h a n n e l le ng th , the a u d io d a t a ar e re ce iv ed b y 1 6 - b it p a c k e ts . th is m e a n s th at e a ch t i me th e r x b u ff e r is full, th e rxne f l ag is se t and an int e r r upt is ge ne r a t e d serial peripheral interface (spi) RM0033 688/1317 doc id 15403 rev 3 if th e rxnei e b i t is se t in spi _cr2 r e g i st e r . de pe ndin g on t h e d a t a an d ch an nel le ngt h con f ig ur a t io n, t he aud io v a l ue r e ceiv e d f o r a r i g h t or lef t chan nel ma y r e sult f r om on e or t w o re ce pt ion s in to t h e rx b u ff er . clear ing the rxne bit is perf o r m ed b y r ead ing t h e spi _dr r e g i st er . chside is up da te d af te r ea ch rece pt ion. it is sen s it iv e t o t he ws sign al ge ner at ed b y t h e i 2 s cell. f o r mo re d e t a ils abo ut t h e rea d op er a t io ns dep end ing o n th e i 2 s st an da r d m o de s e le cte d , re f e r to sect ion 2 5. 4. 2: supp or t ed au dio p r o t o c o l s . i f da ta a r e re ceiv ed while t he pr e v iou s ly r e ceiv e d d a t a ha v e n o t b een r e a d y e t, an o v e r r u n is ge n e r a te d an d th e o v r flag is se t. if th e erri e b i t is se t in t h e spi _cr 2 re gis t e r , a n in te rr u p t is ge ner at ed t o ind i ca te t h e er ror . t o s witc h off the i 2 s , sp ec ific a c t i on s ar e re qu ire d to e n s u r e th at th e i 2 s completes the t r a n sf e r cycle pr op er ly wit h o u t init iat i ng a n e w da ta t r a n sf e r . th e se qu ence de pe nds on t h e con f ig ur a t io n of th e da ta a nd cha nne l l eng th s , a nd o n th e aud io pr ot ocol mo de sele ct ed . i n the case of : 16-bit da ta l eng th e x t e nde d on 3 2 - b it cha n n e l leng th (d a t len = 00 an d chl e n = 1 ) using t h e lsb ju stif ied m ode ( i 2sstd = 10 ) a) w a it f o r t he secon d to last rxne = 1 ( n ? 1) b) the n w a it 17 i 2 s cloc k c ycles (us i ng a soft w a re loop) c) d i sab l e the i 2 s (i2se = 0) 16 -b it da ta le ngt h e x t e n ded o n 32 -bit ch an nel len g t h (d a tlen = 00 an d chl e n = 1 ) in msb justified, i 2 s or pcm modes (i2sstd = 00, i2sstd = 01 or i2sstd = 11, re spect i v e ly) a) w a it f o r the las t r x ne b) the n w a it 1 i 2 s cloc k cycle (us i ng a so ft w a re loop) c) d i sab l e the i 2 s (i2se = 0) f o r all ot he r comb inat ion s o f d a tl en a nd chl e n, what e v e r t he au dio mo de sele ct e d t h ro ug h th e i 2 sstd b i ts , car r y out th e f o llo wing sequ en ce t o s witch of f th e i 2 s: a) w a it f o r t he secon d to last rxne = 1 ( n ? 1) b) the n w a it one i 2 s cl o c k c yc l e ( u si ng a so ft w a re l o op) c) d i sab l e the i 2 s (i2se = 0) note: t he bsy flag is k e pt lo w dur i ng tr ansf ers . 25.4.5 i 2 s sla ve mode f o r t h e sla v e co nf igu r at ion , t he i 2 s ca n be co n f ig ur ed in tr a n s m issio n or re ce p t io n m o de . th e op er a t in g mod e is f o llo wing m a inly t he same r u les as d e scr ibed f o r th e i 2 s master con f ig ur a t io n. in sla v e mod e , t her e is n o cloc k t o b e gen er a t e d b y t he i 2 s in te rf ace . t he cloc k an d ws signa ls a r e in put fr om t h e e xte r n a l m a ste r conn ect ed t o t he i 2 s i n te rf ac e . th er e is t h e n no n eed , f o r t h e user , t o conf ig ure th e clo c k. the configur ation s t eps to f o llo w are listed belo w: 1 . set th e i2 smod bit in th e spi _ i2 scfg r r e g i st er to r e a c h t h e i 2 s fu nct i ona litie s a nd choo se th e i 2 s st an d a r d th ro ug h th e i2 sstd[1 : 0 ] b i ts , th e da ta le ng th th r o u g h t h e d a tl en[ 1 : 0 ] bit s a n d t h e n u mbe r of bit s p e r cha nne l f o r t he f r ame co nf igur ing t he RM0033 serial periphe ral interface (spi) doc id 15403 rev 3 689/1317 chl e n bit . se lect a l so t h e mod e (t r a n s missio n or r e cep t io n) f o r th e sl a v e t h r o u gh t he i2 scfg [1 :0 ] b i ts in spi_ i 2 s cfg r r e g i ste r . 2. if needed, s e lect all the potential interr upt s o urc e s and the dma ca pabilities b y w r iting t he spi _cr2 r e g i st er . 3. t h e i 2 se b i t in spi _i2 s cf g r r e gist er m u st be s e t . t r ansmission s e quence th e t r an smi s sion seq u e n ce be gins wh en t h e e xte r n a l m a ste r de vice sen d s th e clo c k a nd whe n th e nss_ws sign al re que sts th e tr ansf e r o f d a t a . t he sla v e has to b e en ab led b e f o r e t h e e x te r n a l mast er st ar t s t h e comm un icat ion. th e i 2 s d a t a re gist er h a s to be lo ade d be f o re the master initiate s t he comm u n icat ion . fo r t h e i 2 s , msb justified and lsb justified modes , th e fir st da ta it em t o be wr it te n in to t h e d a t a re giste r cor r e s p ond s t o t he d a t a f o r t he lef t ch ann el. wh en t h e com m unicat i on st ar t s , th e da ta a r e tr a n s f e r r e d f r o m th e tx b u ff e r to th e sh ift re gis t e r . th e txe fla g is t h e n se t in or de r to r e q u e st th e r i gh t ch an ne l d a ta to b e wr itte n in to th e i 2 s d a t a r egist er . th e chsi de f l ag in dicat e s wh ich ch an nel is t o b e tr ansmit t ed. co mpa r e d t o th e mast er tr an sm iss i on m o de , in sla v e mo d e , c h sid e is sen sit iv e to th e ws s i gn a l co m i ng fr om the e x t e r n a l ma st er . t h is me ans th at t h e sla v e ne ed s to b e r e a d y t o tr ansmit t h e f i rst d a t a bef or e t h e cloc k is g ene r a t e d b y th e mast er . ws asser t ion cor r e s p ond s t o lef t cha n n e l tr ansmit t ed fir st. no te : t he i2 se ha s t o be wr it te n at lea st two pcl k c ycle s b e f or e th e firs t c l oc k of th e m a s t e r comes on the ck line . th e da ta h a lf -w or d is p a r a llel- load ed in to t h e 1 6 - b it sh ift re giste r ( f r o m t he in te r n a l b u s) d u r i ng t h e fir s t bit tr ansmission , an d th en shif t e d ou t se r i a lly to th e m o si /sd pin m sb f i rst . th e txe f l ag is se t a f t e r each t r a n sf e r f r o m th e tx b u f f e r t o t he shif t r e g i st e r an d an in te rr u p t is gen er a t e d if t h e t x ei e bit i n th e spi _ cr2 r egist er is set . no te t h a t th e txe fla g sh o u ld be ch ec k e d to be at 1 be f o re at tem p tin g to wr ite th e tx b u ff e r . f o r mo re d e t a ils abo ut t h e wr it e op er a t ions dep en ding o n t he i 2 s st and ar d mod e select ed, re f e r to sect ion 2 5. 4. 2: supp or t ed au dio p r o t o c o l s . t o se cu re a con t in uou s a udio d a t a t r an smission , it is ma nda to r y to wr it e t he spi _dr r e g i st er wit h t h e n e xt da ta to t r a n smit b e f o r e th e en d of t h e cu rr en t t r an smi s sion . an u nde rr u n fla g is set an d an int e rr u p t m a y b e gen er a t ed if t h e dat a ar e no t wr it te n int o t he spi _dr r e g i st er bef or e t he f i rst clo c k ed ge o f t he ne xt da ta co mm unica tio n . t h is in dicat e s t o t he sof t w ar e th at th e tr ansf e r r e d dat a ar e wro ng. if th e erri e bit is se t int o t h e spi _cr2 r e g i st er , an int e r r up t is gen er a t e d when t h e udr f l a g in th e spi_ s r re gist er g oes hig h . i n th is ca se , it is m a n d a to r y to s w itch of f th e i 2 s an d t o re st ar t a da ta t r an sf e r st ar t i ng fr om t he le ft ch an nel. t o s wit ch of f t he i 2 s , b y clear i ng the i2se bit, it is mandator y to w a it f o r txe = 1 and bsy = 0. rece ption se quence th e o per at ing m ode is th e same as f o r t h e t r ansmission mod e e xcep t f o r t he p o int 1 (r ef er to t h e pr oced ure de scr i b ed in sect ion 2 5. 4. 5: i 2 s sla v e m ode ), whe r e th e con f ig ur a t io n sho u ld set th e mast er r e cep t ion mo de usin g th e i2 scf g [ 1 : 0 ] bit s in t h e spi _i 2scfgr re gist er . wha t e v er t h e d a t a len g t h or t h e ch ann el len g t h , th e aud io da ta a r e r e ceiv e d b y 16 -b it pa c k e ts . th is m e an s t h a t ea ch tim e th e rx b u ff e r is fu ll, th e rxne flag in t h e spi _sr serial peripheral interface (spi) RM0033 690/1317 doc id 15403 rev 3 r e g i st er is set a nd an int e r r upt is g e n e r a t e d if t h e rxnei e bit is set in t h e spi_ c r2 re giste r . dep end ing on t he d a t a l eng th an d cha n n e l le ngt h co nf igur at ion , t h e au dio v a lue r e ceiv ed f o r a r i g h t o r lef t ch ann el ma y re sult f r om on e or t w o r e cep t io ns int o t he rx b u f f er . th e chsi de f l ag is up dat ed e a ch t i me da t a are rece iv e d t o be r ead f r om spi_ d r. it is sen s it iv e t o t he e x t e r nal ws lin e man a g ed b y t h e e x t e r n a l ma ste r comp one nt . clear ing the rxne bit is perf o r m ed b y r ead ing t h e spi _dr r e g i st er . f o r m o r e de ta ils abo ut t he r e a d o per at ions d epe ndin g t h e i 2 s st an dar d mo de se lect ed, r e f e r to sect ion 2 5. 4. 2: su ppo r t e d au dio pr ot oco l s . i f da ta ar e r e ceiv e d while th e p r e c e d e n t re ce iv ed dat a ha v e no t y e t be en re ad, a n o v er r u n is ge n e r a te d an d th e o v r flag is se t. if th e bit erri e is se t in t h e spi _cr 2 re gis t e r , a n in te rr u p t is ge ner at ed t o ind i ca te t h e er ror . t o s witc h off the i 2 s in r e cep t io n mod e , i 2 se has to be clear ed im med i at ely af te r r e ceiving the las t rx ne = 1. note: t he e x ter n al mas t er compon ents should ha v e the c a pability of s e nding/receiving data in 16- b i t or 32- bit pac k e t s via an a udio ch ann el. 25.4.6 status flags th re e sta t u s f l ag s ar e pr o v id ed f o r th e app licat ion t o f u lly m onit o r th e sta t e o f t h e i 2 s b u s . busy fla g (bsy) the bsy flag is set and cleared b y hardw are (wr i ting to this flag has no eff e ct). it indicates t h e st at e of th e comm un icat ion la y e r of t he i 2 s. wh en bsy is s e t , it ind i ca te s t h a t th e i 2 s is b u sy com m unicat i ng . th er e is o ne e xcep t io n in master receiv e mode (i2scfg = 11) where the bsy flag is k e pt lo w dur i ng reception. the bsy flag is useful to detect the end of a tr ansf e r if the softw a re needs to disab l e the i 2 s. th is a v oid s cor r upt in g th e last t r an sf e r . f o r th is , t h e pro c edu re d e scr i b e d b e lo w m u st be str i c t ly respect e d. the bsy flag is set when a tr an sf er star ts , e x cept when the i 2 s is in master receiv er mode . the bsy flag is cleared: when a tr a n sf er comp let e s (e xcep t in master tr ans m it mode , in which the comm u n icat ion is su ppo sed t o be con t in u o u s ) when t h e i 2 s is dis a b l ed whe n comm un icat ion is co nt in uou s: i n mast er t r a n smit mo de , th e bsy f l ag is k ept hig h dur in g all t he t r an sf e r s in sla v e mode , the bsy fl ag goes l o w f o r one i 2 s cloc k cycle be tw een each t r an sf e r note: d o not use the bsy flag to handle each data tr an smission or reception. it is better to use the txe an d rxne fla g s inste ad. tx b u ff er empty fla g (txe) whe n set , t h is f l a g indica te s t hat t he tx b u ff er is em pt y a nd t he n e xt da ta t o b e tr ansmit t ed can t h e n be lo ade d int o it . the t x e f l ag is r e set when t h e t x b u f f e r alr e a d y con t a i ns dat a t o be transmitted. it is also reset when the i 2 s is disabled (i2se bit is reset). RM0033 serial periphe ral interface (spi) doc id 15403 rev 3 691/1317 rx b u ff er not em pty (rxne) wh en se t, th is flag in d i cat e s th a t th e r e a r e v a lid re ce iv e d d a t a in th e rx b u ff er . it is re se t when spi_d r register is read. chann e l side fla g (chside) i n t r an sm ission m ode , th is f l ag is re fr eshe d when t x e go es high . i t in dicat e s th e ch an nel side t o which th e d a t a t o tr ansf e r on sd has t o belo n g . in case o f an und er r un err o r e v e n t in sla v e tr ansmission mo de , t h is f l ag is n o t rel i ab le and i 2 s nee ds to b e s w it ched of f an d s witche d on b e f o r e re su ming th e co mm un ica t io n. i n r e cept ion mod e , th is f l ag is re fr eshe d when d a t a ar e re ceiv ed in to spi _dr. i t in dicat e s f r o m wh ich ch an nel side d a t a ha v e bee n re ceiv ed . not e t hat in ca se of e r r o r ( lik e o v r) th is f l ag b e come s m ean ingle ss an d th e i 2 s sho u ld be r e set b y disab lin g and t h en en ab ling it ( w i t h con f ig ur a t io n if it ne eds ch an ging ). th is f l ag h a s no me anin g in t he pcm st an da rd ( f o r bo th sh or t a n d l ong f r a m e mo des) . wh en th e o v r o r u dr flag in t h e spi _sr is se t and the er rie bit in spi_cr2 is als o set, a n int e r r upt is g ene r a t e d . th is in te rr u p t can be clear ed b y rea d in g th e spi_ s r sta t u s r e g i st er (on ce th e int e r r up t sour ce has be en clea red ) . 25.4.7 err o r fla g s th er e ar e tw o er ro r f l ags f o r t h e i 2 s cell. underrun fla g (udr) in sla v e tr an sm iss i on mo d e th is f l ag is se t wh en th e fir st c l oc k f o r da ta tr an sm iss i on ap pe a r s while t h e so ft w a re h a s n o t y e t lo ad ed an y v a lue into s p i_dr. it is a v ailab l e when the i 2 smo d b i t in spi _i 2scfgr is set . an in te rr u p t m a y b e ge ner at ed if th e erri e b i t in spi_cr2 is set. th e udr bit is clear ed b y a re ad op er a t io n on t h e spi _sr re giste r . overrun fla g (o vr) th is f l ag is set whe n da ta a r e r e ceiv e d and th e pr e vious da ta h a v e n o t y e t b een rea d f r o m spi _dr. as a r e sult , t he incom i ng dat a ar e lost. an int e r r up t ma y be gen er a t e d if th e errie b i t is se t in spi_ c r2 . i n t h is ca se , th e re ce iv e b u ff er co nt en ts ar e not up dat ed wit h t he n e wly r e ceiv e d da ta f r o m t h e t r a n smit te r de vice . a r ead o p e r at ion t o t he spi _dr r egist er r e t u r n s th e pr e vious cor r e c t l y rece iv e d da ta . all ot he r subseq ue nt ly t r an sm itt e d h a lf -w or ds are l o st. clea r ing t h e o v r bi t is do ne b y a re ad o p e r at ion on t h e spi _ dr re gist er f o llo w e d b y a r ead ac ce ss t o th e spi_ s r r e gist er . 25.4.8 i 2 s interrupts t a b l e 100 pr o vid es th e list of i 2 s interr upts . serial peripheral interface (spi) RM0033 692/1317 doc id 15403 rev 3 25.4.9 dma f eatures dma is w o r k ing in e x a c t l y th e sa me w a y as f o r t h e spi m ode . the r e is no d i ff er en ce o n t he i 2 s . only the cr c f e ature is not a v ailab l e in i 2 s mod e since th er e is n o dat a t r an sf e r prot ec tion syst em. t ab l e 10 0. i 2 s int e r r upt r e que st s i n terrupt e v en t e vent fla g en ab le con t r o l bi t t r ansmit b u ff er empty flag txe t xeie recei v e b u ff er not empty flag rxne rxneie ov e r r un error o vr errie unde rr un error udr RM0033 serial periphe ral interface (spi) doc id 15403 rev 3 693/1317 25.5 spi and i 2 s register s ref e r to se ct ion 1 . 1 on p age 3 6 f o r a list o f ab b r e v ia t i ons used in r e g i st er descr ipt i on s . 25.5.1 spi contr o l register 1 (spi_cr1) (not used in i 2 s mode) ad dre ss of f s e t : 0x00 re se t v a lu e: 0x 00 0 0 1 5 1 4 1 3 1 2 1 1 1 0 987 654321 0 bidi mode bi di oe crc en crc nex t dff rx onl y ss m ss i lsb fi rst sp e b r [2 :0 ] m st r c p o l c ph a rw rw rw rw r w r w rw rw rw rw rw r w rw rw rw rw bit 15 bidimode: bidire ctio nal da ta mod e enab le 0: 2 - line u n idi r ecti ona l d a ta mo de sele cted 1: 1 - line b i dire ctio nal da ta mod e se lected no te : no t u s ed in i 2 s mode bit 14 bidioe: ou tpu t en ab le i n bidi recti onal mod e th is bit combine d with the bidimo de bit sele cts the di re ctio n of transf e r i n bid i recti ona l mo de 0: outpu t disa b l ed (rece iv e-on ly mo de) 1: outpu t ena b l ed (tr a nsmit-o n ly mode) no te : i n master mo de , the mosi pin is used a nd in sla v e mo de , the miso pin is used . no t u s ed in i 2 s mode bit 13 crc en: ha rdw a re crc calcu l ation en ab l e 0: c rc ca lcula t i on disa b l ed 1: c rc ca lcula t i on ena b l e d no te : t hi s b i t sho u ld be wr i t ten o n ly when spi i s di sab l e d (spe = ?0 ?) f o r co rre c t ope r a tion no t u s ed in i 2 s mode bit 12 crc next : crc transf e r n e xt 0: d a ta p hase (no cr c p hase) 1: n e xt transf e r is crc (crc ph ase) no te : w he n the spi i s con f ig ured in full d uple x or tr a n smitte r on ly mod e s , crcnext must be wr itte n as so on as th e last d a ta i s wr itten to the spi_d r re gister . whe n the spi i s con f i gured i n re ceiv e r on ly mo de , crc next m u st be set after th e second la st data recep t i on. thi s b i t sho u ld be k e p t clea red whe n the tr a n sf ers are manag ed b y dma. no t u s ed in i 2 s mode bit 11 dff: data fr ame f o r m at 0: 8 - bit d a ta frame f o r m a t is sele cted f o r tr a n smission/recep t i o n 1: 1 6 -bit data fr ame f o r m at i s sel e cte d f o r transmission /re c e p tion no te : t hi s b i t sho u ld be wr i t ten o n ly when spi i s di sab l e d (spe = ?0 ?) f o r co rre c t ope r a tion no t u s ed in i 2 s mode serial peripheral interface (spi) RM0033 694/1317 doc id 15403 rev 3 bit 10 rxonl y : re ce i v e on l y th is b it co mb ined wi th the bidimo de bit se lects the d i rection of transf e r in 2 - l i ne unidirectional mode . this bit is also us eful in a m u ltisla v e system in which this par t icular sla v e i s no t accesse d, the ou tpu t from the acce sse d sl a v e is not corr upted . 0: ful l d upl e x (t ransmit a nd recei v e) 1: outpu t disa b l ed (re ceiv e -o nly mode) no te : no t u s ed in i 2 s mode bit 9 ssm: softw are sla v e man age me nt wh en th e ssm bit is se t, th e nss pi n inpu t is repl aced with the v a lu e from the ssi bit. 0: so ftw a re sla v e ma nage me nt d i sab l ed 1: so ftw a re sla v e ma nage me nt e nab l e d no te : no t u s ed in i 2 s mode and spi ti mode bit 8 ssi: inter nal sla v e select th is b i t h a s a n eff e ct on ly when the ssm b i t is set. the v a l ue of thi s bi t is f o rced on to the nss pin an d the io v a lue of th e nss pi n is i gno re d. no te : no t u s ed in i 2 s mode and spi ti mode bit 7 lsbf irst : f r ame f o r m at 0: msb transmitted fi rst 1: lsb tr ansmit ted first no te : t hi s b i t sho u ld no t be cha nged wh en comm u n ication i s on going. no t u s ed in i 2 s mode and spi ti mode bit 6 spe: spi enab le 0: p e r i pheral di sa b l e d 1: p e r i pheral en ab le d no te : 1- no t u s ed in i 2 s mode . no te : 2 - wh en d isab l ing the spi, f o l lo w the procedu re de scr ibed in section 25.3.8: disab l ing the sp i . bits 5:3 br[2 : 0]: baud r a te control 000 : f pclk /2 100 : f pc l k /32 001 : f pclk /4 101 : f pc l k /64 010 : f pclk /8 110 : f pc l k /128 011 : f pclk /16 111 : f pc l k /256 no te : t he se bits sho u ld no t be cha nge d when comm u n icatio n is o ngo ing. no t u s ed in i 2 s mode bit 2 mstr: master selection 0: sl a v e config ur a t i o n 1: ma ster config ur atio n no te : t hi s b i t sho u ld no t be cha nged wh en comm u n ication i s on going. no t u s ed in i 2 s mode bi t1 cpol: clo c k po lar i ty 0: c k to 0 when id le 1: c k to 1 when id le no te : t hi s b i t sho u ld no t be cha nged wh en comm u n ication i s on going. no t u s ed in i 2 s mode and spi ti mode RM0033 serial periphe ral interface (spi) doc id 15403 rev 3 695/1317 bit 0 cpha : clo c k ph ase 0: the first clo c k tr an siti on is th e first data capture edg e 1: the seco nd cloc k transitio n is the first da ta ca ptu r e edge no te : t hi s b i t sho u ld no t be cha nged wh en comm u n ication i s on going. note: n o t u s ed in i 2 s mode and spi ti mode serial peripheral interface (spi) RM0033 696/1317 doc id 15403 rev 3 25.5.2 spi contr o l regi ster 2 (spi_cr2) ad dre s s of f s e t : 0x04 re se t v a lu e: 0x 00 0 0 15 14 1 3 12 11 1 0 9 8 7 6 5 4 3 2 1 0 reser v ed txe i e r xnei e e rrie f r f res . ss oe txdmaen rxdmae n r w rw rw rw rw r w rw bits 15 :8 rese r v ed . f o rced to 0 b y hardw a r e . bit 7 txeie: tx b u ff er empty in te rr upt enab le 0: txe i n te rr upt ma sk e d 1: txe i n te rr upt no t mask e d . used to g ene r a te a n in te rr upt requ est when th e txe fla g is se t. bit 6 rxneie: rx b u ff e r no t empty i n terr up t ena b l e 0: rxn e in te rr upt mask e d 1: rxne in terr upt n o t mask ed . used to gen er a t e an i n te rr upt re que st whe n the rxne flag is set. bit 5 errie: error interr upt enab le th is b i t con t rol s the ge neration of an inte rr u p t wh en an error cond ition occurs (crcerr, o v r, mod f in spi mode a nd udr, o v r i n i 2 s mode). 0: error interr upt is mask ed 1: error interr upt is enab l ed bit 4 fr f : f r ame f o r m a t 0: spi motorola mode 1 spi ti mo de note: no t u s ed in i 2 s mode bit 3 r ese r v e d . f o rced to 0 b y hardw a r e . bit 2 ssoe: ss o u tp ut e nab l e 0: ss outpu t is disab l ed in master mode an d th e ce ll can w o r k i n m u ltimaster configu r atio n 1: ss outpu t is enab led i n ma ster mode an d when the cel l is e nab l ed. the cel l canno t w o r k in a m u l t i m a ster en vi ronmen t. note: no t u s ed in i 2 s mo de an d sp i t i mo de bit 1 t x dm ae n: tx b u ff er dma ena b l e whe n th is b i t is set, the dma re quest is ma de when e v er the txe fla g is set. 0: tx b u ff er dma di sa b l e d 1: tx b u ff er dma en ab le d bit 0 rxdmaen: rx b u ff er dma en ab le whe n th is b i t is set, the dma re quest is ma de whene v er the r x n e flag i s set. 0: rx b u ff e r dma disab l ed 1: rx b u ff e r dma enab led RM0033 serial periphe ral interface (spi) doc id 15403 rev 3 697/1317 25.5.3 spi status register (spi_sr) ad dre s s of f s e t : 0x08 re se t v a lu e: 0x 00 0 2 1 5 1 4 1 3 1 2 1 1 1 0 987 654321 0 reser v ed tif r fe bsy o vr modf crc err udr chs id e txe r xne rr rr r c _ w 0 rrr r bits 1 5 :9 r e ser v ed. f o rced to 0 b y ha rdw a re . bit 8 tif r fe : ti fr ame f o r m at e r ro r 0 : no fr ame f o r m at e r ro r 1: a fr am e f o r m at e rro r o ccu rre d bit 7 bsy : busy flag 0: spi (or i2s ) not b u sy 1 : spi (or i2 s) i s b u sy in co mmunica tio n or tx b u ff er is not e m p t y this fl ag is set an d cleare d b y h a rdw a re . note: bsy flag m u st be used with caution: ref e r to secti o n 2 5 . 3.7: sta t us flags an d section 2 5 . 3 . 8 : disab lin g the spi . bit 6 ov r : ov err u n flag 0 : no o v err u n occurred 1: o v err u n o ccu rre d this fl ag is set b y ha rdw a re and rese t b y a softw a re seq uen ce . ref e r to secti o n 2 5 . 4.7 on p age 69 1 f o r the so ftw a re sequ ence . bit 5 modf: mode f a ult 0 : no mode f a ult o ccurred 1 : mode f a ult o c cu rre d this fl ag is set b y ha rdw a re and rese t b y a softw a re seq uen ce . ref e r to secti o n 2 5 . 3.10 o n p age 67 4 f o r the so ftw a re sequ ence . n o te: n ot used in i 2 s mode bit 4 c rcerr: crc error fl ag 0 : crc v a l ue receiv ed match e s the spi_rxcr cr v a lue 1 : crc v a l ue receiv ed doe s no t match th e spi_rxcr cr v a lu e this fl ag is set b y ha rdw a re and cle a red b y softw a re w r iting 0. n o te: n ot used in i 2 s mode bit 3 u dr: u nderr u n fl ag 0: n o u n d e r r u n occ u rr ed 1: u n de rr u n o ccur r ed this fl ag is set b y ha rdw a re and rese t b y a softw a re seq uen ce . ref e r to secti o n 2 5 . 4.7 on p age 69 1 f o r the so ftw a re sequ ence . n o te: n ot used in spi mod e bit 2 ch si d e : chan nel sid e 0: ch ann el left h a s to be tr a n smi t ted o r ha s be en recei v ed 1: ch ann el righ t ha s to be tr an smi t ted or has be en receiv e d n o te: n ot used f o r the spi mode . no meani ng in pcm mo de bit 1 txe: t r an smi t b u f f er em pt y 0 : tx b u ff e r no t empty 1: tx buffer empty serial peripheral interface (spi) RM0033 698/1317 doc id 15403 rev 3 25.5.4 spi data register (spi_dr) ad dre s s of f s e t : 0x0c re se t v a lu e: 0x 00 0 0 25.5.5 spi crc pol ynomial register (spi_crcpr) ( not used in i 2 s mode) ad dre ss of f s e t : 0x10 re se t v a lu e: 0x 00 0 7 25.5.6 spi rx crc register ( spi_rxcrcr) ( not used in i 2 s mode) ad dre ss of f s e t : 0x14 bit 0 rxn e : r e c e i v e b u f f er no t e m pt y 0 : rx b u ff er empty 1 : rx b u ff er not empty 1 5 1 4 1 3 1 2 1 1 1 0 987 654321 0 dr[ 15: 0] rw rw rw rw r w r w rw rw rw rw rw r w rw rw rw rw bits 15:0 d r [15:0]: data regi ster da ta rece iv ed or to be transmitted. the data regi ster is sp lit i n to 2 b u ff ers - one f o r wr iting (t r a n s mi t buff er) a nd ano th er on e f o r rea d ing (re c eiv e b u ff er). a wr ite to the da ta re g i ste r wi ll wr ite in to the tx b u ff e r an d a read from the d a ta re gister will retur n th e v a lu e held i n the rx b u ff e r . n o tes f o r the spi mode : dep end ing on the da ta fr a m e f o r m at selectio n bi t (d ff i n spi_ c r 1 re gi st er) , t h e d a ta sent or receiv ed is ei the r 8 - bit or 16-bi t. th is se lection h a s to be made b e f o re e nab ling the spi to e n sure correct o peration. f o r an 8-bi t da ta fr ame , the b u ff ers are 8-bit and on ly the l s b of th e re gister (spi_ dr[7:0 ] ) is used f o r transmissio n /re cept ion. wh en in receptio n mode , the msb of the regi ster (spi_d r[1 5 :8]) is f o rced to 0. f o r a 16-bi t da ta fr ame , the b u ff ers are 16-bi t and the e n ti re re gister , spi_ dr[1 5 :0] i s used f o r tr a n smission/recep t i on. 1 5 1 4 1 3 1 2 1 1 1 0 987 654321 0 crcp ol y [ 1 5 :0 ] rw rw rw rw r w r w rw rw rw rw rw r w rw rw rw rw bit s 1 5 :0 cr cpol y[1 5 :0]: crc pol yn omial reg ister th is re gister contain s the po lynomia l f o r the cr c ca lcula t i on. th e crc pol ynomial (0 007h ) is the reset v a lue o f this register . anothe r po lynomia l can be config ured as requ ired. no te : n ot u sed f or th e i 2 s mode . RM0033 serial periphe ral interface (spi) doc id 15403 rev 3 699/1317 re se t v a lu e: 0x 00 0 0 25.5.7 spi tx crc register (spi_txcrcr) (not used in i 2 s mod e ) ad dre ss of f s e t : 0x18 re se t v a lu e: 0x 00 0 0 25.5.8 spi_i 2 s configuration regist er (spi_i2scfgr) ad dre ss of f s e t : 0x1c re se t v a lu e: 0x 00 0 0 1 5 1 4 1 3 1 2 1 1 1 0 987 654321 0 rxcrc[15:0] rr rrrrrrr rrrrrr r bits 15 :0 rxcrc [1 5:0]: rx cr c re gister whe n c rc cal c u latio n is enab led , the rxcrc [1 5:0 ] bits con t a in the computed crc v a l ue o f th e subseq uently receiv ed b y tes . th is re gist er is re se t whe n th e crcen bit in spi_c r1 register is wr itte n to 1 . th e crc is ca lcula t e d se r ial ly u s ing the pol ynomia l p r og r a mmed in th e spi_c rcpr re gister . only the 8 lsb bits are consid ered wh en th e data frame f o r m at is set to be 8 - b i t d a ta (dff bit of spi_cr1 is clea red). cr c ca lcula t io n is d one b a sed on an y crc 8 stan dard. th e entire 16 -bits o f this regi ste r are co nside r e d whe n a 16-bi t da ta fr a m e f o r m a t is sel e cte d (dff b i t o f the spi_ cr1 register is set) . crc calcul ation is don e based o n a n y c rc16 sta ndard . note: a read to this register when the bsy flag is set coul d retur n an incorrect v a lue . no t us ed f o r t h e i 2 s mode . 1 5 1 4 1 3 1 2 1 1 1 0 987 654321 0 txcrc[15 :0 ] rr rrrrrrr rrrrrr r bi ts 15:0 txcr c[15:0]: tx crc regi ster whe n c rc ca lcula t i on is ena b l ed , the txcr c[7 : 0 ] bits contain the compu t e d crc v a lu e of the su bsequ ently transmitte d b y tes . th is re gister i s rese t whe n the c rcen bit o f spi_ cr1 is wr itten to 1. the cr c i s cal c ulated se r i all y usi ng th e polyn omial pro g rammed in the spi_cr cpr re gister . onl y the 8 lsb bits a r e co nside r ed whe n the d a ta frame f o r m a t is set to be 8-bi t da ta (dff bit o f spi_ cr1 is cleare d ). crc cal culatio n i s d one ba sed on an y crc8 stand ard. the en tire 16 -b its of this re gister a r e consi der ed whe n a 16 -b it data frame f o r m a t is sele cte d (d ff b i t of th e spi_cr 1 regi ster is se t). c rc ca lcula t i on is done b a sed on a n y crc 16 stan dard. note: a read to this r e gister when the bsy flag is set coul d r e tur n an incorrect v a lue . no t used f o r i 2 s mode . 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reser v e d i2 s m od i 2 s e i2 s c fg pcmsy nc reser v ed i2s s td ckpol d a t len chlen r w rw rw rw rw rw rw r w r w rw rw serial peripheral interface (spi) RM0033 700/1317 doc id 15403 rev 3 bits 15:12 reser v ed : f o rced to 0 b y h a rdw a re bit 11 i2 smo d : i2s mode selection 0: spi mode is selected 1: i2s mo de is selected note: t his bit shoul d be config ured whe n the spi or i 2 s is disab l ed bit 10 i2 se : i2 s en ab le 0: i 2 s per iphe r a l i s di sab l e d 1: i 2 s per iphe r a l i s en ab l e d note: n ot used in s p i m o de bit 9:8 i2 scfg : i2 s co n f i g ur a t i o n mo de 00: sl a v e - tr a n smit 01: sl a v e - re ceiv e 10: master - tr a n smit 11: master - rec e iv e note: t his bit shoul d be config ured whe n the i 2 s is dis a b l ed. no t used f o r the spi mod e bi t 7 pcmsy n c : pcm frame syn chroni za ti on 0: sho r t frame synchron i zation 1: lo ng fr ame synchron i zation note: t his bit has a meani ng onl y if i2 sstd = 11 (pcm stan dard is used ) no t used f o r the spi mod e bi t 6 r eser v e d : f o rced a t 0 b y hardw a r e bit 5:4 i2sstd : i2s standa rd se lection 00: i 2 s phi llips stand ard. 01: msb justified stand ard (l eft justified ) 10: l sb ju stifie d stan dard (r ig ht ju sti f ie d) 11: pcm sta nda rd f o r mo re detail s on i 2 s standa rds , ref e r to secti o n 25.4.2 on pa ge 677 . not used in spi mo de . note: f o r correct operation , th ese bits sh oul d be configu r ed whe n the i 2 s is disa b l ed . bi t 3 ckpol : stea dy state cloc k pola r ity 0: i 2 s cloc k steady state is lo w le v e l 1: i 2 s cloc k ste ady sta t e is hig h le v e l note: f o r correct operation , th is bit sh ould b e co nfigure d when the i 2 s is disab l ed . no t used i n spi mo de bit 2:1 da t l e n : data le ngth to b e transf e rred 00: 1 6 -bit data len g th 01: 2 4 -bit data len g th 10: 3 2 -bit data len g th 11: n ot al lo w ed note: f o r correct operation , th ese bits sh oul d be configu r ed whe n the i 2 s is disa b l ed . no t used i n spi mo de . RM0033 serial periphe ral interface (spi) doc id 15403 rev 3 701/1317 25.5.9 spi_i 2 s prescaler regist er (spi_i2spr) ad dre s s of f s e t : 0x20 re se t v a lu e: 00 0 0 00 10 ( 0 x 0 0 0 2 ) 25.5.10 spi register map th e t a b l e pr o v id es sh o w s th e spi re gist er ma p an d re se t v a lu es . bi t 0 chlen : cha nne l l eng th (n umber of bits p e r a udi o ch anne l) 0: 16 -bit w i de 1: 32 -bit w i de the bit wr i t e ope r a tion has a mean ing only i f d a tlen = 00 otherwi se the ch anne l le ngth i s fix ed to 32-bi t b y hardw a r e w hate v er the v a lue fill ed in. not u sed in spi mod e . note: f o r correct operation , th is bit sh ould b e co nfigure d when the i 2 s is disab l ed . 15 14 13 1 2 11 10 9 8 7 6 5 4 3 2 1 0 reser v ed m c k o e o dd i2 s d iv rw r w rw bits 15:10 reser v ed : f o rced to 0 b y h a rdw a re bi t 9 mck o e : master cl oc k o u tput enab le 0: master cl oc k o u tput i s d i sab l ed 1: master cl oc k o u tput i s e nab l e d note: t his bit sh ould b e co nfi gured wh en th e i 2 s is disa b l ed . it is u s e d only when the i 2 s is in master mode . no t used i n spi mo de . bi t 8 odd : odd f a ctor f o r the pr escaler 0 : re al di vi d e r v a l u e i s = i2 sd iv *2 1: rea l d i vide r v a lue is = (i2sdiv * 2)+ 1 ref e r to section 2 5 . 4.3 on p age 68 4 . no t used i n spi mo de . note: t his bit sh ould b e co nfi gured wh en th e i 2 s is disa b l ed . it is u s e d only when the i 2 s is in master mode . bit 7:0 i2 sdiv : i2 s li nea r pre s ca ler i2sd iv [7 :0 ] = 0 or i2 sdiv [ 7 : 0 ] = 1 are f o rbidd en v a l ues . ref e r to se cti on 25.4.3 on pa ge 684 . not used in spi mod e . note: t hese bi ts shou ld be con f ig ured wh en th e i 2 s is di sa b l e d . it is u s ed on l y w h en t h e i 2 s is in master mo de . t a b l e 101 . spi r e gi st er map a nd res e t v a l ue s offset registe r 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 spi _cr1 reser v e d b i dimode bi dio e crcen crcn e x t df f rxonl y ssm ss i lsb f i r st sp e b r [2 :0 ] mst r cpol cpha r e se t v a l u e 0 000 00 00 000 00 00 0 serial peripheral interface (spi) RM0033 702/1317 doc id 15403 rev 3 refer to table 1 on page 50 for the register boundary addresses. 0x04 spi _cr2 reser v ed txeie rxneie errie frf reserved ssoe txdmaen rxdmaen reset v a lu e 000 0 00 0 0x08 sp i_s r reser v e d tifr fe bsy ovr modf crcerr udr chside txe rxne reset v a lu e 0 000 00 01 0 0x 0c sp i_ dr reser v e d dr[15:0] r e s e t v a l u e 0 000 00 00 000 00 00 0 0x10 sp i_ cr cp r reser v e d crcpoly[15:0] r e s e t v a l u e 0 000 00 00 000 00 11 1 0x14 sp i_ rxcrcr reser v e d rxcrc[15:0] r e s e t v a l u e 0 000 00 00 000 00 00 0 0x18 spi_txcrcr reser v e d txcrc[15:0] r e s e t v a l u e 0 000 00 00 000 00 00 0 0x 1c sp i_ i2 s c fg r reser v e d i2 smod i2se i2scfg pcmsync reserved i2sstd ckpol datlen chlen reset v a lu e 00 00 0 0 00 00 0 0x20 s p i _ i2 spr re se r v e d mck o e odd i2 s d iv reset v a lu e 00 000 00 01 0 t a b l e 101 . spi r e gist er map a nd res e t v a lue s (c ont in ue d) offset registe r 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RM0033 secure digital input/output interface (sdio) doc id 15403 rev 3 703/1317 26 secure digital input/output interface (sdio) 26.1 sdio main features the sd/sdio mmc card host in terface (sdio) provides an interface between the apb2 peripheral bus and multimediacards (mmcs), sd memory cards, sdio cards and ce-ata devices. the multimediacard system sp ecifications are available through the mu ltimediacard association website at www.mmca.org , published by the mmca technical committee. sd memory card and sd i/o card system specifications are available through the sd card association website at www.sdcard.org . ce-ata system specifications are available through the ce-ata workgroup website at www.ce-ata.org . the sdio features include the following: full compliance with multimediacard system specification version 4.2 . card support for three different databus modes: 1-bit (default), 4-bit and 8-bit full compatibility with previous versions of multimediacards (f orward compatibility) full compliance with sd memory card specif ications version 2.0 full compliance with sd i/o card specification version 2.0: card support for two different databus modes: 1-bit (default) and 4-bit full support of the ce-ata features (full compliance with ce-ata digital protocol rev1.1 ) data transfer up to 48 mhz for the 8 bit mode data and command output enable signals to control external bidirectional drivers. note: 1 the sdio does not have an spi-compatible communication mode. 2 the sd memory card protocol is a superset of the multimediacard protocol as defined in the multimediacard system specif ication v2.11. several commands required for sd memory devices are not supported by either sd i/o-only cards or the i/o portion of combo cards. some of these commands have no use in sd i/o devices, such as erase commands, and thus are not supported in the sdio. in addition, several commands are different between sd memory cards and sd i/o cards and thus are not supported in the sdio. for details refer to sd i/o card specification version 1.0. ce-a ta is supported over the mmc electrical interface using a pr otocol that utilizes the existing mm c access primitives. the interface electrical and signaling definition is as defined in the mmc reference. the multimediacard/sd bus con nects cards to the controller. the current version of the sdio supports only one sd/sdio/mmc4.2 card at any one time and a stack of mmc4.1 or previous. 26.2 sdio bus topology communication over the bus is based on command and data transfers. the basic transaction on the multimediacard/sd/sd i/o bus is the command/response transaction. these types of bus transaction transfer their information directly within the command or response structure. in addition, some operations have a data token. secure digital input/output interface (sdio) RM0033 704/1317 doc id 15403 rev 3 data transfers to/from sd/sdio memory cards are done in data blocks. data transfers to/from mmc are done data blocks or streams. data transfers to/from the ce-ata devices are done in data blocks. figure 284. sdio ?no response? and ?no data? operations figure 285. sdio (multiple) block read operation figure 286. sdio (multiple) block write operation operation (no response) operation (no data) sdio_cmd sdio_d from host to card(s) from host to card from card to host response command command ai14734 ai14735 command response data block crc data block crc data block crc block read operation multiple block read operation data stop operation from host to card from card to host data from card to host stop command stops data transfer command response sdio_cmd sdio_d ai14737 block write operation data stop operation multiple block write operation from host to card from card to host data from host to card stop command stops data transfer optional cards busy. needed for ce-ata command response command response data block crc busy busy data block crc busy sdio_cmd sdio_d RM0033 secure digital input/output interface (sdio) doc id 15403 rev 3 705/1317 note: the sdio will not send any data as long as the busy signal is as serted (sdio_d0 pulled low). figure 287. sdio sequential read operation figure 288. sdio sequential write operation 26.3 sdio functional description the sdio consists of two parts: the sdio adapter block provides all functions specific to the mmc/sd/sd i/o card such as the clock generation unit, command and data transfer. the apb2 interface accesses the sdio adapter registers, and generates interrupt and dma request signals. ai14738 data stop operation from card to host stop command stops data transfer command response command response data transfer operation data stream from host to card(s) data from card to host sdio_cmd sdio_d ai14739 data stop operation from card to host stop command stops data transfer command response command response data transfer operation data stream from host to card(s) data from host to card sdio_cmd sdio_d secure digital input/output interface (sdio) RM0033 706/1317 doc id 15403 rev 3 figure 289. sdio block diagram by default sdio_d0 is used for data transfer. after initialization, the host can change the databus width. if a multimediacard is connected to the bus, sdio_d0, sdio_d[3:0] or sdio_d[7:0] can be used for data transfer. mmc v3.31 or previous, supports only 1 bit of data so only sdio_d0 can be used. if an sd or sd i/o card is connected to the bus, data transfer can be configured by the host to use sdio_d0 or sdio_d[3:0]. all data lines are operating in push-pull mode. sdio_cmd has two operational modes: open-drain for initialization (only for mmcv3.31 or previous) push-pull for command transfer (sd/sd i/o card mmc4.2 use push-pull drivers also for initialization) sdio_ck is the clock to the card: one bit is transferred on both command and data lines with each clock cycle. the clock frequency can vary between 0 mhz and 20 mhz (for a multimediacard v3.31), between 0 and 48 mhz for a multimediacard v4.0/4.2, or between 0 and 25 mhz (for an sd/sd i/o card). the sdio uses two clock signals: sdio adapter clock (sdioclk = 48 mhz) apb2 bus clock (pclk2) pclk2 and sdio_ck clock frequencies must respect the following condition: the signals shown in ta b l e 1 0 2 are used on the multimediacard/sd/sd i/o card bus. ! 0 " b u s ! 0 " ) n t e r r u p t s a n d 0 # , + 3 $ ) / ? # + a d a p t e r i n t e r f a c e $ - ! r e q u e s t 3 $ ) / # , + 3 $ ) / 3 $ ) / 3 $ ) / ? $ ; = 3 $ ) / ? # - $ a i frequenc pclk2 () 38 ? frequency sdio_ck () RM0033 secure digital input/output interface (sdio) doc id 15403 rev 3 707/1317 26.3.1 sdio adapter figure 290 shows a simplified block diagram of an sdio adapter. figure 290. sdio adapter the sdio adapter is a multimedia/secure digital memory card bus master that provides an interface to a multimedia card stack or to a secure digital memory card. it consists of five subunits: adapter register block control unit command path data path data fifo note: the adapter regist ers and fifo use the apb2 bus clock domain ( pclk2 ). the control unit, command path and data path use the sdio adapter clock domain (sdioclk). adapter register block the adapter register block contains all system registers. this block also generates the signals that clear the static flags in the multimedia card. the clear signals are generated when 1 is written into the corresponding bit location in the sdio clear register. table 102. sdio i/o definitions pin direction description sdio_ck output multimediacard/sd/sdio card clock. this pin is the clock from host to card. sdio_cmd bidirectional multimediacard/sd/sdio card command. this pin is the bidirectional command/response signal. sdio_d[7:0] bidirectional multimediacard/sd/sdio card data. these pins are the bidirectional databus. 4 o ! 0 " i n t e r f a c e a i # o n t r o l u n i t # o m m a n d p a t h $ a t a p a t h ! d a p t e r r e g i s t e r s & ) & / 3 $ ) / ? # + 3 $ ) / ? # - $ 3 $ ) / ? $ ; = 0 # , + 3 $ ) / # , + # a r d b u s 3 $ ) / a d a p t e r secure digital input/output interface (sdio) RM0033 708/1317 doc id 15403 rev 3 control unit the control unit contains the power management functions and the clock divider for the memory card clock. there are three power phases: power-off power-up power-on figure 291. control unit the control unit is illustrated in figure 291 . it consists of a power management subunit and a clock management subunit. the power management subunit disables the card bus output signals during the power-off and power-up phases. the clock management subunit generates and controls the sdio_ck signal. the sdio_ck output can use either the clock divide or the cl ock bypass mode. the clock output is inactive: after reset during the power-off or power-up phases if the power saving mode is enabled and the card bus is in the idle state (eight clock periods after both the command and data path subunits enter the idle phase) ai14804 power management clock management adapter registers sdio_ck control unit to command and data path RM0033 secure digital input/output interface (sdio) doc id 15403 rev 3 709/1317 command path the command path unit sends commands to and receives responses from the cards. figure 292. sdio adapter command path command path state machine (cpsm) ? when the command register is written to and the enable bit is set, command transfer starts. when the command has been sent, the command path state machine (cpsm) sets the status flags and enters the idle state if a response is not required. if a response is required, it waits for the response (see figure 293 on page 710 ). when the response is received, the received crc code and the internally generated code are compared, and the appropriate status flags are set. a i # - $ 3 t a t u s f l a g # o n t r o l l o g i c # o m m a n d t i m e r # 2 # ! r g u m e n t 3 h i f t r e g i s t e r # - $ 2 e s p o n s e r e g i s t e r s 4 o c o n t r o l u n i t 3 $ ) / ? # - $ i n 3 $ ) / ? # - $ o u t 4 o ! 0 " i n t e r f a c e ! d a p t e r r e g i s t e r s secure digital input/output interface (sdio) RM0033 710/1317 doc id 15403 rev 3 figure 293. command path state machine (cpsm) when the wait state is entered, the command timer starts running. if the timeout is reached before the cpsm moves to the receive state, the timeout flag is set and the idle state is entered. note: the command timeout has a fixed value of 64 sdio_ck clock periods. if the interrupt bit is set in the command register, the timer is disabled and the cpsm waits for an interrupt request from one of the cards. if a pending bit is set in the command register, the cpsm enters the pend state, and waits for a cmdpend signal from the data path subunit. when cmdpend is detected, the cpsm moves to the send state. this enables the data counter to trigger the stop command transmission. note: the cpsm remains in the idle state for at least eight sdio_ck periods to meet the n cc and n rc timing constraints. n cc is the minimum delay between two host commands, and n rc is the minimum delay between the host command and the card response. idle pend send wait receive last data cpsm disabled enabled and command start cpsm disabled or no response wait for response response started response received or disabled or command crc failed cpsm disabled or command timeout cpsm enabled and pending command ai14806b wait_cpl response received in ce-ata mode and no interrupt and wait for ce-ata command completion signal enabled response received in ce-ata mode and no interrupt and wait for ce-ata command completion signal disabled ce-ata command completion signal received or cpsm disabled or command crc failed on reset RM0033 secure digital input/output interface (sdio) doc id 15403 rev 3 711/1317 figure 294. sdio command transfer command format ? command: a command is a token that starts an operation. command are sent from the host either to a single card (addressed command) or to all connected cards (broadcast command are available for mmc v3.31 or previous). commands are transferred serially on the cmd line. all commands have a fixed length of 48 bits. the general format for a command token for multimediacards, sd-memory cards and sdio-cards is shown in ta bl e 1 0 3 . ce-ata commands are an extension of mmc commands v4.2, and so have the same format. the command path operates in a half-duplex mode, so that commands and responses can either be sent or received. if the cpsm is not in the send state, the sdio_cmd output is in the hi-z state, as shown in figure 294 on page 711 . data on sdio_cmd are synchronous with the rising edge of sdio_ck. ta bl e shows the command format. ? response: a response is a token that is sent from an addressed card (or synchronously from all connected cards for mmc v3.31 or previous), to the host as an answer to a previously received command. responses are transferred serially on the cmd line. the sdio supports two response types. both use crc error checking: 48 bit short response 136 bit long response note: if the response does not contain a crc (cmd1 response), the device driver must ignore the crc failed status. table 103. command format bit position width value description 47 1 0 start bit 46 1 1 transmission bit [45:40] 6 - command index [39:8] 32 - argument [7:1] 7 - crc7 011end bit sdio_ck sdio_cmd command response command state idle send wait receive idle send hi-z controller drives hi-z card drives hi-z controller drives ai14707 at least 8 sdio_ck cycles secure digital input/output interface (sdio) RM0033 712/1317 doc id 15403 rev 3 the command register contains the command index (six bits sent to a card) and the command type. these determine whether the command requires a response, and whether the response is 48 or 136 bits long (see section 26.9.4 on page 746 ). the command path implements the status flags shown in ta b l e 1 0 6 : the crc generator calculates the crc checksum for all bits before the crc code. this includes the start bit, transmitter bit, command index, and command argument (or card status). the crc checksum is calculated for t he first 120 bits of cid or csd for the long response format. note that the start bit, transmitter bit and the six reserved bits are not used in the crc calculation. the crc checksum is a 7-bit value: crc[6:0] = remainder [(m(x) * x 7 ) / g(x)] g(x) = x 7 + x 3 + 1 m(x) = (start bit) * x 39 + ... + (last bit before crc) * x 0 , or m(x) = (start bit) * x 119 + ... + (last bit before crc) * x 0 table 104. short response format bit position width value description 47 1 0 start bit 46 1 0 transmission bit [45:40] 6 - command index [39:8] 32 - argument [7:1] 7 - crc7(or 1111111) 011end bit table 105. long response format bit position width value description 135 1 0 start bit 134 1 0 transmission bit [133:128] 6 111111 reserved [127:1] 127 - cid or csd (including internal crc7) 0 11end bit table 106. command path status flags flag description cmdrend set if response crc is ok. ccrcfail set if response crc fails. cmdsent set when command (that does not require response) is sent ctimeout response timeout. cmdact command transfer in progress. RM0033 secure digital input/output interface (sdio) doc id 15403 rev 3 713/1317 data path the data path subunit transfers data to and from cards. figure 295 shows a block diagram of the data path. figure 295. data path the card databus width can be programmed using the clock control register. if the 4-bit wide bus mode is enabled, data is transferred at four bits per clock cycle over all four data signals (sdio_d[3:0]). if the 8-bit wide bus mode is enabled, data is transferred at eight bits per clock cycle over all eight data signals (sdio_d[7:0]). if the wide bus mode is not enabled, only one bit per clock cycle is transferred over sdio_d0. depending on the transfer direction (send or receive), the data path state machine (dpsm) moves to the wait_s or wait_r state when it is enabled: send: the dpsm moves to the wait_s state. if there is data in the transmit fifo, the dpsm moves to the send state, and the data path subunit starts sending data to a card. receive: the dpsm moves to the wait_r state and waits for a start bit. when it receives a start bit, the dpsm moves to the receive state, and the data path subunit starts receiving data from a card. data path state machine (dpsm) the dpsm operates at sdio_ck frequency. data on the card bus signals is synchronous to the rising edge of sdio_ck. the dpsm has six states, as shown in figure 296: data path state machine (dpsm) . ai14808 transmit status flag control logic data timer crc receive shift register to control unit sdio_din[7:0] sdio_dout[7:0] data fifo data path secure digital input/output interface (sdio) RM0033 714/1317 doc id 15403 rev 3 figure 296. data path state machine (dpsm) idle: the data path is inactive, and the sdio_d[7:0] outputs are in hi-z. when the data control register is written and the enable bit is set, the dpsm loads the data counter with a new value and, depending on the data direction bit, moves to either the wait_s or the wait_r state. wait_r: if the data counter equals zero, the dpsm moves to the idle state when the receive fifo is empty. if the data counter is not zero, the dpsm waits for a start bit on sdio_d. the dpsm moves to the receive state if it receives a start bit before a timeout, and loads the data block counter. if it reaches a timeout before it detects a start bit, or a start bit error occurs, it moves to the idle state and sets the timeout status flag. receive: serial data received from a card is packed in bytes and written to the data fifo. depending on the transfer mode bit in the data control register, the data transfer mode can be either block or stream: ? in block mode, when the data block counter reaches zero, the dpsm waits until it receives the crc code. if the received code matches the inte rnally generated crc code, the dpsm moves to the wait_r st ate. if not, the crc fail status flag is set and the dpsm moves to the idle state. ? in stream mode, the dpsm receives data while the data counter is not zero. when the counter is zero, the remaining data in the shift register is written to the data fifo, and the dpsm moves to the wait_r state. if a fifo overrun error occurs, the dpsm sets the fifo error flag and moves to the idle state: wait_s: the dpsm moves to the idle state if the data counter is zero. if not, it waits until the data fifo empty flag is deasserted, and moves to the send state. idle busy send wait_r receive end of packet disabled or crc fail or timeout not busy disabled or end of data data ready end of packet or end of data or fifo overrun enable and not send disabled or rx fifo empty or timeout or start bit error disabled or fifo underrun or end of data or crc fail ai14809b wait_s start bit on reset disabled or crc fail enable and send dpsm disabled read wait dpsm enabled and read wait started and sd i/o mode enabled readwait stop data received and read wait started and sd i/o mode enabled RM0033 secure digital input/output interface (sdio) doc id 15403 rev 3 715/1317 note: the dpsm remains in the wait_s state for at least two clock periods to meet the n wr timing requirements, where n wr is the number of clock cycles between the reception of the card response and the start of the data transfer from the host. send: the dpsm starts sending data to a card. depending on the transfer mode bit in the data control register, the data transfer mode can be either block or stream: ? in block mode, when the data block counter reaches zero, the dpsm sends an internally generated crc code and end bit, and moves to the busy state. ? in stream mode, the dpsm sends data to a card while the enable bit is high and the data counter is not zero. it then moves to the idle state. if a fifo underrun error occurs, the dpsm sets the fifo error flag and moves to the idle state. busy: the dpsm waits for the crc status flag: ? if it does not receive a positive crc status, it moves to the idle state and sets the crc fail status flag. ? if it receives a positive crc status, it moves to the wait_s state if sdio_d0 is not low (the card is not busy). if a timeout occurs while the dpsm is in the busy state, it sets the data timeout flag and moves to the idle state. the data timer is enabled when the dpsm is in the wait_r or busy state, and generates the data timeout error: ? when transmitting data, the timeout occurs if the dpsm stays in the busy state for longer than the programmed timeout period ? when receiving data, the timeout occurs if the end of the data is not true, and if the dpsm stays in the wait_r state for longer than the programmed timeout period. data: data can be transferred from the card to the host or vice versa. data is transferred via the data lines . they are stored in a fifo of 32 words , each word is 32 bits wide. data fifo the data fifo (first-in-first-out) subunit is a data buffer with a transmit and receive unit. the fifo contains a 32-bit wide, 32-word deep data buffer, and transmit and receive logic. because the da ta fifo operates in the apb2 clock do main (pclk2), all signals from the subunits in the sdio clock domain (sdioclk) are resynchronized. table 107. data token format description start bit data crc16 end bit block data 0 - yes 1 stream data 0 - no 1 secure digital input/output interface (sdio) RM0033 716/1317 doc id 15403 rev 3 depending on the txact and rxact flags, the fifo can be disabled, transmit enabled, or receive enabled. txact and rxact are driven by the data path subunit and are mutually exclusive: ? the transmit fifo refers to the transmit logic and data buffer when txact is asserted ? the receive fifo refers to the receive logic and data buffer when rxact is asserted transmit fifo: data can be written to the transmit fifo through the apb2 interface when the sdio is enabled for transmission. the transmit fifo is accessible via 32 sequential addresses. the transmit fifo contains a data output register that holds the data word pointed to by the read pointer. when the data path subunit has loaded its shift register, it increments the read pointer and drives new data out. if the transmit fifo is disabled, all status flags are deasserted. the data path subunit asserts txact when it transmits data. receive fifo when the data path subunit receives a word of data, it drives the data on the write databus. the write pointer is incremented after the write operation completes. on the read side, the contents of the fifo word pointed to by the current value of the read pointer is driven onto the read databus. if the receive fifo is disabled, all status flags are deasserted, and the read and write pointers are reset. the data path subunit asserts rxact when it receives data. ta b l e 1 0 9 lists the receive fifo status flags. the receive fifo is accessible via 32 sequential addresses. table 108. transmit fifo status flags flag description txfifof set to high when all 32 tran smit fifo words contain valid data. txfifoe set to high when the transmit fifo does not contain valid data. txfifohe set to high when 8 or more transmit fifo words are empty. this flag can be used as a dma request. txdavl set to high when the transmit fifo contains valid data. this flag is the inverse of the txfifoe flag. txunderr set to high when an underrun error occurs. this flag is cleared by writing to the sdio clear register. RM0033 secure digital input/output interface (sdio) doc id 15403 rev 3 717/1317 26.3.2 sdio apb2 interface the apb2 interface generates the interrupt and dma request s, and accesses the sdio adapter registers and the data fifo. it consists of a data path, register decoder, and interrupt/dma logic. sdio interrupts the interrupt logic generates an interrupt request signal that is asserted when at least one of the selected status flags is high. a mask register is provided to allow selection of the conditions that will generate an interrupt. a status fl ag generates the inte rrupt request if a corresponding mask flag is set. sdio/dma interface: procedure for data transfers between the sdio and memory in the example shown, the transfer is from the sdio host controller to an mmc (512 bytes using cmd24 (write_block). the sdio fifo is filled by data stored in a memory using the dma controller. 1. do the card identification process 2. increase the sdio_ck frequency 3. select the card by sending cmd7 4. configure the dma2 as follows: a) enable dma2 controller and clear any pending interrupts b) program the dma2_stream3 or dma2_stream6 channel4 source address register with the memory location?s base address and dma2_stream3 or dma2_stream6 channel4 destination address register with the sdio_fifo register address c) program dma2_stream3 or dma2_stream6 channel4 control register (memory increment, not peripheral increment, peripheral and source width is word size) d) enable dma2_stream3 or dma2_stream6 channel4 table 109. receive fifo status flags flag description rxfifof set to high when all 32 receive fifo words contain valid data rxfifoe set to high when the receive fifo does not contain valid data. rxfifohf set to high when 8 or more receive fifo words contain valid data. this flag can be used as a dma request. rxdavl set to high when the receive fifo is not empty. this flag is the inverse of the rxfifoe flag. rxoverr set to high when an overrun error occurs. this flag is cleared by writing to the sdio clear register. secure digital input/output interface (sdio) RM0033 718/1317 doc id 15403 rev 3 5. send cmd24 (write_block) as follows: a) program the sdio data length register (sdio data timer register should be already programmed before the card identification process) b) program the sdio argument register with the address location of the card where data is to be transferred c) program the sdio command register: cmdindex with 24 (write_block); waitresp with ?1? (sdio card host waits for a response ); cpsmen with ?1? (sdio card host enabled to send a command). other fields are at their reset value. d) wait for sdio_sta[6] = cmdrend interrupt, then program the sdio data control register: dten with ?1? (sdi o card host enabled to send data); dtdir with ?0? (from controller to card); dtmode with ?0? (block data transfer); dmaen with ?1? (dma enabled); dblocksize with 0x9 (512 bytes). other fields are don?t care. e) wait for sdio_sta[10] = dbckend 6. check that no channels ar e still enabled by polling the dma enabled channel status register. 26.4 card functional description 26.4.1 card identification mode while in card identification mode the host resets all cards, validates the operation voltage range, identifies cards and sets a relative card address (rca) for each card on the bus. all data communications in the card identification mode use the command line (cmd) only. 26.4.2 card reset the go_idle_state command (cmd0) is the software reset command and it puts the multimediacard and sd memory in the idle state. the io_rw_direct command (cmd52) resets the sd i/o card. after power-up or cmd0, all cards output bus drivers are in the high- impedance state and the cards are initialized with a default relative card address (rca=0x0001) and with a default driver stage register setting (lowest speed, highest driving current capability). 26.4.3 operating voltage range validation all cards can communicate with the sdio card host using any operating voltage within the specification range. the supported minimum and maximum v dd values are defined in the operation conditions register (ocr) on the card. cards that store the card identification number (cid) and card specific data (csd) in the payload memory are able to communicate this information only under data-transfer v dd conditions. when the sdio card host module and the card have incompatible v dd ranges, the card is not able to complete the identifi cation cycle and cannot send csd data. for this purpose, the special commands, send_op_cond (cmd1), sd_app_op_cond (acmd41 for sd memory), and io_send_op_cond (cmd5 for sd i/o), are designed to provide a mechanism to identify and reject cards that do not match the v dd range desired by the sdio card host. the sdio card host sends the required v dd voltage window as the operand of these commands. cards that cannot perform data transfer in the specified range disconnect from the bus and go to the inactive state. RM0033 secure digital input/output interface (sdio) doc id 15403 rev 3 719/1317 by using these commands without including th e voltage range as the operand, the sdio card host can query each card and determine the common voltage range before placing out- of-range cards in the inactive state. this query is used when the sdio card host is able to select a common voltage range or when the user requires notification that cards are not usable. 26.4.4 card identification process the card identification process differs for multimediacards and sd cards. for multimediacard cards, the identification process starts at clock rate f od . the sdio_cmd line output drivers are open-drain and allow parallel card operation during this process. the registration process is accomplished as follows: 1. the bus is activated. 2. the sdio card host broadcasts send_op_cond (cmd1) to receive operation conditions. 3. the response is the wired and operation of the operation condition registers from all cards. 4. incompatible cards are placed in the inactive state. 5. the sdio card host broadcasts all_send_cid (cmd2) to all active cards. 6. the active cards simultaneously send their cid numbers serially. cards with outgoing cid bits that do not match the bits on the command line stop transmitting and must wait for the next identification cycle. one card su ccessfully transmits a full cid to the sdio card host and enters the identification state. 7. the sdio card host issues set_relative_addr (cmd3) to that card. this new address is called the relative card address (rca); it is shorter than the cid and addresses the card. the assigned card changes to the standby state, it does not react to further identification cycles, and its output switches from open-drain to push-pull. 8. the sdio card host repeats steps 5 through 7 until it receives a timeout condition. for the sd card, the identification process starts at clock rate f od , and the sdio_cmd line output drives are push-pull drivers instead of open-drain. the registration process is accomplished as follows: 1. the bus is activated. 2. the sdio card host broadcasts sd_app_op_cond (acmd41). 3. the cards respond with the contents of their operation condition registers. 4. the incompatible cards are placed in the inactive state. 5. the sdio card host broadcasts all_send_cid (cmd2) to all active cards. 6. the cards send back their unique card identification numbers (cids) and enter the identification state. 7. the sdio card host issues set_relative_addr (cmd3) to an active card with an address. this new address is called the relative card address (rca); it is shorter than the cid and addresses the card. the assigned card changes to the standby state. the sdio card host can reissue this command to change the rca. the rca of the card is the last assigned value. 8. the sdio card host repeats steps 5 through 7 with all active cards. secure digital input/output interface (sdio) RM0033 720/1317 doc id 15403 rev 3 for the sd i/o card, the registration process is accomplished as follows: 1. the bus is activated. 2. the sdio card host sends io_send_op_cond (cmd5). 3. the cards respond with the contents of their operation condition registers. 4. the incompatible cards are set to the inactive state. 5. the sdio card host issues set_relative_addr (cmd3) to an active card with an address. this new address is called the relative card address (rca); it is shorter than the cid and addresses the card. the assigned card changes to the standby state. the sdio card host can reissue this command to change the rca. the rca of the card is the last assigned value. 26.4.5 block write during block write (cmd24 - 27) one or more blocks of data are transferred from the host to the card with a crc appended to the end of each block by the host. a card supporting block write is always able to accept a block of data defined by write_bl_len. if the crc fails, the card indicates the failure on the sdio_d line and the transferred data are discarded and not written, and all further transmitted blocks (in multiple block write mode) are ignored. if the host uses partial blocks whose accumulated length is not block aligned and, block misalignment is not allowed (csd parameter write_blk_misalign is not set), the card will detect the block misalignment error before the beginning of the first misaligned block. (address_error error bit is set in the status register). the write operation will also be aborted if the host tries to write over a write-protected area. in this case, however, the card will set the wp_violation bit. programming of the cid and csd registers does not require a previous block length setting. the transferred data is also crc protected. if a part of the csd or cid register is stored in rom, then this unchangeable part must match the corresponding part of the receive buffer. if this match fails, then the card reports an error and does not change any register contents. some cards may require long and unpredictable times to write a block of data. after receiving a block of data and completing the crc check, the card begins writing and holds the sdio_d line low if its write buffer is fu ll and unable to accept new data from a new write_block command. the host may poll the status of the card with a send_status command (cmd13) at any time, and the card will respond wit h its status. the ready_for_data status bit indicates whether the card can accept new data or whether the write process is still in pr ogress. the host may deselect the card by issuing cmd7 (to select a different card), which will place the card in the disconnect state and release the sdio_d line(s) without interrupti ng the write operation. when se lecting the card again, it will reactivate busy indication by pulling sdio_d to low if programming is still in progress and the write buffer is unavailable. 26.4.6 block read in block read mode the basic unit of data transfer is a block whose maximum size is defined in the csd (read_bl_len). if read_bl_partial is set, smaller blocks whose start and end addresses are entirely contained within one physical block (as defined by read_bl_len) may also be transmitted. a crc is appended to the end of each block, ensuring data transfer integrity. cmd17 ( read_single_block ) initiates a block read and after completing the transfer, the card returns to the transfer state. cmd18 ( read_multiple_block ) starts a transfer of several consecutive blocks. RM0033 secure digital input/output interface (sdio) doc id 15403 rev 3 721/1317 the host can abort reading at any time, within a multiple block operation, regardless of its type. transaction abort is done by sending the stop transmission command. if the card detects an error (for example, out of range, address misalignment or internal error) during a multiple block read operation (both types) it stops the data transmission and remains in the data state. the host must than abort the operation by sending the stop transmission command. the read error is reported in the response to the stop transmission command. if the host sends a stop transm ission command after the card transmits the last block of a multiple block operation with a predefined number of blocks, it is responded to as an illegal command, since the card is no longer in the data state. if the host uses partial blocks whose accumulated length is not block-aligned and block misalignment is not allowed, the card detects a block misalignment error condition at the beginning of the first misaligned block (address_error error bit is se t in the status register). 26.4.7 stream access, stre am write and stream r ead (multimediacard only) in stream mode, data is transferred in bytes and no crc is appended at the end of each block. stream write (multimediacard only) write_dat_until_stop (cmd20) starts the data transfer from the sdio card host to the card, beginning at the specified address and continuing until the sdio card host issues a stop command. when partial blocks are allowed (csd parameter write_bl_partial is set), the data stream can start and stop at any address within the card address space, otherwise it can only start and stop at block boundaries. because the amount of data to be transferred is not determined in advance, a crc cannot be used. when the end of the memory range is reached while sending data and no stop command is sent by the sd card host, any additional transferred data are discarded. the maximum clock frequency for a stream write operation is given by the following equation fields of the card-specific data register: maximumspeed = maximum write frequency transpeed = maximum data transfer rate writebllen = maximum write data block length nsac = data read access time 2 in clk cycles taac = data read access time 1 r2wfactor = write speed factor if the host attempts to use a higher frequency, the card may not be able to process the data and stop programming, set the overrun error bit in the status register, and while ignoring all further data transfer, wait (in the receive data state) for a stop command. the write operation is also aborted if the host tries to write over a write-protected area. in this case, however, the card sets the wp_violation bit. maximumspeed min transpeed 82 writebllen () nsac ? () taac r2wfactor ------------------------------------------------------------------------ (, ) = secure digital input/output interface (sdio) RM0033 722/1317 doc id 15403 rev 3 stream read (multimediacard only) read_dat_until_stop (cmd11) controls a stream-oriented data transfer. this command instructs the card to send its data, starting at a specified address, until the sdio card host sends stop_transmission (cmd12). the stop command has an execution delay due to the serial command transmission and the data transfer stops after the end bit of the stop command. when the end of the memory range is reached while sending data and no stop command is sent by the sdio card host, any subsequent data sent are considered undefined. the maximum clock frequency for a stream read operation is given by the following equation and uses fields of the card specific data register. maximumspeed = maximum read frequency transpeed = maximum data transfer rate readbllen = maximum read data block length writebllen = maximum write data block length nsac = data read access time 2 in clk cycles taac = data read access time 1 r2wfactor = write speed factor if the host attempts to use a higher frequency, the card is not able to sustain data transfer. if this happens, the card sets the underrun error bit in the status register, aborts the transmission and waits in the data state for a stop command. 26.4.8 erase: group er ase and sector erase the erasable unit of the multimediacard is the erase group. the erase group is measured in write blocks, which are the basic writable units of the card. the size of the erase group is a card-specific parameter and defined in the csd. the host can erase a contiguous range of er ase groups. starting the erase process is a three-step sequence. first the host defines the start address of the range using the erase_group_start (cmd35) command, next it defines the last address of the range using the erase_group_end (cmd36) command and, finally, it starts the erase process by issuing the erase (cmd38) command. the address field in the erase commands is an erase group address in byte units. the card ignores all lsbs below the erase group size, effectively rounding the address down to the erase group boundary. if an erase command is received out of sequence, the card sets the erase_seq_error bit in the status register and resets the whole sequence. if an out-of-sequence (neither of the erase commands, except send_status) command received, the card sets the erase_reset status bit in th e status register, resets the erase sequence and executes the last command. if the erase range includes write protected blocks, they are left intact and only unprotected blocks are erased. the wp_erase_skip status bit in the status register is set. the card indicates that an erase is in progre ss by holding sdio_d low. the actual erase time may be quite long, and the host may issue cmd7 to deselect the card. maximumspeed min transpeed 82 readbllen () nsac ? () taac r2wfactor ----------------------------------------------------------------------- (, ) = RM0033 secure digital input/output interface (sdio) doc id 15403 rev 3 723/1317 26.4.9 wide bus select ion or deselection wide bus (4-bit bus width) operation mode is selected or deselected using set_bus_width (acmd6). the default bus width after power-up or go_idle_state (cmd0) is 1 bit. set_bus_width (acmd6) is only valid in a transfer state, which means that the bus width can be changed only after a card is selected by select/deselect_card (cmd7). 26.4.10 protection management three write protection methods for the cards are supported in the sdio card host module: 1. internal card write prot ection (card responsibility) 2. mechanical write protection switch (sdi o card host module responsibility only) 3. password-protected card lock operation internal card write protection card data can be protected against write and erase. by setting the permanent or temporary write-protect bits in the csd, the entire card can be permanently write-protected by the manufacturer or content provider. for cards that support write protection of groups of sectors by setting the wp_grp_enable bit in the csd, portions of the data can be protected, and the write protection can be changed by the application. the write protection is in units of wp_grp_size sectors as specified in the csd. the set_write_prot and clr_write_prot commands control the protection of the addressed group. the send_write_prot command is similar to a single block read command. the card sends a data block containing 32 write protection bits (representing 32 write protect groups starting at the specified address) followed by 16 crc bits. the address field in the write protect commands is a group address in byte units. the card ignores all lsbs below the group size. mechanical write protect switch a mechanical sliding tab on the side of the card allows the user to set or clear the write protection on a card. when the sliding tab is positioned with the window open, the card is write-protected, and when the window is closed, the card contents can be changed. a matched switch on the socket side indicates to the sdio card host module that the card is write-protected. the sdio card host module is responsible for protecting the card. the position of the write protect switch is unknown to the internal circuitry of the card. password protect the password protection feature enables the sdio card host module to lock and unlock a card with a password. the password is stored in the 128-bit pwd register and its size is set in the 8-bit pwd_len register. these registers are nonvolatile so that a power cycle does not erase them. locked cards respond to and execute certain commands. this means that the sdio card host module is allowed to re set, initialize, select, and query for status, however it is not allowed to access data on the card. when the password is set (as indicated by a nonzero value of pwd_len), the card is locked automatically after power-up. as with the csd and cid register write commands, the lock/unlock commands are available in the transfer state only. in this state, the command does not include an address argument and the card must be se lected before using it. the card lock/unlock commands have the structure and bus transaction types of a regular single-block write command. the transferred data block includes all of the required information for the command (the secure digital input/output interface (sdio) RM0033 724/1317 doc id 15403 rev 3 password setting mode, the pwd itself, and card lock/unlock). the command data block size is defined by the sdio card host module before it sends the card lock/unlock command, and has the structure shown in ta b l e 1 2 3 . the bit settings are as follows: erase: setting it forces an erase operation. all other bits must be zero, and only the command byte is sent lock_unlock: setting it locks the card. lock_ unlock can be set simultaneously with set_pwd, however not with clr_pwd clr_pwd: setting it cl ears the password data set_pwd: setting it saves the password data to memory pwd_len: it defines the length of the password in bytes pwd: the password (new or currently used, depending on the command) the following sections list the command sequences to set/reset a password, lock/unlock the card, and force an erase. setting the password 1. select a card ( select/deselect_card , cmd7), if none is already selected. 2. define the block length ( set_blocklen , cmd16) to send, given by the 8-bit card lock/unlock mode, the 8-bit pwd_len, and the number of bytes of the new password. when a password replacement is done, the block size must take into account that both the old and the new passwords are sent with the command. 3. send lock/unlock (cmd42) with the appropriate data block size on the data line including the 16-bit crc. the data block indicates the mode (set_pwd = 1), the length (pwd_len), and the password (pwd) itself. when a password replacement is done, the length value (pwd_len) includes the length of both passwords, the old and the new one, and the pwd field includes the old password (currently used) followed by the new password. 4. when the password is matched, the new password and its size are saved into the pwd and pwd_len fields, respectively. when the old password sent does not correspond (in size and/or content) to the expected password, the lock_unlock_failed error bit is set in the card status register, and the password is not changed. the password length field (pwd_len) indicates whether a password is currently set. when this field is nonzero, there is a password set and the card locks itself after power-up. it is possible to lock the card immediately in the current power session by setting the lock_unlock bit (while setting the password) or sending an additional command for card locking. resetting the password 1. select a card ( select/deselect_card , cmd7), if none is already selected. 2. define the block length ( set_blocklen , cmd16) to send, given by the 8-bit card lock/unlock mode, the 8-bit pwd_len , and the number of bytes in the currently used password. 3. send lock/unlock (cmd42) with the appropriate data block size on the data line including the 16-bit crc. the data block indicates the mode (clr_pwd = 1), the length (pwd_len) and the password (pwd) itself. the lock_unlock bit is ignored. 4. when the password is matched, the pwd field is cleared and pwd_len is set to 0. when the password sent does not correspond (in size and/or content) to the expected RM0033 secure digital input/output interface (sdio) doc id 15403 rev 3 725/1317 password, the lock_unlock_failed error bit is set in the card status register, and the password is not changed. locking a card 1. select a card ( select/deselect_card , cmd7), if none is already selected. 2. define the block length (set_blocklen, cmd16) to send, given by the 8-bit card lock/unlock mode (byte 0 in table 123 ), the 8-bit pwd_len, and the number of bytes of the current password. 3. send lock/unlock (cmd42) with the appropriate data block size on the data line including the 16-bit crc. the data block indicates the mode (lock_unlock = 1), the length (pwd_len), and the password (pwd) itself. 4. when the password is matched, the card is locked and the card_is_locked status bit is set in the card status register. when the password sent does not correspond (in size and/or content) to the expected password, the lock_unlock_failed error bit is set in the card status register, and the lock fails. it is possible to set the password and to lock the card in the same sequence. in this case, the sdio card host module performs all the required steps for setting the password (see setting the password on page 724 ), however it is necessary to set the lock_unlock bit in step 3 when the new password command is sent. when the password is previously set (pwd_len is not 0), the card is locked automatically after power on reset. an attempt to lock a locked card or to lock a card that does not have a password fails and the lock_unlock_failed error bit is set in the card status register. unlocking the card 1. select a card ( select/deselect_card , cmd7), if none is already selected. 2. define the block length ( set_blocklen , cmd16) to send, given by the 8-bit cardlock/unlock mode (byte 0 in table 123 ), the 8-bit pwd_len, and the number of bytes of the current password. 3. send lock/unlock (cmd42) with the appropriate data block size on the data line including the 16-bit crc. the data block indicates the mode (lock_unlock = 0), the length (pwd_len), and the password (pwd) itself. 4. when the password is matched, the card is unlocked and the card_is_locked status bit is cleared in the card status register. when the password sent is not correct in size and/or content and does not correspond to the expected password, the lock_unlock_failed error bit is set in the card status register, and the card remains locked. the unlocking function is only valid for the current power session. when the pwd field is not clear, the card is locked automatically on the next power-up. an attempt to unlock an unlocked card fails and the lock_unlock_failed error bit is set in the card status register. forcing erase if the user has forgotten the password (pwd conten t), it is possible to access the card after clearing all the data on the card. this forced erase operation erases all card data and all password data. secure digital input/output interface (sdio) RM0033 726/1317 doc id 15403 rev 3 1. select a card ( select/deselect_card , cmd7), if none is already selected. 2. set the block length ( set_blocklen , cmd16) to 1 byte. only the 8-bit card lock/unlock byte (byte 0 in ta b l e 1 2 3 ) is sent. 3. send lock/unlock (cmd42) with the appropriate data byte on the data line including the 16-bit crc. the data block indicates the mode (erase = 1). all other bits must be zero. 4. when the erase bit is the on ly bit set in the data field, all card contents are erased, including the pwd and pwd_len fields, and the card is no longer locked. when any other bits are set, the lock_unlock_failed error bit is set in the card status register and the card retains all of its data, and remains locked. an attempt to use a force erase on an unlocked card fails and the lock_unlock_failed error bit is set in the card status register. 26.4.11 card status register the response format r1 contains a 32-bit field named card status. this field is intended to transmit the card status information (which may be stored in a local status register) to the host. if not specified otherwise, the status entries are always related to the previously issued command. table 110 defines the different entries of the status. the type and clear condition fields in the table are abbreviated as follows: ty p e : e: error bit s: status bit r: detected and set for the actual command response x: detected and set during command execution. the sdio card host must poll the card by issuing the status command to read these bits. clear condition: a: according to the card current state b: always related to the previous command. reception of a valid command clears it (with a delay of one command) c: clear by read RM0033 secure digital input/output interface (sdio) doc id 15403 rev 3 727/1317 table 110. card status bits identifier type value description clear condition 31 address_ out_of_range e r x ?0?= no error ?1?= error the command address argument was out of the allowed range for this card. a multiple block or stream read/write operation is (although started in a valid address) attempting to read or write beyond the card capacity. c 30 address_misalign ?0?= no error ?1?= error the commands address argument (in accordance with the currently set block length) positions the first data block misaligned to the card physical blocks. a multiple block read/write operation (although started with a valid address/block-length combination) is attempting to read or write a data block which is not aligned with the physical blocks of the card. c 29 block_len_error ?0?= no error ?1?= error either the argument of a set_blocklen command exceeds the maximum value allowed for the card, or the previously defined block length is illegal for the current command (e.g. the host issues a write command, the current block length is smaller than the maximum allowed value for the card and it is not allowed to write partial blocks) c 28 erase_seq_error ?0?= no error ?1?= error an error in the sequence of erase commands occurred. c 27 erase_param e x ?0?= no error ?1?= error an invalid selection of erase groups for erase occurred. c 26 wp_violation e x ?0?= no error ?1?= error attempt to program a write-protected block. c 25 card_is_locked s r ?0? = card unlocked ?1? = card locked when set, signals that the card is locked by the host a 24 lock_unlock_ failed e x ?0?= no error ?1?= error set when a sequence or password error has been detected in lock/unlock card command c 23 com_crc_error e r ?0?= no error ?1?= error the crc check of the previous command failed. b 22 illegal_command e r ?0?= no error ?1?= error command not legal for the card state b 21 card_ecc_failed e x ?0?= success ?1?= failure card internal ecc was applied but failed to correct the data. c 20 cc_error e r ?0?= no error ?1?= error (undefined by the standard) a card error occurred, which is not related to the host command. c secure digital input/output interface (sdio) RM0033 728/1317 doc id 15403 rev 3 19 error e x ?0?= no error ?1?= error (undefined by the standard) a generic card error related to the (and detected during) execution of the last host command (e.g. read or write failures). c 18 reserved 17 reserved 16 cid/csd_overwrite e x ?0?= no error ?1?= error can be either of the following errors: ? the cid register has already been written and cannot be overwritten ? the read-only section of the csd does not match the card contents ? an attempt to reverse the copy (set as original) or permanent wp (unprotected) bits was made c 15 wp_erase_skip e x ?0?= not protected ?1?= protected set when only partial address space was erased due to existing write c 14 card_ecc_disabled s x ?0?= enabled ?1?= disabled the command has been executed without using the internal ecc. a 13 erase_reset ?0?= cleared ?1?= set an erase sequence was cleared before executing because an out of erase sequence command was received (commands other than cmd35, cmd36, cmd38 or cmd13) c 12:9 current_state s r 0 = idle 1 = ready 2 = ident 3 = stby 4 = tran 5 = data 6 = rcv 7 = prg 8 = dis 9 = btst 10-15 = reserved the state of the card when receiving the command. if the command execution causes a state change, it will be visible to the host in the response on the next command. the four bits are interpreted as a binary number between 0 and 15. b 8 ready_for_data s r ?0?= not ready ?1? = ready corresponds to buffer empty signalling on the bus 7 switch_error e x ?0?= no error ?1?= switch error if set, the card did not switch to the expected mode as requested by the switch command b 6reserved 5 app_cmd s r ?0? = disabled ?1? = enabled the card will expect acmd, or an indication that the command has been interpreted as acmd c 4 reserved for sd i/o card table 110. card status (continued) bits identifier type value description clear condition RM0033 secure digital input/output interface (sdio) doc id 15403 rev 3 729/1317 26.4.12 sd status register the sd status contains status bits that are related to the sd memory card proprietary features and may be used for future application-specific usage. the size of the sd status is one data block of 512 bits. the contents of this register are transmitted to the sdio card host if acmd13 is sent (cmd55 followed with cmd13). acmd13 can be sent to a card in transfer state only (card is selected). table 111 defines the different entries of the sd status register. the type and clear condition fields in the table are abbreviated as follows: ty p e : e: error bit s: status bit r: detected and set for the actual command response x: detected and set during command execution. the sdio card host must poll the card by issuing the status command to read these bits clear condition: a: according to the card current state b: always related to the previous command. reception of a valid command clears it (with a delay of one command) c: clear by read 3 ake_seq_error e r ?0?= no error ?1?= error error in the sequence of the authentication process c 2 reserved for application specific commands 1 reserved for manufacturer test mode 0 table 110. card status (continued) bits identifier type value description clear condition table 111. sd status bits identifier type value description clear condition 511: 510 dat_bus_width s r ?00?= 1 (default) ?01?= reserved ?10?= 4 bit width ?11?= reserved shows the currently defined databus width that was defined by set_bus_width command a 509 secured_mode s r ?0?= not in the mode ?1?= in secured mode card is in secured mode of operation (refer to the ?sd security specification?). a 508: 496 reserved secure digital input/output interface (sdio) RM0033 730/1317 doc id 15403 rev 3 size_of_protected_area setting this field differs between standard- and high-capacity cards. in the case of a standard-capacity card, the capacity of protected area is calculated as follows: protected area = size_of_protected_area_* mult * block_len. size_of_protected_area is specifie d by the unit in mult*block_len. in the case of a high-capacity card, the capacity of protected area is specified in this field: protected area = size_of_protected_area size_of_protected_area is spec ified by the unit in bytes. speed_class this 8-bit field indicates the speed class and the value can be calculated by p w /2 (where p w is the write performance). 495: 480 sd_card_type s r ?00xxh?= sd memory cards as defined in physical spec ver1.01- 2.00 (?x?= don?t care). the following cards are currently defined: ?0000?= regular sd rd/wr card. ?0001?= sd rom card in the future, the 8 lsbs will be used to define different variations of an sd memory card (each bit will define different sd types). the 8 msbs will be used to define sd cards that do not comply with current sd physical layer specification. a 479: 448 size_of_prote ct ed_area s r size of protected area (see below) (see below) a 447: 440 speed_class s r speed class of the card (see below) (see below) a 439: 432 performance_ move s r performance of move indicated by 1 [mb/s] step. (see below) (see below) a 431:428 au_size s r size of au (see below) (see below) a 427:424 reserved 423:408 erase_size s r number of aus to be erased at a time (see below) a 407:402 erase_timeout s r timeout value for erasing areas specified by unit_of_erase_au (see below) a 401:400 erase_offset s r fixed offset value added to erase time. (see below) a 399:312 reserved 311:0 reserved for manufacturer table 111. sd status (continued) bits identifier type value description clear condition RM0033 secure digital input/output interface (sdio) doc id 15403 rev 3 731/1317 performance_move this 8-bit field indicates pm (performance move) and the value can be set by 1 [mb/sec] steps. if the card does not move used rus (rec ording units), pm should be considered as infinity. setting the field to ffh means infinity. au_size this 4-bit field indicates the au size and the value can be selected in the power of 2 base from 16 kb. table 112. speed class code field speed_class value definition 00h class 0 01h class 2 02h class 4 03h class 6 04h ? ffh reserved table 113. performance move field performance_move value definition 00h not defined 01h 1 [mb/sec] 02h 02h 2 [mb/sec] --------- --------- feh 254 [mb/sec] ffh infinity table 114. au_size field au_size value definition 00h not defined 01h 16 kb 02h 32 kb 03h 64 kb 04h 128 kb 05h 256 kb 06h 512 kb 07h 1 mb 08h 2 mb secure digital input/output interface (sdio) RM0033 732/1317 doc id 15403 rev 3 the maximum au size, which depends on the card capacity, is defined in ta b l e 1 1 5 . the card can be set to any au size between ru size and maximum au size. erase_size this 16-bit field indicates n erase . when n erase numbers of aus are erased, the timeout value is specified by erase_timeout (refer to erase_timeout ). the host should determine the proper number of aus to be erased in one operation so that the host can show the progress of the erase operation. if this field is set to 0, the erase timeout calculation is not supported. erase_timeout this 6-bit field indicates t erase and the value indicates the erase timeout from offset when multiple aus are being erased as sp ecified by erase_size. the range of erase_timeout can be defined as up to 63 seconds and the card manufacturer can choose any combination of erase_si ze and erase_timeout depending on the implementation. determining erase_ timeout determines the erase_size. 09h 4 mb ah ? fh reserved table 115. maximum au size capacity 16 mb-64 mb 128 mb-256 mb 512 mb 1 gb-32 gb maximum au size 512 kb 1 mb 2 mb 4 mb table 116. erase size field erase_size value definition 0000h erase timeout calculation is not supported. 0001h 1 au 0002h 2 au 0003h 3 au --------- --------- ffffh 65535 au table 117. erase timeout field erase_timeout value definition 00 erase timeout calculation is not supported. 01 1 [sec] 02 2 [sec] 03 3 [sec] table 114. au_size field (continued) au_size value definition RM0033 secure digital input/output interface (sdio) doc id 15403 rev 3 733/1317 erase_offset this 2-bit field indicates t offset and one of four values can be selected. this field is meaningless if the erase_size and erase_timeout fields are set to 0. 26.4.13 sd i/o mode sd i/o interrupts to allow the sd i/o card to interrupt the mult imediacard/sd module, an interrupt function is available on a pin on the sd interface. pin 8, used as sdio_d1 when operating in the 4-bit sd mode, signals the cards interrupt to the multimediacard/sd module. the use of the interrupt is optional for each card or function within a card. the sd i/o interrupt is level- sensitive, which means that the interrupt line must be held acti ve (low) until it is either recognized and acted upon by the multimediacard/sd module or deasserted due to the end of the interrupt period. after the multimediacard/sd module has serviced the interrupt, the interrupt status bit is cleared via an i/o write to the appropriate bit in the sd i/o card?s internal registers. the interrupt output of all sd i/o cards is active low and the multimediacard/sd module provides pull-up resistors on all da ta lines (sdio_d[3:0]). the multimediacard/sd module sample s the level of pin 8 (sdio_ d/irq) into the interrupt detector only during the interrupt period. at all other times, the multimediacard/sd module ignores this value. the interrupt period is applicable for both memory and i/o operations. the definition of the interrupt period for operations with single blocks is different from the definition for multiple- block data transfers. sd i/o suspend and resume within a multifunction sd i/o or a card with both i/o and memory functions, there are multiple devices (i/o and memory) that share access to the mmc/sd bu s. to share access to the mmc/sd module among multiple devices, sd i/o and combo cards optionally implement the concept of suspend/resume. when a card supports suspend/resume, the mmc/sd module can temporarily halt a data transfer operation to one function or memory (suspend) to free the bus for a higher-priority transfer to a different function or memory. after this higher-priority transfer is complete, the or iginal transfer is resume d (restarted) where it left off. support of suspend/resume is optional on a per-card basis. to perform the --------- --------- 63 63 [sec] table 118. erase offset field erase_offset value definition 0h 0 [sec] 1h 1 [sec] 2h 2 [sec] 3h 3 [sec] table 117. erase timeout field (continued) erase_timeout value definition secure digital input/output interface (sdio) RM0033 734/1317 doc id 15403 rev 3 suspend/resume operation on the mmc/sd bus, the mmc/sd module performs the following steps: 1. determines the function currently using the sdio_d [3:0] line(s) 2. requests the lower-priority or slower transaction to suspend 3. waits for the transaction suspension to complete 4. begins the higher-priority transaction 5. waits for the completion of the higher priority transaction 6. restores the suspended transaction sd i/o readwait the optional readwait (rw) operation is defined only for the sd 1-bit and 4-bit modes. the readwait operation allows the mmc/sd module to signal a card that it is reading multiple registers (io_rw_extended, cmd53) to tempor arily stall the data tr ansfer while allowing the mmc/sd module to send commands to any function within the sd i/o device. to determine when a card supports the readwait protocol, the mmc/sd module must test capability bits in the internal card registers. the timing for readwait is based on the interrupt period. 26.4.14 commands and responses application-specific and general commands the sd card host module system is designed to provide a standard interface for a variety of applications types. in this environment, ther e is a need for specific customer/application features. to implement these features, two types of generic commands are defined in the standard: application-specific commands (acmd) and general commands (gen_cmd). when the card receives the app_cmd (cmd 55) command, the card expects the next command to be an application-specific command. acmds have the same structure as regular multimediacard commands and can have the same cmd number. the card recognizes it as acmd be cause it appears after app_cm d (cmd55). when the command immediately following the app_cmd (cmd55) is not a defined application-specific command, the standard command is used. for example, when the card has a definition for sd_status (acmd13), and receives cmd 13 immediately following app_cmd (cmd55), this is interpreted as sd_status (acmd13). however, when the card receives cmd7 immediately following app_cmd (cmd55) and the card does not have a definition for acmd7, this is interpre ted as the standa rd (select/deselect_card) cmd7. to use one of the manufacturer-specific acmds the sd card host must perform the following steps: 1. send app_cmd (cmd55) the card responds to the mu ltimediacard/sd module, indi cating that the app_cmd bit is set and an acmd is now expected. 2. send the required acmd the card responds to the mu ltimediacard/sd module, indi cating that the app_cmd bit is set and that the accepted command is interpreted as an acmd. when a nonacmd is sent, it is handled by the card as a normal multimediacard command and the app_cmd bit in the card stat us register stays clear. when an invalid command is sent (neither acmd nor cmd) it is handled as a standard multimediacard illegal command error. RM0033 secure digital input/output interface (sdio) doc id 15403 rev 3 735/1317 the bus transaction for a gen_cmd is the same as the single-block read or write commands (write_block, cmd24 or read_single_block,cmd17). in this case, the argument denotes the direction of the data transfer rather than the address, and the data block has vendor-specific format and meaning. the card must be selected (in transfer state) before sending gen_cmd (cmd56). the data block size is defined by set_blocklen (cmd16). the response to gen_cmd (cmd56) is in r1b format. command types both application-specific and general commands are divided into the four following types: broadcast command (bc) : sent to all cards; no responses returned. broadcast command with response (bcr): sent to all cards; responses received from all cards simultaneously. addressed (point-to-point) command (ac): sent to the card that is selected; does not include a data transfer on the sdio_d line(s). addressed (point-to-point) data transfer command (adtc): sent to the card that is selected; includes a data transfer on the sdio_d line(s). command formats see table 103 on page 711 for command formats. commands for the multimediacard/sd module table 119. block-oriented write commands cmd index type argument response format abbreviation description cmd23 ac [31:16] set to 0 [15:0] number of blocks r1 set_block_count defines the number of blocks which are going to be transferred in the multiple-block read or write command that follows. cmd24 adtc [31:0] data address r1 write_block writes a block of the size selected by the set_blocklen command. cmd25 adtc [31:0] data address r1 write_multiple_block continuously writes blocks of data until a stop_transmission follows or the requested number of blocks has been received. cmd26 adtc [31:0] stuff bits r1 program_cid programming of the card identification register. this command must be issued only once per card. the card contains hardware to prevent this operation after the first programming. normally this command is reserved for manufacturer. cmd27 adtc [31:0] stuff bits r1 program_csd programming of the programmable bits of the csd. secure digital input/output interface (sdio) RM0033 736/1317 doc id 15403 rev 3 table 120. block-oriented write protection commands cmd index type argument response format abbreviation description cmd28 ac [31:0] data address r1b set_write_prot if the card has write protection features, this command sets the write protection bit of the addressed group. the properties of write protection are coded in the card- specific data (wp_grp_size). cmd29 ac [31:0] data address r1b clr_write_prot if the card provides write protection features, this command clears the write protection bit of the addressed group. cmd30 adtc [31:0] write protect data address r1 send_write_prot if the card provides write protection features, this command asks the card to send the status of the write protection bits. cmd31 reserved table 121. erase commands cmd index type argument response format abbreviation description cmd32 ... cmd34 reserved. these command indexes cannot be used in or der to maintain backward compatibility with older versions of the multimediacard. cmd35 ac [31:0] data address r1 erase_group_start sets the address of the first erase group within a range to be selected for erase. cmd36 ac [31:0] data address r1 erase_group_end sets the address of the last erase group within a continuous range to be selected for erase. cmd37 reserved. this command index cannot be used in order to maintain backward compatibility with older versions of the multimediacards cmd38 ac [31:0] stuff bits r1 erase erases all previously selected write blocks. table 122. i/o mode commands cmd index type argument response format abbreviation description cmd39 ac [31:16] rca [15:15] register write flag [14:8] register address [7:0] register data r4 fast_io used to write and read 8-bit (register) data fields. the command addresses a card and a register and provides the data for writing if the write flag is set. the r4 response contains data read from the addressed register. this command accesses application-dependent registers that are not defined in the multimediacard standard. RM0033 secure digital input/output interface (sdio) doc id 15403 rev 3 737/1317 26.5 response formats all responses are sent via the mccmd command line sdio_cmd. the response transmission always starts with the left bit of the bit string corresponding to the response code word. the code length depends on the response type. a response always starts with a start bit (always 0), followed by the bit indicating the direction of transmission (card = 0). a value denoted by x in the tables below indicates a variable entry. all responses, except for the r3 response type, are protected by a crc. every command code word is terminated by the end bit (always 1). there are five types of responses. their formats are defined as follows: cmd40 bcr [31:0] stuff bits r5 go_irq_state places the system in the interrupt mode. cmd41 reserved table 122. i/o mode commands (continued) cmd index type argument response format abbreviation description table 123. lock card cmd index type argument response format abbreviation description cmd42 adtc [31:0] stuff bits r1b lock_unlock sets/resets the password or locks/unlocks the card. the size of the data block is set by the set_block_len command. cmd43 ... cmd54 reserved table 124. application-specific commands cmd index type argument response format abbreviation description cmd55 ac [31:16] rca [15:0] stuff bits r1 app_cmd indicates to the card that the next command bits is an application specific command rather than a standard command cmd56 adtc [31:1] stuff bits [0]: rd/wr used either to transfer a data block to the card or to get a data block from the card for general purpose/application-s pecific commands. the size of the data block shall be set by the set_block_len command. cmd57 ... cmd59 reserved. cmd60 ... cmd63 reserved for manufacturer. secure digital input/output interface (sdio) RM0033 738/1317 doc id 15403 rev 3 26.5.1 r1 (normal response command) code length = 48 bits. the 45:40 bits indicate the index of the command to be responded to, this value being interpreted as a binary-coded number (between 0 and 63). the status of the card is coded in 32 bits. 26.5.2 r1b it is identical to r1 with an optional busy signal transmitted on the data line. the card may become busy after receiving these commands based on its state prior to the command reception. 26.5.3 r2 (cid, csd register) code length = 136 bits. the contents of the cid register are sent as a response to the cmd2 and cmd10 commands. the contents of the csd register are sent as a response to cmd9. only the bits [127...1] of the cid and csd are transferred, the reserved bit [0] of these registers is replaced by the end bit of the response. the card indicates that an erase is in progress by holding mcdat low. the actual erase time may be quite long, and the host may issue cmd7 to deselect the card. table 125. r1 response bit position width (bits value description 47 1 0 start bit 46 1 0 transmission bit [45:40] 6 x command index [39:8] 32 x card status [7:1] 7 x crc7 0 1 1 end bit table 126. r2 response bit position width (bits value description 135 1 0 start bit 134 1 0 transmission bit [133:128] 6 ?111111? command index [127:1] 127 x card status 0 1 1 end bit RM0033 secure digital input/output interface (sdio) doc id 15403 rev 3 739/1317 26.5.4 r3 (ocr register) code length: 48 bits. the contents of the ocr register are sent as a response to cmd1. the level coding is as follows: restricted voltage windows = low, card busy = low. 26.5.5 r4 (fast i/o) code length: 48 bits. the argument field contains the rca of the addressed card, the register address to be read out or written to, and its content. 26.5.6 r4b for sd i/o only: an sdio card receiving the cmd5 will respond with a unique sdio response r4. the format is: table 127. r3 response bit position width (bits value description 47 1 0 start bit 46 1 0 transmission bit [45:40] 6 ?111111? reserved [39:8] 32 x ocr register [7:1] 7 ?1111111? reserved 0 1 1 end bit table 128. r4 response bit position width (bits value description 47 1 0 start bit 46 1 0 transmission bit [45:40] 6 ?111111? reserved [39:8] argument field [31:16] 16 x rca [15:8] 8 x register address [7:0] 8 x read register contents [7:1] 7 ?1111111? crc7 0 1 1 end bit table 129. r4b response bit position width (bits value description 47 1 0 start bit 46 1 0 transmission bit [45:40] 6 x reserved secure digital input/output interface (sdio) RM0033 740/1317 doc id 15403 rev 3 once an sd i/o card has received a cmd5, the i/o portion of that card is enabled to respond normally to all further commands. this i/o enable of the function within the i/o card will remain set until a reset, powe r cycle or cmd52 with write to i/o reset is received by the card. note that an sd memory-only card may respond to a cmd5. the proper response for a memory-only card would be present memory = 1 and number of i/o functions = 0. a memory-only card built to meet the sd memory card specification version 1.0 would detect the cmd5 as an illegal command and not re spond. the i/o aware host will send cmd5. if the card responds with response r4, the host determines the card?s configuration based on the data contained within the r4 response. 26.5.7 r5 (interrupt request) only for multimediacard. code length: 48 bits. if the response is generated by the host, the rca field in the argument will be 0x0. [39:8] argument field 39 16 x card is ready [38:36] 3 x number of i/o functions 35 1 x present memory [34:32] 3 x stuff bits [31:8] 24 x i/o orc [7:1] 7 x reserved 0 1 1 end bit table 129. r4b response (continued) bit position width (bits value description table 130. r5 response bit position width (bits value description 47 1 0 start bit 46 1 0 transmission bit [45:40] 6 ?111111? cmd40 [39:8] argument field [31:16] 16 x rca [31:16] of winning card or of the host [15:0] 16 x not defined. may be used for irq data [7:1] 7 x crc7 0 1 1 end bit RM0033 secure digital input/output interface (sdio) doc id 15403 rev 3 741/1317 26.5.8 r6 only for sd i/o. the normal response to cmd3 by a memory device. it is shown in table 131 . the card [23:8] status bits are changed when cmd3 is sent to an i/o-only card. in this case, the 16 bits of response are the sd i/o-only values: bit [15] com_crc_error bit [14] illegal_command bit [13] error bits [12:0] reserved 26.6 sdio i/o card-specific operations the following features are sd i/o-specific operations: sdio read wait operation by sdio_d2 signalling sdio read wait operation by stopping the clock sdio suspend/resume operation (write and read suspend) sdio interrupts the sdio supports these operations only if the sdio_dctrl[11] bit is set, except for read suspend that does not need specific hardware implementation. 26.6.1 sdio i/o read wait oper ation by sdio_d2 signalling it is possible to start the readwait interval before the first block is received: when the data path is enabled (sdio_dctrl[0] bit set), the sdio-specific operation is enabled (sdio_dctrl[11] bit set), read wait starts (sdi0_dctrl[10] =0 and sdi_dctrl[8] =1) and data direction is from card to sdio (sdio_dctrl[1] = 1), the dpsm directly moves from idle to readwait. in readwait the dpsm drives sdio_d2 to 0 after 2 sdio_ck clock cycles. in this state, when you set the rwstop bit (sdio_dctrl[9]), the dpsm remains in wait for two more sdio_ck clock cycles to drive sdio_d2 to 1 for one clock cycle (in accordance with sdio specificat ion). the dpsm then starts wa iting again until it receives data from the card. the dpsm will not start a re adwait interval while receiving a block even if read wait start is set: the readwait interval will start after the crc is received. the rwstop bit has to be cleared to start a new read wait operation. during the readwait interval, the sdio can detect sdio interrupts on sdio_d1. table 131. r6 response bit position width (bits) value description 47 1 0 start bit 46 1 0 transmission bit [45:40] 6 ?101000? cmd40 [39:8] argument field [31:16] 16 x rca [31:16] of winning card or of the host [15:0] 16 x not defined. may be used for irq data [7:1] 7 x crc7 0 1 1 end bit secure digital input/output interface (sdio) RM0033 742/1317 doc id 15403 rev 3 26.6.2 sdio read wait opera tion by stopping sdio_ck if the sdio card does not support the previous read wait method, the sdio can perform a read wait by stopping sdio_ck (sdio_dctrl is set just like in the method presented in section 26.6.1 , but sdio_dctrl[10] =1): dspm stops the clock two sdio_ck cycles after the end bit of the current received block and starts the clock again after the read wait start bit is set. as sdio_ck is stopped, any command can be issued to the card. during a read/wait interval, the sdio can detect sdio interrupts on sdio_d1. 26.6.3 sdio suspend/resume operation while sending data to the card, the sdio can suspend the write operation. the sdio_cmd[11] bit is set and indicates to the cpsm that the current command is a suspend command. the cpsm analyzes the response and when the ack is received from the card (suspend accepted), it acknowledges the dpsm that goes idle after receiving the crc token of the current block. the hardware does not save the number of the remaining block to be sent to complete the suspended operation (resume). the write operation can be suspended by software, just by disabling the dpsm (sdio_dctrl[0] =0) when the ack of the suspend command is received from the card. the dpsm enters then the idle state. to suspend a read: the dpsm waits in the wait_r state as the function to be suspended sends a complete packet just before stopping the data transaction. the application continues reading rxfifo until the fif0 is empty, and the dpsm goes idle automatically. 26.6.4 sdio interrupts sdio interrupts are detected on the sdio_d1 line once the sdio_dctrl[11] bit is set. 26.7 ce-ata specific operations the following features are ce-ata specific operations: sending the command completion signal disable to the ce-ata device receiving the command completion signal from the ce-ata device signaling the completion of the ce-ata command to the cpu, using the status bit and/or interrupt. the sdio supports these operations only for the ce-ata cmd61 command, that is, if sdio_cmd[14] is set. 26.7.1 command completion signal disable command completion signal disable is sent 8 bit cycles after the reception of a short response if the ?enable cmd comp letion? bit, sdio_cmd[12], is not set and the ?not interrupt enable? bit, sdio_cmd[13], is set. the cpsm enters the pend state, loading the command shift register with the disable sequence ?00001? and, the command counter with 43. eight cycles after, a trigger moves RM0033 secure digital input/output interface (sdio) doc id 15403 rev 3 743/1317 the cpsm to the send state. when the command counter reaches 48, the cpsm becomes idle as no response is awaited. 26.7.2 command completion signal enable if the ?enable cmd completion? bit sdio_cmd[12] is set and the ?not interrupt enable? bit sdio_cmd[13] is set, the cpsm waits for the command completion signal in the waitcpl state. when ?0? is received on the cm d line, the cpsm enters the idle state. no new command can be sent for 7 bit cycles. then, for the last 5 cycles (out of the 7) the cmd line is driven to ?1? in push-pull mode. 26.7.3 ce-ata interrupt the command completion is signaled to the cpu by the status bit sdio_sta[23]. this static bit can be cleared with the clear bit sdio_icr[23]. the sdio_sta[23] status bit can generate an interrupt on each interrupt line, depending on the mask bit sdio_maskx[23]. 26.7.4 aborting cmd61 if the command completion disable signal has not been sent and cmd61 needs to be aborted, the command state machine must be disabled. it then becomes idle, and the cmd12 command can be sent. no command completion disable signal is sent during the operation. 26.8 hw flow control the hw flow control functionality is used to avoid fifo underrun (tx mode) and overrun (rx mode) errors. the behavior is to stop sdio_ck and freeze sdio state machines. the data transfer is stalled while the fifo is unable to transmit or receive data. only state machines clocked by sdioclk are frozen, the apb2 interface is still a live. the fifo can thus be filled or emptied even if flow control is activated. to enable hw flow control, the sdio_clkcr[14] register bit must be set to 1. after reset flow control is disabled. 26.9 sdio registers the device communicates to the system via 32-bit-wide control registers accessible via apb2. secure digital input/output interface (sdio) RM0033 744/1317 doc id 15403 rev 3 26.9.1 sdio power control register (sdio_power) address offset: 0x00 reset value: 0x0000 0000 note: at least seven hclk clock periods are needed between two write accesses to this register. note: after a data write, data cannot be written to this register for three sdioclk (48 mhz) clock periods plus two pclk2 clock periods. 26.9.2 sdi clock control register (sdio_clkcr) address offset: 0x04 reset value: 0x0000 0000 the sdio_clkcr register controls the sdio_ck output clock. 313029282726252423222120191817161514131211109876543210 reserved pwrc trl rw rw bits 31:2 reserved, always read as 0. [1:0] pwrctrl: power supply control bits. these bits are used to define the current functional state of the card clock: 00: power-off: the clock to card is stopped. 01: reserved 10: reserved power-up 11: power-on: the card is clocked. 313029282726252423222120191817161514131211109876543210 reserved hwfc_en negedge wid bus bypass pwrsav clken clkdiv rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:15 reserved, always read as 0. bit 14 hwfc_en: hw flow control enable 0b: hw flow control is disabled 1b: hw flow control is enabled when hw flow control is enabled, the me aning of the txfifoe and rxfifof interrupt signals, please see sdio status register definition in section 26.9.11 . bit 13 negedge: sdio_ck dephasing selection bit 0b: sdio_ck generated on the rising edge of the master clock sdioclk 1b: sdio_ck generated on the falling edge of the master clock sdioclk bits 12:11 widbus: wide bus mode enable bit 00: default bus mode: sdio_d0 used 01: 4-wide bus mode: sdio_d[3:0] used 10: 8-wide bus mode: sdio_d[7:0] used RM0033 secure digital input/output interface (sdio) doc id 15403 rev 3 745/1317 note: 1 while the sd/sdio card or multimediacard is in iden tification mode, the sdio_ck frequency must be less than 400 khz. 2 the clock frequency can be changed to the maximum card bus frequency when relative card addresses are assigned to all cards. 3 after a data write, data cannot be written to this register for three sdioclk (48 mhz) clock periods plus two pclk2 clock periods. sdio_ck can also be stopped during the read wait interval for sd i/o cards: in this case the sdio_clkcr register does not control sdio_ck. 26.9.3 sdio argument register (sdio_arg) address offset: 0x08 reset value: 0x0000 0000 the sdio_arg register contains a 32-bit command argument, which is sent to a card as part of a command message. bit 10 bypass: clock divider bypass enable bit 0: disable bypass: sdioclk is divided according to the clkdiv value before driving the sdio_ck output signal. 1: enable bypass: sdioclk directly drives the sdio_ck output signal. bit 9 pwrsav: power saving configuration bit for power saving, the sdio_ck clock output can be disabled when the bus is idle by setting pwrsav: 0: sdio_ck clock is always enabled 1: sdio_ck is only enabled when the bus is active bit 8 clken: clock enable bit 0: sdio_ck is disabled 1: sdio_ck is enabled bits 7:0 clkdiv: clock divide factor this field defines the divide factor between t he input clock (sdioclk) and the output clock (sdio_ck): sdio_ck frequency = sdioclk / [clkdiv + 2]. 313029282726252423222120191817161514131211109876543210 cmdarg rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:0 cmdarg: command argument command argument sent to a card as part of a command message. if a command contains an argument, it must be loaded into this regi ster before writing a command to the command register. secure digital input/output interface (sdio) RM0033 746/1317 doc id 15403 rev 3 26.9.4 sdio command register (sdio_cmd) address offset: 0x0c reset value: 0x0000 0000 the sdio_cmd register contains the command index and command type bits. the command index is sent to a card as part of a command message. the command type bits control the command path state machine (cpsm). note: 1 after a data write, data cannot be written to this register for three sdioclk (48 mhz) clock periods plus two pclk2 clock periods. 2 multimediacards can send two kinds of response: short responses, 48 bits long, or long responses,136 bits long. sd card and sd i/o card can send only short responses, the 313029282726252423222120191817161514131211109876543210 reserved ce-atacmd nien encmdcompl sdiosuspend cpsmen waitpend waitint waitresp cmdindex rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:15 reserved, always read as 0. bit 14 atacmd: ce-ata command if atacmd is set, the cpsm transfers cmd61. bit 13 nien: not interrupt enable if this bit is 0, interrupts in the ce-ata device are enabled. bit 12 encmdcompl: enable cmd completion if this bit is set, the command completion signal is enabled. bit 11 sdiosuspend: sd i/o suspend command if this bit is set, the command to be sent is a suspend command (to be used only with sdio card). bit 10 cpsmen: command path state machine (cpsm) enable bit if this bit is set, the cpsm is enabled. bit 9 waitpend: cpsm waits for ends of data transfer (cmdpend internal signal). if this bit is set, the cpsm waits for the end of data transfer before it starts sending a command. bit 8 waitint: cpsm waits for interrupt request if this bit is set, the cpsm disables command timeout and waits for an interrupt request. bits 7:6 waitresp: wait for response bits they are used to configure whether the cpsm is to wait for a response, and if yes, which kind of response. 00: no response, expect cmdsent flag 01: short response, expect cmdrend or ccrcfail flag 10: no response, expect cmdsent flag 11: long response, expect cmdrend or ccrcfail flag bit 5:0 cmdindex: command index the command index is sent to the card as part of a command message. RM0033 secure digital input/output interface (sdio) doc id 15403 rev 3 747/1317 argument can vary according to the type of response: the software will distinguish the type of response according to the sent command. ce-ata devices send only short responses. 26.9.5 sdio command response r egister (sdio_respcmd) address offset: 0x10 reset value: 0x0000 0000 the sdio_respcmd register contains the command index field of the last command response received. if the command response transmission does not contain the command index field (long or ocr response), the respc md field is unknown, although it must contain 111111b (the value of the reserved field from the response). 26.9.6 sdio response 1..4 register (sdio_respx) address offset: (0x10 + (4 x)); x = 1..4 reset value: 0x0000 0000 the sdio_resp1/2/3/4 registers contain the status of a card, which is part of the received response. the card status size is 32 or 127 bits, depending on the response type. the most significant bit of the card status is received first. the sdio_resp3 register lsb is always 0b. 313029282726252423222120191817161514131211109876543210 reserved respcmd rrrrrr bits 31:6 reserved, always read as 0. bits 5:0 respcmd: response command index read-only bit field. contains the command index of the last command response received. 313029282726252423222120191817161514131211109876543210 cardstatusx rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr bits 31:0 cardstatusx: see ta bl e 1 3 2 . table 132. response type and sdio_respx registers register short response long response sdio_resp1 card status[31: 0] card status [127:96] sdio_resp2 unused card status [95:64] sdio_resp3 unused card status [63:32] sdio_resp4 unused card status [31:1]0b secure digital input/output interface (sdio) RM0033 748/1317 doc id 15403 rev 3 26.9.7 sdio data timer r egister (sdio_dtimer) address offset: 0x24 reset value: 0x0000 0000 the sdio_dtimer register contains the data timeout period, in card bus clock periods. a counter loads the value from the sdio_dtimer register, and starts decrementing when the data path state machine (dpsm) enters the wait_r or busy state. if the timer reaches 0 while the dpsm is in either of these states, the timeout status flag is set. note: a data transfer must be written to the data timer register and the data length register before being written to the data control register. 26.9.8 sdio data length register (sdio_dlen) address offset: 0x28 reset value: 0x0000 0000 the sdio_dlen register contains the number of data bytes to be transferred. the value is loaded into the data counter when data transfer starts. note: for a block data transfer, the value in the data length register must be a multiple of the block size (see sdio_dctrl). a data transfer must be written to the data timer register and the data length register before being written to the data control register. for an sdio multibyte transfer the value in the data length register must be between 1 and 512. 313029282726252423222120191817161514131211109876543210 datatime rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:0 datatime: data timeout period data timeout period expressed in card bus clock periods. 313029282726252423222120191817161514131211109876543210 reserved datalength rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:25 reserved, always read as 0. bits 24:0 datalength: data length value number of data bytes to be transferred. RM0033 secure digital input/output interface (sdio) doc id 15403 rev 3 749/1317 26.9.9 sdio data control re gister (sdio_dctrl) address offset: 0x2c reset value: 0x0000 0000 the sdio_dctrl register control the data path state machine (dpsm). 313029282726252423222120191817161514131211109876543210 reserved sdioen rwmod rwstop rwstart dblocksize dmaen dtmode dtdir dten rw rw rw rw rw rw rw rw rw rw rw rw bits 31:12 reserved, always read as 0. bit 11 sdioen: sd i/o enable functions if this bit is set, the dpsm perform s an sd i/o-card-specific operation. bit 10 rwmod: read wait mode 0: read wait control stopping sdio_d2 1: read wait control using sdio_ck bit 9 rwstop: read wait stop 0: read wait in progress if rwstart bit is set 1: enable for read wait stop if rwstart bit is set bit 8 rwstart: read wait start if this bit is set, read wait operation starts. bits 7:4 dblocksize: data block size define the data block length when the block data transfer mode is selected: 0000: (0 decimal) lock length = 2 0 = 1 byte 0001: (1 decimal) lock length = 2 1 = 2 bytes 0010: (2 decimal) lock length = 2 2 = 4 bytes 0011: (3 decimal) lock length = 2 3 = 8 bytes 0100: (4 decimal) lock length = 2 4 = 16 bytes 0101: (5 decimal) lock length = 2 5 = 32 bytes 0110: (6 decimal) lock length = 2 6 = 64 bytes 0111: (7 decimal) lock length = 2 7 = 128 bytes 1000: (8 decimal) lock length = 2 8 = 256 bytes 1001: (9 decimal) lock length = 2 9 = 512 bytes 1010: (10 decimal) lock length = 2 10 = 1024 bytes 1011: (11 decimal) lock length = 2 11 = 2048 bytes 1100: (12 decimal) lock length = 2 12 = 4096 bytes 1101: (13 decimal) lock length = 2 13 = 8192 bytes 1110: (14 decimal) lock length = 2 14 = 16384 bytes 1111: (15 decimal) reserved bit 3 dmaen: dma enable bit 0: dma disabled. 1: dma enabled. secure digital input/output interface (sdio) RM0033 750/1317 doc id 15403 rev 3 note: after a data write, data cannot be written to this register for three sdioclk (48 mhz) clock periods plus two pclk2 clock periods. the meaning of the dtmode bit changes according to the value of the sdioen bit. when sdioen=0 and dtmode=1, the multimediacard stream mode is enabled, and when sdioen=1 and dtmode=1, the peripheral enables an sdio multibyte transfer. 26.9.10 sdio data counter register (sdio_dcount) address offset: 0x30 reset value: 0x0000 0000 the sdio_dcount register loads the value from the data length register (see sdio_dlen) when the dpsm moves from the idle state to the wait_r or wait_s state. as data is transferred, the counter decrements the value until it reaches 0. the dpsm then moves to the idle state and the data status end flag, dataend, is set. note: this register should be read only when the data transfer is complete. bit 2 dtmode: data transfer mode selection 1: stre am or sdio multibyte data transfer. 0: block data transfer 1: stream or sdio multibyte data transfer bit 1 dtdir: data transfer di rection selection 0: from controller to card. 1: from card to controller. [0] dten: data transfer enabled bit data transfer starts if 1b is written to the dt en bit. depending on the direction bit, dtdir, the dpsm moves to the wait_s, wait_r state or readwait if rw start is set immediately at the beginning of the transfer. it is not necessary to clear the enable bit after the end of a data transfer but the sdio_dctrl must be updated to enable a new data transfer 313029282726252423222120191817161514131211109876543210 reserved datacount rrrrrrrrrrrrrrrrrrrrrrrrr bits 31:25 reserved, always read as 0. bits 24:0 datacount: data count value when this bit is read, the number of remaining data bytes to be transferred is returned. write has no effect. RM0033 secure digital input/output interface (sdio) doc id 15403 rev 3 751/1317 26.9.11 sdio status r egister (sdio_sta) address offset: 0x34 reset value: 0x0000 0000 the sdio_sta register is a read-only register. it contains two types of flag: static flags (bits [23:22,10:0]): these bits remain asserted until they are cleared by writing to the sdio interrupt clear register (see sdio_icr) dynamic flags (bits [21:11]): these bits change state depending on the state of the underlying logic (for example, fifo full and empty flags are asserted and deasserted as data while written to the fifo) 313029282726252423222120191817161514131211109876543210 reserved ceataend sdioit rxdavl txdavl rxfifoe txfifoe rxfifof txfifof rxfifohf txfifohe rxact txact cmdact dbckend stbiterr dataend cmdsent cmdrend rxoverr txunderr dtimeout ctimeout dcrcfail ccrcfail res. rrrrrrrrrrrrrrrrrrrrrrrr bits 31:24 reserved, always read as 0. bit 23 ceataend: ce-ata command completion signal received for cmd61 bit 22 sdioit: sdio interrupt received bit 21 rxdavl: data available in receive fifo bit 20 txdavl: data available in transmit fifo bit 19 rxfifoe: receive fifo empty bit 18 txfifoe: transmit fifo empty when hw flow control is enabled, txfifoe signals becomes activated when the fifo contains 2 words. bit 17 rxfifof: receive fifo full when hw flow control is enabled, rxfifof signals becomes activated 2 words before the fifo is full. bit 16 txfifof: transmit fifo full bit 15 rxfifohf: receive fifo half full: there ar e at least 8 words in the fifo bit 14 txfifohe: transmit fifo half empty: at leas t 8 words can be written into the fifo bit 13 rxact: data receive in progress bit 12 txact: data transmit in progress bit 11 cmdact: command transfer in progress bit 10 dbckend: data block sent/received (crc check passed) bit 9 stbiterr: start bit not detected on all data signals in wide bus mode bit 8 dataend: data end (data counter, sdidcount, is zero) bit 7 cmdsent: command sent (no response required) bit 6 cmdrend: command response received (crc check passed) bit 5 rxoverr: received fifo overrun error secure digital input/output interface (sdio) RM0033 752/1317 doc id 15403 rev 3 26.9.12 sdio interrupt cl ear register (sdio_icr) address offset: 0x38 reset value: 0x0000 0000 the sdio_icr register is a write-only r egister. writing a bit with 1b clears the corresponding bit in the sdio_sta status register. bit 4 txunderr: transmit fifo underrun error bit 3 dtimeout: data timeout bit 2 ctimeout: command response timeout the command timeout period has a fixed value of 64 sdio_ck clock periods. bit 1 dcrcfail: data block sent/received (crc check failed) bit 0 ccrcfail: command response received (crc check failed) 313029282726252423222120191817161514131211109876543210 reserved ceataendc sdioitc reserved dbckendc stbiterrc dataendc cmdsentc cmdrendc rxoverrc txunderrc dtimeoutc ctimeoutc dcrcfailc ccrcfailc rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:24 reserved, always read as 0. bit 23 ceataendc: ceataend flag clear bit set by software to clear the ceataend flag. 0: ceataend not cleared 1: ceataend cleared bit 22 sdioitc: sdioit flag clear bit set by software to clear the sdioit flag. 0: sdioit not cleared 1: sdioit cleared bits 21:11 reserved, always read as 0. bit 10 dbckendc: dbckend flag clear bit set by software to clear the dbckend flag. 0: dbckend not cleared 1: dbckend cleared bit 9 stbiterrc: stbiterr flag clear bit set by software to clear the stbiterr flag. 0: stbiterr not cleared 1: stbiterr cleared bit 8 dataendc: dataend flag clear bit set by software to clear the dataend flag. 0: dataend not cleared 1: dataend cleared RM0033 secure digital input/output interface (sdio) doc id 15403 rev 3 753/1317 bit 7 cmdsentc: cmdsent flag clear bit set by software to clear the cmdsent flag. 0: cmdsent not cleared 1: cmdsent cleared bit 6 cmdrendc: cmdrend flag clear bit set by software to clear the cmdrend flag. 0: cmdrend not cleared 1: cmdrend cleared bit 5 rxoverrc: rxoverr flag clear bit set by software to clear the rxoverr flag. 0: rxoverr not cleared 1: rxoverr cleared bit 4 txunderrc: txunderr flag clear bit set by software to clear txunderr flag. 0: txunderr not cleared 1: txunderr cleared bit 3 dtimeoutc: dtimeout flag clear bit set by software to clear the dtimeout flag. 0: dtimeout not cleared 1: dtimeout cleared bit 2 ctimeoutc: ctimeout flag clear bit set by software to clear the ctimeout flag. 0: ctimeout not cleared 1: ctimeout cleared bit 1 dcrcfailc: dcrcfail flag clear bit set by software to clear the dcrcfail flag. 0: dcrcfail not cleared 1: dcrcfail cleared bit 0 ccrcfailc: ccrcfail flag clear bit set by software to clear the ccrcfail flag. 0: ccrcfail not cleared 1: ccrcfail cleared secure digital input/output interface (sdio) RM0033 754/1317 doc id 15403 rev 3 26.9.13 sdio mask register (sdio_mask) address offset: 0x3c reset value: 0x0000 0000 the interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1b. 313029282726252423222120191817161514131211109876543210 reserved ceataendie sdioitie rxdavlie txdavlie rxfifoeie txfifoeie rxfifofie txfifofie rxfifohfie txfifoheie rxactie txactie cmdactie dbckendie stbiterrie dataendie cmdsentie cmdrendie rxoverrie txunderrie dtimeoutie ctimeoutie dcrcfailie ccrcfailie rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:24 reserved, always read as 0. bit 23 ceataendie: ce-ata command completion signal received interrupt enable set and cleared by software to enable/disabl e the interrupt generated when receiving the ce-ata command completion signal. 0: ce-ata command completion signal received interrupt disabled 1: ce-ata command completion signal received interrupt enabled bit 22 sdioitie: sdio mode interrupt received interrupt enable set and cleared by software to enable/disabl e the interrupt generated when receiving the sdio mode interrupt. 0: sdio mode interrupt received interrupt disabled 1: sdio mode interrupt received interrupt enabled bit 21 rxdavlie: data available in rx fifo interrupt enable set and cleared by software to enable/disable the interrupt generated by the presence of data available in rx fifo. 0: data available in rx fifo interrupt disabled 1: data available in rx fifo interrupt enabled bit 20 txdavlie: data available in tx fifo interrupt enable set and cleared by software to enable/disable the interrupt generated by the presence of data available in tx fifo. 0: data available in tx fifo interrupt disabled 1: data available in tx fifo interrupt enabled bit 19 rxfifoeie: rx fifo empty interrupt enable set and cleared by software to enable/di sable interrupt caused by rx fifo empty. 0: rx fifo empty interrupt disabled 1: rx fifo empty interrupt enabled bit 18 txfifoeie: tx fifo empty interrupt enable set and cleared by software to enable/di sable interrupt caused by tx fifo empty. 0: tx fifo empty interrupt disabled 1: tx fifo empty interrupt enabled bit 17 rxfifofie: rx fifo full interrupt enable set and cleared by software to enable/di sable interrupt caused by rx fifo full. 0: rx fifo full interrupt disabled 1: rx fifo full interrupt enabled RM0033 secure digital input/output interface (sdio) doc id 15403 rev 3 755/1317 bit 16 txfifofie: tx fifo full interrupt enable set and cleared by software to enable/disable interrupt caused by tx fifo full. 0: tx fifo full interrupt disabled 1: tx fifo full interrupt enabled bit 15 rxfifohfie: rx fifo half full interrupt enable set and cleared by software to enable/disa ble interrupt caused by rx fifo half full. 0: rx fifo half full interrupt disabled 1: rx fifo half full interrupt enabled bit 14 txfifoheie: tx fifo half empty interrupt enable set and cleared by software to enable/disa ble interrupt caused by tx fifo half empty. 0: tx fifo half em pty interrupt disabled 1: tx fifo half em pty interrupt enabled bit 13 rxactie: data receive acting interrupt enable set and cleared by software to enable/disable interrupt caused by data being received (data receive acting). 0: data receive acti ng interrupt disabled 1: data receive acti ng interrupt enabled bit 12 txactie: data transmit acting interrupt enable set and cleared by software to enable/disable interrupt caused by data being transferred (data transmit acting). 0: data transmit acting interrupt disabled 1: data transmit acting interrupt enabled bit 11 cmdactie: command acting interrupt enable set and cleared by software to enable/disable interrupt caused by a command being transferred (command acting). 0: command acting interrupt disabled 1: command acting interrupt enabled bit 10 dbckendie: data block end interrupt enable set and cleared by software to enable/disable interrupt caused by data block end. 0: data block end interrupt disabled 1: data block end interrupt enabled bit 9 stbiterrie: start bit error interrupt enable set and cleared by software to enable/disable interrupt caused by start bit error. 0: start bit error interrupt disabled 1: start bit error interrupt enabled bit 8 dataendie: data end interrupt enable set and cleared by software to enable/disable interrupt caused by data end. 0: data end interrupt disabled 1: data end interrupt enabled bit 7 cmdsentie: command sent interrupt enable set and cleared by software to enable/disable interrupt caused by sending command. 0: command sent interrupt disabled 1: command sent interrupt enabled secure digital input/output interface (sdio) RM0033 756/1317 doc id 15403 rev 3 26.9.14 sdio fifo counter register (sdio_fifocnt) address offset: 0x48 reset value: 0x0000 0000 the sdio_fifocnt register contains the remaining number of words to be written to or read from the fifo. the fifo counter loads the value from the data length register (see sdio_dlen) when the data transfer enable bit, dten, is set in the data control register (sdio_dctrl register) and the dpsm is at the idle state. if the data length is not word- aligned (multiple of 4), the remaining 1 to 3 bytes are regarded as a word. bit 6 cmdrendie: command response received interrupt enable set and cleared by software to enable/disable interrupt caused by receiving command response. 0: command response received interrupt disabled 1: command response received interrupt enabled bit 5 rxoverrie: rx fifo overrun error interrupt enable set and cleared by software to enable/disabl e interrupt caused by rx fifo overrun error. 0: rx fifo overrun error interrupt disabled 1: rx fifo overrun error interrupt enabled bit 4 txunderrie: tx fifo underrun error interrupt enable set and cleared by software to enable/disable interrupt caused by tx fifo underrun error. 0: tx fifo underrun error interrupt disabled 1: tx fifo underrun error interrupt enabled bit 3 dtimeoutie: data timeout interrupt enable set and cleared by software to enable/disable interrupt caused by data timeout. 0: data timeout interrupt disabled 1: data timeout interrupt enabled bit 2 ctimeoutie: command timeout interrupt enable set and cleared by software to enable/disable interrupt caused by command timeout. 0: command timeout interrupt disabled 1: command timeout interrupt enabled bit 1 dcrcfailie: data crc fail interrupt enable set and cleared by software to enable/disable interrupt caused by data crc failure. 0: data crc fail interrupt disabled 1: data crc fail interrupt enabled bit 0 ccrcfailie: command crc fail interrupt enable set and cleared by software to enable/disable interrupt caused by command crc failure. 0: command crc fail interrupt disabled 1: command crc fail interrupt enabled 313029282726252423222120191817161514131211109876543210 reserved fifocount rrrrrrrrrrrrrrrrrrrrrrrr bits 31:24 reserved, always read as 0. bits 23:0 fifocount: remaining number of words to be written to or read from the fifo. RM0033 secure digital input/output interface (sdio) doc id 15403 rev 3 757/1317 26.9.15 sdio data fifo register (sdio_fifo) address offset: 0x80 reset value: 0x0000 0000 the receive and transmit fifos can be read or written as 32-bit wide registers. the fifos contain 32 entries on 32 sequential addresses. this allows the cpu to use its load and store multiple operands to read from/write to the fifo. 26.9.16 sdio register map the following table summarizes the sdio registers. 313029282726252423222120191817161514131211109876543210 fif0data rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:0 fifodata: receive and transmit fifo data the fifo data occupies 32 entries of 32-bit words, from address: sdio base + 0x080 to sdio base + 0xfc. table 133. sdio register map offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 sdio_power reserved pwrctrl 0x04 sdio_clkcr reserved hwfc_en negedge widbus bypass pwrsav clken clkdiv 0x08 sdio_arg cmdarg 0x0c sdio_cmd reserved ce-atacmd nien encmdcompl sdiosuspend cpsmen waitpend waitint waitresp cmdindex 0x10 sdio_respcm d reserved respcmd 0x14 sdio_resp1 cardstatus1 0x18 sdio_resp2 cardstatus2 0x1c sdio_resp3 cardstatus3 0x20 sdio_resp4 cardstatus4 0x24 sdio_dtimer datatime 0x28 sdio_dlen reserved datalength 0x2c sdio_dctrl reserved sdioen rwmod rwstop rwstart dblocksize dmaen dtmode dtdir dten 0x30 sdio_dcount reserved datacount 0x34 sdio_sta reserved ceataend sdioit rxdavl txdavl rxfifoe txfifoe rxfifof txfifof rxfifohf txfifohe rxact txact cmdact dbckend stbiterr dataend cmdsent cmdrend rxoverr txunderr dtimeout ctimeout dcrcfail ccrcfail secure digital input/output interface (sdio) RM0033 758/1317 doc id 15403 rev 3 refer to table 1 on page 50 for the register boundary addresses. 0x38 sdio_icr reserved ceataendc sdioitc reserved dbckendc stbiterrc dataendc cmdsentc cmdrendc rxoverrc txunderrc dtimeoutc ctimeoutc dcrcfailc ccrcfailc 0x3c sdio_mask reserved ceataendie sdioitie rxdavlie txdavlie rxfifoeie txfifoeie rxfifofie txfifofie rxfifohfie txfifoheie rxactie txactie cmdactie dbckendie stbiterrie dataendie cmdsentie cmdrendie rxoverrie txunderrie dtimeoutie ctimeoutie dcrcfailie ccrcfailie 0x48 sdio_fifocnt reserved fifocount 0x80 sdio_fifo fif0data table 133. sdio register map (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RM0033 controller area network (bxcan) doc id 15403 rev 3 759/1317 27 controller area network (bxcan) 27.1 bxcan introduction the basic extended can peripheral, named bxcan , interfaces the can network. it supports the can protocols version 2.0a and b. it has been designed to manage a high number of incoming messages efficiently with a minimum cpu load. it also meets the priority requirements for transmit messages. for safety-critical applications, the can cont roller provides all ha rdware functions for supporting the can time triggered communication option. 27.2 bxcan main features supports can protocol version 2.0 a, b active bit rates up to 1 mbit/s supports the time triggered communication option transmission three transmit mailboxes configurable transmit priority time stamp on sof transmission reception two receive fifos with three stages scalable filter banks: ? 28 filter banks shared between can1 and can2 identifier list feature configurable fifo overrun time stamp on sof reception time-triggered communication option disable automatic retransmission mode 16-bit free running timer time stamp sent in last two data bytes management maskable interrupts software-efficient mailbox mapping at a unique address space dual can can1: master bxcan for managing the communication between a slave bxcan and the 512-byte sram memory can2: slave bxcan, with no direct access to the sram memory. the two bxcan cells share the 512-byte sram memory (see figure 298: dual can block diagram ) controller area network (bxcan) RM0033 760/1317 doc id 15403 rev 3 27.3 bxcan general description in today?s can applications, the number of nodes in a network is increasing and often several networks are linked together via gateways. typically the number of messages in the system (and thus to be handled by each node) has significantly increased. in addition to the application messages, network management and diagnostic messages have been introduced. an enhanced filtering mechanism is required to handle each type of message. furthermore, application tasks require more cpu time, therefore real-time constraints caused by message reception have to be reduced. a receive fifo scheme allows the cpu to be dedicated to application tasks for a long time period without losing messages. the standard hlp (higher layer protocol) based on standard can drivers requires an efficient interface to the can controller. figure 297. can network topology 27.3.1 can 2.0b active core the bxcan module handles the transmission and the reception of can messages fully autonomously. standard identifiers (11-bit) and extended identifiers (29-bit) are fully supported by hardware. 27.3.2 control, status and configuration registers the application uses these registers to: configure can parameters, e.g. baud rate request transmissions handle receptions manage interrupts get diagnostic information 27.3.3 tx mailboxes three transmit mailboxes are provided to the software for setting up messages. the transmission scheduler decides which mailbox has to be transmitted first. can node 1 can node 2 can node n can can high low can can rx tx can transceiver can controller mcu can bus application RM0033 controller area network (bxcan) doc id 15403 rev 3 761/1317 27.3.4 acceptance filters the bxcan provides 28 scalable/configurable identifier filter banks for selecting the incoming messages the software needs and discarding the others. the bxcan provides 28 scalable/configurable identifier filter banks for selecting the incoming messages the software needs and discarding the others. in other devices there are 14 scalable/configurable identifier filter banks. receive fifo two receive fifos are used by hardware to store the incoming messages. three complete messages can be stored in each fifo. the fifos are managed completely by hardware. controller area network (bxcan) RM0033 762/1317 doc id 15403 rev 3 figure 298. dual can block diagram 27.4 bxcan operating modes bxcan has three main operating modes: initialization , normal and sleep . after a hardware reset, bxcan is in sleep mode to reduce power consumption and an internal pull- up is active on cantx. the software requests bxcan to enter initialization or sleep mode by setting the inrq or sleep bits in the can_mcr register. once the mode has been entered, bxcan confirms it by setting the inak or slak bits in the can_msr register and the internal pull-up is disabled. when neither inak nor slak are set, bxcan is in normal mode. before entering normal mode bxcan always has to synchronize on the can bus. 26 .. accept a nce filter s .. 3 2 1 filter 0 27 tr a n s mi ss ion s ched u ler m a il b ox 0 1 2 receive fifo 1 m a il b ox 0 1 2 receive fifo 0 m a il b ox 0 1 2 tx m a il b oxe s tr a n s mi ss ion s ched u ler m a il b ox 0 1 2 receive fifo 1 m a il b ox 0 1 2 receive fifo 0 m a il b ox 0 1 2 tx m a il b oxe s memory acce ss controller m as ter control m as ter s t a t us rx fifo 0 s t a t us rx fifo 1 s t a t us error s t a t us bit timing interr u pt en ab le control/ s t a t us /config u r a tion tx s t a t us m as ter control m as ter s t a t us rx fifo 0 s t a t us rx fifo 1 s t a t us error s t a t us bit timing filter mode filter s c a le interr u pt en ab le control/ s t a t us /config u r a tion tx s t a t us filter fifo a ss ign filter m as ter filter activ a tion can 2.0b active core can2 ( s lave) can 2.0b active core can1 (ma s ter) with 512 byte s s ram m as ter r e t s a m r e t s a m m as ter filter s s l a ve s l a ve s l a ve s l a ve filter s (n to 27) (0 to n) note: can 2 s t a rt filter ba nk n u m b er n i s config u r ab le b y writing to the can2 s b[5:0] b it s in the can_ fmr regi s ter. a i16094 RM0033 controller area network (bxcan) doc id 15403 rev 3 763/1317 to synchronize, bxcan waits until the can bus is idle, this means 11 consecutive recessive bits have been monitored on canrx. 27.4.1 initialization mode the software initializat ion can be done while the hardware is in initialization mode. to enter this mode the software sets the inrq bit in the can_mcr register and waits until the hardware has confirmed the request by setting the inak bit in the can_msr register. to leave initialization mode, the software clea rs the inqr bit. bxcan has left initialization mode once the inak bit has been cleared by hardware. while in initialization mode, all message transfers to and from the can bus are stopped and the status of the can bus output cantx is recessive (high). entering initialization mode does not change any of the configuration registers. to initialize the can controller, software ha s to set up the bit timing (can_btr) and can options (can_mcr) registers. to initialize the registers associated with the can filter banks (mode, scale, fifo assignment, activation and filter values), software has to set the finit bit (can_fmr). filter initialization also can be done outside the init ialization mode. note: when finit=1, can reception is deactivated. the filter values also can be modified by deacti vating the associated filter activation bits (in the can_fa1r register). if a filter bank is not used, it is recommended to leave it non active (leave the corresponding fact bit cleared). 27.4.2 normal mode once the initialization has been done, the software must request the hardware to enter normal mode, to synchronize on the can bus and start reception and transmission. entering normal mode is done by clearing the inrq bit in the can_mcr register and waiting until the hardware has confirmed the request by clearing the inak bit in the can_msr register. afterwards, the bxcan sync hronizes with the data transfer on the can bus by waiting for the occurrence of a sequence of 11 consecutive recessive bits ( bus idle) before it can take part in bus activities and start message transfer. the initialization of the filter values is independent from initialization mode but must be done while the filter is not active (corresponding factx bit cleared). the filter scale and mode configuration must be configured before entering normal mode. 27.4.3 sleep mode (low power) to reduce power consumption, bxcan has a low-power mode called sleep mode. this mode is entered on so ftware request by setting the sleep bit in the can_mcr register. in this mode, the bxcan clock is stopped, ho wever software can still access the bxcan mailboxes. if software requests entry to initialization mode by setting the inrq bit while bxcan is in sleep mode, it must also clear the sleep bit. bxcan can be woken up (exit sleep mode) eith er by software clearing the sleep bit or on detection of can bus activity. controller area network (bxcan) RM0033 764/1317 doc id 15403 rev 3 o n can b u s a c t i vity de te ct ion , h a r d w a re au t o ma tically pe rf or ms t h e w a k e u p se qu ence b y cle a r i n g th e slee p b i t if th e a w um b i t in t h e can _ m c r re g i ste r is s e t. if th e a w um b i t is cleared, softw a re has to clear the sleep bit when a w a k eup in terr upt occurs , in order to e x it fr om sle e p m o de . no te : if th e w a k e up in te rr u p t is e n a b l ed ( w kui e b i t s e t in can_ ier re g i ste r ) a w a k e u p inte r r up t will be gener a ted on detection of can b u s activity , e v en if the bxc a n automatic ally perf or ms t h e w a k e u p sequ ence . after the sleep bit has been cl eared, sleep mode is e x ited once bxca n has synchroniz ed with the can b u s , ref e r to figu re 2 99: bxcan op er a t in g mod e s . th e sleep mod e is e x it ed o n ce th e slak bit h a s bee n clear ed b y h a r d w a re . figu re 29 9. b x can ope rat i n g m o des 1. ack = the wait state during which hardwa r e confirms a reque st by settin g the inak or s l a k bits in the can_msr registe r 2. sync = the state durin g which bxcan waits until t he can b u s is idle, meaning 11 co nsecutive rece ssive bits ha ve be en monitored on canrx 27.5 t est mode t e st mo de can be sele ct ed b y th e si lm an d lbkm b i ts in t h e can_btr re giste r . th ese bit s m u s t be configured while bx can is in init ializat ion m ode . once t e st m ode h a s bee n se lec t ed , th e inrq b i t in t h e c a n_ mc r r e g i st er m u st be r e se t to e n t e r no r m a l m o d e . 27.5.1 silent mode th e bxcan can b e put in silen t mo de b y set t i ng t h e si lm bit in t he can_ btr r e g i st er . in sile nt m o d e , th e b xc a n is a b le to re ce iv e v a lid da ta fr a m es an d v a lid re mo te f r a m es , b u t it send s only r e cessiv e bit s on t h e can b u s a nd it can not sta r t a tr ansmission . i f th e b x can h a s t o sen d a do mina nt b i t ( a ck bit , o v er lo ad f l ag , a c t i v e er ro r f l ag) , t h e b i t is re rou t ed in te r n a lly so t hat t he can cor e mon i to rs th is d o min ant bit , a l th ou gh t he can b u s ma y re m a in in r e ce ss iv e sta t e . sile nt m o d e ca n be u se d to a n a l yz e th e tr af fic on a can b u s wit hou t a f f e ct ing it b y th e t r an smission o f do min ant bit s ( a c k n o wle dge bit s , err o r f r a m es). 3 l e e p ) n i t i a l i z a t i o n . o r m a l 2 e s e t 3 , ! + ) . ! + 3 , ! + ) . ! + 3 , ! + ) . ! + 3 , % % 0 ) . 2 1 ! # + 3 , % % 0 ) . 2 1 ! # + ) . 2 1 ! # + ) . 2 1 3 9 . # 3 , % % 0 3 , % % 0 ! # + 3 , % % 0 3 9 . # ) . 2 1 a i RM0033 controller area network (bxcan) doc id 15403 rev 3 765/1317 figure 300. bxcan in silent mode 27.5.2 loop back mode the bxcan can be set in loop back mode by setting the lbkm bit in the can_btr register. in loop back mode, the bxcan trea ts its own transmitted messages as received messages and stores them (if they pass acceptance filtering) in a receive mailbox. figure 301. bxcan in loop back mode this mode is provided for self-test functions. to be independent of external events, the can core ignores acknowledge errors (no dominant bit sampled in the acknowledge slot of a data / remote frame) in loop back mode. in this mode, the bxcan performs an internal feedback from its tx output to its rx input. the actual value of the canrx input pin is disregarded by the bxcan. the transmitted messages can be monitored on the cantx pin. 27.5.3 loop back combined with silent mode it is also possible to combine loop back mode and silent mode by setting the lbkm and silm bits in the can_btr register. this mode can be used for a ?hot selftest?, meaning the bxcan can be tested like in loop back mode but without affecting a running can system connected to the cantx and canrx pins. in this mode, the canrx pin is disconnected from the bxcan and the cantx pin is held recessive. bxcan cantx canrx tx rx =1 bxcan cantx canrx tx rx controller area network (bxcan) RM0033 766/1317 doc id 15403 rev 3 figure 302. bxcan in combined mode 27.6 stm32f20x and st m32f21x in debug mode when the microcontroller enters the debug mode (cortex-m3 core halted), the bxcan continues to work normally or stops, depending on: the dbg_can1_stop bit for can1 or the dbg_can2_stop bit for can2 in the dbg module. for more details, refer to section 32.16.2: debug support for timers, watchdog, bxcan and i 2 c . the dbf bit in can_mcr. fo r more details, refer to section 27.9.2: can control and status registers . 27.7 bxcan functional description 27.7.1 transmission handling in order to transmit a message, the application must select one empty transmit mailbox, set up the identifier, the data length code (dlc) and the data before requesting the transmission by setting the corresponding txrq bit in the can_tixr register. once the mailbox has left empty state, the software no longer has write access to the mailbox registers. immediately after the txrq bit has been set, the mailbox enters pending state and waits to become the highest priority mailbox, see transmit priority . as soon as the mailbox has the highest priority it will be scheduled for transmission. the transmission of the message of the scheduled mailbox will start (enter transmit state) when the can bus becomes idle. once the mailbox has been successfu lly transmitted, it will become empty again. the hardware indicates a successful transmission by setting the rqcp and txok bits in the can_tsr register. if the transmission fails, the cause is indicated by the alst bit in the can_tsr register in case of an arbitration lost, and/or the terr bit, in case of transmission error detection. transmit priority by identifier: when more than one transmit mailbox is pending, the transmission order is given by the identifier of the message stored in the mailbox. the message with the lowest identifier value has the highest priority according to the arbitration of the can protocol. if the identifier values are equal, the lower mailbox number will be scheduled first. by transmit request order: bxcan cantx canrx tx rx =1 RM0033 controller area network (bxcan) doc id 15403 rev 3 767/1317 the transmit mailboxes can be configured as a transmit fifo by setting the txfp bit in the can_mcr register. in this mode the priority order is given by the transmit request order. this mode is very useful for segmented transmission. abort a transmission request can be aborted by the user setting the abrq bit in the can_tsr register. in pending or scheduled state, the mailbox is aborted immediately. an abort request while the mailbox is in transmit state can have two results. if the mailbox is transmitted successfully the mailbox becomes empty with the txok bit set in the can_tsr register. if the transmis sion fails, the mailbox becomes scheduled, the transmission is aborted and becomes empty with txok cleared. in all cases the mailbox will become empty again at least at the end of the current transmission. nonautomatic retransmission mode this mode has been implemented in order to fulfil the requirement of the time triggered communication option of the can standard. to configure the hardware in this mode the nart bit in the can_mcr register must be set. in this mode, each transmission is started only once. if the first attempt fails, due to an arbitration loss or an error, the hardware will not automatically restart the message transmission. at the end of the first transmission attempt, the hardware considers the request as completed and sets the rqcp bit in the can_tsr register. the result of the transmission is indicated in the can_ts r register by the txok, alst and terr bits. figure 303. transmit mailbox states empty txrq=1 rqcp=x txok=x pending rqcp=0 txok=0 scheduled rqcp=0 txok=0 mailbox has transmit rqcp=0 txok=0 can bus = idle transmit failed * nart transmit succeeded mailbox does not empty rqcp=1 txok=0 highest priority have highest priority empty rqcp=1 txok=1 abrq=1 abrq=1 transmit failed * nart tme = 1 tme = 0 tme = 0 tme = 0 tme = 1 tme = 1 controller area network (bxcan) RM0033 768/1317 doc id 15403 rev 3 27.7.2 time triggered communication mode in this mode, the internal counter of the can hardware is activated and used to generate the time stamp value stored in the can_rdtxr/can _tdtxr registers, respectively (for rx and tx mailboxes). the internal counter is incremented each can bit time (refer to section 27.7.7: bit timing ). the internal counter is captured on the sample point of the start of frame bit in both reception and transmission. 27.7.3 reception handling for the reception of can messages, three mailboxes organized as a fifo are provided. in order to save cpu load, simplify the software and guarantee data consistency, the fifo is managed completely by hardware. the application accesses the messages stored in the fifo through the fifo output mailbox. valid message a received message is considered as valid when it has been received correctly according to the can protocol (no error until the last but one bit of the eof field) and it passed through the identifier filtering successfully, see section 27.7.4: identifier filtering . figure 304. receive fifo states empty valid message fmp=0x00 fovr=0 pending_1 fmp=0x01 fovr=0 received pending_2 fmp=0x10 fovr=0 pending_3 fmp=0x11 fovr=0 valid message received release overrun fmp=0x11 fovr=1 mailbox release mailbox valid message received valid message received release mailbox release mailbox valid message received rfom=1 rfom=1 rfom=1 RM0033 controller area network (bxcan) doc id 15403 rev 3 769/1317 fifo management starting from the empty state, the first valid message rece ived is stored in the fifo which becomes pending_1 . the hardware signals the event setting the fmp[1:0] bits in the can_rfr register to the value 01b. the messa ge is available in the fifo output mailbox. the software reads out the mailbox content and releases it by setting the rfom bit in the can_rfr register. the fifo becomes empty again. if a new valid message has been received in the meantime, the fifo stays in pending_1 state and the new message is available in the output mailbox. if the application does not rele ase the mailbox, the next valid message will be stored in the fifo which enters pending_2 state (fmp[1:0] = 10b). the storage process is repeated for the next valid message putting the fifo into pending_3 state (fmp[1:0] = 11b). at this point, the software must release the output mailbox by setting the rfom bit, so that a mailbox is free to store the next valid message. otherwise the next valid message received will cause a loss of message. refer also to section 27.7.5: message storage overrun once the fifo is in pending_3 state (i.e. the three mailboxes are full) the next valid message reception will lead to an overrun and a message will be lost. the hardware signals the overrun condition by setting the fovr bit in the can_rfr register. which message is lost depends on the configuration of the fifo: if the fifo lock function is disabled (rflm bit in the can_mcr register cleared) the last message stored in the fifo will be over written by the new incoming message. in this case the latest messages will be always available to the application. if the fifo lock function is enabled (rflm bit in the can_mcr register set) the most recent message will be discarde d and the software will have the three oldest messages in the fifo available. reception related interrupts once a message has been stored in the fifo, the fmp[1:0] bits are updated and an interrupt request is generated if the fmpie bit in the can_ier register is set. when the fifo becomes full (i.e. a third message is stored) the full bit in the can_rfr register is set and an interrupt is generated if the ffie bit in the can_ier register is set. on overrun condition, the fovr bit is set and an interrupt is generated if the fovie bit in the can_ier register is set. 27.7.4 identifier filtering in the can protocol the identifier of a message is not associated with the address of a node but related to the content of the message. consequently a transmitter broadcasts its message to all receivers. on message reception a receiver node decides - depending on the identifier value - whether the software needs the message or not. if the message is needed, it is copied into the sram. if not, the message must be discarded without intervention by the software. to fulfill this requirement, th e bxcan controller provides 28 28 configurable and scalable filter banks (2727-0) to the application. in other devices the bxcan controller provides 14 configurable and scalable filter banks (13-0) to the application in order to receive only the messages the software needs. this hardware filtering saves cpu resources which would be controller area network (bxcan) RM0033 770/1317 doc id 15403 rev 3 otherwise needed to perform filtering by software. each filter bank x consists of two 32-bit registers, can_fxr0 and can_fxr1. scalable width to optimize and adapt the filters to the application needs, each filter bank can be scaled independently. depending on the filter scale a filter bank provides: one 32-bit filter for the stdid[10:0], extid[17:0], ide and rtr bits. two 16-bit filters for the stdid[10:0], rtr, ide and extid[17:15] bits. refer to figure 305 . furthermore, the filters can be configured in mask mode or in identifier list mode. mask mode in mask mode the identifier registers are associat ed with mask registers specifying which bits of the identifier are handled as ?must match? or as ?don?t care?. identifier list mode in identifier list mode, the mask registers are used as identifier registers. thus instead of defining an identifier and a mask, two identifiers are specified, doubling the number of single identifiers. all bits of the incoming identifier must match the bits specified in the filter registers. filter bank scale and mode configuration the filter banks are configured by means of the corresponding can_fmr register. to configure a filter bank it must be deactivated by clearing the fact bit in the can_far register. the filter scale is configured by means of the corresponding fscx bit in the can_fs1r register, refer to figure 305 . the identifier list or identifier mask mode for the corresponding mask/identifier registers is configured by means of the fbmx bits in the can_fmr register. to filter a group of identifiers, configure the mask/identifier registers in mask mode. to select single identifiers, configure the ma sk/identifier registers in identifier list mode. filters not used by the application should be left deactivated. each filter within a filter b ank is numbered (called the filter number ) from 0 to a maximum dependent on the mode and the scale of each of the filter banks. concerning the filter configuration, refer to figure 305 . RM0033 controller area network (bxcan) doc id 15403 rev 3 771/1317 figure 305. filter bank scale configuration - register organization filter match index once a message has been received in the fifo it is available to the application. typically, application data is copied into sram locations. to copy the data to the right location the application has to identify the data by means of the identifier. to avoid this, and to ease the access to the sram location s, the can controller provides a filter match index. this index is stored in the mailbox together with the message according to the filter priority rules. thus each received message has its associated filter match index. the filter match index can be used in two ways: compare the filter match index with a list of expected values. use the filter match index as an index on an array to access the data destination location. for nonmasked filters, the software no longer has to compare the identifier. if the filter is masked the software reduces the comparison to the masked bits only. the index value of the filter number does not take into account the activation state of the filter banks. in addition, two independent numbering schemes are used, one for each fifo. refer to figure 306 for an example. one 32-bit filter - identifier mask two 16-bit filters - identifier mask can_fxr1[31:24] can_fxr2[31:24] can_fxr1[15:8] can_fxr1[31:24] can_fxr1[7:0] can_fxr1[23:16] x = filter bank number fscx = 1 fscx = 0 1 these bits are located in the can_fs1r register filter bank scale id mask id mask stid[10:3] stid[2:0] exid[12:5] mapping stid[10:3] id mask mapping rtr two 32-bit filters - identifier list id id stid[10:3] stid[2:0] exid[12:5] mapping four 16-bit filters - identifier list id id stid[10:3] id id mapping n n+1 n+2 n+3 n+1 filter bank mode 2 n n n+1 exid[4:0] ide exid[17:13] exid[17:13] stid[2:0] rtr ide exid[17:15] fbmx = 0 fbmx = 1 filter 2 these bits are located in the can_fm1r register n num. fbmx = 0 fbmx = 1 config. bits 1 stid[2:0] rtr ide exid[17:15] 0 rtr exid[4:0] ide 0 can_fxr1[23:16] can_fxr1[15:8] can_fxr1[7:0] can_fxr2[7:0] can_fxr2[15:8] can_fxr2[23:16] can_fxr1[31:24] can_fxr2[31:24] can_fxr1[23:16] can_fxr1[15:8] can_fxr1[7:0] can_fxr2[7:0] can_fxr2[15:8] can_fxr2[23:16] can_fxr2[15:8] can_fxr2[31:24] can_fxr2[7:0] can_fxr2[23:16] can_fxr1[15:8] can_fxr1[31:24] can_fxr1[7:0] can_fxr1[23:16] can_fxr2[15:8] can_fxr2[31:24] can_fxr2[7:0] can_fxr2[23:16] id=identifier controller area network (bxcan) RM0033 772/1317 doc id 15403 rev 3 figure 306. example of filter numbering filter priority rules depending on the filter combination it may occur that an identifier passes successfully through several filters. in this case the filter match value stored in the receive mailbox is chosen according to the following priority rules: a 32-bit filter takes priori ty over a 16-bit filter. for filters of equal scale, priority is given to the identifier list mode over the identifier mask mode for filters of equal scale and mode, priority is given by the filter number (the lower the number, the higher the priority). 9 8 id list (32-bit) id mask (32-bit) id list (16-bit) id list (32-bit) deactivated id mask (16-bit) id list (32-bit) filter 0 1 3 5 6 9 id mask (32-bit) 13 fifo0 filter 0 1 2 3 4 5 6 7 10 11 12 13 id mask (16-bit) id list (32-bit) id mask (16-bit) id list (16-bit) deactivated id mask (16-bit) id list (32-bit) filter 2 4 7 8 10 11 id mask (32-bit) 12 fifo1 filter 0 1 2 4 5 6 7 8 11 12 13 14 3 deactivated 9 10 num. num. bank bank id=identifier RM0033 controller area network (bxcan) doc id 15403 rev 3 773/1317 figure 307. filtering mechanism - example the example above shows the filtering principle of the bxcan. on reception of a message, the identifier is compared first with the filters configured in identifier list mode. if there is a match, the message is stored in the associated fifo and the index of the matching filter is stored in the filter match index. as shown in the example, the identifier matches with identifier #2 thus the message content and fmi 2 is stored in the fifo. if there is no match, the incoming identifier is then compared with the filters configured in mask mode. if the identifier does not match any of the identifiers configured in the filters, the message is discarded by hardware without disturbing the software. 27.7.5 message storage the interface between the software and the hardware for the can messages is implemented by means of mailboxes. a mailbox contains all information related to a message; identifier, data, control, status and time stamp information. transmit mailbox the software sets up the message to be transmitted in an empty transmit mailbox. the status of the transmission is indicated by hardware in the can_tsr register. identifier list message discarded identifier & mask identifier 0 identifier 1 identifier 4 identifier 5 identifier 2 mask identifier 3 mask identifier message received ctrl data identifier #4 match message stored receive fifo no match found filter number stored in the filter match index field within the can_rdtxr register fmi filter bank 0 2 3 1 4 example of 3 filter banks in 32-b it unidentified list mode and num the remaining in 32-bit identifier mask mode controller area network (bxcan) RM0033 774/1317 doc id 15403 rev 3 receive mailbox when a message has been received, it is available to the software in the fifo output mailbox. once the software has handled the message (e.g. read it) the software must release the fifo output mailbox by means of the rfom bit in the can_rfr register to make the next incoming message available. the f ilter match index is stored in the mfmi field of the can_rdtxr register. the 16-bit time stamp value is stored in the time[15:0] field of can_rdtxr. figure 308. can error state diagram table 134. transmit mailbox mapping offset to transmit mailbox base address register name 0can_tixr 4 can_tdtxr 8can_tdlxr 12 can_tdhxr table 135. receive mailbox mapping offset to receive mailbox base address (bytes) register name 0can_rixr 4 can_rdtxr 8can_rdlxr 12 can_rdhxr % 2 2 / 2 0 ! 3 3 ) 6 % 7 h e n 4 % # o r 2 % # 7 h e n 4 % # a n d 2 % # % 2 2 / 2 ! # 4 ) 6 % " 5 3 / & & 7 h e n 4 % # 7 h e n r e c e s s i v e b i t s o c c u r a i RM0033 controller area network (bxcan) doc id 15403 rev 3 775/1317 27.7.6 error management the error management as described in the can protocol is handled entirely by hardware using a transmit error counter (tec value, in can_esr register) and a receive error counter (rec value, in the can_esr register), which get incremented or decremented according to the error condition. for detailed information about tec and rec management, please refer to the can standard. both of them may be read by software to determine the stabilit y of the network. furthermore, the can hardware provides detailed information on the current error status in can_esr register. by means of the can_ier register (errie bit, etc.), the software can configure the interrupt generation on error detection in a very flexible way. bus-off recovery the bus-off state is reached when tec is greater than 255, this state is indicated by boff bit in can_esr register. in bus-off state, the bxcan is no longer able to transmit and receive messages. depending on the abom bit in the can_mcr register bxcan will recover from bus-off (become error active again) either automatically or on software request. but in both cases the bxcan has to wait at least for the recovery sequence specified in the can standard (128 occurrences of 11 consecutive recessive bits monitored on canrx). if abom is set, the bxcan will start the recove ring sequence automatic ally after it has entered bus-off state. if abom is cleared, the software must initiate the recovering sequence by requesting bxcan to enter and to le ave initialization mode. note: in initialization mode, bxcan does not mo nitor the canrx signal, therefore it cannot complete the recovery sequence. to recover, bxcan must be in normal mode . 27.7.7 bit timing the bit timing logic monitors the serial bus-line and performs sampling and adjustment of the sample point by synchronizing on the star t-bit edge and resynchronizing on the following edges. its operation may be explained simply by splitting nominal bit time into three segments as follows: synchronization segment (sync_seg) : a bit change is expected to occur within this time segment. it has a fixed length of one time quantum (1 x t can ). bit segment 1 (bs1) : defines the location of the sample point. it includes the prop_seg and phase_seg1 of the can standard. its duration is programmable between 1 and 16 time quanta but may be automatically lengthened to compensate for positive phase drifts due to differences in the frequency of the various nodes of the network. bit segment 2 (bs2) : defines the location of the transmit point. it represents the phase_seg2 of the can standard. its duration is programmable between 1 and 8 time quanta but may also be automatically shortened to compensate for negative phase drifts. the resynchronization jump width (sjw) defines an upper bound to the amount of lengthening or shortening of the bit segments. it is programmable between 1 and 4 time quanta. controller area network (bxcan) RM0033 776/1317 doc id 15403 rev 3 a valid edge is defined as the first transition in a bit time from dominant to recessive bus level provided the controller itself does not send a recessive bit. if a valid edge is detected in bs1 instead of sync_seg, bs1 is extended by up to sjw so that the sample point is delayed. conversely, if a valid edge is detected in bs2 instead of sync_seg, bs2 is shortened by up to sjw so that the transmit point is moved earlier. as a safeguard against programming errors, t he configuration of the bit timing register (can_btr) is only possible while the device is in standby mode. note: for a detailed description of the can bit timing and resynchronization mechanism, please refer to the iso 11898 standard. figure 309. bit timing sync_seg bit segment 1 (bs1) bit segment 2 (bs2) nominal bit time 1 x t q t bs1 t bs2 sample point transmit point nominalbittime 1 t q t bs1 t bs2 ++ = with: t bs1 = t q x (ts1[3:0] + 1), t bs2 = t q x (ts2[2:0] + 1), t q = (brp[9:0] + 1) x t pclk t pclk = time period of the apb clock, brp[9:0], ts1[3:0] and ts2[2:0] ar e defined in the can_btr register. baudrate 1 nominalbittime ---------------------------------------------- = where t q refers to the time quantum RM0033 controller area network (bxcan) doc id 15403 rev 3 777/1317 figure 310. can frames 27.8 bxcan interrupts four interrupt vectors are dedicated to bxcan. each interrupt source can be independently enabled or disabled by means of the can interrupt enable register (can_ier). data frame or remote frame data field 8 * n ctrl field 6 arbitration field 32 crc field 16 ack field 7 sof id dlc crc data frame (standard identifier) 44 + 8 * n arbitration field 32 rtr ide r0 sof id dlc remote frame 44 crc field 16 7 crc ctrl field 6 overload overload frame error 6 error delimiter 8 error frame flag echo 6 bus idle inter-frame space suspend 8 intermission 3 transmission ack ack 2 2 inter-frame space or overload frame inter-frame space inter-frame space or overload frame inter-frame space inter-frame space or overload frame notes: 0 <= n <= 8 sof = start of frame id = identifier rtr = remote transmission request ide = identifier extension bit r0 = reserved bit dlc = data length code crc = cyclic redundancy code error flag: 6 dominant bits if node is error active else 6 recessive bits. suspend transmission: applies to error passive nodes only. eof = end of frame ack = acknowledge bit ctrl = control data frame or remote frame any frame inter-frame space or error frame end of frame or error delimiter or overload delimiter ack field eof rtr ide r0 eof data field 8 * n ctrl field 6 32 crc field 16 ack field 7 sof id dlc crc data frame (extended identifier) 64 + 8 * n ack 2 inter-frame space or overload frame inter-frame space srr ide eof rtr r1 r0 32 6 overload 8 6 overload flag echo delimiter flag ai15154 arbitration field arbitration field controller area network (bxcan) RM0033 778/1317 doc id 15403 rev 3 figure 311. event flags and interrupt generation the transmit interrupt can be generated by the following events: ? transmit mailbox 0 becomes empty, rqcp0 bit in the can_tsr register set. ? transmit mailbox 1 becomes empty, rqcp1 bit in the can_tsr register set. ? transmit mailbox 2 becomes empty, rqcp2 bit in the can_tsr register set. the fifo 0 interrupt can be generated by the following events: ? reception of a new message, fmp0 bits in the can_rf0r register are not ?00?. ? fifo0 full condition, full0 bit in the can_rf0r register set. ? fifo0 overrun condition, fovr0 bit in the can_rf0r register set. the fifo 1 interrupt can be generated by the following events: ? reception of a new message, fmp1 bits in the can_rf1r register are not ?00?. ? fifo1 full condition, full1 bit in the can_rf1r register set. ? fifo1 overrun condition, fovr1 bit in the can_rf1r register set. rqcp0 rqcp1 fmp1 can_tsr + tmeie can_ier transmit & fmpie1 full1 & ffie1 fovr1 & fovie1 & + can_rf1r fifo 1 ewgf ewgie epvf epvie boff bofie 1 lec 6 lecie & & & & can_esr + & errie interrupt interrupt fmp0 & fmpie0 full0 & ffie0 fovr0 & fovie0 + can_rf0r fifo 0 interrupt rqcp2 wkui & wkuie can_msr + interrupt error status change erri slaki slkie & can_msr RM0033 controller area network (bxcan) doc id 15403 rev 3 779/1317 the error and status change interrupt can be generated by the following events: ? error condition, for more details on error conditions please refer to the can error status register (can_esr). ? wakeup condition, sof monitored on the can rx signal. ? entry into sleep mode. 27.9 can registers 27.9.1 register access protection erroneous access to certain configuration registers can cause the hardware to temporarily disturb the whole can network. therefore the can_btr register can be modified by software only while the can hardwa re is in initialization mode. although the transmission of incorrect data will not cause problems at the can network level, it can severely disturb the application. a transmit mailbox can be only modified by software while it is in empty state, refer to figure 303: transmit mailbox states . the filter values can be modified either deactivating the associated filter banks or by setting the finit bit. moreover, the modification of the filter configuration (scale, mode and fifo assignment) in can_fmxr, can_fsxr and can_ffar registers can only be done when the filter initialization mode is se t (finit=1) in the can_fmr register. 27.9.2 can control an d status registers refer to section 1.1 for a list of abbreviations used in register descriptions. can master control register (can_mcr) address offset: 0x00 reset value: 0x0001 0002 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved dbf rw 1514131211109876543210 reset reserved ttcm abom awum nart rflm txfp sleep inrq rs rw rw rw rw rw rw rw rw bits 31:17 reserved, forced by hardware to 0. bit 16 dbf: debug freeze 0: can working during debug 1: can reception/transmission frozen dur ing debug. reception fifos can still be accessed/controlled normally. bit 15 reset: bxcan software master reset 0: normal operation. 1: force a master reset of the bxcan -> sl eep mode activated after reset (fmp bits and can_mcr register are initialized to the reset values). this bit is automatically reset to 0. controller area network (bxcan) RM0033 780/1317 doc id 15403 rev 3 bits 14:8 reserved, forc ed by hardware to 0. bit 7 ttcm : time triggered communication mode 0: time triggered communication mode disabled. 1: time triggered communication mode enabled note: for more information on time triggered communication mode, please refer to section 27.7.2: time triggered communication mode . bit 6 abom: automatic bus-off management this bit controls the behavior of the can hardware on leaving the bus-off state. 0: the bus-off state is left on software reques t, once 128 occurrences of 11 recessive bits have been monitored and the software has first set and cleared the inrq bit of the can_mcr register. 1: the bus-off state is left automatically by hardware once 128 occurrences of 11 recessive bits have been monitored. for detailed information on the bus-off state please refer to section 27.7.6: error management . bit 5 awum : automatic wakeup mode this bit controls the behavior of the can hardware on message reception during sleep mode. 0: the sleep mode is left on software request by clearing the sleep bit of the can_mcr register. 1: the sleep mode is left automatically by hardware on can message detection. the sleep bit of the can_mcr register and the slak bit of the can_msr register are cleared by hardware. bit 4 nart : no automatic retransmission 0: the can hardware will automatically re transmit the message until it has been successfully transmitted according to the can standard. 1: a message will be transmitted only once, independently of the transmission result (successful, error or arbitration lost). bit 3 rflm : receive fifo locked mode 0: receive fifo not locked on overrun. once a receive fifo is full the next incoming message will overwrite the previous one. 1: receive fifo locked against overrun. once a receive fifo is full the next incoming message will be discarded. bit 2 txfp : transmit fifo priority this bit controls the transmission order when several mailboxes are pending at the same time. 0: priority driven by the identifier of the message 1: priority driven by the request order (chronologically) bit 1 sleep : sleep mode request this bit is set by software to request the can hardware to enter the sleep mode. sleep mode will be entered as soon as the current ca n activity (transmission or reception of a can frame) has been completed. this bit is cleared by software to exit sleep mode. this bit is cleared by hardware when the awum bit is set and a sof bit is detected on the can rx signal. this bit is set after reset - can starts in sleep mode. RM0033 controller area network (bxcan) doc id 15403 rev 3 781/1317 can master status register (can_msr) address offset: 0x04 reset value: 0x0000 0c02 bit 0 inrq : initialization request the software clears this bit to switch the hardware into normal mode. once 11 consecutive recessive bits have been monitored on the rx signal the can hardware is synchronized and ready for transmission and reception. hardware signals this event by clearing the inak bit in the can_msr register. software sets this bit to request the can hardware to enter initialization mode. once software has set the inrq bit, the can ha rdware waits until the current can activity (transmission or reception) is completed before entering the initialization mode. hardware signals this event by setting the inak bit in the can_msr register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 reserved. rx samp rxm txm reserved slaki wkui erri slak inak rrrr rc_w1rc_w1rc_w1rr bits 31:12 reserved, forced by hardware to 0. bit 11 rx : can rx signal monitors the actual value of the can_rx pin. bit 10 samp : last sample point the value of rx on the last sample point (current received bit value). bit 9 rxm : receive mode the can hardware is currently receiver. bit 8 txm : transmit mode the can hardware is currently transmitter. bits 7:5 reserved, forced by hardware to 0. bit 4 slaki : sleep acknowledge interrupt when slkie=1, this bit is set by hardware to signal that the bxcan has entered sleep mode. when set, this bit generates a status change interrupt if the slkie bit in the can_ier register is set. this bit is cleared by software or by hardware, when slak is cleared. note: when slkie=0, no polling on slaki is possible. in this case the slak bit can be polled. bit 3 wkui : wakeup interrupt this bit is set by hardware to signal that a sof bit has been detected while the can hardware was in sleep mode. setting this bit generates a status c hange interrupt if the wkuie bit in the can_ier register is set. this bit is cleared by software. controller area network (bxcan) RM0033 782/1317 doc id 15403 rev 3 can transmit status register (can_tsr) address offset: 0x08 reset value: 0x1c00 0000 bit 2 erri : error interrupt this bit is set by hardware when a bit of the can_esr has been set on error detection and the corresponding interrupt in the can_ier is enabled. setting this bit generates a status change interrupt if the errie bit in the can_ier register is set. this bit is cleared by software. bit 1 slak : sleep acknowledge this bit is set by hardware and indicates to the software that the can hardware is now in sleep mode. this bit acknowledges the slee p mode request from the software (set sleep bit in can_mcr register). this bit is cleared by hardware when t he can hardware has left sleep mode (to be synchronized on the can bus). to be synchronized the hardware has to monitor a sequence of 11 consecutive rece ssive bits on the can rx signal. note: the process of leaving sleep mode is triggered when the sleep bit in the can_mcr register is cleared. please refer to the awum bit of the can_mcr register description for detailed informatio n for clearing sleep bit bit 0 inak : initialization acknowledge this bit is set by hardware and indicates to the software that the can hardware is now in initialization mode. this bit acknowledges the initialization request from the software (set inrq bit in can_mcr register). this bit is cleared by hardware when the can hardware has left the initialization mode (to be synchronized on the can bus). to be synchronized the hardware has to monitor a sequence of 11 consecutive rece ssive bits on the can rx signal. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 low2 low1 low0 tme2 tme1 tme0 code[1:0] abrq 2 reserved terr 2 alst2 txok 2 rqcp 2 rrrrrrrrrs rc_w1rc_w1rc_w1rc_w1 1514131211109876543210 abrq 1 reserved res. terr 1 alst1 txok 1 rqcp 1 abrq 0 reserved terr 0 alst0 txok 0 rqcp 0 rs rc_w1 rc_w1 rc_w1 rc_w1 rs rc_w1 rc_w1 rc_w1 rc_w1 bit 31 low2 : lowest priority flag for mailbox 2 this bit is set by hardware when more than one mailbox are pending for transmission and mailbox 2 has the lowest priority. bit 30 low1 : lowest priority flag for mailbox 1 this bit is set by hardware when more than one mailbox are pending for transmission and mailbox 1 has the lowest priority. bit 29 low0 : lowest priority flag for mailbox 0 this bit is set by hardware when more than one mailbox are pending for transmission and mailbox 0 has the lowest priority. note: the low[2:0] bits are set to zero when only one mailbox is pending. bit 28 tme2 : transmit mailbox 2 empty this bit is set by hardware when no transmit request is pending for mailbox 2. RM0033 controller area network (bxcan) doc id 15403 rev 3 783/1317 bit 27 tme1 : transmit mailbox 1 empty this bit is set by hardware when no transmit request is pending for mailbox 1. bit 26 tme0 : transmit mailbox 0 empty this bit is set by hardware when no transmit request is pending for mailbox 0. bits 25:24 code[1:0] : mailbox code in case at least one transmit mailbox is free, the code value is equal to the number of the next transmit mailbox free. in case all transmit mailboxes are pending, the code value is equal to the number of the transmit mailbox with the lowest priority. bit 23 abrq2 : abort request for mailbox 2 set by software to abort the transmission request for the corresponding mailbox. cleared by hardware when the mailbox becomes empty. setting this bit has no effect when the mailbox is not pending for transmission. bits 22:20 reserved, forced by hardware to 0. bit 19 terr2 : transmission error of mailbox 2 this bit is set when the previous tx failed due to an error. bit 18 alst2 : arbitration lost for mailbox 2 this bit is set when the previous tx failed due to an arbitration lost. bit 17 txok2 : transmission ok of mailbox 2 the hardware updates this bit after each transmission attempt. 0: the previous transmission failed 1: the previous transmission was successful this bit is set by hardware when the transmission request on mailbox 2 has been completed successfully. please refer to figure 303 . bit 16 rqcp2 : request completed mailbox2 set by hardware when the last request (transmit or abort) has been performed. cleared by software writing a ?1? or by hardware on transmission request (txrq2 set in can_tmid2r register). clearing this bit clears all the status bi ts (txok2, alst2 and terr2) for mailbox 2. bit 15 abrq1 : abort request for mailbox 1 set by software to abort the transmission request for the corresponding mailbox. cleared by hardware when the mailbox becomes empty. setting this bit has no effect when the mailbox is not pending for transmission. bits 14:12 reserved, forced by hardware to 0. bit 11 terr1 : transmission error of mailbox1 this bit is set when the previous tx failed due to an error. bit 10 alst1 : arbitration lost for mailbox1 this bit is set when the previous tx failed due to an arbitration lost. bit 9 txok1 : transmission ok of mailbox1 the hardware updates this bit after each transmission attempt. 0: the previous transmission failed 1: the previous transmission was successful this bit is set by hardware when the transmission request on mailbox 1 has been completed successfully. please refer to figure 303 controller area network (bxcan) RM0033 784/1317 doc id 15403 rev 3 can receive fifo 0 register (can_rf0r) address offset: 0x0c reset value: 0x00 bit 8 rqcp1 : request completed mailbox1 set by hardware when the last request (transmit or abort) has been performed. cleared by software writing a ?1? or by hardware on transmission request (txrq1 set in can_ti1r register). clearing this bit clears all the status bi ts (txok1, alst1 and terr1) for mailbox 1. bit 7 abrq0 : abort request for mailbox0 set by software to abort the transmission request for the corresponding mailbox. cleared by hardware when the mailbox becomes empty. setting this bit has no effect when the mailbox is not pending for transmission. bits 6:4 reserved, forced by hardware to 0. bit 3 terr0 : transmission error of mailbox0 this bit is set when the previous tx failed due to an error. bit 2 alst0 : arbitration lost for mailbox0 this bit is set when the previous tx failed due to an arbitration lost. bit 1 txok0 : transmission ok of mailbox0 the hardware updates this bit after each transmission attempt. 0: the previous transmission failed 1: the previous transmission was successful this bit is set by hardware when the transmission request on mailbox 1 has been completed successfully. please refer to figure 303 bit 0 rqcp0 : request completed mailbox0 set by hardware when the last request (transmit or abort) has been performed. cleared by software writing a ?1? or by hardware on transmission request (txrq0 set in can_ti0r register). clearing this bit clears all the status bi ts (txok0, alst0 and terr0) for mailbox 0. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876 5 4 3210 reserved rfom0 fovr0 full0 res. fmp0[1:0] rs rc_w1 rc_w1 r r bit 31:6 reserved, forced by hardware to 0. bit 5 rfom0 : release fifo 0 output mailbox set by software to release the output mailbox of the fifo. the output mailbox can only be released when at least one message is pending in the fifo. setting this bit when the fifo is empty has no effect. if at least two message s are pending in the fifo, the software has to release the output mailbox to access the next message. cleared by hardware when the output mailbox has been released. RM0033 controller area network (bxcan) doc id 15403 rev 3 785/1317 can receive fifo 1 register (can_rf1r) address offset: 0x10 reset value: 0x00 bit 4 fovr0 : fifo 0 overrun this bit is set by hardware when a new message has been received and passed the filter while the fifo was full. this bit is cleared by software. bit 3 full0 : fifo 0 full set by hardware when three messages are stored in the fifo. this bit is cleared by software. bit 2 reserved, forced by hardware to 0. bits 1:0 fmp0[1:0] : fifo 0 message pending these bits indicate how many messages are pending in the receive fifo. fmp is increased each time the hardware st ores a new message in to the fifo. fmp is decreased each time the software releases the output mailbox by setting the rfom0 bit. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876 5 43210 reserved rfom1 fovr1 full1 res. fmp1[1:0] rs rc_w1 rc_w1 r r bits 31:6 reserved, forced by hardware to 0. bit 5 rfom1 : release fifo 1 output mailbox set by software to release the output mailbox of the fifo. the output mailbox can only be released when at least one message is pending in the fifo. setting this bit when the fifo is empty has no effect. if at least two messages are pending in the fifo, the software has to release the output mailbox to access the next message. cleared by hardware when the output mailbox has been released. bit 4 fovr1 : fifo 1 overrun this bit is set by hardware when a new message has been received and passed the filter while the fifo was full. this bit is cleared by software. bit 3 full1 : fifo 1 full set by hardware when three messages are stored in the fifo. this bit is cleared by software. bit 2 reserved, forced by hardware to 0. bits 1:0 fmp1[1:0] : fifo 1 message pending these bits indicate how many message s are pending in the receive fifo1. fmp1 is increased each time the hardware stor es a new message in to the fifo1. fmp is decreased each time the software releases the output mailbox by setting the rfom1 bit. controller area network (bxcan) RM0033 786/1317 doc id 15403 rev 3 can interrupt enable register (can_ier) address offset: 0x14 reset value: 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved slkie wkuie rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 errie reserved lec ie bof ie epv ie ewg ie res. fov ie1 ff ie1 fmp ie1 fov ie0 ff ie0 fmp ie0 tme ie rw rw rw rw rw rw rw rw rw rw rw rw bits 31:18 reserved, forced by hardware to 0. bit 17 slkie : sleep interrupt enable 0: no interrupt when slaki bit is set. 1: interrupt generated when slaki bit is set. bit 16 wkuie : wakeup interrupt enable 0: no interrupt when wkui is set. 1: interrupt generated when wkui bit is set. bit 15 errie : error interrupt enable 0: no interrupt will be generated when an error condition is pending in the can_esr. 1: an interrupt will be generation when an error condition is pending in the can_esr. bits 14:12 reserved, forced by hardware to 0. bit 11 lecie : last error code interrupt enable 0: erri bit will not be set when the error code in lec[2:0] is set by hardware on error detection. 1: erri bit will be set when the error code in lec[2:0] is set by hardware on error detection. bit 10 bofie : bus-off interrupt enable 0: erri bit will not be set when boff is set. 1: erri bit will be set when boff is set. bit 9 epvie : error passive interrupt enable 0: erri bit will not be set when epvf is set. 1: erri bit will be set when epvf is set. bit 8 ewgie : error warning interrupt enable 0: erri bit will not be set when ewgf is set. 1: erri bit will be set when ewgf is set. bit 7 reserved, forced by hardware to 0. bit 6 fovie1 : fifo overrun interrupt enable 0: no interrupt when fovr is set. 1: interrupt generation when fovr is set. bit 5 ffie1 : fifo full interrupt enable 0: no interrupt when full bit is set. 1: interrupt generated when full bit is set. RM0033 controller area network (bxcan) doc id 15403 rev 3 787/1317 can error status register (can_esr) address offset: 0x18 reset value: 0x00 bit 4 fmpie1 : fifo message pending interrupt enable 0: no interrupt generated when stat e of fmp[1:0] bits are not 00b. 1: interrupt generated when stat e of fmp[1:0] bits are not 00b. bit 3 fovie0 : fifo overrun interrupt enable 0: no interrupt when fovr bit is set. 1: interrupt generated when fovr bit is set. bit 2 ffie0 : fifo full interrupt enable 0: no interrupt when full bit is set. 1: interrupt generated when full bit is set. bit 1 fmpie0 : fifo message pending interrupt enable 0: no interrupt generated when stat e of fmp[1:0] bits are not 00b. 1: interrupt generated when stat e of fmp[1:0] bits are not 00b. bit 0 tmeie : transmit mailbox empty interrupt enable 0: no interrupt when rqcpx bit is set. 1: interrupt generated when rqcpx bit is set. note: refer to section 27.8: bxcan interrupts . 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rec[7:0] tec[7:0] rrrrrrrrrrrrrrrr 1514131211109876543210 reserved lec[2:0] res. boff epvf ewgf rw rw rw r r r bits 31:24 rec[7:0] : receive error counter the implementing part of the fault confinement mechanism of the can protocol. in case of an error during reception, this counter is incremented by 1 or by 8 depending on the error condition as defined by the can standard. afte r every successful rec eption the counter is decremented by 1 or reset to 120 if its value was higher than 128. when the counter value exceeds 127, the can controller enters the error passive state. bits 23:16 tec[7:0] : least significant byte of the 9-bit transmit error counter the implementing part of the fault confi nement mechanism of the can protocol. bits 15:7 reserved, forced by hardware to 0. controller area network (bxcan) RM0033 788/1317 doc id 15403 rev 3 can bit timing register (can_btr) address offset: 0x1c reset value: 0x0123 0000 note: this register can only be accessed by the software when the can hardware is in initialization mode. bits 6:4 lec[2:0] : last error code this field is set by hardware and holds a code which indicates the error condition of the last error detected on the can bus. if a me ssage has been transferred (reception or transmission) without error, this field will be cleared to ?0?. the lec[2:0] bits can be set to value 0b111 by software. they are updated by hardware to indicate the current communication status. 000: no error 001: stuff error 010: form error 011: acknowledgment error 100: bit recessive error 101: bit dominant error 110: crc error 111: set by software bit 3 reserved, forced by hardware to 0. bit 2 boff : bus-off flag this bit is set by hardware when it enters t he bus-off state. the bus-off state is entered on tec overflow, greater than 255, refer to section 27.7.6 on page 775 . bit 1 epvf : error passive flag this bit is set by hardware when the error passive limit has been reached (receive error counter or transmit error counter>127). bit 0 ewgf : error warning flag this bit is set by hardware when the warning limit has been reached (receive error counter or transmit error counter 96). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 silm lbkm reserved sjw[1:0] res. ts2[2:0] ts1[3:0] rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 reserved brp[9:0] rw rw rw rw rw rw rw rw rw rw bit 31 silm : silent mode (debug) 0: normal operation 1: silent mode bit 30 lbkm : loop back mode (debug) 0: loop back mode disabled 1: loop back mode enabled bits 29:26 reserved, forced by hardware to 0. RM0033 controller area network (bxcan) doc id 15403 rev 3 789/1317 27.9.3 can mailbox registers this chapter describes the registers of the transmit and receive mailboxes. refer to section 27.7.5: message storage on page 773 for detailed register mapping. transmit and receive mailboxes have the same registers except: the fmi field in the can_rdtxr register. a receive mailbox is always write protected. a transmit mailbox is write-enabled only while empty, corresponding tme bit in the can_tsr register set. there are 3 tx mailboxes and 2 rx mailboxes. ea ch rx mailbox allows access to a 3 level depth fifo, the access being offered only to the oldest received message in the fifo. each mailbox consist of 4 registers. bits 25:24 sjw[1:0] : resynchronization jump width these bits define the maximum number of time quanta the can hardware is allowed to lengthen or shorten a bit to perform the resynchronization. t rjw = t can x (sjw[1:0] + 1) bit 23 reserved, forced by hardware to 0. bits 22:20 ts2[2:0] : time segment 2 these bits define the number of time quanta in time segment 2. t bs2 = t can x (ts2[2:0] + 1) bits 19:16 ts1[3:0] : time segment 1 these bits define the number of time quanta in time segment 1 t bs1 = t can x (ts1[3:0] + 1) for more information on bit timing, please refer to section 27.7.7: bit timing on page 775 . bits 15:10 reserved, forced by hardware to 0. bits 9:0 brp[9:0] : baud rate prescaler these bits define the l ength of a time quanta. t q = (brp[9:0]+1) x t pclk can_ri0r can_rdt0r can_rl0r can_rh0r can_ti0r can_tdt0r can_tdl0r can_tdh0r fifo0 three tx mailboxes can_ri1r can_rdt1r can_rl1r can_rh1r fifo1 can_ti1r can_tdt1r can_tdl1r can_tdh1r can_ti2r can_tdt2r can_tdl2r can_tdh2r controller area network (bxcan) RM0033 790/1317 doc id 15403 rev 3 can tx mailbox identifier register (can_tixr) (x=0..2) address offsets: 0x180, 0x190, 0x1a0 reset value: undefined (except bit 0, txrq = 0) note: 1 all tx registers are write protected when the mailbox is pending transmission (tmex reset). 2 this register also implements the tx request control (bit 0) - reset value 0. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 stid[10:0]/exid[28:18] exid[17:13] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 exid[12:0] ide rtr txrq rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:21 stid[10:0]/exid[28:18] : standard identifier or extended identifier the standard identifier or the msbs of th e extended identifier (depending on the ide bit value). bit 20:3 exid[17:0] : extended identifier the lsbs of the extended identifier. bit 2 ide : identifier extension this bit defines the identifier type of message in the mailbox. 0: standard identifier. 1: extended identifier. bit 1 rtr : remote transmission request 0: data frame 1: remote frame bit 0 txrq : transmit mailbox request set by software to request the transmission for the corresponding mailbox. cleared by hardware when the mailbox becomes empty. RM0033 controller area network (bxcan) doc id 15403 rev 3 791/1317 can mailbox data length control and time stamp register (can_tdtxr) (x=0..2) all bits of this register are write protected when the mailbox is not in empty state. address offsets: 0x184, 0x194, 0x1a4 reset value: undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 time[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 reserved tgt reserved dlc[3:0] rw rw rw rw rw bits 31:16 time[15:0] : message time stamp this field contains the 16-bit timer value captured at the sof transmission. bits 15:9 reserved bit 8 tgt : transmit global time this bit is active only when the hardware is in the time trigger communication mode, ttcm bit of the can_mcr register is set. 0: time stamp time[15:0] is not sent. 1: time stamp time[15:0] value is sent in t he last two data bytes of the 8-byte message: time[7:0] in data byte 7 and time[15:8] in dat a byte 6, replacing the data written in can_tdhxr[31:16] register (data6[7:0] and da ta7[7:0]). dlc must be programmed as 8 in order these two bytes to be sent over the can bus. bits 7:4 reserved bits 3:0 dlc[3:0] : data length code this field defines the number of data bytes a data frame contains or a remote frame request. a message can contain from 0 to 8 data bytes, depending on the value in the dlc field. controller area network (bxcan) RM0033 792/1317 doc id 15403 rev 3 can mailbox data low register (can_tdlxr) (x=0..2) all bits of this register are write protected when the mailbox is not in empty state. address offsets: 0x188, 0x198, 0x1a8 reset value: undefined can mailbox data high register (can_tdhxr) (x=0..2) all bits of this register are write protected when the mailbox is not in empty state. address offsets: 0x18c, 0x19c, 0x1ac reset value: undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 data3[7:0] data2[7:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 data1[7:0] data0[7:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:24 data3[7:0] : data byte 3 data byte 3 of the message. bits 23:16 data2[7:0] : data byte 2 data byte 2 of the message. bits 15:8 data1[7:0] : data byte 1 data byte 1 of the message. bits 7:0 data0[7:0] : data byte 0 data byte 0 of the message. a message can contain from 0 to 8 da ta bytes and starts with byte 0. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 data7[7:0] data6[7:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 data5[7:0] data4[7:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:24 data7[7:0] : data byte 7 data byte 7 of the message. note: i f tgt of this message and ttcm are active , data7 and data6 will be replaced by the time stamp value. bits 23:16 data6[7:0] : data byte 6 data byte 6 of the message. bits 15:8 data5[7:0] : data byte 5 data byte 5 of the message. bits 7:0 data4[7:0] : data byte 4 data byte 4 of the message. RM0033 controller area network (bxcan) doc id 15403 rev 3 793/1317 can receive fifo mailbox identifier register (can_rixr) (x=0..1) address offsets: 0x1b0, 0x1c0 reset value: undefined note: all rx registers are write protected. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 stid[10:0]/exid[28:18] exid[17:13] rrrrrrrrrrrrrrrr 1514131211109876543210 exid[12:0] ide rtr res. rrrrrrrrrrrrrrr bits 31:21 stid[10:0]/exid[28:18] : standard identifier or extended identifier the standard identifier or the msbs of the ex tended identifier (depending on the ide bit value). bits 20:3 exid[17:0] : extended identifier the lsbs of the extended identifier. bit 2 ide : identifier extension this bit defines the identifier type of message in the mailbox. 0: standard identifier. 1: extended identifier. bit 1 rtr : remote transmission request 0: data frame 1: remote frame bit 0 reserved controller area network (bxcan) RM0033 794/1317 doc id 15403 rev 3 can receive fifo mailbox data length control and time stamp register (can_rdtxr) (x=0..1) address offsets: 0x1b4, 0x1c4 reset value: undefined note: all rx registers are write protected. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 time[15:0] rrrrrrrrrrrrrrrr 1514131211109876543210 fmi[7:0] reserved dlc[3:0] rrrrrrrr rrrr bits 31:16 time[15:0] : message time stamp this field contains the 16-bit timer value captured at the sof detection. bits 15:8 fmi[7:0] : filter match index this register contains the index of the fi lter the message stored in the mailbox passed through. for more details on identifier filtering please refer to section 27.7.4: identifier filtering on page 769 - filter match index paragraph. bits 7:4 reserved, forced by hardware to 0. bits 3:0 dlc[3:0] : data length code this field defines the number of data bytes a data frame contains (0 to 8). it is 0 in the case of a remote frame request. RM0033 controller area network (bxcan) doc id 15403 rev 3 795/1317 can receive fifo mailbox data low register (can_rdlxr) (x=0..1) all bits of this register are write protected when the mailbox is not in empty state. address offsets: 0x1b8, 0x1c8 reset value: undefined note: all rx registers are write protected. can receive fifo mailbox data high register (can_rdhxr) (x=0..1) address offsets: 0x1bc, 0x1cc reset value: undefined note: all rx registers are write protected. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 data3[7:0] data2[7:0] rrrrrrrrrrrrrrrr 1514131211109876543210 data1[7:0] data0[7:0] rrrrrrrrrrrrrrrr bits 31:24 data3[7:0] : data byte 3 data byte 3 of the message. bits 23:16 data2[7:0] : data byte 2 data byte 2 of the message. bits 15:8 data1[7:0] : data byte 1 data byte 1 of the message. bits 7:0 data0[7:0] : data byte 0 data byte 0 of the message. a message can contain from 0 to 8 data bytes and starts with byte 0. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 data7[7:0] data6[7:0] rrrrrrrrrrrrrrrr 1514131211109876543210 data5[7:0] data4[7:0] rrrrrrrrrrrrrrrr bits 31:24 data7[7:0] : data byte 7 data byte 3 of the message. bits 23:16 data6[7:0] : data byte 6 data byte 2 of the message. controller area network (bxcan) RM0033 796/1317 doc id 15403 rev 3 27.9.4 can filter registers can filter master register (can_fmr) address offset: 0x200 reset value: 0x2a1c 0e01 note: all bits of this register are set and cleared by software. bits 15:8 data5[7:0] : data byte 5 data byte 1 of the message. bits 7:0 data4[7:0] : data byte 4 data byte 0 of the message. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved 1514131211109876543210 reserved finit rw reserved can2sb[5:0] reserved finit rw rw rw rw rw rw rw bits 31:144 reserved, forced to reset value bits 13:8 can2sb[5:0] : can2 start bank these bits are set and cleared by software. they define the start bank for the can2 interface (slave) in the range 1 to 27. bits 7:1 reserved, forced to reset value bits 13:8 can2sb[5:0] : can2 start bank these bits are set and cleared by software. they define the start bank for the can2 interface (slave) in the range 1 to 27. bits 7:1 reserved, forced to reset value bit 0 finit : filter init mode initialization mode for filter banks 0: active filters mode. 1: initialization mode for the filters. RM0033 controller area network (bxcan) doc id 15403 rev 3 797/1317 can filter mode register (can_fm1r) address offset: 0x204 reset value: 0x00 note: this register can be written only when the f ilter initialization mode is set (finit=1) in the can_fmr register. note: please refer to figure 305: filter bank scale configuration - register organization on page 771 can filter scale register (can_fs1r) address offset: 0x20c reset value: 0x00 note: this register can be written only when the f ilter initialization mode is set (finit=1) in the can_fmr register. note: please refer to figure 305: filter bank scale configuration - register organization on page 771 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved fbm27 fbm26 fbm25 fbm24 fbm23 fbm22 fbm21 fbm20 fbm19 fbm18 fbm17 fbm16 rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 fbm15 fbm14 fbm13 fbm12 fbm11 fbm10 fbm9 fbm8 fbm7 fbm6 fbm5 fbm4 fbm3 fbm2 fbm1 fbm0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:28 reserved. forced to 0 by hardware. bits 27:0 fbm x : filter mode mode of the regist ers of filter x. 0: two 32-bit registers of filter bank x are in identifier mask mode. 1: two 32-bit registers of filter bank x are in identifier list mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved fsc27 fsc26 fsc25 fsc24 fsc23 fsc22 fsc21 fsc20 fsc19 fsc18 fsc17 fsc16 rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 fsc15 fsc14 fsc13 fsc12 fsc11 fsc10 fsc9 fs c8 fsc7 fsc6 fsc5 fsc4 fsc3 fsc2 fsc1 fsc0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:28 reserved, forced by hardware to 0. bits 27:0 fscx : filter scale configuration these bits define the scale configuration of filters 13-0. 0: dual 16-bit scale configuration 1: single 32-bit scale configuration controller area network (bxcan) RM0033 798/1317 doc id 15403 rev 3 can filter fifo assignment register (can_ffa1r) address offset: 0x214 reset value: 0x00 note: this register can be written only when the f ilter initialization mode is set (finit=1) in the can_fmr register. can filter activation register (can_fa1r) address offset: 0x21c reset value: 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved ffa27 ffa26 ffa25 ffa24 ffa23 ffa22 ffa21 ffa20 ffa19 ffa18 ffa17 ffa16 rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 ffa15 ffa14 ffa13 ffa12 ffa11 ffa10 ffa9 ffa8 ffa7 ffa6 ffa5 ffa4 ffa3 ffa2 ffa1 ffa0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:28 reserved, forced by hardware to 0. bits 27:0 ffa x : filter fifo assi gnment for filter x the message passing through this filter will be stored in the specified fifo. 0: filter assigned to fifo 0 1: filter assigned to fifo 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved fact27 fact26 fact25 fact24 fact23 fact22 fact21 fact20 fact19 fact18 fact17 fact16 rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 fact15 fact14 fact13 fact12 fact11 fact10 fact9 fact8 fact7 fact6 fact5 fact4 fact3 fact2 fact1 fact0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:28 reserved, forced by hardware to 0. bits 27:0 fact x : filter active the software sets this bit to activate filter x. to modify the filter x registers (can_fxr[0:7]), the factx bit must be cleared or the finit bit of the can_fmr register must be set. 0: filter x is not active 1: filter x is active RM0033 controller area network (bxcan) doc id 15403 rev 3 799/1317 filter bank i register x (can_firx) (i=0..27, x=1, 2) address offsets: 0x240..0x31c reset value: undefined note: there are 28 filter banks, i=0 .. 27. each filter bank i is composed of two 32-bit registers, can_fir[2:1]. this register can only be modified when the factx bit of the can_faxr register is cleared or when the finit bit of the can_fmr register is set. in all configurations: note: depending on the scale and mode configuration of the filter the function of each register can differ. for the filter mapping, functions description and mask registers association, refer to section 27.7.4: identifier filtering on page 769 . a mask/identifier register in mask mode has the same bit mapping as in identifier list mode. for the register mapping/addresses of the filter banks please refer to the table 136 on page 800 . 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 fb31 fb30 fb29 fb28 fb27 fb26 fb25 fb24 fb23 fb22 fb21 fb20 fb19 fb18 fb17 fb16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 fb15 fb14 fb13 fb12 fb11 fb10 fb9 fb8 fb7 fb6 fb5 fb4 fb3 fb2 fb1 fb0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:0 fb[31:0] : filter bits identifier each bit of the register specifies the level of the corresponding bit of the expected identifier. 0: dominant bit is expected 1: recessive bit is expected mask each bit of the register specifies whether the bit of the associated id entifier register must match with the corresponding bit of the expected identifier or not. 0: don?t care, the bit is not used for the comparison 1: must match, the bit of the incoming identifie r must have the same level has specified in the corresponding identifier register of the filter. controller area network (bxcan) RM0033 800/1317 doc id 15403 rev 3 27.9.5 bxcan register map refer to table 1 on page 50 for the register boundary addresses. the registers from offset 0x200 to 31c are present only in can1. table 136. bxcan register map and reset values offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x000 can_mcr reserved dbf reset reserved ttcm abom awum nart rflm txfp sleep inrq reset value 10 00000010 0x004 can_msr reserved rx samp rxm txm reserved slaki wkui erri slak inak reset value 1100 00010 0x008 can_tsr low[2:0] tme[2:0] code[1:0] abrq2 reserved terr2 alst2 txok2 rqcp2 abrq1 reserved terr1 alst1 txok1 rqcp1 abrq0 reserved terr0 alst0 txok0 rqcp0 reset value 000111000 00000 00000 0000 0x00c can_rf0r reserved rfom0 fovr0 full0 reserved fmp0[1:0] reset value 000 00 0x010 can_rf1r reserved rfom1 fovr1 full1 reserved fmp1[1:0] reset value 000 00 0x014 can_ier reserved slkie wkuie errie reserved lecie bofie epvie ewgie reserved fovie1 ffie1 fmpie1 fovie0 ffie0 fmpie0 tmeie reset value 000 0000 0000000 0x018 can_esr rec[7:0] tec[7:0] reserved lec[2:0] reserved boff epvf ewgf reset value 0000000000000000 0 00 000 0x01c can_btr silm lbkm reserved sjw[1:0] reserved ts2[2:0] ts1[3:0] reserved brp[9:0] reset value 00 00 0100011 0000000000 0x020- 0x17f reserved 0x180 can_ti0r stid[10:0]/exid[28:18] exid[17:0] ide rtr txrq reset value xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0 0x184 can_tdt0r time[15:0] reserved tgt reserved dlc[3:0] reset value xxxxxxxxxxxxxxxx x xxxx 0x188 can_tdl0r data3[7:0] data2[7:0] data1[7:0] data0[7:0] reset value xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 0x18c can_tdh0r data7[7:0] data6[7:0] data5[7:0] data4[7:0] reset value xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 0x190 can_ti1r stid[10:0]/exid[28:18] exid[17:0] ide rtr txrq reset value xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0 RM0033 controller area network (bxcan) doc id 15403 rev 3 801/1317 0x194 can_tdt1r time[15:0] reserved tgt reserved dlc[3:0] reset value xxxxxxxxxxxxxxxx x xxxx 0x198 can_tdl1r data3[7:0] data2[7:0] data1[7:0] data0[7:0] reset value xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 0x19c can_tdh1r data7[7:0] data6[7:0] data5[7:0] data4[7:0] reset value xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 0x1a0 can_ti2r stid[10:0]/exid[28:18] exid[17:0] ide rtr txrq reset value xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0 0x1a4 can_tdt2r time[15:0] reserved tgt reserved dlc[3:0] reset value xxxxxxxxxxxxxxxx x xxxx 0x1a8 can_tdl2r data3[7:0] data2[7:0] data1[7:0] data0[7:0] reset value xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 0x1ac can_tdh2r data7[7:0] data6[7:0] data5[7:0] data4[7:0] reset value xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 0x1b0 can_ri0r stid[10:0]/exid[28:18] exid[17:0] ide rtr reserved reset value xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 0x1b4 can_rdt0r time[15:0] fmi[7:0] reserved dlc[3:0] reset value xxxxxxxxxxxxxxxxxxxxxxxx xxxx 0x1b8 can_rdl0r data3[7:0] data2[7:0] data1[7:0] data0[7:0] reset value xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 0x1bc can_rdh0r data7[7:0] data6[7:0] data5[7:0] data4[7:0] reset value xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 0x1c0 can_ri1r stid[10:0]/exid[28:18] exid[17:0] ide rtr reserved reset value xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 0x1c4 can_rdt1r time[15:0] fmi[7:0] reserved dlc[3:0] reset value xxxxxxxxxxxxxxxxxxxxxxxx xxxx 0x1c8 can_rdl1r data3[7:0] data2[7:0] data1[7:0] data0[7:0] reset value xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 0x1cc can_rdh1r data7[7:0] data6[7:0] data5[7:0] data4[7:0] reset value xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 0x1d0- 0x1ff reserved table 136. bxcan register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 controller area network (bxcan) RM0033 802/1317 doc id 15403 rev 3 0x200 can_fmr reserved can2sb[5:0] reserved finit reset value 001110 1 0x204 can_fm1r reserved fbm[27:0] reset value 0000000000000000000000000000 0x208 reserved 0x20c can_fs1r reserved fsc[27:0] reset value 0000000000000000000000000000 0x210 reserved 0x214 can_ffa1r reserved ffa[27:0] reset value 0000000000000000000000000000 0x218 reserved 0x21c can_fa1r reserved fact[27:0] reset value 0000000000000000000000000000 0x220 reserved 0x224- 0x23f reserved 0x240 can_f0r1 fb[31:0] reset value xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 0x244 can_f0r2 fb[31:0] reset value xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 0x248 can_f1r1 fb[31:0] reset value xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 0x24c can_f1r2 fb[31:0] reset value xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx . . . . . . . . . . . . 0x318 can_f27r1 fb[31:0] reset value xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 0x31c can_f27r2 fb[31:0] reset value xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx table 136. bxcan register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 803/1317 28 ethernet (eth): media access control (mac) with dma controller 28.1 ethernet introduction portions copyright (c) 2004, 2005 synopsys, inc. all rights reserved. used with permission. the ethernet peripheral enables the stm32f20x and stm32f21x to transmit and receive data over ethernet in compliance with the ieee 802.3-2002 standard. the ethernet provides a configurable, flexible peripheral to meet the needs of various applications and customers. it supports two industry standard interfaces to the external physical layer (phy): the default media inde pendent interface (mii) defined in the ieee 802.3 specifications and the reduced media independent interface (rmii). it can be used in number of applications such as switches, network interface cards, etc. the ethernet is compliant with the following standards: ieee 802.3-2002 for ethernet mac ieee 1588-2002 standard for precision networked clock synchronization amba 2.0 for ahb master/slave ports rmii specification from rmii consortium 28.2 ethernet main features the ethernet (eth) peripheral includes the following features, listed by category: ethernet (eth): media access control (mac) with dma controller RM0033 804/1317 doc id 15403 rev 3 28.2.1 mac core features supports 10/100 mbit/s data transfer rates with external phy interfaces ieee 802.3-compliant mii interface to communicate with an external fast ethernet phy supports both full-duplex and half-duplex operations ? supports csma/cd protocol for half-duplex operation ? supports ieee 802.3x flow control for full-duplex operation ? optional forwarding of received pause control frames to the user application in full- duplex operation ? back-pressure support for half-duplex operation ? automatic transmission of zero-quanta pause frame on deassertion of flow control input in full-duplex operation preamble and start-of-frame data (sfd) insertion in transmit, and deletion in receive paths automatic crc and pad generation controllable on a per-frame basis options for automatic pad/crc stripping on receive frames programmable frame length to support standard frames with sizes up to 16 kb programmable interframe gap (40-96 bit times in steps of 8) supports a variety of flexible address filtering modes: ? up to four 48-bit perfect (da) address filters with masks for each byte ? up to three 48-bit sa address comparison check with masks for each byte ? 64-bit hash filter (optional) for multicast and unicast (da) addresses ? option to pass all multicast addressed frames ? promiscuous mode support to pass all frames without any filtering for network monitoring ? passes all incoming packets (as per filter) with a status report separate 32-bit status returned for transmission and reception packets supports ieee 802.1q vlan tag detection for reception frames separate transmission, reception, and control interfaces to the application supports mandatory network statistics with rmon/mib counters (rfc2819/rfc2665) mdio interface for phy device configuration and management detection of lan wakeup frames and amd magic packet? frames receive feature for checksum off-load for received ipv4 and tcp packets encapsulated by the ethernet frame enhanced receive feature for checking ipv4 header checksum and tcp, udp, or icmp checksum encapsulated in ipv4 or ipv6 datagrams support ethernet frame time stamping as described in ieee 1588- 2002. sixty-four-bit time stamps are given in each frame?s transmit or receive status two sets of fifos: a 2-kb transmit fifo with programmable thre shold capability, and a 2-kb receive fifo with a configurable threshold (default of 64 bytes) receive status vectors inserted into the receive fifo after the eof transfer enables multiple-frame storage in the receive fifo without requiring another fifo to store those frames? receive status RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 805/1317 option to filter all error frames on reception and not forward them to the application in store-and-forward mode option to forward under-sized good frames supports statistics by generating pulses for frames dropped or corrupted (due to overflow) in the receive fifo supports store and forward mechanism for transmission to the mac core automatic generation of pause frame control or back pressure signal to the mac core based on receive fifo-fill (thr eshold configurable) level handles automatic retransmission of collision frames for transmission discards frames on late collision, excessiv e collisions, excessive deferral and underrun conditions software control to flush tx fifo calculates and inserts ipv4 header checksum and tcp, udp, or icmp checksum in frames transmitted in store-and-forward mode supports internal loopback on the mii for debugging 28.2.2 dma features supports all ahb burst types in the ahb slave interface software can select the type of ahb burst (fixed or indefinite burst) in the ahb master interface. option to select address-aligned bursts from ahb master port optimization for packet-oriented dma transfers with frame delimiters byte-aligned addressing for data buffer support dual-buffer (ring) or linked-list (chained) descriptor chaining descriptor architecture, a llowing large blocks of data transfer with minimum cpu intervention; each descriptor can transfer up to 8 kb of data comprehensive status reporting for normal operation and transfers with errors individual programmable burst size for transmit and receive dma engines for optimal host bus utilization programmable interrupt options for different operational conditions per-frame transmit/receive complete interrupt control round-robin or fixed-priority arbitration between receive and transmit engines start/stop modes current tx/rx buffer pointer as status registers current tx/rx descriptor pointer as status registers 28.2.3 ptp features received and transmitted frames time stamping coarse and fine correction methods trigger interrupt when system time becomes greater than target time pulse per second output (product alternate function output) ethernet (eth): media access control (mac) with dma controller RM0033 806/1317 doc id 15403 rev 3 28.3 ethernet pins table 137 shows the mac signals and the corresponding mii/rmii signal mapping. all mac signals are mapped onto af11, some signals are mapped onto different i/o pins, and should be configured in alternate function mode (for more details, refer to section 6.3.2: i/o pin multiplexer and mapping ). table 137. alternate function mapping port af11 eth pa0-wkup eth_mii_crs pa1 eth_mii _rx_clk / eth_rmii _ref_clk pa 2 e t h _ m d i o pa3 eth _mii_col pa7 eth_mii _rx_dv / eth_rmii _crs_dv pb0 eth _mii_rxd2 pb1 eth _mii_rxd3 pb5 eth _pps_out pb8 eth _mii_txd3 pb10 eth_ mii_rx_er pb11 eth _mii_tx_en / eth _rmii_tx_en pb12 eth _mii_txd0 / eth _rmii_txd0 pb13 eth _mii_txd1 / eth _rmii_txd1 pc1 eth _mdc pc2 eth _mii_txd2 pc3 eth _mii_tx_clk pc4 eth_mii_rxd0 / eth_rmii_rxd0 pc5 eth _mii_rxd1/ eth _rmii_rxd1 pe2 eth_mii_txd3 pg8 eth_pps_out pg11 eth _mii_tx_en / eth _rmii_tx_en pg13 eth _mii_txd0 / eth _rmii_txd0 pg14 eth _mii_txd1 / eth _rmii_txd1 ph2 eth _mii_crs ph3 eth _mii_col ph6 eth _mii_rxd2 ph7 eth _mii_rxd3 pi10 eth _mii_rx_er RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 807/1317 28.4 ethernet functional description: smi, mii and rmii the ethernet peripheral consists of a mac 802.3 (media access control) with a dedicated dma controller. it supports both default media-independent interface (mii) and reduced media-independent interf ace (rmii) through one select ion bit (refer to syscfg_pmc register) . the dma controller interfaces with the core and memories through the ahb master and slave interfaces. the ahb master interface controls data transfers while the ahb slave interface accesses control and status registers (csr) space. the transmit fifo (tx fifo) buffers data read from system memory by the dma before transmission by the mac core. similarly, the receive fifo (rx fifo) stores the ethernet frames received from the line until they are transferred to system memory by the dma. the ethernet peripheral also includes an smi to communicate with external phy. a set of configuration registers permit the user to select the wanted mode and features for the mac and the dma controller. note: the ahb clock frequency must be at least 25 mhz when the ethernet is used. figure 312. eth block diagram 1. for ahb connections please refer to figure 1: system architecture . 28.4.1 station manage ment interface: smi the station management interface (smi) allows the application to access any phy registers through a 2-wire clock and data lines. the interface supports accessing up to 32 phys. the application can select one of the 32 phys and one of the 32 registers within any phy and send control data or receive status information. only one register in one phy can be addressed at any given time. both the mdc clock line and the mdio data line are implemented as alternate function i/o in the microcontroller: mdc: a periodic clock that provides the timing reference for the data transfer at the maximum frequency of 2.5 mhz. the minimum high and low times for mdc must be + b y t e 2 8 & ) & / % t h e r n e t $ - ! - e d i a a c c e s s c o n t r o l - ! # - ! # c o n t r o l r e g i s t e r s $ - ! c o n t r o l s t a t u s r e g i s t e r s / p e r a t i o n m o d e r e g i s t e r ) n t e r f a c e 3 e l e c t - ) ) - $ # - $ ) / ! ( " 3 l a v e i n t e r f a c e 2 - ) ) a i c " u s m a t r i x % x t e r n a l 0 ( 9 # h e c k s u m o f f l o a d 0 4 0 ) % % % 0 - 4 - - # + b y t e 4 8 & ) & / ethernet (eth): media access control (mac) with dma controller RM0033 808/1317 doc id 15403 rev 3 160 ns each, and the minimum period for mdc must be 400 ns. in idle state the smi management interface drives the mdc clock signal low. mdio: data input/output bitstream to transfer status information to/from the phy device synchronously with the mdc clock signal figure 313. smi interface signals smi frame format the frame structure related to a read or write operation is shown in ta b l e 1 3 , the order of bit transmission must be from left to right. the management frame consists of eight fields: preamble : each transaction (read or write) can be initiated with the preamble field that corresponds to 32 contiguous logic one bi ts on the mdio line with 32 corresponding cycles on mdc. this field is used to es tablish synchronization with the phy device. start : the start of frame is defined by a <01> pattern to verify transitions on the line from the default logic one state to zero and back to one. operation : defines the type of transaction (read or write) in progress. paddr : the phy address is 5 bits, allowing 32 unique phy addresses. the msb bit of the address is the first transmitted and received. raddr : the register address is 5 bits, allowing 32 individual registers to be addressed within the selected phy device. the msb bit of the address is the first transmitted and received. ta : the turn-around field defines a 2-bit pattern between the raddr and data fields to avoid contention during a read transaction. for a read transaction the mac controller drives high-impedance on the mdio line for the 2 bits of ta. the phy device must drive a high-impedance state on the first bit of ta, a zero bit on the second one. for a write transaction, the mac controller drives a <10> pattern during the ta field. the phy device must drive a high-impedance state for the 2 bits of ta. data : the data field is 16-bit. the first bit transmitted and received must be bit 15 of the eth_miid register. table 138. management frame format management frame fields preamble (32 bits) start operation paddr raddr ta data (16 bits) idle read 1... 1 01 10 ppppp rrrrr z0 ddddddddddddddd z write 1... 1 01 01 ppppp rrrrr 10 ddddddddddddddd z stm32 mdio mdc external phy ai15621 802.3 mac RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 809/1317 idle : the mdio line is driven in high-impedance state. all three-state drivers must be disabled and the phy?s pull-up resistor keeps the line at logic one. smi write operation when the application sets the mii write and busy bits (in ethernet mac mii address register (eth_macmiiar) ), the smi initiates a write operation into the phy registers by transferring the phy address, the register address in phy, and the write data (in ethernet mac mii data register (eth_macmiidr) . the application should not change the mii address register contents or the mii data register while the transaction is ongoing. write operations to the mii address register or the mii data register during this period are ignored (the busy bit is high), and the transaction is completed without any error. after the write operation has completed, the smi indicates this by resetting the busy bit. figure 314 shows the frame format for the write operation. figure 314. mdio timing and frame structure - write cycle smi read operation when the user sets the mii busy bit in the ethernet mac mii address register (eth_macmiiar) with the mii write bit at 0, the smi initiates a read operation in the phy registers by transferring the phy address and the register address in phy. the application should not change the mii address register contents or the mii data register while the transaction is ongoing. write operations to the mii address register or mii data register during this period are ignored (the busy bit is high) and the transaction is completed without any error. after the read operation has completed, the smi resets the busy bit and then updates the mii data register with the data read from the phy. figure 315 shows the frame format for the read operation. figure 315. mdio timing and frame structure - read cycle mdc mdio 32 1's 0 1 0 1 a4 a3 a2 a1 a0 r4 r3 r2 r1 r0 d15 d14 d1 d0 preamble start of frame op code phy address register address turn around data data to phy ai15626 mdc mdio 32 1's 0 1 1 0 a4 a3 a2 a1 a0 r4 r3 r2 r1 r0 d15 d14 d1 d0 preamble start of frame op code phy address register address turn around data data to phy ai15627 data from phy ethernet (eth): media access control (mac) with dma controller RM0033 810/1317 doc id 15403 rev 3 smi clock selection the mac initiates the management write/read operation. the smi clock is a divided clock whose source is the application clock (ahb cl ock). the divide factor depends on the clock range setting in the mii address register. table 139 shows how to set the clock ranges. 28.4.2 media-independent interface: mii the media-independent interface (mii) defines the interconnection between the mac sublayer and the phy for data transfer at 10 mbit/s and 100 mbit/s. figure 316. media independent interface signals mii_tx_clk: continuous clock that provid es the timing reference for the tx data transfer. the nominal frequency is: 2.5 mhz at 10 mbit/s speed; 25 mhz at 100 mbit/s speed. mii_rx_clk: continuous clock that provides the timing reference for the rx data transfer. the nominal frequency is: 2.5 mhz at 10 mbit/s speed; 25 mhz at 100 mbit/s speed. mii_tx_en: transmission enable indicates that the mac is presenting nibbles on the mii for transmission. it must be asserted synchronously (mii_tx_clk) with the first nibble of the preamble and must remain asserted while all nibbles to be transmitted are presented to the mii. mii_txd[3:0]: transmit data is a bundle of 4 data signals driven synchronously by the mac sublayer and qualified (valid data) on the assertion of the mii_tx_en signal. table 139. clock range selection hclk clock mdc clock 000 60-100 mhz ahb clock / 42 001 100-120 mhz ahb clock / 62 010 20-35 mhz ahb clock / 16 011 35-60 mhz ahb clock / 26 100, 101, 110, 111 reserved - 3 4 - - $ # - $ ) / 2 8 ? $ 6 # 2 3 # / , 4 8 ? % . 2 8 ? # , + 2 8 $ ; = 2 8 ? % 2 4 8 ? # , + 4 8 $ ; = % x t e r n a l 0 ( 9 a i b - ! # RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 811/1317 mii_txd[0] is the least significant bit, mii_txd[3] is the most significant bit. while mii_tx_en is deasserted the transmit data must have no effect upon the phy. mii_crs: carrier sense is asserted by the phy when either the transmit or receive medium is non idle. it shall be deasserted by the phy when both the transmit and receive media are idle. the phy must ensure that the mii_cs signal remains asserted throughout the duration of a co llision condition. this signal is not required to transition synchronously with respect to the tx and rx clocks. in full duplex mode the state of this signal is don?t care for the mac sublayer. mii_col: collision detection mu st be asserted by the phy upon detection of a collision on the medium and must remain asserted while the collision condition persists. this signal is not required to transition synchronously with respect to the tx and rx clocks. in full duplex mode the state of this signal is don?t care for the mac sublayer. mii_rxd[3:0]: reception data is a bundle of 4 data signals driven synchronously by the phy and qualified (valid data) on the assertion of the mii_rx_dv signal. mii_rxd[0] is the least significant bit, mii_rxd[3] is the most significant bit. while mii_rx_en is deasserted and mii_rx_er is asserted, a sp ecific mii_rxd[3:0] value is used to transfer specific information from the phy (see ta b l e 1 4 1 ). mii_rx_dv: receive data valid indicates that the phy is presenting recovered and decoded nibbles on the mii for reception. it must be asserted synchronously (mii_rx_clk) with the first recovered nibble of the frame and must remain asserted through the final recovered nibble. it must be deasserted prior to the first clock cycle that follows the final nibble. in order to receive the frame correctly, the mii_rx_dv signal must encompass the frame, starting no later than the sfd field. mii_rx_er: receive error must be asserted for one or more clock periods (mii_rx_clk) to indicate to the mac sublayer that an error was detected somewhere in the frame. this error condition must be qualified by mii_rx_dv assertion as described in ta b l e 1 4 1 . table 140. tx interface signal encoding mii_tx_en mii_txd[3:0] description 0 0000 through 1111 normal inter-frame 1 0000 through 1111 normal data transmission table 141. rx interface signal encoding mii_rx_dv mii_rx_err mii_rxd[3:0] description 0 0 0000 through 1111 normal inter-frame 0 1 0000 normal inter-frame 0 1 0001 through 1101 reserved 0 1 1110 false carrier indication 0 1 1111 reserved 1 0 0000 through 1111 normal data reception 1 1 0000 through 1111 data reception with errors ethernet (eth): media access control (mac) with dma controller RM0033 812/1317 doc id 15403 rev 3 mii clock sources to generate both tx_clk and rx_clk clock si gnals, the external phy must be clocked with an external 25 mhz as shown in figure 317 . instead of using an external 25 mhz quartz to provide this clock, the stm32f20x and stm32f21x microcontroller can output this signal on its mco pin. in this case, the pll multiplier has to be configured so as to get the desired frequency on the mco pin, from the 25 mhz external quartz. figure 317. mii clock sources 28.4.3 reduced media-ind ependent interface: rmii the reduced media-independent interface (rmii) specification reduces the pin count between the stm32f20x and stm32f21x ethernet peripheral and the external ethernet in 10/100 mbit/s. according to t he ieee 802.3u standard, an mii co ntains 16 pins for data and control. the rmii specification is dedicated to reduce the pin count to 7 pins (a 62.5% decrease in pin count). the rmii is instantiated between the mac and the phy. this helps translation of the mac?s mii into the rmii. the rmii block has the following characteristics: it supports 10-mbit/s and 100-mbit/s operating rates the clock reference must be doubled to 50 mhz the same clock reference must be sourced externally to both mac and external ethernet phy it provides independent 2-bit wide (dibit) transmit and receive data paths stm32 mco 25 mhz 25 mhz 25 mhz tx _clk for 10/100 mbit/s rx _clk hse 802.3 mac ai15623 external phy RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 813/1317 figure 318. reduced media-independent interface signals rmii clock sources as described in the rmii clock sources section, the stm32f20x and stm32f21x could provide this 50 mhz clock signal on its mco output pin and you then have to configure this output value through pll configuration. figure 319. rmii clock sources 28.4.4 mii/rmii selection the mode, mii or rmii, is selected using the configuration bit 23, mii_rmii_sel, in the syscfg_pmc register. the applic ation has to set the mii/rm ii mode while the ethernet controller is under reset or before enabling the clocks. mii/rmii internal clock scheme the clock scheme required to support both the mii and rmii, as well as 10 and 100 mbit/s operations is described in figure 320 . stm32 txd[ 1:0] tx_en rxd[1:0] crs_dv mdc mdio ref_clk clock source 802.3 mac external phy ai15624 stm32 ref_clk 50 mhz 50 mhz mco 25 mhz pll for 10/100 mbit/s external phy ai15625 802.3 mac ethernet (eth): media access control (mac) with dma controller RM0033 814/1317 doc id 15403 rev 3 figure 320. clock scheme 1. the mii/rmii selection is controlled through bi t 23, mii_rmii_sel, in the syscfg_pmc register. to save a pin, the two input clock signals, rmii_ref_ck and mii_rx_clk, are multiplexed on the same gpio pin. 28.5 ethernet functional description: mac 802.3 the ieee 802.3 international standard for local area networks (lans) employs the csma/cd (carrier sense multiple access with collision detection) as the access method. the ethernet peripheral consists of a mac 802.3 (media access control) controller with media independent interface (mii) and a dedicated dma controller. the mac block implements the lan csma/ cd sublayer for the following families of systems: 10 mbit/s and 100 mbit/s of data rates for baseband and broadband systems. half- and full-duplex operation modes are supported. the collision detection a ccess method is applied only to the half-duplex operation mode. the mac control frame sublayer is supported. the mac sublayer performs the following functions associated with a data link control procedure: data encapsulation (transmit and receive) ? framing (frame boundary delimitation, frame synchronization) ? addressing (handling of source and destination addresses) ? error detection media access management ? medium allocation (collision avoidance) ? contention resolution (collision handling) gpio and af controller gpio and af controller mii_tx_clk as af (25 mhz or 2.5 mhz) mii_rx_clk as af (25 mhz or 2.5 mhz) sync. divider /2 for 100 mb/s /20 for 10 mb/s 50 mhz 0 1 0 1 25 mhz or 2.5 mhz 25 mhz or 2.5 mhz 0 mii 1 rmii (1) 25 mhz or 2.5 mhz 25 mhz or 2.5 mhz mactxclk macrxclk tx rx ahb hclk hclk mac must be greater than 25 mhz ai15650 rmii rmii_ref_ck as af (50 mhz) RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 815/1317 basically there are two operating modes of the mac sublayer: half-duplex mode: the stations contend for the use of the physical medium, using the csma/cd algorithms. full duplex mode: simultaneous transmission and reception without contention resolution (csma/cd algorithm are unnecessary) when all the following conditions are met: ? physical medium capability to support simultaneous transm ission and reception ? exactly 2 stations connected to the lan ? both stations configured for full-duplex operation 28.5.1 mac 802.3 frame format the mac block implements the mac sublayer and the optional mac control sublayer (10/100 mbit/s) as sp ecified by the ieee 802.3-2002 standard. two frame formats are specified for data communication systems using the csma/cd mac: basic mac frame format tagged mac frame format (extension of the basic mac frame format) figure 322 and figure 323 describe the frame structure (untagged and tagged) that includes the following fields: preamble: 7-byte field used for synchronization purposes (pls circuitry) hexadecimal value: 55-55-55-55-55-55-55 bit pattern: 01010101 01010101 01010101 01010101 01010101 01010101 01010101 (right-to-left bit transmission) start frame delimiter (sfd): 1-byte field used to indicate the start of a frame. hexadecimal value: d5 bit pattern: 11010101 (right-to-left bit transmission) destination and source address fields: 6-byte fields to indicate the destination and source station addresses as follows (see figure 321 ): ? each address is 48 bits in length ? the first lsb bit (i/g) in the destination address field is used to indicate an individual (i/g = 0) or a group address (i/g = 1). a group address could identify none, one or more, or all the stations connected to the lan. in the source address the first bit is reserved and reset to 0. ? the second bit (u/l) distinguishes between locally (u/l = 1) or globally (u/l = 0) administered addresses. for broadcast addresses this bit is also 1. ? each byte of each address field must be transmitted least significant bit first. the address designation is based on the following types: individual address: this is the physical address associated with a particular station on the network. group address. a multidestination address associated with one or more stations on a given network. there are two kinds of multicast address: ? multicast-group address: an address associated with a group of logically related stations. ? broadcast address: a distinguished, predefined multicast address (all 1?s in the destination address field) that always denotes all the stations on a given lan. ethernet (eth): media access control (mac) with dma controller RM0033 816/1317 doc id 15403 rev 3 figure 321. address field format qtag prefix: 4-byte field in serted between the source ad dress field and the mac client length/type field. this field is an extension of the basic frame (untagged) to obtain the tagged mac frame. the untagged mac frames do not include this field. the extensions for tagging are as follows: ? 2-byte constant length/type field value consistent with the type interpretation (greater than 0x0600) equal to the value of the 802.1q tag protocol type (0x8100 hexadecimal). this constant field is used to distinguish tagged and untagged mac frames. ? 2-byte field containing the tag control information field subdivided as follows: a 3- bit user priority, a canonical format indicator (cfi) bit and a 12-bit vlan identifier. the length of the tagged mac frame is extended by 4 bytes by the qtag prefix. mac client length/type: 2-byte field with different meaning (mutually exclusive), depending on its value: ? if the value is less than or equal to maxvalidframe (0d1500) then this field indicates the number of mac client data bytes contained in the subsequent data field of the 802.3 frame (length interpretation). ? if the value is greater than or equal to mintypevalue (0d1536 decimal, 0x0600) then this field indicates the nature of the mac client protocol (type interpretation) related to the ethernet frame. regardless of the interpretation of the length/type field, if the length of the data field is less than the minimum required for proper operation of the protocol, a pad field is added after the data field but prior to the fcs (frame check sequence) field. the length/type field is transmitted and received with the higher-order byte first. for length/type field values in the range between maxvalidlength and mintypevalue (boundaries excluded), the behavior of the ma c sublayer is not specified: they may or may not be passed by the mac sublayer. data and pad fields: n-byte data field. full data transparency is provided, it means that any arbitrary sequence of byte values may appear in the data field. the size of the pad, if any, is determined by the size of the data field. max and min length of the data and pad field are: ? maximum length = 1500 bytes ? minimum length for untagged mac frames = 46 bytes ? minimum length for tagged mac frames = 42 bytes when the data field length is less than th e minimum required, the pad field is added to match the minimum length (42 bytes for tagged frames, 46 bytes for untagged frames). frame check sequence: 4-byte field that contains t he cyclic redundancy check (crc) value. the crc computation is based on the following fields: source address, msb lsb bit transmission order (right to left) u/l i/g 46-bit address i/g = 0 individual address i/g = 1 group address u/l = 0 globally administered address u/l = 1 locally administered address ai15628 RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 817/1317 destination address, qtag prefix, length/type, llc data and pad (that is, all fields except the preamble, sfd). the generating polynomial is the following: the crc value of a frame is computed as follows: the first 2 bits of the frame are complemented the n-bits of the frame are the coefficients of a polynomial m(x) of degree (n ? 1). the first bit of the destination address corresponds to the x n ? 1 term and the last bit of the data field corresponds to the x 0 term m(x) is multiplied by x 32 and divided by g(x), producing a remainder r(x) of degree 31 the coefficients of r(x) are considered as a 32-bit sequence the bit sequence is complemented and the result is the crc the 32-bits of the crc value are placed in the frame check sequence. the x 32 term is the first transmitted, the x 0 term is the last one figure 322. mac frame format gx () x 32 x 26 x 23 x 22 x 16 x 12 x 11 x 10 x 8 x 7 x 5 x 4 x 2 x1 + + + + + + + +++++++ = preamble sfd destination address source address mac client length/type mac client data pad frame check sequence 7 bytes 1 byte 6 bytes 6 bytes 2 bytes 46-1500 bytes 4 bytes msb lsb bit transmission order (right to left) bytes within frame transmitted top to bottom ai15629 ethernet (eth): media access control (mac) with dma controller RM0033 818/1317 doc id 15403 rev 3 figure 323. tagged mac frame format each byte of the mac frame, except the fcs field, is transmitted low-order bit first. an invalid mac frame is defined by one of the following conditions: the frame length is inconsistent with the expected value as specified by the length/type field. if the length/type field contains a type value, then the frame length is assumed to be consistent with this field (no invalid frame) the frame length is not an integer number of bytes (extra bits) the crc value computed on the incoming frame does not match the included fcs 28.5.2 mac frame transmission the dma controls all transactions for the transmit path. ethernet frames read from the system memory are pushed into the fifo by the dma. the frames are then popped out and transferred to the mac core. when the end-of-frame is transferred, the status of the transmission is taken from the mac core and transferred back to the dma. the transmit fifo has a depth of 2 kbyte. fifo-fill level is in dicated to the dma so that it can initiate a data fetch in required bursts from the system memory, using the ahb interface. the data from the ahb master interface is pushed into the fifo. when the sof is detected, the mac accepts th e data and begins transmitting to the mii. the time required to transmit the frame data to the mii after the application initiates transmission is variable, depending on delay factors like ifg delay, time to transmit preamble/sfd, and any back-off delays for half-duplex mode. after the eof is transferred to the mac core, the core completes normal transmission and then gives the status of transmission back to the dma. if a normal collision (in half-duplex mode) occurs during transmission, the mac core makes the transmit status valid, then accepts and drops all further data until the next sof is received. the same frame should be retransmitted from sof on observing a retry request (in the status) from the mac. the mac issues an underflow status if the data are not provided continuously during the transmission. during the normal transfer of a frame, if the mac receives an sof without getting an eof for the previous frame, then the sof is ignored and the new frame is considered as the continuation of the previous frame. preamble sfd destination address source address length/type = 802.1qtagtype tag control information mac client length/type mac client data 7 bytes 1 byte 6 bytes 6 bytes qtag prefix 42-1500 bytes 2 bytes msb lsb bit transmission order (r ight to left) bytes within frame transmitted top to bottom frame check sequence pad 4 bytes 4 bytes 1 0 0 0 0 0 0 0 1 vlan identifier (vid, 12 bits) cfi user priority msb lsb 0 0 0 0 0 0 0 0 0 ai15630 RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 819/1317 there are two modes of operation for popping data towards the mac core: in threshold mode, as soon as the number of bytes in the fifo crosses the configured threshold level (or when the end-of-frame is written before the threshold is crossed), the data is ready to be popped out and forwarded to the mac core. the threshold level is configured using the ttc bits of eth_dmabmr. in store-and-forward mode, only after a complete frame is stored in the fifo, the frame is popped towards the mac core. if the tx fifo size is smaller than the ethernet frame to be transmitted, then the frame is popped towards the mac core when the tx fifo becomes almost full. the application can flush the transmit fifo of all contents by setting the ftf (eth_dmaomr register [20]) bit. this bit is self -clearing and initializes the fifo pointers to the default state. if the ftf bit is set during a frame transfer to the mac core, then transfer is stopped as the fifo is considered to be empty. hence an underflow event occurs at the mac transmitter and the corresponding status word is forwarded to the dma. automatic crc and pad generation when the number of bytes received from the application falls below 60 (da+sa+lt+data), zeros are appended to the transmitting frame to make the data length exactly 46 bytes to meet the minimum data field requirement of ieee 802.3. the mac can be programmed not to append any padding. the cyclic redundancy check (crc) for the frame check sequence (fcs) field is calculated and appended to the data being transmitted. when the mac is programmed to not append the crc value to the end of ethernet frames, the computed crc is not transmitted. an exception to this rule is that when the mac is programmed to append pads for frames (da+sa+lt+data) le ss than 60 bytes, crc will be appended at the end of the padded frames. the crc generator calculates the 32-bit crc fo r the fcs field of the ethernet frame. the encoding is defined by the following polynomial. transmit protocol the mac controls the operation of ethernet frame transmission. it performs the following functions to meet the ieee 802 .3/802.3z specifications. it: generates the preamble and sfd generates the jam pattern in half-duplex mode controls the jabber timeout controls the flow for half-duplex mode (back pressure) generates the transmit frame status contains time stamp snapshot lo gic in accordance with ieee 1588 when a new frame transmission is requested, the mac sends out the preamble and sfd, followed by the data. the preamble is defined as 7 bytes of 0b10101010 pattern, and the sfd is defined as 1 byte of 0b10101011 pa ttern. the collision window is defined as 1 slot time (512 bit times for 10/100 mbit/s ethernet). the jam pattern generation is applicable only to half-duplex mode, not to full-duplex mode. in mii mode, if a collision occurs at any time from the beginni ng of the frame to the end of the crc field, the mac sends a 32-bit jam pattern of 0x5555 5555 on th e mii to inform all gx () x 32 x 26 x 23 x 22 x 16 x 12 x 11 x 10 x 8 x 7 x 5 x 4 x 2 x1 + + + + + + + +++++++ = ethernet (eth): media access control (mac) with dma controller RM0033 820/1317 doc id 15403 rev 3 other stations that a collision has occurred. if the collision is seen during the preamble transmission phase, the mac completes the transmission of the preamble and sfd and then sends the jam pattern. a jabber timer is maintained to cut off the transmission of ethernet frames if more than 2048 (default) bytes have to be transferred. the mac uses the deferral mechanism for flow control (back pressure) in half-duplex mode. when the application requests to stop receiving frames, the mac sends a jam pattern of 32 bytes whenever it senses the reception of a frame, provided th at transmit flow control is enab led. this results in a collision and the remote station backs off. the application requests flow control by setting the bpa bit (bit 0) in the eth_macfcr register. if the application requests a frame to be transmitted, then it is scheduled and transmitted even when back pressure is activated. note that if back pressure is kept activated for a long time (and more than 16 consecutive collision events occur) then the remote stations abort their transmis sions due to excessive collisions. if ieee 1588 time stamping is enabled for the transmit frame, this block takes a snapshot of the system time when the sfd is put onto the transmit mii bus. transmit scheduler the mac is responsible for scheduling the frame transmission on the mii. it maintains the interframe gap between two transmitted frames and follows the truncated binary exponential backoff algorithm for half-duplex mode. the mac enables transmission after satisfying the ifg and backoff delays. it maintains an idle period of the configured interframe gap (ifg bits in the eth_maccr register) between any two transmitted frames. if frames to be transmitted arrive sooner than the configured ifg time, the mii waits for the enable signal from the mac before starting the transmission on it. the mac starts its ifg counter as soon as the carrier signal of the mii goes inactive. at the end of the programmed ifg value, the mac enables transmission in full-duplex mo de. in half-duplex mode and when ifg is configured for 96 bit times, the mac follows the rule of deference specified in section 4.2.3.2.1 of the ieee 802.3 spec ification. the mac re sets its ifg counte r if a carrier is detected during the first two-thirds (64-bit times for all ifg values) of the ifg interval. if the carrier is detected during the final one third of the ifg interval, the mac continues the ifg count and enables the transmitter after the ifg interval. the mac implements the truncated binary exponential backoff algorithm when it operates in half-duplex mode. transmit flow control when the transmit flow control enable bit (tfe bit in eth_macfcr) is set, the mac generates pause frames and transmits them as necessary, in full-duplex mode. the pause frame is appended with the calculated crc, and is sent. pause frame generation can be initiated in two ways. a pause frame is sent either when the application sets the fcb bit in the eth_macfcr register or when the receive fifo is full (packet buffer). if the application has requested flow control by setting the fcb bit in eth_macfcr, the mac generates and transmits a single pause frame. the value of the pause time in the generated frame contains the programmed pause time value in eth_macfcr. to extend the pause or end the pause prior to the time specified in the previously transmitted pause frame, the application must request another pause frame transmission after programming the pause time value (pt in eth_macfcr register) with the appropriate value. if the application has requested flow control when the receive fifo is full, the mac generates and transmits a pause frame. the value of the pause time in the generated frame is the programmed pause time value in eth_macfcr. if the receive fifo RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 821/1317 remains full at a configurable number of slot-times (plt bits in eth_macfcr) before this pause time runs out, a second pause frame is transmitted. the process is repeated as long as the receive fifo remains full. if this condition is no more satisfied prior to the sampling time, the mac transmits a pause frame with zero pause time to indicate to the remote end that the receive buffer is ready to receive new data frames. single-packet transmit operation the general sequence of events for a transmit operation is as follows: 1. if the system has data to be transferred, the dma controller fetches them from the memory through the ahb master interface and starts forwarding them to the fifo. it continues to receive the data until the end of frame is transferred. 2. when the threshold level is crossed or a full packet of data is received into the fifo, the frame data are popped and driven to the mac core. the dma continues to transfer data from the fifo until a complete packet has been transferred to the mac. upon completion of the frame, the dma controller is notified by the status coming from the mac. transmit operation?two packets in the buffer 1. because the dma must update the descriptor status before releasing it to the host, there can be at the most two frames inside a transmit fifo. the second frame is fetched by the dma and put into the fifo only if the osf (operate on second frame) bit is set. if this bit is not set, the next frame is fetched from the memory only after the mac has completely processed the frame and the dma has released the descriptors. 2. if the osf bit is set, the dma starts fetching the second frame immediately after completing the transfer of the first frame to the fifo. it does not wait for the status to be updated. in the meantime, the second frame is received into the fifo while the first frame is being transmitted. as soon as the first frame has been transferred and the status is received from the mac, it is pushed to the dma. if the dma has already completed sending the second packet to the fifo, the second transmission must wait for the status of the first packet before proceeding to the next frame. retransmission during collision while a frame is being transferred to the ma c, a collision event may occur on the mac line interface in half-duplex mode. the mac would then indicate a retry attempt by giving the status even before the end of frame is received. then the retransmission is enabled and the frame is popped out again from the fifo. after more than 96 bytes have been popped towards the mac core, the fifo controller frees up that space and makes it available to the dma to push in more data. this means that the retransmission is not possible after this threshold is crossed or when the mac core indicates a late collision event. transmit fifo flush operation the mac provides a control to the software to flush the transmit fifo through the use of bit 20 in the operation mode register. the flush operation is immediate and the tx fifo and the corresponding pointers are cleared to the initial state even if the tx fifo is in the middle of transferring a frame to the mac core. this results in an underflow event in the mac transmitter, and the frame transmission is aborted. the status of such a frame is marked with both underflow and frame flush events (tdes0 bits 13 and 1). no data are coming to the fifo from the application (dma) during the flush operation. transfer transmit status words are transferred to the application for the number of frames that is flushed (including partial frames). frames that are completely flushed have the frame flush status bit (tdes0 13) set. the flush operation is completed when the application (dma) has accepted all of ethernet (eth): media access control (mac) with dma controller RM0033 822/1317 doc id 15403 rev 3 the status words for the frames that were flus hed. the transmit fifo flush control register bit is then cleared. at this point, new frames from the application (dma) are accepted. all data presented for transmission after a flush operation are discarded unless they start with an sof marker. transmit status word at the end of the ethernet frame transfer to the mac core and after the core has completed the transmission of the frame, the transmit stat us is given to the application. the detailed description of the transmit status is the same as for bits [23: 0] in tdes0. if ieee 1588 time stamping is enabled, a specific frames? 64-bit time stamp is returned, along with the transmit status. transmit checksum offload communication protocols such as tcp and udp implement checksum fields, which helps determine the integrity of data transmitted over a network. because the most widespread use of ethernet is to encapsulate tcp and udp over ip datagrams, the ethernet controller has a transmit checksum offload feature that supports checksum calculation and insertion in the transmit path, and error detection in the receive path. this section explains the operation of the checksum offload feature for transmitted frames. note: 1 the checksum for tcp, udp or icmp is calculated over a complete frame, then inserted into its corresponding header field. due to this requirement, this function is enabled only when the transmit fifo is configured for store-and-forward mode (that is, when the tsf bit is set in the eth_eth_dmaomr register). if the core is configured for threshold (cut-through) mode, the transmit checksum offload is bypassed. 2 you must make sure the transmit fifo is deep enough to store a complete frame before that frame is transferred to the mac core transmitter. if the fifo depth is less than the input ethernet frame size, the payload (tcp/udp/icmp) checksum insertion function is bypassed and only the frame?s ipv4 header checksum is modified, even in store-and-forward mode. the transmit checksum offload supports two types of checksum calculation and insertion. this checksum can be controlled for each frame by setting the cic bits (bits 28:27 in tdes1, described in tdes1: transmit descriptor word1 on page 855 ). see ietf specifications rfc 791, rfc 793, rfc 768, rfc 792, rfc 2460 and rfc 4443 for ipv4, tcp, udp, icmp, ipv6 and icmpv6 packet header specifications, respectively. ip header checksum in ipv4 datagrams, the integrity of the header fields is indicated by the 16-bit header checksum field (the eleventh and twelfth bytes of the ipv4 datagram). the checksum offload detects an ipv4 datagram when the ethernet frame?s type field has the value 0x0800 and the ip datagram?s version field has the value 0x4. the input frame?s checksum field is ignored during calculation an d replaced by the calculated value. ipv6 headers do not have a checksum field; thus, the checksum offload does not modify ipv6 header fields. the result of this ip header checksum calculation is indicated by the ip header error status bit in the transmit status (bit 16). this status bit is set whenever the values of the ethernet type field and the ip header?s version field are not consistent, or when the ethernet frame does not have enough data, as indicated by the RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 823/1317 ip header length field. in other words, this bit is set when an ip header error is asserted under the following circumstances: a) for ipv4 datagrams: ? the received ethernet type is 0x0800, but the ip header?s version field does not equal 0x4 ? the ipv4 header length field indicates a value less than 0x5 (20 bytes) ? the total frame length is less than the value given in the ipv4 header length field b) for ipv6 datagrams: ? the ethernet type is 0x86dd but the ip header version field does not equal 0x6 ? the frame ends before the ipv6 header (40 bytes) or extension header (as given in the corresponding header length field in an extension header) has been completely received. even when the checksum offload detects such an ip header error, it inserts an ipv4 header checksum if the ethernet type field indicates an ipv4 payload. tcp/udp/icmp checksum the tcp/udp/icmp checksum processes the ipv4 or ipv6 header (including extension headers) and determines whether the encapsulated payload is tcp, udp or icmp. note that: a) for non-tcp, -udp, or -icmp/icmpv6 payloads, this checksum is bypassed and nothing further is modified in the frame. b) fragmented ip frames (ipv4 or ipv6), ip frames with security features (such as an authentication header or encapsulated security payload), and ipv6 frames with routing headers are bypassed and not processed by the checksum. the checksum is calculated for the tcp, udp, or icmp payload and inserted into its corresponding field in the header. it can work in the following two modes: ? in the first mode, the tcp, udp, or icmpv6 pseudo-header is not included in the checksum calculation and is assumed to be present in the input frame?s checksum field. the checksum field is included in the checksum calculation, and then replaced by the final calculated checksum. ? in the second mode, the checksum field is ignored, the tcp, udp, or icmpv6 pseudo-header data are included into the checksum calculation, and the checksum field is overwritten with the final calculated value. note that: for icmp-over-ipv4 packets, the checksum field in the icmp packet must always be 0x0000 in both modes, because pseudo-headers are not defined for such packets. if it does not equal 0x0000, an incorrect checksum may be inserted into the packet. the result of this operation is indicated by the payload checksum error status bit in the transmit status vector (bit 12). the payload checksum error status bit is set when either of the following is detected: ? the frame has been forwarded to the mac transmitter in store-and-forward mode without the end of frame being written to the fifo ? the packet ends before the number of bytes indicated by the payload length field in the ip header is received. when the packet is longer than the indicated payload length, the bytes are ignored as stuff bytes, and no error is reported. when the first type of error is detected, the tcp, ethernet (eth): media access control (mac) with dma controller RM0033 824/1317 doc id 15403 rev 3 udp or icmp header is not modified. for th e second error type, still, the calculated checksum is inserted into the corresponding header field. mii/rmii transmit bit order each nibble from the mii is transmitted on the rmii a dibit at a time with the order of dibit transmission shown in figure 324 . lower order bits (d1 and d0) are transmitted first followed by higher order bits (d2 and d3). figure 324. transmission bit order mii/rmii transmit timing diagrams figure 325. transmission with no collision d0 d1 d2 d3 lsb mii_txd[3:0] msb d0 d1 lsb msb rmii_txd[1:0] bibit stream nibble stream ai15632 mii_tx_clk mii_tx_en m ii _txd[ 3:0] pr ea mb le mii_cs mii_col ai15631 low RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 825/1317 figure 326. transmission with collision figure 327 shows a frame transmission in mii and rmii. figure 327. frame transmission in mmi and rmii modes 28.5.3 mac frame reception the mac received frames are push es into the rx fifo. the status (fill level) of this fifo is indicated to the dma once it crosses the configured receive threshold (rtc in the eth_dmaomr register) so that the dma can initiate pre-configured burst transfers towards the ahb interface. in the default cut-through mode, when 64 bytes (configured with the rtc bits in the eth_dmaomr register) or a full packet of data are received into the fifo, the data are popped out and the dma is notified of its availability. once the dma has initiated the transfer to the ahb interface, the data transfer continues from the fifo until a complete packet has mii_tx_clk mii_tx_en m ii _txd[ 3:0] pr eam ble sfd mii_cs mii_col ai15651 da da jam jam jam jam mii_rx_clk mii_tx_en mii_txd[3:0] rmii_ref_clk rmii_txd[1:0] rmii_tx_en ai15652 ethernet (eth): media access control (mac) with dma controller RM0033 826/1317 doc id 15403 rev 3 been transferred. upon completion of the eof frame transfer, the status word is popped out and sent to the dma controller. in rx fifo store-and-forward mode (configured by the rsf bit in the eth_dmaomr register), a frame is read out only after being written completely into the receive fifo. in this mode, all error frames are dropped (if the core is configured to do so) such that only valid frames are read out and forwarded to the application. in cut-through mode, some error frames are not dropped, because the error status is received at the end of the frame, by which time the start of that frame has already been read out of the fifo. a receive operation is initiated when the mac detects an sfd on the mii. the core strips the preamble and sfd before proceeding to process the frame. the header fields are checked for the filtering and the fcs fi eld used to verify the crc for the frame. the frame is dropped in the core if it fails the address filter. receive protocol the received frame preamble and sfd are stripped. once the sfd has been detected, the mac starts sending the ethernet frame data to the receive fifo, beginning with the first byte following the sfd (destina tion address). if ieee 1588 ti me stamping is enabled, a snapshot of the system time is taken when any frame's sfd is detected on the mii. unless the mac filters out and drops the frame, this time stamp is passed on to the application. if the received frame length/type field is less than 0x600 and if the mac is programmed for the auto crc/pad stripping option, the mac sends the data of the frame to rxfifo up to the count specified in the length/type field, then starts dropping bytes (including the fcs field). if the length/type field is greater than or equal to 0x600, the mac sends all received ethernet frame data to rx fifo, regardless of the value on the programmed auto-crc strip option. the mac watchdog timer is enabled by default, that is, frames above 2048 bytes (da + sa + lt + data + pad + fcs) are cut off. this feature can be disabled by programming the watchdog disable (wd) bit in the mac configuration register. however, even if the watchdog timer is disabled, frames greater than 16 kb in size are cut off and a watchdog timeout status is given. receive crc: automatic crc and pad stripping the mac checks for any crc error in the receiv ing frame. it calculat es the 32-bit crc for the received frame that includes the destination address field through the fcs field. the encoding is defined by the following polynomial. regardless of the auto-pad/crc strip, the mac receives the entire frame to compute the crc check for the received frame. receive checksum offload both ipv4 and ipv6 frames in the received ethernet frames are detected and processed for data integrity. you can enable the receive checksum offload by setting the ipco bit in the eth_maccr register. the mac receiver identifies ipv4 or ipv6 frames by checking for value 0x0800 or 0x86dd, respectively, in the received ethernet frame type field. this identification applies to vlan-tagged frames as well. the receive checksum offload calculates ipv4 header checksums and checks that they match the received ipv4 header checksums. the ip header error bit is set for any mismatch between the indicated payload gx () x 32 x 26 x 23 x 22 x 16 x 12 x 11 x 10 x 8 x 7 x 5 x 4 x 2 x1 + + + + + + + +++++++ = RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 827/1317 type (ethernet type field) and the ip header version, or when the received frame does not have enough bytes, as indicated by the ipv4 header?s length field (or when fewer than 20 bytes are available in an ipv4 or ipv6 header). the receive checksum offload also identifies a tcp, udp or icmp payload in the received ip datagrams (ipv4 or ipv6) and calculates the checksum of such payloads properly, as defined in the tcp, udp or icmp specifications. it includes the tcp/udp/icmpv6 pseudo-header bytes for checksum calculation and checks whether the received checksum field matches the calculated value. the result of this operation is given as a payload checksum error bit in the receive status word. this status bit is also set if the length of the tcp, udp or icmp payload does not match the expected payload length given in the ip header. as mentioned in tcp/udp/icmp checksum on page 823 , the receive checksum offload bypasses the payload of fragmented ip datagrams, ip datagrams with security features, ipv6 routing headers, and payloads other than tcp, udp or icmp. this information (whether the checksum is bypassed or not) is given in the receive status, as described in the rdes0: receive descriptor word0 section. in this configuration, the core does not append any payload checksum bytes to the received ethernet frames. as mentioned in rdes0: receive descriptor word0 on page 861 , the meaning of certain register bits changes as shown in ta bl e 1 4 2 . receive frame controller if the ra bit is reset in the mac csr frame filter register, the mac performs frame filtering based on the destination/source address (the application still ne eds to perform another level of filtering if it decides not to receive any bad frames like runt, crc er ror frames, etc.). on detecting a filter-fail, the frame is dropped and not transferred to the application. when the filtering parameters are changed dynamically, and in case of (da-sa) filter-fail, the rest of table 142. frame statuses bit 18: ethernet frame bit 27: header checksum error bit 28: payload checksum error frame status 00 0 the frame is an ieee 802.3 frame (length field value is less than 0x0600). 10 0 ipv4/ipv6 type frame in which no checksum error is detected. 10 1 ipv4/ipv6 type frame in which a payload checksum error (as described for pce) is detected 11 0 ipv4/ipv6 type frame in which ip header checksum error (as described for ipco hce) is detected. 11 1 ipv4/ipv6 type frame in which both pce and ipco hce are detected. 00 1 ipv4/ipv6 type frame in which there is no ip hce and the payload check is bypassed due to unsupported payload. 01 1 type frame which is neither ipv4 or ipv6 (checksum offload bypasses the checksum check completely) 0 1 0 reserved ethernet (eth): media access control (mac) with dma controller RM0033 828/1317 doc id 15403 rev 3 the frame is dropped and the rx status word is immediately updated (with zero frame length, crc error and runt error bits set), indicating the filter fail. in ethernet power down mode, all received frames are dropped, and are not forwarded to the application. receive flow control the mac detects the receiving pause frame and pauses the frame transmission for the delay specified within the received pause frame (only in full-duplex mode). the pause frame detection function can be enabled or disabled with the rfce bit in eth_macfcr. once receive flow control has been enabled, the received frame destination address begins to be monitored for any match with the multicast address of the control frame (0x0180 c200 0001). if a match is detected (the destination address of the received frame matches the reserved control frame destination address), the mac then decides whether or not to transfer the received control frame to the application, based on the level of the pcf bit in eth_macffr. the mac also decodes the type, opcode, and p ause timer fields of the receiving control frame. if the byte count of the status indicates 64 bytes, and if there is no crc error, the mac transmitter pauses the transmission of any data frame for the duration of the decoded pause time value, multiplied by the slot time (64 byte times for both 10/100 mbit/s modes). meanwhile, if another pause frame is detected with a zero pause time value, the mac resets the pause time and manages this new pause request. if the received control frame matches neither the type field (0x8808), the opcode (0x00001), nor the byte length (64 bytes), or if there is a crc error, the mac does not generate a pause. in the case of a pause frame with a multicast destination address, the mac filters the frame based on the address match. for a pause frame with a unicast destination address, the mac filtering depends on whether the da matched the contents of the mac address 0 register and whether the updf bit in eth_macfcr is set (detecting a pause fram e even with a unicast destination address). the pcf register bits (bits [7:6] in eth_mac ffr) control filtering fo r control frames in addition to address filtering. receive operation multiframe handling since the status is available immediately following the data, the fifo is capable of storing any number of frames into it, as long as it is not full. error handling if the rx fifo is full before it receives the eof data from the mac, an overflow is declared and the whole frame is dropped, and the overflow counter in the (eth_dmamfbocr register) is incremented. the status indicates a partial frame due to overflow. the rx fifo can filter error and undersized frames, if enabled (using the fef and fugf bits in eth_dmaomr). if the receive fifo is configured to operate in store-and-forward mode, all error frames can be filtered and dropped. in cut-through mode, if a frame's status and length are available when that frame's sof is read from the rx fifo, then the complete erroneous frame can be dropped. the dma can flush the error frame being read from the fifo, by enabling the receive frame flash bit. the data transfer to the application (dma) is then stopped and the rest of the frame is internally read and dropped. the next frame transfer can then be started, if available. RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 829/1317 receive status word at the end of the ethernet frame reception, the mac outputs the receive status to the application (dma). the detailed description of the receive status is the same as for bits[31:0] in rdes0, given in rdes0: receive descriptor word0 on page 861 . frame length interface in case of switch applications, data transmission and reception between the application and mac happen as complete frame transfers. the application layer should be aware of the length of the frames received from the ingress port in order to transfer the frame to the egress port. the mac core provides the frame length of each received frame inside the status at the end of each frame reception. note: a frame length value of 0 is given for partial frames written into the rx fifo due to overflow. mii/rmii receive bit order each nibble is transmitted to the mii from the dibit received from the rmii in the nibble transmission order shown in figure 328 . the lower-order bits (d0 and d1) are received first, followed by the higher-order bits (d2 and d3). figure 328. receive bit order d0 d1 d2 d3 lsb mii_rxd[3:0] msb d0 d1 lsb msb rmii_rxd[1:0] di-bit stream nibble stream ai15633 ethernet (eth): media access control (mac) with dma controller RM0033 830/1317 doc id 15403 rev 3 figure 329. reception with no error figure 330. reception with errors figure 331. reception with false carrier indication 28.5.4 mac interrupts interrupts can be generated from the mac core as a result of various events. the eth_macsr register describes the events that can cause an interrupt from the mac core. you can prevent each event from asserting the interrupt by setting the corresponding mask bits in the interrupt mask register. mii_rx_clk mii_rx_dv mii_rxd[3:0] preamble sfd mii_rx_err ai15634 fcs mii_rx_clk mii_rx_dv mii_rxd[3:0] preamble sfd mii_rx_err ai15635 da da xx xx xx mii_rx_clk mii_rx_dv mii_rxd[3:0] xx mii_rx_err ai15636 0e xx xx xx xx xx xx xx RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 831/1317 the interrupt register bits only indicate the block from which the event is reported. you have to read the corresponding status registers and other registers to clear the interrupt. for example, bit 3 of the interrupt register, set high, indicates that the magic packet or wake-on- lan frame is received in power-down mode. you must read the eth_macpmtcsr register to clear this interrupt event. figure 332. mac core interrupt masking scheme 28.5.5 mac filtering address filtering address filtering checks the destination and source addresses on all received frames and the address filtering status is reported accordingly. address checking is based on different parameters (frame filter register) chosen by the application. the filtered frame can also be identified: multicast or broadcast frame. address filtering uses the station's physical (mac) address and the multicast hash table for address checking purposes. unicast destination address filter the mac supports up to 4 mac addresses for unicast perfect filtering. if perfect filtering is selected (hu bit in the frame filter register is reset), the mac compares all 48 bits of the received unicast address with the programmed mac address for any match. default macaddr0 is always enabled, other addresses macaddr1?macaddr3 are selected with an individual enable bit. each byte of these other addresses (macaddr1?macaddr3) can be masked during comparison with the corresponding received da byte by setting the corresponding mask byte control bit in the register. this helps group address filtering for the da. in hash filtering mode (when hu bit is set), the mac performs imperfect filtering for unicast addresses using a 64-bit hash table. for hash filtering, the mac uses the 6 upper crc (see note 1 below) bits of the received destination address to index the content of the hash table. a value of 000000 selects bit 0 in the selected register, and a value of 111111 selects bit 63 in the hash table register. if the corresponding bit (indicated by the 6-bit crc) is set to 1, the unicast frame is said to have passed the hash filter; otherwise, the frame has failed the hash filter. note: 1 this crc is a 32-bit value coded by the fo llowing polynomial (for more details refer to section 28.5.3: mac frame reception ): and and or tsti pmti interrupt tsts pmts pmtim ai15637 tstim gx () x 32 x 26 x 23 x 22 x 16 x 12 x 11 x 10 x 8 x 7 x 5 x 4 x 2 x1 + + + + + + + +++++++ = ethernet (eth): media access control (mac) with dma controller RM0033 832/1317 doc id 15403 rev 3 multicast destination address filter the mac can be programmed to pass all multicast frames by setting the pam bit in the frame filter register. if the pam bit is reset, the mac performs the filtering for multicast addresses based on the hm bit in the frame filter register. in perfect filtering mode, the multicast address is compared with the programmed mac destination address registers (1? 3). group address filtering is also supported. in hash filtering mode, the mac performs imperfect filtering using a 64-bit hash table. for hash filtering, the mac uses the 6 upper crc (see note 1 below) bits of the received multicast address to index the content of the hash table. a value of 000000 selects bit 0 in the selected register and a value of 111111 selects bit 63 in the hash table register. if the corresponding bit is set to 1, then the multicast frame is said to have passed the hash filter; otherwise, the frame has failed the hash filter. note: 1 this crc is a 32-bit value coded by the fo llowing polynomial (for more details refer to section 28.5.3: mac frame reception ): hash or perfect address filter the da filter can be configured to pass a frame when its da matches either the hash filter or the perfect filter by setting the hpf bit in the frame filter register and setting the corresponding hu or hm bits. this configurat ion applies to both unicast and multicast frames. if the hpf bit is reset, only one of the filters (hash or perfect) is applied to the received frame. broadcast address filter the mac does not filter any broadcast frames in the default mode. however, if the mac is programmed to reject all broadcast frames by setting the bfd bit in the frame filter register, any broadcast frames are dropped. unicast source address filter the mac can also perform perfect filtering based on the source address field of the received frames. by default, the mac compares the sa field with the values programmed in the sa registers. the mac address registers [1:3] can be configured to contain sa instead of da for comparison, by setting bit 30 in the corresponding register. group filtering with sa is also supported. the frames that fail the sa filter are dropped by the mac if the saf bit in the frame filter register is set. otherwise, the result of the sa filter is given as a status bit in the receive status word (see rdes0: receive descriptor word0 ). when the saf bit is set, the result of the sa and da filters is and?ed to decide whether the frame needs to be forwarded. th is means that either of the filter fail result will drop the frame. both filters have to pass the frame for the frame to be forwarded to the application. inverse filtering operation for both destination and source address filtering, there is an option to invert the filter-match result at the final output. these are controlled by the daif and saif bits in the frame filter register, respectively. the daif bit is applicable for both unicast and multicast da frames. the result of the unicast/mult icast destination address filter is inverted in this mode. similarly, when the saif bit is set, the result of the unicast sa filter is inverted. ta b l e 1 4 3 gx () x 32 x 26 x 23 x 22 x 16 x 12 x 11 x 10 x 8 x 7 x 5 x 4 x 2 x1 + + + + + + + +++++++ = RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 833/1317 and ta b l e 1 4 4 summarize destination and source address filtering based on the type of frame received. table 143. destination address filtering table frame type pm hpf hu daif hm pam db da filter operation broadcast 1xxx x xxpass 0xxx x x0pass 0xxx x x1fail unicast 1 x x x x x x pass all frames 0 x 0 0 x x x pass on perfect/group filter match 0 x 0 1 x x x fail on perfect/group filter match 0 0 1 0 x x x pass on hash filter match 0 0 1 1 x x x fail on hash filter match 01 1 0 x xx pass on hash or perfect/group filter match 0 1 1 1 x x x fail on hash or perfect/group filter match multicast 1 x x x x x x pass all frames x x x x x 1 x pass all frames 0xx0 0 0 x pass on perfect/group filter match and drop pause control frames if pcf = 0x 00 x0 1 0 x pass on hash filter match and drop pause control frames if pcf = 0x 01 x0 1 0 x pass on hash or perfect/group filter match and drop pause control frames if pcf = 0x 0xx1 0 0 x fail on perfect/group filter match and drop pause control frames if pcf = 0x 00 x1 1 0 x fail on hash filter match and drop pause control frames if pcf = 0x 01 x1 1 0 x fail on hash or perfect/group filter match and drop pause control frames if pcf = 0x ethernet (eth): media access control (mac) with dma controller RM0033 834/1317 doc id 15403 rev 3 28.5.6 mac loopback mode the mac supports loopback of transmitted frames onto its receiver. by default, the mac loopback function is disabled, but this feature can be enabled by programming the loopback bit in the mac eth_maccr register. 28.5.7 mac management counters: mmc the mac management counters (mmc) maintain a set of registers for gathering statistics on the received and transmitted frames. these include a contro l register for controlling the behavior of the registers, two 32-bit registers containing generated interrupts (receive and transmit), and two 32-bit registers containing masks for the interrupt register (receive and transmit). these registers are accessible from the application. each register is 32 bits wide. section 28.8: ethernet register descriptions describes the various counters and lists the addresses of each of the statistics counters. this address is used for read/write accesses to the desired transmit/receive counter. the receive mmc counters are updated for frames that pass address filtering. dropped frames statistics are not updated unless the dropped frames are runt frames of less than 6 bytes (da bytes are not received fully). good transmitted and received frames transmitted frames are considered ?good? if transmitted successfully. in other words, a transmitted frame is good if the frame transmission is not aborted due to any of the following errors: + jabber timeout + no carrier/lo ss of carrier + late collision + frame underflow + excessive deferral + excessive collision table 144. source address filtering table frame type rtp r saif saf sa filter operation unicast 1 x x pass all frames 000 pass status on perfect/group fi lter match but do not drop frames that fail 010fail status on perfect/group filter match but do not drop frame 001pass on perfect/group filter match and drop frames that fail 011fail on perfect/group filter match and drop frames that fail RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 835/1317 received frames are considered ?good? if none of the following errors exists: + crc error + runt frame (shorter than 64 bytes) + alignment error (in 10/ 100 mbit/s only) + length error (non-type frames only) + out of range (non-type frames only, longer than maximum size) + mii_rxer input error the maximum frame size depends on the frame type, as follows: + untagged frame maxsize = 1518 + vlan frame maxsize = 1522 28.5.8 power management: pmt this section describes the power management (pmt) mechanisms supported by the mac. pmt supports the reception of network (remote) wakeup frames and magic packet frames. pmt generates interrupts for wakeup frames and magic packets received by the mac. the pmt block is enabled with remote wakeup frame enable and magic packet enable. these enable bits (wfe and mpe) are in the eth_macpmtcsr register and are programmed by the application. when the power down mode is enabled in the pmt, then all received frames are dropped by the mac and they are not forwarded to the application. the mac comes out of the power down mode only when either a magic packet or a remote wakeup frame is received and the corresponding detection is enabled. remote wakeup frame filter register there are eight wakeup frame filter registers. to write on each of them, load the wakeup frame filter register value by value. the wanted values of the wakeup frame filter are loaded by sequentially loading eight times the wakeup frame filter register. the read operation is identical to the write operation. to read the eight values, you have to read eight times the wakeup frame filter register to reach the last register. each read/write points the wakeup frame filter register to the next filter register. ethernet (eth): media access control (mac) with dma controller RM0033 836/1317 doc id 15403 rev 3 figure 333. wakeup frame filter register filter i byte mask this register defines which bytes of the frame are examined by filter i (0, 1, 2, and 3) in order to determine whether or not the frame is a wakeup frame. the msb (thirty-first bit) must be zero. bit j [30:0] is the byte mask. if bit j (byte number) of the byte mask is set, then filter i offset + j of the incoming frame is processed by the crc block; otherwise filter i o ffset + j is ignored. filter i command this 4-bit command controls the filter i operation. bit 3 specifies the address type, defining the pattern?s destination address type. when the bit is set, the pattern applies to only multicast frames. when the bit is reset, the pattern applies only to unicast frames. bit 2 and bit 1 are reserved. bit 0 is the enable bit for filter i; if bit 0 is not set, filter i is disabled. filter i offset this register defines the offset (within the frame) from which the frames are examined by filter i. this 8-bit pattern offset is the offset for the filter i first byte to be examined. the minimum allowed is 12, which refers to the 13th byte of the frame (offset value 0 refers to the first byte of the frame). filter i crc-16 this register contains the crc_16 value calculated from the pattern, as well as the byte mask programmed to the wakeup filter register block. remote wakeup frame detection when the mac is in sleep mode and the remote wakeup bit is enabled in the eth_macpmtcsr register, normal operation is resumed after receiving a remote wakeup frame. the application writes all eight wakeup filter registers, by performing a sequential write to the wakeup frame filter register address. the application enables remote wakeup by writing a 1 to bit 2 in the eth_macpmtcsr register. pmt supports four programmable filters that provide different receive frame patterns. if the incoming frame passes the address filtering of filter command, and if filter crc-16 matches the incoming examined pattern, then the wakeup frame is received. filter_offset (minimum value 12, which refers to the 13th byte of the frame) determines the offset from which the frame is to be examined. filter byte mask determines which bytes of the frame must be examined. the thirty-first bit of byte mask must be set to zero. the wakeup frame is checked only for length error, fcs error, dribble bit error, mii error, collision, and to ensu re that it is not a r unt frame. even if the filter 0 byte mask filter 1 byte mask filter 2 byte mask filter 3 byte mask rsvd filter 3 command rsvd filter 2 command rsvd filter 1 command rsvd filter 0 command filter 3 offset filter 2 offset filter 1 offset filter 0 offset filter 1 crc - 16 filter 0 crc - 16 filter 3 crc - 16 filter 2 crc - 16 wakeup frame filter reg0 wakeup frame filter reg1 wakeup frame filter reg2 wakeup frame filter reg3 wakeup frame filter reg4 wakeup frame filter reg5 wakeup frame filter reg6 wakeup frame filter reg7 ai15647 RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 837/1317 wakeup frame is more than 512 bytes long, if the frame has a valid crc value, it is considered valid. wakeup frame detection is updated in the eth_macpmtcsr register for every remote wakeup frame received. if enabled, a pmt interrupt is generated to indicate the reception of a remote wakeup frame. magic packet detection the magic packet frame is based on a method that uses advanced micro device?s magic packet technology to power up the sleeping device on the network. the mac receives a specific packet of information, called a magic packet, addressed to the node on the network. only magic packets that are addressed to the device or a broadcast address are checked to determine whether they meet the wakeup requirements. magic packets that pass address filtering (unicast or broadcast) are checked to determine whether they meet the remote wake-on-lan data format of 6 bytes of all ones followed by a mac address appearing 16 times. the application enables magic packet wakeup by writing a 1 to bit 1 in the eth_macpmtcsr register. the pmt block constantly monitors each frame addressed to the node for a specific magic packet pattern. each received frame is checked for a 0xffff ffff ffff pattern following the destination and source address field. the pmt block then checks the frame for 16 repetitions of the mac address without any breaks or interruptions. in case of a break in the 16 repetitions of the address, the 0xffff ffff ffff pattern is scanned for again in the incoming frame. the 16 repetitions can be anywhere in the frame, but must be preceded by the synchronization stream (0xffff ffff ffff). the device also accepts a multicast frame, as lo ng as the 16 duplications of the mac address are detected. if the mac address of a node is 0x0011 2233 4455, then the mac scans for the data sequence: destination address source address ??????.. ffff ffff ffff 0011 2233 4455 0011 2233 4455 0011 2233 4455 0011 2233 4455 0011 2233 4455 0011 2233 4455 0011 2233 4455 0011 2233 4455 0011 2233 4455 0011 2233 4455 0011 2233 4455 0011 2233 4455 0011 2233 4455 0011 2233 4455 0011 2233 4455 0011 2233 4455 ?crc magic packet detection is updated in the eth_macpmtcsr register for received magic packet. if enabled, a pmt interrupt is generated to indicate the reception of a magic packet. system consideration during power-down the ethernet pmt block is able to detect frames while the system is in the stop mode, provided that the exti line 19 is enabled. the mac receiver state machine should remain enabled during the power-down mode. this means that the re bit has to remain set in the eth_maccr register because it is involved in magic packet/ wake-on-lan frame detection. the transmit state machine should however be turned off during the power-down mode by clearing the te bit in the eth_maccr register. moreover, the ethernet dma should be disabled during the power-down mode, because it is not necessary to copy the magic packet/wake-on-lan frame into the sram. to disable the ethernet dma, clear the st bit and the sr bit (for the transmit dma and the receive dma, respectively) in the eth_dmaomr register. the recommended power-down and wakeup sequences are as follows: ethernet (eth): media access control (mac) with dma controller RM0033 838/1317 doc id 15403 rev 3 1. disable the transmit dma and wait for any previous frame transmissions to complete. these transmissions can be detected wh en the transmit interrupt eth_dmasr register[0] is received. 2. disable the mac transmitter and mac receiver by clearing the re and te bits in the eth_maccr configuration register. 3. wait for the receive dma to have emptied all the frames in the rx fifo. 4. disable the receive dma. 5. configure and enable the exti line 19 to generate either an event or an interrupt. 6. if you configure the exti line 19 to generate an interrupt, you also have to correctly configure the eth_wkup_irq handler function, which should clear the pending bit of the exti line 19. 7. enable magic packet/wake-on-lan frame detection by setting the mfe/ wfe bit in the eth_macpmtcsr register. 8. enable the mac power-down mode, by setting the pd bit in the eth_macpmtcsr register. 9. enable the mac receiver by setting the re bit in the eth_maccr register. 10. enter the system?s stop mode (for more details refer to section 5.3.4: stop mode ): 11. on receiving a valid wakeup frame, the ethernet peripheral exits the power-down mode. 12. read the eth_macpmtcsr to clear the power management event flag, enable the mac transmitter state machine, and the receive and transmit dma. 13. configure the system clock: enable the hse and set the clocks. 28.5.9 precision time pr otocol (ieee1588 ptp) the ieee 1588 standard defines a protocol that allows precise clock synchronization in measurement and control systems implemented with technologies such as network communication, local computing and distributed objects. the protocol applies to systems that communicate by local area networks suppor ting multicast messaging, including (but not limited to) ethernet. this protocol is used to synchronize heterogeneous systems that include clocks of varying inherent precision, resolution and stability. the protocol supports system-wide synchronizati on accuracy in the submicrosecond range with minimum network and local clock computing resources. the message-based protocol, known as the precision time protocol (ptp), is transported over udp/ ip. the system or networ k is classified into master and slave nodes for distributing the timing/clock information. the protocol?s technique for synchronizing a slave node to a master node by exchanging ptp messages is described in figure 334 . RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 839/1317 figure 334. networked time synchronization 1. the master broadcasts ptp sync messages to all its nodes. the sync message contains the master?s reference time information. the time at which this message leaves the master?s system is t 1 . for ethernet ports, this time has to be captured at the mii. 2. a slave receives the sync message and also captures the exact time, t 2 , using its timing reference. 3. the master then sends the slave a follow_up message, which contains the t 1 information for later use. 4. the slave sends the master a delay_req message, noting the exact time, t 3 , at which this frame leaves the mii. 5. the master receives this message and captures the exact time, t 4 , at which it enters its system. 6. the master sends the t 4 information to the slave in the delay_resp message. 7. the slave uses the four values of t 1 , t 2 , t 3 , and t 4 to synchronize its local timing reference to the master?s timing reference. most of the protocol implementation occurs in the software, above the udp layer. as described above, however, hardware support is required to capture the exact time when specific ptp packets enter or leave the ethernet port at the mii. this timing information has to be captured and returned to the software for a proper, high-accuracy implementation of ptp. reference timing source to get a snapshot of the time, the core requires a reference time in 64-bit format (split into two 32-bit channels, with the upper 32 bits providing time in seconds, and the lower 32 bits indicating time in nanoseconds) as defined in the ieee 1588 specification. the ptp reference clock input is used to internally generate the reference time (also called the system time) and to capture time stamps. the frequency of this reference clock must master clock time slave clock time data at slave clock sync message follow_up message containing value of t1 delay_req message delay_resp message containing value of t4 time t 1 t 2m t 3m t 4 t 1 , t 2 , t 3 , t 4 t 2 t 1 , t 2 t 3 t 2 t 1 , t 2 , t 3 ai15669 ethernet (eth): media access control (mac) with dma controller RM0033 840/1317 doc id 15403 rev 3 be greater than or equal to the resolution of time stamp counter. the synchronization accuracy target between the master node and the slaves is around 100 ns. the generation, update and modification of the system time are described in the section : system time correction methods . the accuracy depends on the ptp reference clock input period, the characteristics of the oscillator (drift) and the frequency of the synchronization procedure. due to the synchronization from the tx and rx clock input domain to the ptp reference clock domain, the uncertainty on the time stamp latched value is 1 reference clock period. if we add the uncertainty due to resolution, we will add half th e period for time stamping. transmission of frames with the ptp feature when a frame?s sfd is output on the mii, a time stamp is captured. frames for which time stamp capture is required are controllable on a per-frame basis. in other words, each transmitted frame can be marked to indicate whether a time stamp must be captured or not for that frame. the transmitted frames are no t processed to identify ptp frames. frame control is exercised through the control bits in the transmit descriptor. captured time stamps are returned to the application in the same way as the status is provided for frames. the time stamp is sent back along with the transmit status of the frame, inside the corresponding transmit descriptor, thus connecting the time stamp automatically to the specific ptp frame. the 64-bit time stamp information is written back to the tdes2 and tdes3 fields, with tdes2 holding the time stamp?s 32 least significant bits. reception of frames with the ptp feature when the ieee 1588 time stampi ng feature is enabled, the et hernet mac captures the time stamp of all frames received on the mii. the mac provides the time stamp as soon as the frame reception is complete. captured time stamps are returned to the application in the same way as the frame status is provided. the time stamp is sent back along with the receive status of the frame, inside the corresponding receive descriptor. the 64-bit time stamp information is written back to the rd es2 and rdes3 fields, with rdes2 holding the time stamp?s 32 least significant bits. system time correction methods the 64-bit ptp time is updated using the ptp input reference clock, hclk. this ptp time is used as a source to take snapshots (time stamps) of the ethernet frames being transmitted or received at the mii. the system time counter can be initialized or corrected using either the coarse or the fine correction method. in the coarse correction method, the initial value or the offset value is written to the time stamp update register (refer to section 28.8.3: ieee 1588 time stamp registers on page 898 ). for initialization, the system time coun ter is written with the value in the time stamp update registers, whereas for system time correction, the offset value (time stamp update register) is added to or subtracted from the system time. in the fine correction method, the slave clock (reference clock) frequency drift with respect to the master clock (as defined in ieee 1588) is corrected ov er a period of time, unlike in the coarse correction me thod where it is corrected in a sing le clock cycle. the longer correction time helps maintain linea r time and does not introduce drastic changes (or a large jitter) in the reference time between ptp sync message intervals. in this method, an accumulator sums up the contents of the addend register as shown in figure 335 . the arithmetic carry that the accumulator generates is used as a pulse to increment the system time counter. RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 841/1317 the accumulator and the addend are 32-bit registers. here, the accumulator acts as a high- precision frequency multiplier or divider. figure 335 shows this algorithm. figure 335. system time update using the fine correction method the system time update logic requires a 50 mhz clock frequency to achieve 20 ns accuracy. the frequency division is the ratio of the re ference clock frequency to the required clock frequency. hence, if the reference clock (hclk) is, let us say, 66 mhz, the ratio is calculated as 66 mhz/50 mhz = 1.32. hence, the default addend value to be set in the register is 2 32 /1.32, which is equal to 0xc1f0 7c1f. if the reference clock drifts lower, to 65 mhz for example, the ratio is 65/50 or 1.3 and the value to set in the addend register is 2 32 /1.30 equal to 0xc4ec 4ec4. if the clock drifts higher, to 67 mhz for example, the addend register must be set to 0xbf0 b7672. when the clock drift is zero, the default addend value of 0xc1f0 7c1f (2 32 /1.32) should be programmed. in figure 335 , the constant value used to increment the subsecond register is 0d43. this makes an accuracy of 20 ns in the system time (in other words, it is incremented by 20 ns steps). the software has to calculate the drift in frequency based on the sync messages, and to update the addend register accordingly. initially, the slave clock is set with freqcompensationvalue0 in the addend register. this value is as follows: freqcompensationvalue0 = 2 32 / freqdivisionratio if mastertoslavedelay is initially assumed to be the same for consecutive sync messages, the algorithm described below must be applied. after a few sync cycles, frequency lock occurs. the slave clock can then determine a precise mastertoslavedelay value and re- synchronize with the master using the new value. addend register + accumulator register subsecond register + constant value second register increment second register addend update ai15670 increment subsecond register ethernet (eth): media access control (mac) with dma controller RM0033 842/1317 doc id 15403 rev 3 the algorithm is as follows: at time mastersynctime (n) the master sends the slave clock a sync message. the slave receives this message when its local clock is slav eclocktime (n) and computes masterclocktime (n) as: masterclocktime (n) = mastersynctime (n) + mastertoslavedelay (n) the master clock count for current sync cycle, masterclockcount (n) is given by: masterclockcount (n) = masterclocktime (n) ? masterclocktime (n ? 1) (assuming that mastertoslavedelay is the sa me for sync cycles n and n ? 1) the slave clock count for current sync cycle, slaveclockcount (n) is given by: slaveclockcount (n) = slaveclocktime (n) ? slaveclocktime (n ? 1) the difference between master and slave clock counts for current sync cycle, clockdiffcount (n) is given by: clockdiffcount (n) = masterclockcount (n) ? slaveclockcount (n) the frequency-scaling factor for slave clock, freqscalefactor (n) is given by: freqscalefactor (n) = (masterclockcount (n) + clockdiffcount (n)) / slaveclockcount (n) the frequency compensation value for addend register, freqcompensationvalue (n) is given by: freqcompensationvalue (n) = freqscalefactor (n) freqcompensationvalue (n ? 1) in theory, this algorithm achieves lock in one sync cycle; however, it may take several cycles, due to changing network propagation delays and operating conditions. this algorithm is self-correctin g: if for any reason the slave clock is initially set to a value from the master that is incorrect, the algorithm corrects it at the cost of more sync cycles. programming steps for system time generation initialization the time stamping feature can be enabled by setting bit 0 in the time stamp control register (eth__ptptscr). however, it is essential to in itialize the time stamp counter after this bit is set to start time stamp operation. the proper sequence is the following: 1. mask the time stamp trigger interrupt by setting bit 9 in the macimr register. 2. program time stamp register bit 0 to enable time stamping. 3. program the subsecond increment register based on the ptp clock frequency. 4. if you are using the fine correction method, program the time stamp addend register and set time stamp control register bit 5 (addend register update). 5. poll the time stamp control register until bit 5 is cleared. 6. to select the fine correction method (if required), program time stamp control register bit 1. 7. program the time stamp high update and time stamp low update registers with the appropriate time value. 8. set time stamp control register bit 2 (time stamp init). 9. the time stamp counter starts operation as soon as it is initialized with the value written in the time stamp update register. 10. enable the mac receiver and transmitter for proper time stamping. note: if time stamp operation is disabled by clearing bit 0 in the eth_ptptscr register, the above steps must be repeated to restart the time stamp operation. RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 843/1317 programming steps for system time update in the coarse correction method to synchronize or update the system time in one process (coarse correction method), perform the following steps: 1. write the offset (positive or negative) in the time stamp update high and low registers. 2. set bit 3 (tsstu) in the time stamp control register. 3. the value in the time stamp update registers is added to or subtracted from the system time when the tsstu bit is cleared. programming steps for system time update in the fine correction method to synchronize or update the system time to reduce system-time jitter (fine correction method), perform the following steps: 1. with the help of the algorithm explained in section : system time correction methods , calculate the rate by which you want to speed up or slow down the system time increments. 2. update the time stamp. 3. wait the time you want the new value of the addend register to be active. you can do this by activating the time stamp trigger interrupt after the system time reaches the target value. 4. program the required target time in the target time high and low registers. unmask the time stamp interrupt by clearing bit 9 in the eth_macimr register. 5. set time stamp control register bit 4 (tsaru). 6. when this trigger causes an interrupt, read the eth_macsr register. 7. reprogram the time stamp addend register with the old value and set eth_tptscr bit 5 again. ptp trigger internal connection with tim2 the mac provides a tri gger interrupt when the system time becomes greater th an the target time. using an interrupt introduces a known latency plus an uncertainty in the command execution time. in order to avoid this uncertainty, a ptp trigger output signal is set high when the system time is greater than the target time. it is internally connected to the tim2 input trigger. with this signal, the input capture feature, the output compare feature and the waveforms of the timer can be used, triggered by the synchronized ptp system time. no uncertainty is introduced since the clock of the timer (pclk1: tim2 apb1 clock) and ptp reference clock (hclk) are synchronous. this ptp trigger signal is connected to the tim2 itr1 input selectable by software. the connection is enabled through bits 11 and 10 in the tim2 option register (tim2_or). figure 336 shows the connection. figure 336. ptp trigger output to tim2 itr1 connection ethernet mac ai15671 tim2 itr1 ptp trigger ethernet (eth): media access control (mac) with dma controller RM0033 844/1317 doc id 15403 rev 3 ptp pulse-per-second output signal this ptp pulse output is used to check the synchronization between all nodes in the network. to be able to test the difference between the local slave clock and the master reference clock, both clocks were given a pulse -per-second (pps) output signal that may be connected to an oscilloscope if necessary. the deviation between the two signals can therefore be meas ured. the pulse width of the pps output is 125 ms. the pps output is enable d through bits 11 and 10 in the tim2 op tion register (tim2_or). the default frequency of th e pps output is 1 hz. ppsfreq[ 3:0] (in eth_ptpppscr) can be used to set the frequency of the pps output to 2 ppsfreq hz. when set to 1 hz, the pps puls e width is 125 ms with binary rollover (tsssr=0, bit 9 in eth_ptptscr) and 100 ms with digital rollover (tsssr=1). when set to 2 hz and higher, the duty cycle of the pps output is 50% with binary rollover. with digital rollover (tsssr=1), it is re commended not to use the pps output with a frequency other than 1 hz as it would have irregular waveforms (though its average frequency would always be correct during any one-second window). figure 337. pps output 28.6 ethernet functional descri ption: dma controller operation the dma has independent transmit and receive engines, and a csr space. the transmit engine transfers data from system memory into the tx fifo while the receive engine transfers data from the rx fifo into system memory. the controller ut ilizes descriptors to efficiently move data from source to destination with minimum cpu intervention. the dma is designed for packet-oriented data transfers such as frames in ethernet. the controller can be programmed to interrupt the cpu in cases such as frame transmit and receive transfer completion, and other normal/error conditions. the dma and the stm32f20x and stm32f21x communicate through two data structures: control and status registers (csr) descriptor lists and data buffers. control and status registers are described in detail in section 28.8 on page 872 . descriptors are described in detail in section on page 852 . the dma transfers the received data frames to the receive buffer in the stm32f20x and stm32f21x memory, and transmits data frames from the transmit buffer in the stm32f20x and stm32f21x memory. descriptors that reside in the stm32f20x and stm32f21x memory act as pointers to these buffers. there are two descriptor lists: one for reception, and one for transmission. the base address of each list is written into dma registers 3 and 4, respectively. a descriptor list is forward-linked (either implicitly or explicitly). the last descriptor may point back to the first entry to create a ring structure. explicit chaining of descriptors is accomplished by configuring the second address chained in both the receive and transmit descriptors (rdes1[14] and tdes0[20]). the descriptor lists reside in the host?s physical memory space. each descriptor can point to a maximum of two buffers. this ethernet mac ai15672 pps output RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 845/1317 enables the use of two physically addressed buffers, instead of two contiguous buffers in memory. a data buffer resides in the host?s physical memory space, and consists of an entire frame or part of a frame, but cannot exceed a single frame. buffers contain only data. the buffer status is maintained in the descript or. data chaining refers to frames that span multiple data buffers. however, a single de scriptor cannot span mult iple frames. the dma skips to the next frame buffer when the end of frame is detected. data chaining can be enabled or disabled. the descriptor ring and chain structure is shown in figure 338 . figure 338. descriptor ring and chain structure 28.6.1 initialization of a transfer using dma initialization for the mac is as follows: 1. write to eth_dmabmr to set stm32f20x and stm32f21x bus access parameters. 2. write to the eth_dmaier register to mask unnecessary interrupt causes. 3. the software driver creates the transmit and receive descriptor lists. then it writes to both the eth_dmardlar and eth_dmatdlar registers, providing the dma with the start address of each list. 4. write to mac registers 1, 2, and 3 to choose the desired filtering options. 5. write to the mac eth_maccr register to configure and enable the transmit and receive operating modes. the ps and dm bits are set based on the auto-negotiation result (read from the phy). 6. write to the eth_dmaomr register to set bits 13 and 1 and start transmission and reception. 7. the transmit and receive engines enter the running state and attempt to acquire descriptors from the respective descriptor lists. the receive and transmit engines then begin processing receive and transmit oper ations. the transmit and receive processes are independent of each other and can be started or stopped separately. 28.6.2 host bus burst access the dma attempts to execute fixed-length burst transfers on the ahb master interface if configured to do so (fb bit in eth_dmabmr). the maximum burst length is indicated and limited by the pbl field (eth_dmabmr [13:8]). the receive and transmit descriptors are descriptor 0 ai15638 descriptor 1 descriptor 2 descriptor n buffer 1 buffer 2 buffer 1 buffer 2 buffer 1 buffer 2 buffer 1 buffer 2 ring structure chain structure descriptor 0 descriptor 1 descriptor 2 buffer 1 buffer 1 buffer 1 next descriptor ethernet (eth): media access control (mac) with dma controller RM0033 846/1317 doc id 15403 rev 3 always accessed in the maximum possible burst size (limited by pbl) for the 16 bytes to be read. the transmit dma initiates a data transfer only when there is sufficient space in the transmit fifo to accommodate the configured burst or the number of bytes until the end of frame (when it is less than the configured burst length). the dma indicates the start address and the number of transfers required to the ahb master interface. when the ahb interface is configured for fixed-length burst, then it transfers data using the best combination of incr4, incr8, incr16 and single transactions. otherwise (no fixed-length burst), it transfers data using incr (undefined length) and single transactions. the receive dma initiates a data transfer only when sufficient data for the configured burst is available in receive fifo or when the end of frame (when it is less than the configured burst length) is detected in the receive fifo. the dma indicates the start address and the number of transfers required to the ahb master interface. when the ahb interface is configured for fixed-length burst, then it transfers data using the best combination of incr4, incr8, incr16 and single transactions. if the end of frame is reached before the fixed- burst ends on the ahb interface, then dummy transfers are performed in order to complete the fixed-length burst. otherwise (fb bit in eth_dmabmr is reset), it transfers data using incr (undefined length) and single transactions. when the ahb interface is configured for address-aligned beats, both dma engines ensure that the first burst transfer the ahb initiates is less than or equal to the size of the configured pbl. thus, all subsequent beats start at an address that is aligned to the configured pbl. the dma can only align the address for beats up to size 16 (for pbl > 16), because the ahb interface does not support more than incr16. 28.6.3 host data buffer alignment the transmit and receive data buffers do not have any restrictions on start address alignment. in our system with 32-bit memory, the start address for the buffers can be aligned to any of the four bytes. however, the dma always initiates transfers with address aligned to the bus width with dummy data for the byte lanes not required. this typically happens during the transfer of the beginning or end of an ethernet frame. example of buffer read: if the transmit buffer address is 0x0000 0ff2, and 15 bytes need to be transferred, then the dma will read five fu ll words from address 0x0000 0ff0, but when transferring data to the transmit fifo, the extra byte s (the first two bytes) will be dropped or ignored. similarly, the last 3 bytes of the last transfer will also be ignored. the dma always ensures it transfers a full 32-bit data items to the transmit fifo, unless it is the end of frame. example of buffer write: if the receive buffer address is 0x0000 0ff2, and 16 bytes of a received frame need to be transferred, then the dma will write five full 32-bit data items from address 0x0000 0ff0. but the first 2 bytes of the first transfer and the last 2 bytes of the third transfer will have dummy data. 28.6.4 buffer size calculations the dma does not update the size fields in the transmit and receive descriptors. the dma updates only the status fields (xdes0) of the descriptors. the driver has to calculate the sizes. the transmit dma transfers the exact number of bytes (indicated by buffer size field in tdes1) towards the mac core. if a descriptor is marked as first (fs bit in tdes0 is set), RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 847/1317 then the dma marks the first transfer from the buffer as the start of frame. if a descriptor is marked as last (ls bit in tdes0), then the dma marks the last transfer from that data buffer as the end of frame. the receive dma transfers data to a buffer until the buffer is full or the end of frame is received. if a descriptor is not marked as last (ls bit in rdes0), then the buffer(s) that correspond to the descriptor are full and the amount of valid data in a buffer is accurately indicated by the buffer size field minus the data buffer pointer offset when the descriptor?s fs bit is set. the offset is zero when the data buffer pointer is aligned to the databus width. if a descriptor is marked as last, then the buffer may not be full (as indicated by the buffer size in rdes1). to compute the amount of valid data in this final buffer, the driver must read the frame length (fl bits in rdes0[29:16]) and subtract the sum of the buffer sizes of the preceding buffers in this frame. the receive dma always transfers the start of next frame with a new descriptor. note: even when the start address of a receive buffer is not aligned to the system databus width the system should allocate a rece ive buffer of a size aligned to the system bus width. for example, if the system allocates a 1024 byte (1 kb) receive buffer starting from address 0x1000, the software can program the buffer start address in the receive descriptor to have a 0x1002 offset. the receive dma writes the frame to this buffer with dummy data in the first two locations (0x1000 and 0x1001). the actual frame is written from location 0x1002. thus, the actual useful space in this buffer is 1022 bytes, even though the buffer size is programmed as 1024 bytes, due to the start address offset. 28.6.5 dma arbiter the arbiter inside the dma takes care of the arbitration between transmit and receive channel accesses to the ahb master interface. two types of arbitrations are possible: round-robin, and fixed-priority. when round-robin arbitration is selected (da bit in eth_dmabmr is reset), the arbiter allocates the databus in the ratio set by the rtpr bits in eth_dmabmr, when both transmit and receive dmas request access simultaneously. when the da bit is set, the receive dma always gets priority over the transmit dma for data access. 28.6.6 error response to dma for any data transfer initiated by a dma channel, if the slave replies with an error response, that dma stops all operations and updates the error bits and the fatal bus error bit in the status register (eth_dmasr register). that dma controller can resume operation only after soft- or hard-resetting the peripheral and re-initializing the dma. 28.6.7 tx dma configuration txdma operation: default (non-osf) mode the transmit dma engine in default mode proceeds as follows: 1. the user sets up the transmit descriptor (tdes0-tdes3) and sets the own bit (tdes0[31]) after setting up the corresponding data buffer(s) with ethernet frame data. 2. once the st bit (eth_dmaomr register[13]) is set, the dma enters the run state. 3. while in the run state, th e dma polls the transmit descri ptor list for frames requiring transmission. after polling starts , it continues in either seq uential descriptor ring order or chained order. if the dma detects a descriptor flagged as owned by the cpu, or if an error condition occurs, transmission is suspended and both the transmit buffer ethernet (eth): media access control (mac) with dma controller RM0033 848/1317 doc id 15403 rev 3 unavailable (eth_dmasr register[2]) and normal interrupt summary (eth_dmasr register[16]) bits are set. the transmit engine proceeds to step 9. 4. if the acquired descriptor is flagged as owned by dma (tdes0[31] is set), the dma decodes the transmit data buffer address from the acquired descriptor. 5. the dma fetches the transmit data from the stm32f20x and stm32f21x memory and transfers the data. 6. if an ethernet frame is stored over data buffers in multiple descriptors, the dma closes the intermediate descriptor and fetches the next descriptor. steps 3, 4, and 5 are repeated until the end of ethernet frame data is transferred. 7. when frame transmission is complete, if ieee 1588 time stamping was enabled for the frame (as indicated in the transmit status) the time stamp value is written to the transmit descriptor (tdes2 and tdes3) that contains the end-of-frame buffer. the status information is then written to this transmit descriptor (tdes0). because the own bit is cleared during this step, the cpu now owns this descriptor. if time stamping was not enabled for this frame, the dma does not alter the contents of tdes2 and tdes3. 8. transmit interrupt (eth_dmasr register [0]) is set after completing the transmission of a frame that has interrupt on completion (tdes1[31]) set in its last descriptor. the dma engine then returns to step 3. 9. in the suspend state, the dma tries to re-acquire the descriptor (and thereby returns to step 3) when it receives a transmit poll demand, and the underflow interrupt status bit is cleared. figure 339 shows the txdma transmission flow in default mode. RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 849/1317 figure 339. txdma operation in default mode txdma operation: osf mode while in the run state, the transmit process can simultaneously acquire two frames without closing the status descriptor of the first (if the osf bit is set in eth_dmaomr register[2]). as the transmit process finishes transferring th e first frame, it immediately polls the transmit descriptor list for the second frame. if the second frame is valid, the transmit process transfers this frame before writing the first frame?s status information. in osf mode, the run-state transmit dma operates according to the following sequence: start txdma (re-)fetch next descriptor write status word to tdes0 wait for tx status transfer data from buffer(s) (ahb) error? own bit set? (ahb) error? frame xfer complete? time stamp present? (ahb) error? write time stamp to tdes2 and tdes3 (ahb) error? stop txdma txdma suspended no ye s no ye s no no start ye s ye s ye s close intermediate descriptor no ye s no ye s no poll demand ai15639 ethernet (eth): media access control (mac) with dma controller RM0033 850/1317 doc id 15403 rev 3 1. the dma operates as described in steps 1?6 of the txdma (default mode). 2. without closing the previous frame?s last descriptor, the dma fetches the next descriptor. 3. if the dma owns the acquired descriptor, the dma decodes the transmit buffer address in this descriptor. if the dma does not own the descriptor, the dma goes into suspend mode and skips to step 7. 4. the dma fetches the transmit frame from the stm32f20x and stm32f21x memory and transfers the frame until the end of frame data are transferred, closing the intermediate descriptors if this frame is split across multiple descriptors. 5. the dma waits for the transmission status and time stamp of the previous frame. when the status is available, the dma writes the time stamp to tdes2 and tdes3, if such time stamp was captured (as indicated by a status bit). the dma then writes the status, with a cleared own bit, to the correspondi ng tdes0, thus closing the descriptor. if time stamping was not enabled for the previous frame, the dma does not alter the contents of tdes2 and tdes3. 6. if enabled, the transmit interrupt is set, the dma fetches the next descriptor, then proceeds to step 3 (when status is normal). if the previous transmission status shows an underflow error, the dma goes into suspend mode (step 7). 7. in suspend mode, if a pending status and time stamp are received by the dma, it writes the time stamp (if enabled for the current frame) to tdes2 and tdes3, then writes the status to the corresponding tdes0. it then sets relevant interrupts and returns to suspend mode. 8. the dma can exit suspend mode and enter the run state (go to step 1 or step 2 depending on pending status) only after receiving a transmit poll demand (eth_dmatpdr register). figure 340 shows the basic flowchart in osf mode. RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 851/1317 figure 340. txdma operation in osf mode transmit frame processing the transmit dma expects that the data buffers contain complete ethernet frames, excluding preamble, pad bytes, and fcs fields. the da, sa, and type/len fields contain valid data. if the transmit descriptor indicates that the mac core must disable crc or pad insertion, the buffer must have complete ethernet frames (excluding preamble), including the crc bytes. frames can be data-chained and span over several buffers. frames have to be delimited by the first descriptor (tdes0[28]) and the last descriptor (tdes0[29]). as the transmission starts, tdes0[28] has to be set in the first descriptor. when this occurs, the frame data are transferred from the memory buffer to the transmit fifo. concurrently, if the last descriptor (tdes0[29]) of the current frame is cleared, the transmit process attempts to acquire the next descriptor. the transmit process expects tdes0[28] to be cleared in this descriptor. if tdes0[29] is cleared, it indicates an intermediary buffer. if tdes0[29] is set, it previous frame status available start txdma (re-)fetch next descriptor write status word to prev. frame?s tdes0 transfer data from buffer(s) (ahb) error? own bit set? (ahb) error? frame xfer complete? time stamp present? (ahb) error? write time stamp to tdes2 & tdes3 for previous frame (ahb) error? stop txdma no ye s no ye s no start ye s close intermediate descriptor no no wait for previous frame?s tx status second frame? ye s ye s no ye s ye s write time stamp to tdes2 & tdes3 for previous frame (ahb) error? (ahb) error? ye s time stamp present? ye s write status word to prev. frame?s tdes0 txdma suspended ye s no ye s no no poll demand no no ai15640 ethernet (eth): media access control (mac) with dma controller RM0033 852/1317 doc id 15403 rev 3 indicates the last buffer of the frame. after the last buffer of the frame has been transmitted, the dma writes back the final status information to the transmit descriptor 0 (tdes0) word of the descriptor that has the last segment set in transmit descriptor 0 (tdes0[29]). at this time, if interrupt on completion (tdes0[30]) is set, transmit interrupt (in eth_dmasr register [0]) is set, the next descriptor is fetched, and the process repeats. actual frame transmission begins after the transmit fifo has reached either a programmable transmit threshold (eth_dmaomr register[16:14]), or a full frame is contained in the fifo. there is also an option for the store and forward mode (eth_dmaomr register[21]). descriptors are released (own bit tdes0[31] is cleared) when the dma finishes transferring the frame. transmit polling suspended transmit polling can be suspended by either of the following conditions: the dma detects a descriptor owned by the cpu (tdes0[31]=0) and the transmit buffer unavailable flag is set (eth_dmasr register[2]). to resume, the driver must give descriptor ownership to the dma and then issue a poll demand command. a frame transmission is aborted when a transmit error due to underflow is detected. the appropriate transmit descriptor 0 (tdes0) bit is set. if the second condition occurs, both the abnormal interrupt summary (in eth_dmasr register [15]) and transmit underflow bits (in eth_dmasr register[5]) are set, and the information is written to transmit descriptor 0, causing the suspension. if the dma goes into suspend state due to the first condition, then both the normal interrupt summary (eth_dmasr register [16]) and transmit buffer unavailable (eth_dmasr register[2]) bits are set. in both cases, the position in the transmit list is retained. the retained position is that of the descriptor following the last descriptor closed by the dma. the driver must explicitly issue a transmit poll demand command after rectifying the suspension cause. normal tx dma descriptors the normal transmit descriptor structure consists of four 32-bit words as shown in figure 341 . the bit descriptions of tdes0, tdes1, tdes2 and tdes3 are given below. note that enhanced descriptors must be used if time stamping is activated (eth_ptptscr bit 0, tse=1) or if ipv4 checksum offload is activated (eth_maccr bit 10, ipco=1). figure 341. normal transmit descriptor tde s 3 o w n ctrl [ 3 0:26] re s . 24 ctrl [2 3 :20] re s erved [19:1 8 ] s t a t us [16:0] re s erved [ 3 1:29] b u ffer 2 b yte co u nt [2 8 :16] re s erved [15:1 3 ] b u ffer 1 b yte co u nt [12:0] b u ffer 1 a ddre ss [ 3 1:0] / time s t a mp low [ 3 1:0] b u ffer 2 a ddre ss [ 3 1:0] or next de s criptor a ddre ss [ 3 1:0] / time s t a mp high [ 3 1:0] tde s 0 tde s 1 tde s 2 3 1 0 a i15642 b t t s e t t s s RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 853/1317 tdes0: transmit descriptor word0 the application software has to program the control bits [30:26]+[23:20] plus the own bit [31] during descriptor initialization. when the dma updates the descriptor (or writes it back), it resets all the control bits plus the own bit, and reports only the status bits. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 o w n ic ls fs dc dp tt se res cic te r tc h res. tt ss ih e es jt ff ip e lc a nc lc o ec vf cc ed uf db rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bit 31 own: own bit when set, this bit indicates that the descriptor is owned by the dma. when this bit is reset, it indicates that the descriptor is owned by the cp u. the dma clears this bit either when it completes the frame transmission or when the bu ffers allocated in the descriptor are read completely. the ownership bit of the frame?s fi rst descriptor must be se t after all subsequent descriptors belonging to the same frame have been set. bit 30 ic: interrupt on completion when set, this bit sets the tr ansmit interrupt (register 5[0]) after the present frame has been transmitted. bit 29 ls: last segment when set, this bit indicates that the buff er contains the last segment of the frame. bit 28 fs: first segment when set, this bit indicates that the buff er contains the first segment of a frame. bit 27 dc: disable crc when this bit is set, the mac does not appe nd a cyclic redundancy check (crc) to the end of the transmitted frame. this is valid only when the first segment (tdes0[28]) is set. bit 26 dp: disable pad when set, the mac does not automatically a dd padding to a frame shorter than 64 bytes. when this bit is reset, the dma automatically adds padding and crc to a frame shorter than 64 bytes, and the crc field is added despite the state of the dc (tdes0[27]) bit. this is valid only when the first segm ent (tdes0[28]) is set. bit 25 ttse: transmit time stamp enable when ttse is set and when tse is set (eth_ptptscr bit 0), ieee1588 hardware time stamping is activated for the transmit frame descri bed by the descriptor. this field is only valid when the first segment control bit (tdes0[28]) is set. bit 24 reserved bits 23:22 cic: checksum insertion control these bits control the checksum calculation and insertion. bit encoding is as shown below: 00: checksum insertion disabled 01: only ip header checksum calculation and insertion are enabled 10: ip header checksum and payload checksum calculation and insertion are enabled, but pseudo-header checksum is not calculated in hardware 11: ip header checksum and payload checksum calculation and insertion are enabled, and pseudo-header checksum is calculated in hardware. bit 21 ter: transmit end of ring when set, this bit indicates that the descriptor list reached its final descriptor. the dma returns to the base address of the list, creating a descriptor ring. ethernet (eth): media access control (mac) with dma controller RM0033 854/1317 doc id 15403 rev 3 bit 20 tch: second address chained when set, this bit indicates that the second address in the descriptor is the next descriptor address rather than the second buffer address. when tdes0[20] is set, tbs2 (tdes1[28:16]) is a ?don?t care? value. tdes0[21] takes precedence over tdes0[20]. bits 19:18 reserved bit 17 ttss: transmit time stamp status this field is used as a status bit to indicate that a time stamp was captured for the described transmit frame. when this bit is set, tdes2 and tdes3 have a time stamp value captured for the transmit frame. this field is only valid when the descriptor?s last segment control bit (tdes0[29]) is set. note that when enhanced descriptors are enabled (edfe=1 in eth_dmabmr), ttss=1 indicates that tdes6 and tdes7 have the time stamp value. bit 16 ihe: ip header error when set, this bit indicates that the mac transmitter detected an error in the ip datagram header. the transmitter checks the header length in the ipv4 packet against the number of header bytes received from the application and in dicates an error status if there is a mismatch. for ipv6 frames, a header error is reported if the main header length is not 40 bytes. furthermore, the ethernet length/type field value for an ipv4 or ipv6 frame must match the ip header version received with the packet. for ipv4 frames, an error status is also indicated if the header length field has a value less than 0x5. bit 15 es: error summary indicates the logical or of the following bits: ? tdes0[14]: jabber timeout ? tdes0[13]: frame flush ? tdes0[11]: loss of carrier ? tdes0[10]: no carrier ? tdes0[9]: late collision ? tdes0[8]: excessive collision ? tdes0[2]:excessive deferral ? tdes0[1]: un derflow error ? tdes0[16]: ip header error ? tdes0[12]: ip payload error bit 14 jt: jabber timeout when set, this bit indicates the mac transmitter has experienced a jabber timeout. this bit is only set when the mac configuratio n register?s jd bit is not set. bit 13 ff: frame flushed when set, this bit indicates that the dma/mt l flushed the frame due to a software flush command given by the cpu. bit 12 ipe: ip payload error when set, this bit indicates that mac transmitter detected an error in the tcp, udp, or icmp ip datagram payload. the transmitter checks the payload length received in the ipv4 or ipv6 header against the actual number of tcp, udp or icmp packet bytes received from the application and issues an error status in case of a mismatch. bit 11 lca: loss of carrier when set, this bit indicates th at a loss of carrier occurred during frame transmission (that is, the mii_crs signal was inactive for one or more transmit clock periods during frame transmission). this is valid only for the frames transmitted without collision when the mac operates in half-duplex mode. RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 855/1317 tdes1: transmit descriptor word1 bit 10 nc: no carrier when set, this bit indicates that the carrier sense signal form the phy was not asserted during transmission. bit 9 lco: late collision when set, this bit indicates that frame transmission was aborted due to a collision occurring after the collision window (64 byte times, including preamble, in mii mode). this bit is not valid if the underflow error bit is set. bit 8 ec: excessive collision when set, this bit indicates that the transmission was aborted after 16 successive collisions while attempting to transmit the current frame. if the rd (disable retry) bit in the mac configuration register is set, this bit is set af ter the first collision, and the transmission of the frame is aborted. bit 7 vf: vlan frame when set, this bit indicates that the transmitted frame was a vlan-type frame. bits 6:3 cc: collision count this 4-bit counter value indicates the number of collisions occurring before the frame was transmitted. the count is not valid when the excessive collisions bit (tdes0[8]) is set. bit 2 ed: excessive deferral when set, this bit indicates that the transmission has ended because of excessive deferral of over 24 288 bit times if the deferral check (dc) bit in the mac control register is set high. bit 1 uf: underflow error when set, this bit indicates that the mac abor ted the frame because data arrived late from the ram memory. underflow error indicates that the dma encountered an empty transmit buffer while transmitting the frame. the transmission process enters the suspended state and sets both transmit underflow (register 5[5]) and transmit interrupt (register 5[0]). bit 0 db: deferred bit when set, this bit indicates that the mac defers before transmission because of the presence of the carrier. this bit is valid only in half-duplex mode. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved tbs2 reserved tbs1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 31:29 reserved 28:16 tbs2: transmit buffer 2 size these bits indicate the second data buffer size in bytes. this field is not valid if tdes0[20] is set. 15:13 reserved 12:0 tbs1: transmit buffer 1 size these bits indicate the first data bu ffer byte size, in bytes. if this field is 0, the dma ignores this buffer and uses buffer 2 or the next descrip tor, depending on the value of tch (tdes0[20]). ethernet (eth): media access control (mac) with dma controller RM0033 856/1317 doc id 15403 rev 3 tdes2: transmit descriptor word2 tdes2 contains the address pointer to the first buffer of the descriptor or it contains time stamp data. tdes3: transmit descriptor word3 tdes3 contains the address pointer either to the second buffer of the descriptor or the next descriptor, or it contains time stamp data. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tbap1/tbap/ttsl rw bits 31:0 tbap1: transmit buffer 1 address pointer / transmit frame time stamp low these bits have two different functions: they indicate to the dma the location of data in memory, and after all data are transferred, the dma can then use these bits to pass back time stamp data. tbap: when the software makes this descriptor avai lable to the dma (at the moment that the own bit is set to 1 in tdes0), these bits indicate the physical address of buffer 1. there is no limitation on the buffer address alignment. see host data buffer alignment on page 846 for further details on buffer address alignment. ttsl: before it clears the own bit in tdes0, the dma updates this field with the 32 least significant bits of the time st amp captured for the corresponding transmit frame (overwriting the value for tbap1). this field has th e time stamp only if time stamping is acti vated for this frame (see ttse, tdes0 bit 25) and if the last segm ent control bit (ls) in the descriptor is set. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tbap2/tbap2/ttsh rw bits 31:0 tbap2: transmit buffer 2 address pointer (next descriptor address) / transmit frame time stamp high these bits have two different functions: they indicate to the dma the location of data in memory, and after all data are transferred, the dma can then use these bits to pass back time stamp data. tbap2: when the software makes this descriptor available to the dma (at the moment when the own bit is set to 1 in tdes0), these bits indicate the physical address of buffer 2 when a descriptor ring structure is used. if the second address chained (tdes1 [24]) bit is set, this address contains the pointer to the physical memory where the next descriptor is present. the buffer address pointer must be aligned to the bus width only when tdes1 [24] is set. (lsbs are ignored internally.) ttsh: before it clears the own bit in tdes0, the dma updates this field with the 32 most significant bits of the time stamp captured fo r the corresponding transmit frame (overwriting the value for tbap2). this field has the time stamp on ly if time stamping is activated for this frame (see tdes0 bit 25, ttse) and if the last segment control bit (ls) in the descriptor is set. RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 857/1317 enhanced tx dma descriptors enhanced descriptors (enabled with edfe=1, ethdmabmr bit 7), must be used if time stamping is activated (tse=1, eth_ptptscr bit 0) or if ipv4 checksum offload is activated (ipco=1, eth_maccr bit 10). enhanced descriptors comprise eight 32-bit words, twice the size of normal descriptors. tdes0, tdes1, tdes2 and tdes3 have the same definitions as for normal transmit descriptors (refer to normal tx dma descriptors ). tdes6 and tdes7 hold the time stamp. tdes4, tdes5, tdes6 and tdes7 are defined below. when the enhanced descriptor mode is selected, the software needs to allocate 32-bytes (8 dwords) of memory for every descriptor. when time stamping or ipv4 checksum offload are not being used, the enhanced descriptor format may be disabled and the software can use normal descriptors with the default size of 16 bytes. figure 342. enhanced transmit descriptor tdes4: transmit descriptor word4 reserved tdes5: transmit descriptor word5 reserved tdes6: transmit descriptor word6 4 $ % 3 / 7 . # t r l ; = 2 e s # t r l ; = 2 e s e r v e d ; = 3 t a t u s ; = 2 e s e r v e d ; = " u f f e r b y t e c o u n t ; = 2 e s e r v e d ; = " u f f e r b y t e c o u n t ; = " u f f e r a d d r e s s ; = " u f f e r a d d r e s s ; = o r . e x t d e s c r i p t o r a d d r e s s ; = 4 $ % 3 4 $ % 3 4 $ % 3 a i b 4 4 3 % 4 4 3 3 4 $ % 3 4 $ % 3 4 $ % 3 4 $ % 3 2 e s e r v e d 2 e s e r v e d 4 i m e s t a m p l o w ; = 4 i m e s t a m p h i g h ; = 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ttsl rw bits 31:0 ttsl: transmit frame time stamp low this field is updated by dma with the 32 least significant bits of the time stamp captured for the corresponding transmit frame. this field has the time stamp only if the last segment control bit (ls) in the descriptor is set. ethernet (eth): media access control (mac) with dma controller RM0033 858/1317 doc id 15403 rev 3 tdes7: transmit descriptor word7 28.6.8 rx dma configuration the receive dma engine?s recept ion sequence is illustrated in figure 343 and described below: 1. the cpu sets up receive descriptors (rdes0-rdes3) and sets the own bit (rdes0[31]). 2. once the sr (eth_dmaomr register[1]) bit is set, the dma enters the run state. while in the run state, the dma polls the receive descriptor list, attempting to acquire free descriptors. if the fetched descriptor is not free (is owned by the cpu), the dma enters the suspend state and jumps to step 9. 3. the dma decodes the receive data buffer address from the acquired descriptors. 4. incoming frames are processed and placed in the acquired descriptor?s data buffers. 5. when the buffer is full or the frame transfer is complete, the receive engine fetches the next descriptor. 6. if the current frame transfer is complete, the dma proceeds to step 7. if the dma does not own the next fetched descriptor and the frame transfer is not complete (eof is not yet transferred), the dma sets the descriptor error bit in rdes0 (unless flushing is disabled). the dma closes the current descriptor (clears the own bit) and marks it as intermediate by clearing the last segment (ls) bit in the rdes1 value (marks it as last descriptor if flushing is not disabled), then proceeds to step 8. if the dma owns the next descriptor but the current frame transfer is not complete, the dma closes the current descriptor as intermediate and returns to step 4. 7. if ieee 1588 time stamping is enabled, the dma writes the time stamp (if available) to the current descriptor?s rdes2 and rdes3. it then takes the received frame?s status and writes the status word to the current descriptor?s rdes0, with the own bit cleared and the last segment bit set. 8. the receive engine checks the latest descriptor?s own bit. if the cpu owns the descriptor (own bit is at 0) the receive buffer unavailable bit (in eth_dmasr register[7]) is set and the dma receive engine enters the suspended state (step 9). if the dma owns the descriptor, the engine returns to step 4 and awaits the next frame. 9. before the receive engine enters the suspend state, partial frames are flushed from the receive fifo (you can control flushing using bit 24 in the eth_dmaomr register). 10. the receive dma exits the suspend state when a receive poll demand is given or the start of next frame is available from the receive fifo. the engine proceeds to step 2 and re-fetches the next descriptor. the dma does not acknowledge accepting the status until it has completed the time stamp write-back and is ready to perform status write-back to the descriptor. if software has enabled time stamping through csr, when a valid time stamp value is not available for the 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ttsh rw bits 31:0 ttsh: transmit frame time stamp high this field is updated by dma with the 32 most si gnificant bits of the time stamp captured for the corresponding transmit frame. this field has the time stamp only if the last segment control bit (ls) in the descriptor is set. RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 859/1317 frame (for example, because the receive fifo was full before the time stamp could be written to it), the dma writes all ones to rdes2 and rdes3. otherwise (that is, if time stamping is not enabled), rdes2 and rdes3 remain unchanged. figure 343. receive dma operation (re-)fetch next descriptor (ahb) error? no own bit set? yes yes stop rxdma start rxdma start (ahb) error? no rxdma suspended yes frame data available ? wait for frame data write data to buffer(s) yes yes fetch next descriptor yes no frame transfer complete? no set descriptor error yes time stamp present? no close rdes0 as last descriptor write time stamp to rdes2 & rdes3 no (ahb) error? yes close rdes0 as intermediate descriptor frame transfer complete? no flush disabled? no flush the remaining frame yes yes no no no yes yes poll demand/ new frame available no yes (ahb) error? (ahb) error? no own bit set for next desc? flush disabled? ai15643 ethernet (eth): media access control (mac) with dma controller RM0033 860/1317 doc id 15403 rev 3 receive descriptor acquisition the receive engine always attempts to acquire an extra descriptor in anticipation of an incoming frame. descriptor acquisition is attemp ted if any of the following conditions is/are satisfied: the receive start/stop bit (eth_dmaomr register[1]) has been set immediately after the dma has been placed in the run state. the data buffer of the current descriptor is full before the end of the frame currently being transferred the controller has completed frame reception, but the current receive descriptor has not yet been closed. the receive process has been suspended because of a cpu-owned buffer (rdes0[31] = 0) and a new frame is received. a receive poll demand has been issued. receive frame processing the mac transfers the received frames to the stm32f20x and stm32f21x memory only when the frame passes the address filter and the frame size is greater than or equal to the configurable threshold bytes set for the receive fifo, or when the complete frame is written to the fifo in store-and-forward mode. if the frame fails the address filtering, it is dropped in the mac block itself (unless receive all eth_macffr [31] bit is set). frames that are shorter than 64 bytes, becaus e of collision or premature term ination, can be purged from the receive fifo. after 64 (configurable threshold) bytes have been received, the dma block begins transferring the frame data to the receive buffer pointed to by the current descriptor. the dma sets the first descriptor (rdes0[9]) after the dma ahb interface becomes ready to receive a data transfer (if dma is not fetching transmit data from the memory), to delimit the frame. the descriptors are released when the own (rdes0[31]) bit is reset to 0, either as the data buffer fills up or as the last segment of the frame is transferred to the receive buffer. if the frame is contained in a single descriptor, both the last descriptor (rdes0[8]) and first descriptor (rdes0[9]) bits are set. the dma fetches the next descriptor, sets the last descriptor (rdes0[8]) bit, and releases the rdes0 status bits in the previous frame descriptor. then the dma sets the receive interrupt bit (eth_dmasr register [6]). the same process repeats unless the dma encounters a descriptor flagged as being owned by the cpu. if this occurs, the receive process sets the receive buffer unavailable bit (eth_dmasr register[7]) and then enters the suspend state. the position in the receive lis t is retained. receive process suspended if a new receive frame arrives while the receive process is in suspend state, the dma re- fetches the current descriptor in the stm32f20x and stm32f21x memory. if the descriptor is now owned by the dma, the receive process re-enters the run state and starts frame reception. if the descriptor is still owned by the host, by default, the dma discards the current frame at the top of the rx fifo and increments the missed frame counter. if more than one frame is stored in the rx fifo, the process repeats. the discarding or flushing of the frame at the top of the rx fifo can be avoided by setting the dma operation mode register bit 24 (dfrf). in such conditions, the receive process sets the receive buffer unavailable status bit and returns to the suspend state. RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 861/1317 normal rx dma descriptors the normal receive descriptor structure consists of four 32-bit words (16 bytes). these are shown in figure 344 . the bit descriptions of rdes0, rdes1, rdes2 and rdes3 are given below. note that enhanced descriptors must be used if time stamping is activated (tse=1, eth_ptptscr bit 0) or if ipv4 checksum offload is activated (ipco=1, eth_maccr bit 10). figure 344. normal rx dma descriptor structure rdes0: receive descriptor word0 rdes0 contains the received frame status, the frame length and the descriptor ownership information. rdes 3 o w n status [30:0] reserved [30:29] buffer 2 byte count [28:16] ctrl [15:14] buffer 1 byte count [12:0] buffer 1 address [31:0] buffer 2 address [31:0] or next descriptor address [31:0] rdes 0 rdes 1 rdes 2 31 0 ai15644 res. ct rl 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 own afm fl es de saf le oe vlan fs ls iphce/tsv lco ft rwt re de ce pce/esa rw bit 31 own: own bit when set, this bit indicates th at the descriptor is owned by the dma of the mac subsystem. when this bit is reset, it indicates that the descr iptor is owned by the host. the dma clears this bit either when it completes the frame reception or when the buffers that are associated with this descriptor are full. bit 30 afm: destination address filter fail when set, this bit indicates a frame that failed the da filter in the mac core. bits 29:16 fl: frame length these bits indicate the byte length of the rece ived frame that was transferred to host memory (including crc). this field is valid only when last descriptor (rdes0[8]) is set and descriptor error (rdes0[14]) is reset. this field is valid when last descriptor (rdes0 [8]) is set. when the last descriptor and error summary bits are not set, this field indicates the accumulated number of bytes that have been transferred for the current frame. ethernet (eth): media access control (mac) with dma controller RM0033 862/1317 doc id 15403 rev 3 bit 15 es: error summary indicates the logical or of the following bits: ? rdes0[1]: crc error ? rdes0[3]: receive error ? rdes0[4]: watchdog timeout ? rdes0[6]: late collision ? rdes0[7]: giant frame (this is not applicable when rdes0[7] indicates an ipv4 header checksum error.) ? rdes0[11]: overflow error ? rdes0[14]: descriptor error. this field is valid only when the last descriptor (rdes0[8]) is set. bit 14 de: descriptor error when set, this bit indicates a frame truncation caus ed by a frame that does not fit within the current descriptor buffers, and that the dma does not own t he next descriptor. the fr ame is truncated. this field is valid only when the last descriptor (rdes0[8]) is set. bit 13 saf: source address filter fail when set, this bit indicates that the sa field of frame failed the sa filter in the mac core. bit 12 le: length error when set, this bit indicates that the actual length of the received frame does not match the value in the length/ type field. this bit is valid only when the frame type (rdes0[5]) bit is reset. bit 1 1 oe: overflow error when set, this bit indicates that the received frame was damaged due to buffer overflow. bit 10 vlan: vlan tag when set, this bit indicates that the frame pointed to by this descriptor is a vlan frame tagged by the mac core. bit 9 fs: first descriptor when set, this bit indicates th at this descriptor contains the first bu ffer of the frame. if the size of the first buffer is 0, the second buffer contains the beginning of the frame. if the size of the second buffer is also 0, the next descriptor contains the beginning of the frame. bit 8 ls: last descriptor when set, this bit indicates that the buffers pointed to by this descriptor are the last buffers of the frame. bit 7 iphce/tsv: ipv header checksum error / time stamp valid if iphce is set, it indicates an error in the ipv4 or ipv6 header. this error ca n be due to inconsistent ethernet type field and ip header version field va lues, a header checksum mismatch in ipv4, or an ethernet frame lacking the expected number of ip header bytes. this bit can take on special meaning as specified in ta bl e 1 4 5 . if enhanced descriptor format is enabled (edfe=1, bit 7 of eth_dmabmr), this bit takes on the tsv function (otherwise it is iphce). when ts v is set, it indicates that a snapshot of the timestamp is written in descriptor words 6 (rd es6) and 7 (rdes7). tsv is valid only when the last descriptor bit (rdes0[8]) is set. bit 6 lco: late collision when set, this bit indicates that a late collision has occurred while receiving the frame in half- duplex mode. RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 863/1317 bits 5, 7, and 0 reflect the conditions discussed in ta bl e 1 4 5 . bit 5 ft: frame type when set, this bit indicates that the receive frame is an ethernet-type frame (the lt field is greater than or equal to 0x0600). when this bit is reset, it indicates that the received frame is an ieee802.3 frame. this bit is not valid for runt frames less than 14 bytes. when the normal descriptor format is used (eth_dmabmr edfe=0), ft can take on special meaning as specified in table 145 . bit 4 rwt: receive watchdog timeout when set, this bit indica tes that the receive watchdog timer has expired while receiving the current frame and the current frame is truncated after the watchdog timeout. bit 3 re: receive error when set, this bit indicates that the rx_err signal is asserted while rx_dv is asserted during frame reception. bit 2 de: dribble bit error when set, this bit indicates that the received frame has a non-integer multiple of bytes (odd nibbles). this bit is valid only in mii mode. bit 1 ce: crc error when set, this bit indicates that a cyclic redundancy check (crc) error occurred on the received frame. this field is valid only when the last descriptor (rdes0[8]) is set. bit 0 pce/esa : payload checksum error / extended status available when set, it indicates that the tcp, udp or icmp checksum the core calculated does not match the received encapsulated tcp, udp or icmp segment?s checksum field. this bit is also set when the received number of payload byte s does not match the value indicated in the length field of the encapsulated ip v4 or ipv6 datagram in the received ethernet frame. this bit can take on special meaning as specified in ta bl e 1 4 5 . if the enhanced descriptor format is enabled (e dfe=1, bit 7 in eth_dmabmr), this bit takes on the esa function (otherwise it is pce). wh en esa is set, it indicate s that the extended status is available in descriptor word 4 (rdes4). esa is valid only when the last descriptor bit (rdes0[8]) is set. table 145. receive descriptor 0 - encoding for bits 7, 5 and 0 (normal descriptor format only, edfe=0) bit 5: frame type bit 7: ipc checksum error bit 0: payload checksum error frame status 00 0 ieee 802.3 type frame (length field value is less than 0x0600.) 1 0 0 ipv4/ipv6 type frame, no checksum error detected 10 1 ipv4/ipv6 type frame with a payload checksum error (as described for pce) detected 11 0 ipv4/ipv6 type frame with an ip header checksum error (as described for ipc ce) detected 11 1 ipv4/ipv6 type frame with both ip header and payload checksum errors detected 00 1 ipv4/ipv6 type frame with no ip header checksum error and the payload check bypassed, due to an unsupported payload ethernet (eth): media access control (mac) with dma controller RM0033 864/1317 doc id 15403 rev 3 01 1 a type frame that is neither ipv4 or ipv6 (the checksum offload engine bypasses checksum completely.) 01 0reserved table 145. receive descriptor 0 - encoding for bits 7, 5 and 0 (normal descriptor format only, edfe=0) (continued) bit 5: frame type bit 7: ipc checksum error bit 0: payload checksum error frame status RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 865/1317 rdes1: receive descriptor word1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dic rbs2 rbs2 rer rch reserved rbs rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bit 31 dic: disable interrup t on completion when set, this bit prevents setting the status register?s rs bit (csr5[6]) for the received frame ending in the buffer indicated by this descriptor. this, in turn, disables the assertion of the interrupt to host due to rs for that frame. bits 30:29 reserved bits 28:16 rbs2: receive buffer 2 size these bits indicate the second data buffer size, in by tes. the buffer size must be a multiple of 4, 8, or 16, depending on the bus widths (32, 64 or 128, respectively), even if the value of rdes3 (buffer2 address pointer) is not ali gned to bus width. if the buffer size is not an appropriate multiple of 4, 8 or 16, the resulting behavior is undefined. this field is not valid if rdes1 [14] is set. bit 15 rer: receive end of ring when set, this bit indicates that the descriptor list reached its final descriptor. the dma returns to the base address of the list, cr eating a descriptor ring. bit 14 rch: second address chained when set, this bit indicates that the second address in the descriptor is the next descriptor address rather than the second buffer address. when this bit is set, rbs2 (rdes1[28:16]) is a ?don?t care? value. rdes1[15] takes precedence over rdes1[14]. bit 13 reserved bits 12:0 rbs1: receive buffer 1 size indicates the first data buffer size in bytes. the buffer size must be a multiple of 4, 8 or 16, depending upon the bus widths (32, 64 or 128), even if the value of rdes2 (buffer1 address pointer) is not aligned. when the buffer size is not a multiple of 4, 8 or 16, the resulting behavior is undefined. if this field is 0, the dma ignores this buffer and uses buffer 2 or next descriptor depending on the value of rch (bit 14). ethernet (eth): media access control (mac) with dma controller RM0033 866/1317 doc id 15403 rev 3 rdes2: receive descriptor word2 rdes2 contains the address pointer to the first data buffer in the descriptor, or it contains time stamp data. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rbp1 / rtsl rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:0 rbap1 / rtsl: receive buffer 1 address pointer / receive frame time stamp low these bits take on two different functions: the application uses them to indicate to the dma where to store the data in memory, and then af ter transferring all the data the dma may use these bits to pass back time stamp data. rbap1: when the software makes this descriptor available to th e dma (at the mo ment that the own bit is set to 1 in rdes0), these bits indicate the physical address of buffer 1. there are no limitations on the buffer address alignment except for the following condition: the dma uses the configured value for its address generation when the rdes2 value is used to store the start of frame. note that the dma performs a write operation with the rdes2[3/2/1:0] bits as 0 during the transfer of the start of frame but the frame data is sh ifted as per the actual buffer address pointer. the dma ignores rdes2[3/2/1:0] (corresponding to bus width of 128/64/32) if the address pointer is to a buffer where the middle or last part of the frame is stored. rtsl: before it clears the own bit in rdes0, the dma updates this field with the 32 least significant bits of the time stamp captured for the corresponding receive frame (overwriting the value for rbap1). this field has the time stamp only if time stamping is activated for this frame and if the last segment control bit (ls) in the descriptor is set. RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 867/1317 rdes3: receive descriptor word3 rdes3 contains the address pointer either to the second data buffer in the descriptor or to the next descriptor, or it contains time stamp data. enhanced rx dma descriptors format with ieee1588 time stamp enhanced descriptors (enabled with edfe=1, ethdmabmr bit 7), must be used if time stamping is activated (tse=1, eth_ptptscr bit 0) or if ipv4 checksum offload is activated (ipco=1, eth_maccr bit 10). enhanced descriptors comprise eight 32-bit words, twice the size of normal descriptors. rdes0, rdes1, rdes2 and rdes3 have the same definitions as for normal receive descriptors (refer to normal rx dma descriptors ). rdes4 contains extended status while rdes6 and rdes7 hold the time stamp. rdes4, rdes5, rdes6 and rdes7 are defined below. when the enhanced descriptor mode is selected, the software needs to allocate 32 bytes (8 dwords) of memory for every descriptor. when time stamping or ipv4 checksum offload are not being used, the enhanced descriptor format may be disabled and the software can use normal descriptors with the default size of 16 bytes. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rbp2 / rtsh rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:0 rbap2 / rtsh: receive buffer 2 address pointer (next descriptor address) / receive frame time stamp high these bits take on two different functions: the application uses them to indicate to the dma the location of where to store the data in memory, and then after transferring all the data the dma may use these bits to pass back time stamp data. rbap1: when the software makes this descriptor available to the dma (at the moment that the own bit is set to 1 in rdes0), these bits indicate the physical address of buffer 2 when a descriptor ring structure is used. if the second addr ess chained (rdes1 [24]) bit is set, this address contains the pointer to the physical memory where the next descriptor is present. if rdes1 [24] is set, the buffer (next descriptor) address pointer mu st be bus width-aligned (rdes3[3, 2, or 1:0] = 0, corresponding to a bus width of 128, 64 or 32. lsbs are ignored internally.) however, when rdes1 [24] is reset, there are no limitations on th e rdes3 value, except for the following condition: the dma uses the configured value for its buffer address generation when the rdes3 value is used to store the start of frame. the dma ignores rdes3[3, 2, or 1:0] (corresponding to a bus width of 128, 64 or 32) if the address pointer is to a buffer wher e the middle or last part of the frame is stored. rtsh: before it clears the own bit in rdes0, the dma updates this field with the 32 most significant bits of the time stamp captured for the corresponding receive frame (overwriting the value for rbap2). this field has the time stamp only if time stamping is ac tivated and if the last segment control bit (ls) in the descriptor is set. ethernet (eth): media access control (mac) with dma controller RM0033 868/1317 doc id 15403 rev 3 figure 345. enhanced receive descriptor field format with ieee1588 time stamp enabled rdes4: receive descriptor word4 the extended status, shown below, is valid only when there is status related to ipv4 checksum or time stamp available as indicated by bit 0 in rdes0. rde s 3 o w n s t a t us [ 3 0:0] re s erved [ 3 0:29] b u ffer 2 b yte co u nt [2 8 :16] ctrl [15:14] b u ffer 1 b yte co u nt [12:0] b u ffer 1 a ddre ss [ 3 1:0] b u ffer 2 a ddre ss [ 3 1:0] or next de s criptor a ddre ss [ 3 1:0] rde s 0 rde s 1 rde s 2 3 1 0 a i17104 re s . ct rl rde s 7 rde s 4 rde s 5 rde s 6 extended s t a t us [ 3 1:0] re s erved time s t a mp low [ 3 1:0] time s t a mp high [ 3 1:0] 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved pv pft pmt ipv6pr ipv4pr ipcb ippe iphe ippt rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:14 reserved bit 13 pv: ptp version when set, indicates t hat the received ptp message uses the ieee 1588 version 2 format. when cleared, it uses version 1 format. this is valid only if the message type is non-zero. bit 12 pft: ptp frame type when set, this bit indicates that the ptp message is sent directly over ethernet. when this bit is cleared and the message type is non-zero, it indi cates that the ptp message is sent over udp- ipv4 or udp-ipv6. the information on ipv4 or ipv6 can be obtained from bits 6 and 7. RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 869/1317 rdes5: receive descriptor word5 reserved. rdes6: receive descriptor word6 the table below describes the fields that have different meaning for rdes6 when the receive descriptor is closed and time stamping is enabled. bits 11:8 pmt: ptp message type these bits are encoded to give the type of the message received. ? 0000: no ptp message received ? 0001: sync (all clock types) ? 0010: follow_up (all clock types) ? 0011: delay_req (all clock types) ? 0100: delay_resp (all clock types) ? 0101: pdelay_req (in peer-to-peer transparent clock) or announce (in ordinary or boundary clock) ? 0110: pdelay_resp (in peer-to-peer transpar ent clock) or management (in ordinary or boundary clock) ? 0111: pdelay_resp_follow_up (in peer-to-peer tr ansparent clock) or signaling (for ordinary or boundary clock) ? 1xxx - reserved bit 7 ipv6pr: ipv6 packet received when set, this bit indicates that the received packet is an ipv6 packet. bit 6 ipv4pr: ipv4 packet received when set, this bit indicates that the received packet is an ipv4 packet. bit 5 ipcb: ip checksum bypassed when set, this bit indicates that the checksum offload engine is bypassed. bit 4 ippe: ip payload error when set, this bit indicates that the 16-bit ip payload checksum (that is, the tcp, udp, or icmp checksum) that the core calculated does not match the corresponding checksum field in the received segment. it is also set when the tcp, udp, or icmp segment length does not match the payload length value in the ip header field. bit 3 iphe: ip header error when set, this bit indicates either that the 16 -bit ipv4 header checksum calculated by the core does not match the received checksum bytes, or that the ip datagram ve rsion is not consistent with the ethernet type value. bits 2:0 ippt: ip payload type if ipv4 checksum offload is activated (ipco=1, eth_maccr bit 10), these bits indicate the type of payload encapsulated in the ip datagram. these bits are ?00? if there is an ip header error or fragmented ip. ? 000: unknown or did not process ip payload ? 001: udp ? 010: tcp ? 011: icmp ? 1xx: reserved ethernet (eth): media access control (mac) with dma controller RM0033 870/1317 doc id 15403 rev 3 . rdes7: receive descriptor word7 the table below describes the fields that have a different meaning for rdes7 when the receive descriptor is closed and time stamping is enabled. . 28.6.9 dma interrupts interrupts can be generated as a result of various events. the eth_dmasr register contains all the bits that might cause an interrupt. the eth_dmaier register contains an enable bit for each of the events that can cause an interrupt. there are two groups of interrupts, normal and abnormal, as described in the eth_dmasr register. interrupts are cleared by writing a 1 to the corresponding bit position. when all the enabled interrupts within a group are cleared, the corresponding summary bit is cleared. if the mac core is the cause for assertion of the interrupt, then any of the tsts or pmts bits in the eth_dmasr register is set high. interrupts are not queued and if the interrupt event occurs before the driver has responded to it, no additional interrupts are generated. for example, the receive interrupt bit (eth_dmasr register [6]) indicates that one or more frames were transferred to the stm32f20x and stm32f21x buffer. the driver must scan all descriptors, from the last recorded position to the first one owned by the dma. an interrupt is generated only once for simultaneous, multiple events. the driver must scan the eth_dmasr register for the cause of the interrupt. the interrupt is not generated again unless a new interrupting event occurs, after the driver has cleared the appropriate bit in the eth_dmasr register. for example, the controller generates a receive interrupt (eth_dmasr register[6]) and the driver begins reading the eth_dmasr register. next, receive buffer unavailable (eth_dmasr register[7]) occurs. the driver clears the receive interrupt. even then, a new interrupt is generated, due to the active or pending receive buffer unavailable interrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rtsl rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:0 rtsl: receive frame time stamp low the dma updates this field with the 32 least signifi cant bits of the time stamp captured for the corresponding receive frame. the dm a updates this field only for the last descriptor of the receive frame indicated by last descriptor status bit (rdes0 [8]). when this field and the rtsh field in rdes7 show all ones, the time stam p must be treated as corrupt. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rtsh rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:0 rtsh: receive frame time stamp high the dma updates this field with the 32 most signifi cant bits of the time stamp captured for the corresponding receive frame. the dma updates this fiel d only for the last descriptor of the receive frame indicated by last descripto r status bit (rdes0[8]). when this field and rdes7?s rtsl field show all ones, the time stamp must be treated as corrupt. RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 871/1317 figure 346. interrupt scheme 28.7 ethernet interrupts the ethernet controller has two interrupt vectors: one dedicated to normal ethernet operations and the other, used only for the ethernet wakeup event (with wakeup frame or magic packet detection) when it is mapped on exti line19. the first ethernet vector is reserved for interrupts generated by the mac and the dma as listed in the mac interrupts and dma interrupts sections. the second vector is reserved for interrupts generated by the pmt on wakeup events. the mapping of a wakeup event on exti line19 causes the stm32f20x and stm32f21x to exit the low power mode, and generates an interrupt. when an ethernet wakeup event mapped on exti line19 occurs and the mac pmt interrupt is enabled and the exti line19 interrupt, with detection on rising edge, is also enabled, both interrupts are generated. a watchdog timer (see eth_dmarswtr register) is given for flexible control of the rs bit (eth_dmasr register). when this watchdog timer is programmed with a non-zero value, it gets activated as soon as the rxdma completes a transfer of a received frame to system memory without asserting the receive status because it is not enabled in the corresponding receive descriptor (rdes1[31]). when this timer runs out as per the programmed value, the rs bit is set and the interrupt is asserted if the corresponding rie is enabled in the eth_dmaier register. this timer is disabled before it runs out, when a frame is transferred to memory and the rs is set because it is enabled for that descriptor. and and or or and nis nise and ais aise or interrupt ts tie fbes fbeie ai15646 pmti tsti mmci and tbus tbuie and rs rie and ers erie and tpss tpssie and tjts tjtie and ros roie and tus tuie and rbu rbuie and rpss rpssie and rwts rwtie and ets etie ethernet (eth): media access control (mac) with dma controller RM0033 872/1317 doc id 15403 rev 3 note: reading the pmt control and status register automatically clears the wakeup frame received and magic packet received pmt interrupt flags. however, since the registers for these flags are in the clk_rx domain, there may be a significant delay before this update is visible by the firmware. the delay is especially long when the rx clock is slow (in 10 mbit mode) and when the ahb bus is high-frequency. since interrupt requests from the pmt to the cpu are based on the same registers in the clk_rx domain, the cpu may spuriously call the interrupt routine a second time even after reading pmt_csr. thus, it may be necessary that the firmware polls the wakeup frame received and magic packet received bits and exits the interrupt service routine only when they are found to be at ?0?. 28.8 ethernet register descriptions the peripheral registers can be accessed by bytes (8-bit), half-words (16-bit) or words (32- bits). 28.8.1 mac register description ethernet mac configuration register (eth_maccr) address offset: 0x0000 reset value: 0x0000 8000 the mac configuration register is the operation mode register of the mac. it establishes receive and transmit operating modes. 313029282726252423222120191817161514131211109876543210 reserved cstf reserved wd jd reserved ifg csd reserved fes rod lm dm ipco rd reserved apcs bl dc te re reserved rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:246 reserved bits 25 cstf: crc stripping for type frames when set, the last 4 bytes (fcs) of all fram es of ether type (type field greater than 0x0600) will be stripped and dropped before forwarding the frame to the application. bits 24 reserved bit 23 wd: watchdog disable when this bit is set, the mac disables the watchdog timer on the receiver, and can receive frames of up to 16 384 bytes. when this bit is reset, the mac allows no more than 2 048 bytes of the frame being received and cuts off any bytes received after that. bit 22 jd: jabber disable when this bit is set, the mac disables the jabber timer on the transmitter, and can transfer frames of up to 16 384 bytes. when this bit is reset, the mac cuts off the tr ansmitter if the application sends out more than 2 048 bytes of data during transmission. bits 21:20 reserved RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 873/1317 bits 19:17 ifg: interframe gap these bits control the minimum interframe gap between frames during transmission. 000: 96 bit times 001: 88 bit times 010: 80 bit times ?. 111: 40 bit times note: in half-duplex mode, the minimum ifg ca n be configured for 64 bit times (ifg = 100) only. lower values are not considered. bit 16 csd: carrier sense disable when set high, this bit makes the mac transmit ter ignore the mii crs signal during frame transmission in half-duplex mode. no error is generated due to loss of carrier or no carrier during such transmission. when this bit is low, the mac transmitter generates such errors due to carrier sense and even aborts the transmissions. bit 15 reserved bit 14 fes: fast ethernet speed indicates the speed in fast ethernet (mii) mode: 0: 10 mbit/s 1: 100 mbit/s bit 13 rod: receive own disable when this bit is set, the mac disables th e reception of frames in half-duplex mode. when this bit is reset, the mac receives all packets that are given by the phy while transmitting. this bit is not applicable if the mac is operating in full-duplex mode. bit 12 lm: loopback mode when this bit is set, the mac operates in loopback mode at the mii. the mii receive clock input (rx_clk) is required for the loopback to work properly, as the transmit clock is not looped-back internally. bit 11 dm: duplex mode when this bit is set, the mac operates in a full-duplex mode where it can transmit and receive simultaneously. bit 10 ipco: ipv4 checksum offload when set, this bit enables ipv4 checksum checking for received frame payloads' tcp/udp/icmp headers. when this bit is reset, the checksum offload function in the receiver is disabled and the corresponding pce and ip hce status bits (see table 142 on page 827 ) are always cleared. bit 9 rd: retry disable when this bit is set, the mac attempts only 1 transmission. when a collision occurs on the mii, the mac ignores the current frame tr ansmission and reports a frame abort with excessive collision error in the transmit frame status. when this bit is reset, the mac attempts retries based on the settings of bl. note: this bit is applicable only in the half-duplex mode. bit 8 reserved ethernet (eth): media access control (mac) with dma controller RM0033 874/1317 doc id 15403 rev 3 bit 7 apcs: automatic pad/crc stripping when this bit is set, the mac strips the pad/fc s field on incoming frames only if the length?s field value is less than or equal to 1 500 bytes. all received frames with length field greater than or equal to 1 501 bytes are passed on to the application without stripping the pad/fcs field. when this bit is reset, the mac passes all incoming frames unmodified. bits 6:5 bl: back-off limit the back-off limit determines the random integer number (r) of slot time delays (4 096 bit times for 1000 mbit/s and 512 bit times for 10/100 mbit/s) the mac waits before rescheduling a transmission attempt during retries after a collision. note: this bit is applicable only to half-duplex mode. 00: k = min ( n , 10) 01: k = min ( n , 8) 10: k = min ( n , 4) 11: k = min ( n , 1), where n = retransmission attempt. the random integer r takes the value in the range 0 r < 2 k bit 4 dc: deferral check when this bit is set, the deferral check function is enabled in the mac. the mac issues a frame abort status, along with the excessive deferra l error bit set in the transmit frame status when the transmit state machine is deferred for mo re than 24 288 bit times in 10/100-mbit/s mode. deferral begins when the transmitter is ready to transmit, but is prevented because of an active crs (carrier sense) signal on the mii. defer time is not cumulative. if the transmitter defers for 10 000 bit times, then transmits, collides, backs off, and then has to defer again after completion of back-off, the deferral timer resets to 0 and restarts. when this bit is reset, the deferral check function is disabled and the mac defers until the crs signal goes inactive. this bit is applicable only in half-duplex mode. bit 3 te: transmitter enable when this bit is set, the transmit state machine of the mac is enabled for transmission on the mii. when this bit is reset, the mac transmit st ate machine is disabled after the completion of the transmission of the current frame, and does not transmit any further frames. bit 2 re: receiver enable when this bit is set, the receiver state mach ine of the mac is enabled for receiving frames from the mii. when this bit is reset, the ma c receive state machine is disabled after the completion of the reception of the current fram e, and will not receive any further frames from the mii. bits 1:0 reserved RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 875/1317 ethernet mac frame filter register (eth_macffr) address offset: 0x0004 reset value: 0x0000 0000 the mac frame filter register contains the filter controls for receiving frames. some of the controls from this register go to the address check block of the mac, which performs the first level of address filtering. the second level of filtering is performed on the incoming frame, based on other controls such as pass bad frames and pass control frames. 313029282726252423222120191817161514131211109876543210 ra reserved hpf saf saif pcf bfd pa m daif hm hu pm rw rw rw rw rw rw rw rw rw rw rw rw bit 31 ra: receive all when this bit is set, the mac receiver passes all received frames on to the application, irrespective of whether they have passed the addr ess filter. the result of the sa/da filtering is updated (pass or fail) in the corresponding bits in the receive status word. when this bit is reset, the mac receiver passes on to the application only those frames that have passed the sa/da address filter. bits 30:11 reserved bit 10 hpf: hash or perfect filter when this bit is set and if the hm or hu bit is set, the address filter passes frames that match either the perfect filter ing or the hash filtering. when this bit is cleared and if the hu or hm bit is set, only frames that match the hash filter are passed. bit 9 saf: source address filter the mac core compares the sa field of the rece ived frames with the values programmed in the enabled sa registers. if the comparison matches, then the samatch bit in the rxstatus word is set high. when this bit is set high and the sa filter fails, the mac drops the frame. when this bit is reset, the mac core forwards the received frame to the application. it also forwards the updated sa match bit in rx status depending on the sa address comparison. bit 8 saif: source address inverse filtering when this bit is set, the address check block operates in inverse filtering mode for the sa address comparison. the frames whose sa matc hes the sa registers are marked as failing the sa address filter. when this bit is reset, frames whose sa does not match the sa registers are marked as failing the sa address filter. ethernet (eth): media access control (mac) with dma controller RM0033 876/1317 doc id 15403 rev 3 ethernet mac hash table high register (eth_machthr) address offset: 0x0008 reset value: 0x0000 0000 the 64-bit hash table is used for group address filtering. for hash filtering, the contents of the destination address in the incoming frame are passed through the crc logic, and the upper 6 bits in the crc register are used to index the contents of the hash table. this crc bits 7:6 pcf: pass control frames these bits control the forwarding of all control frames (including unicast and multicast pause frames). note that the processing of pause co ntrol frames depends only on rfce in flow control register[2]. 00: mac prevents all control frames from reaching the application 01: mac forwards all control frames to application except pause control frames 10: mac forwards all control frames to ap plication even if they fail the address filter 11: mac forwards control frames that pass the address filter. these bits control the forwarding of all control frames (including unicast and multicast pause frames). note that the processing of pause co ntrol frames depends only on rfce in flow control register[2]. 00 or 01: mac prevents all control fram es from reaching the application 10: mac forwards all control frames to ap plication even if they fail the address filter 11: mac forwards control frames that pass the address filter. bit 5 bfd: broadcast frames disable when this bit is set, the address filter s filter all incoming broadcast frames. when this bit is reset, the address filters pass all received broadcast frames. bit 4 pam : pass all multicast when set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed. when reset, filtering of multic ast frame depends on the hm bit. bit 3 daif: destination address inverse filtering when this bit is set, the address check block operates in inverse filtering mode for the da address comparison for both uni cast and multicast frames. when reset, normal filtering of frames is performed. bit 2 hm: hash multicast when set, mac performs destination address filtering of received multicast frames according to the hash table. when reset, the mac performs a perfect destination address filtering for multicast frames, that is, it compares the da field with the values programmed in da registers. bit 1 hu: hash unicast when set, mac performs destination address filter ing of unicast frames according to the hash table. when reset, the mac performs a perfect destinati on address filtering for unicast frames, that is, it compares the da field with the values programmed in da registers. bit 0 pm: promiscuous mode when this bit is set, the address filters pass all incoming frames regardless of their destination or source address. the sa/da filter fails stat us bits in the receive status word are always cleared when pm is set. RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 877/1317 is a 32-bit value coded by the following polynomial (for more details refer to section 28.5.3: mac frame reception ): the most significant bit determines the register to be used (hash table high/hash table low), and the other 5 bits determine which bit within the register. a hash value of 0b0 0000 selects bit 0 in the selected register, and a value of 0b1 1111 selects bit 31 in the selected register. for example, if the da of the incoming frame is received as 0x1f52 419c b6af (0x1f is the first byte received on the mii interface), then the internally calculated 6-bit hash value is 0x2c and the hth register bit[12] is checked for filtering. if the da of the incoming frame is received as 0xa00a 9800 0045, then the calculated 6-bit hash value is 0x07 and the htl register bit[7] is checked for filtering. if the corresponding bit value in the register is 1, the frame is accepted. otherwise, it is rejected. if the pam (pass all multicast) bit is set in the eth_macffr register, then all multicast frames are accepted regardless of the multicast hash values. the hash table high register contains the higher 32 bits of the multicast hash table. ethernet mac hash table low register (eth_machtlr) address offset: 0x000c reset value: 0x0000 0000 the hash table low register contains the lower 32 bits of the multi-cast hash table. ethernet mac mii address register (eth_macmiiar) address offset: 0x0010 reset value: 0x0000 0000 the mii address register controls the management cycles to the external phy through the management interface. gx () x 32 x 26 x 23 x 22 x 16 x 12 x 11 x 10 x 8 x 7 x 5 x 4 x 2 x1 + + + + + + + +++++++ = 313029282726252423222120191817161514131211109876543210 hth rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:0 hth: hash table high this field contains the upper 32 bits of hash table. 313029282726252423222120191817161514131211109876543210 htl rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:0 htl: hash table low this field contains the lower 32 bits of the hash table. 3130292827262524232221201918171615141312111098765432 1 0 reserved pa m r reserved cr mw mb rw rw rw rw rw rw rw rw rw rw rw rw rw rw rc_ w1 ethernet (eth): media access control (mac) with dma controller RM0033 878/1317 doc id 15403 rev 3 ethernet mac mii data register (eth_macmiidr) address offset: 0x0014 reset value: 0x0000 0000 the mac mii data register stores write data to be written to the phy register located at the address specified in eth_macmiiar. eth_macmiidr also stores read data from the phy register located at the address specified by eth_macmiiar. ethernet mac flow control register (eth_macfcr) address offset: 0x0018 bits 31:16 reserved bits 15:11 pa: phy address this field tells which of the 32 possible phy devices are being accessed. bits 10:6 mr: mii register these bits select the desired mii r egister in the selected phy device. bit 5 reserved bits 4:2 cr: clock range the cr clock range selection determines the hclk frequency and is used to decide the frequency of the mdc clock: selection hclk mdc clock 000 60-100 mhz hclk/42 001 100-120 mhz hclk/62 010 20-35 mhz hclk/16 011 35-60 mhz hclk/26 100, 101, 110, 111 reserved - bit 1 mw: mii write when set, this bit tells the phy that this will be a write operation using the mii data register. if this bit is not set, this will be a read operation, placing the data in the mii data register. bit 0 mb: mii busy this bit should read a logic 0 before writin g to eth_macmiiar and eth_macmiidr. this bit must also be reset to 0 during a write to eth_macmiiar. during a phy register access, this bit is set to 0b1 by the application to indicate that a read or write access is in progress. eth_macmiidr (mii data) should be kept valid until this bit is cleared by the mac during a phy write operation. the eth_macmiidr is invalid until this bit is cleared by the mac during a phy read operation. the eth_macmiiar (mii addr ess) should not be written to until this bit is cleared. 3130292827262524232221201918171615141312111098765432 1 0 reserved md rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:16 reserved bits 15:0 md: mii data this contains the 16-bit data value read from the phy after a management read operation, or the 16-bit data value to be written to th e phy before a management write operation. RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 879/1317 reset value: 0x0000 0000 the flow control register controls the generation and reception of the control (pause command) frames by the mac. a write to a register with the busy bit set to '1' causes the mac to generate a pause control frame. the fields of the control frame are selected as specified in the 802.3x specification, and the pause time value from this register is used in the pause time field of the control frame. the busy bit remains set until the control frame is transferred onto the cable. the host must make sure that the busy bit is cleared before writing to the register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pt reserved zqpd reserved plt upfd rfce tfce fcb/ bpa rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rc_w1 /rw bits 31:16 pt: pause time this field holds the value to be used in the pause time field in the transmit control frame. if the pause time bits is configured to be double-synchronized to the mii clock domain, then consecutive write operations to this register should be performed only after at least 4 clock cycles in the destin ation clock domain. bits 15:8 reserved bit 7 zqpd: zero-quanta pause disable when set, this bit disables the automatic gener ation of zero-quanta pause control frames on the deassertion of the flow-contr ol signal from the fifo layer. when this bit is reset, normal operation wit h automatic zero-quanta pause control frame generation is enabled. bit 6 reserved bits 5:4 plt: pause low threshold this field configures the threshold of t he pause timer at which the pause frame is automatically retransmitted. the threshold values should always be less than the pause time configured in bits[31:16]. for example, if pt = 100h (256 slot-times), and plt = 01, then a second pause frame is automatically transmitted if initiated at 228 (25 6 ? 28) slot-times after the first pause frame is transmitted. selection threshold 00 pause time minus 4 slot times 01 pause time minus 28 slot times 10 pause time minus 144 slot times 11 pause time minus 256 slot times slot time is defined as time taken to transmit 512 bits (64 bytes) on the mii interface. bit 3 upfd: unicast pause frame detect when this bit is set, the mac detects the p ause frames with the station?s unicast address specified in the eth_maca0hr and eth_maca0lr registers, in addition to detecting pause frames with the unique multicast address. when this bit is reset, the mac detects only a pause frame with the unique multicast address specified in the 802.3x standard. bit 2 rfce: receive flow control enable when this bit is set, the mac decodes the received pause frame and disables its transmitter for a specified (pause time) time. when this bit is reset, the decode fu nction of the pause frame is disabled. ethernet (eth): media access control (mac) with dma controller RM0033 880/1317 doc id 15403 rev 3 ethernet mac vlan tag register (eth_macvlantr) address offset: 0x001c reset value: 0x0000 0000 the vlan tag register contains the ieee 802. 1q vlan tag to identify the vlan frames. the mac compares the 13 th and 14 th bytes of the receiving frame (length/type) with 0x8100, and the following 2 bytes are compared with the vlan tag; if a match occurs, the received vlan bit in the receive frame status is set. the legal length of the frame is increased from 1518 bytes to 1522 bytes. bit 1 tfce: transmit flow control enable in full-duplex mode, when this bit is set, the mac enables the flow control operation to transmit pause frames. when this bit is rese t, the flow control operation in the mac is disabled, and the mac does not transmit any pause frames. in half-duplex mode, when this bit is set, th e mac enables the back-pressure operation. when this bit is reset, the back pressure feature is disabled. bit 0 fcb/bpa: flow control busy/ba ck pressure activate this bit initiates a pause control frame in full-duplex mode and activates the back pressure function in half-duplex mode if tfce bit is set. in full-duplex mode, this bit should be read as 0 before writing to the flow control register. to initiate a pause control frame, the application mu st set this bit to 1. during a transfer of the control frame, this bit continues to be set to si gnify that a frame transmission is in progress. after completion of the pause control frame tran smission, the mac resets this bit to 0. the flow control register should not be written to until this bit is cleared. in half-duplex mode, when this bit is set (and tfce is set), back pressure is asserted by the mac core. during back pressure, when the mac re ceives a new frame, the transmitter starts sending a jam pattern resulting in a collisio n. when the mac is configured to full-duplex mode, the bpa is automatically disabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved vlantc vlanti rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:17 reserved bit 16 vlantc: 12-bit vlan tag comparison when this bit is set, a 12-bit vlan identifier, rath er than the complete 16-bit vlan tag, is used for comparison and filtering. bits[11:0] of th e vlan tag are compared with the corresponding field in the received vlan-tagged frame. when this bit is reset, all 16 bits of the rece ived vlan frame?s fifteenth and sixteenth bytes are used for comparison. RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 881/1317 bits 15:0 vlanti: vlan tag identifier (for receive frames) this contains the 802.1q vlan tag to identify vlan frames, and is compared to the fifteenth and sixteenth bytes of the frames being receiv ed for vlan frames. bits[15:13] are the user priority, bit[12] is the canonical format indicato r (cfi) and bits[11:0] are the vlan tag?s vlan identifier (vid) field. when the vlantc bit is set, only the vid (bits[11:0]) is used for comparison. if vlanti (vlanti[11:0] if vlantc is set) is all zeros, the mac does not check the fifteenth and sixteenth bytes for vlan tag comparison, and declares all frames with a type field value of 0x8100 as vlan frames. ethernet (eth): media access control (mac) with dma controller RM0033 882/1317 doc id 15403 rev 3 ethernet mac remote wakeup frame filter register (eth_macrwuffr) address offset: 0x0028 reset value: 0x0000 0000 this is the address through which the remote wakeup frame filter registers are written/read by the application. the wakeup frame filter register is actually a pointer to eight (not transparent) such wakeup frame filter registers. eight sequential write operations to this address with the offset (0 x0028) will write all wakeup frame fi lter registers. eight sequential read operations from this addr ess with the offset (0x0028) w ill read all wakeup frame filter registers. this register contains the higher 16 bits of the 7 th mac address. refer to remote wakeup frame filter register section for additional information. figure 347. ethernet mac remote wakeup frame filter register (eth_macrwuffr) filter 0 byte mask filter 1 byte mask filter 2 byte mask filter 3 byte mask rsvd filter 3 command rsvd filter 2 command rsvd filter 1 command rsvd filter 0 command filter 3 offset filter 2 offset filter 1 offset filter 0 offset filter 1 crc - 16 filter 0 crc - 16 filter 3 crc - 16 filter 2 crc - 16 wakeup frame filter reg0 wakeup frame filter reg1 wakeup frame filter reg2 wakeup frame filter reg3 wakeup frame filter reg4 wakeup frame filter reg5 wakeup frame filter reg6 wakeup frame filter reg7 ai15648 RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 883/1317 ethernet mac pmt control and status register (eth_macpmtcsr) address offset: 0x002c reset value: 0x0000 0000 the eth_macpmtcsr programs the request wakeup events and monitors the wakeup events. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wffrpr reserved gu reserved wfr mpr reserved wfe mpe pd rs res. rw rc_r rc_r rw rw rs bit 31 wffrpr: wakeup frame filter register pointer reset when set, it resets the remote wakeup frame filter register pointer to 0b00 0. it is automatically cleared after 1 clock cycle. bits 30:10 reserved bit 9 gu: global unicast when set, it enables any unicast packet filtered by the mac (daf) address recognition to be a wakeup frame. bits 8:7 reserved bit 6 wfr: wakeup frame received when set, this bit indicates the power management event was generated due to reception of a wakeup frame. this bit is cleared by a read into this register. bit 5 mpr: magic packet received when set, this bit indicates the power management event was generated by the reception of a magic packet. this bit is cleared by a read into this register. bits 4:3 reserved bit 2 wfe: wakeup frame enable when set, this bit enables the generation of a power management event due to wakeup frame reception. bit 1 mpe: magic packet enable when set, this bit enables the generation of a power management event due to magic packet reception. bit 0 pd: power down when this bit is set, all received frames will be dropped. this bit is cleared automatically when a magic packet or wakeup frame is received, and power-down mode is disabled. frames received after this bit is cleared are forwarded to the application. this bit must only be set when either the magic packet enable or wakeup frame enable bit is set high. ethernet (eth): media access control (mac) with dma controller RM0033 884/1317 doc id 15403 rev 3 ethernet mac debug register (eth_macdbgr) address offset: 0x0034 reset value: 0x0000 0000 this debug register gives the status of all the main modules of the transmit and receive data paths and the fifos. an all-zero status indicates that the mac core is in idle state (and fifos are empty) and no activity is going on in the data paths. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved tff tfne reserved tfwa tfrs mtp mtfcs mmtea reserved rffl reserved rfrcs rfwra reserved msfrwcs mmrpea ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro bits 31:26 reserved bit 25 tff: tx fifo full when high, it indicates that the tx fifo is fu ll and hence no more frames will be accepted for transmission. bit 24 tfne: tx fifo not empty when high, it indicates that the txfifo is not empty and has some data left for transmission. bit 23 reserved bit 22 tfwa: tx fifo write active when high, it indicates that th e txfifo write controller is active and transferring data to the txfifo. bits 21:20 tfrs: tx fifo read status this indicates the state of the txfifo read controller: 00: idle state 01: read state (transferring data to the mac transmitter) 10: waiting for txstatus from mac transmitter 11: writing the received txstat us or flushing the txfifo bit 19 mtp: mac transmitter in pause when high, it indicates that the mac transmitt er is in pause condition (in full-duplex mode only) and hence will not schedule any frame for transmission bits 18:17 mtfcs: mac transmit frame controller status this indicates the state of the mac transmit frame controller: 00: idle 01: waiting for status of previous frame or ifg/backoff period to be over 10: generating and transmitting a pause control frame (in full duplex mode) 11: transferring input frame for transmission bit 16 mmtea: mac mii transmit engine active when high, it indicates that the mac mii transmit engine is actively transmitting data and that it is not in the idle state. bits 15:10 reserved RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 885/1317 bits 9:8 rffl: rx fifo fill level this gives the status of the rx fifo fill-level: 00: rxfifo empty 01: rxfifo fill-level below flow-control de-activate threshold 10: rxfifo fill-level above flow-control activate threshold 11: rxfifo full bit 7 reserved bits 6:5 rfrcs: rx fifo read c ontroller status it gives the state of the rx fifo read controller: 00: idle state 01: reading frame data 10: reading frame status (or time-stamp) 11: flushing the fr ame data and status bit 4 rfwra: rx fifo write controller active when high, it indicates that the rx fifo write controller is active and transferring a received frame to the fifo. bit 3 reserved bits 2:1 msfrwcs: mac small fifo read / write controllers status when high, these bits indicate the respective active state of the small fifo read and write controllers of the mac receive frame controller module. bit 0 mmrpea: mac mii receive protocol engine active when high, it indicates that the mac mii receiv e protocol engine is actively receiving data and is not in the idle state. ethernet (eth): media access control (mac) with dma controller RM0033 886/1317 doc id 15403 rev 3 ethernet mac interrupt status register (eth_macsr) address offset: 0x0038 reset value: 0x0000 0000 the eth_macsr register contents identify the events in the mac that can generate an interrupt. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved tsts reserved mmcts mmcrs mmcs pmts reserved rc_r r r r r bits 15:10 reserved bit 9 tsts: time stamp trigger status this bit is set high when the system time val ue equals or exceeds the value specified in the target time high and low registers. this bit is cleared when this register is read. bits 8:7 reserved bit 6 mmcts: mmc transmit status this bit is set high whenever an interrupt is generated in the eth_mmctir register. this bit is cleared when all the bits in this interrupt register (eth_mmctir) are cleared. bit 5 mmcrs: mmc receive status this bit is set high whenever an interrupt is gener ated in the eth_mmcrir register. this bit is cleared when all the bits in this interrupt register (eth_mmcrir) are cleared. bit 4 mmcs: mmc status this bit is set high whenever any of bits 6:5 is set high. it is cleared only when both bits are low. bit 3 pmts: pmt status this bit is set whenever a magic packet or wake-on-lan frame is received in power-down mode (see bits 5 and 6 in the eth_macpmtcsr register ethernet mac pmt control and status register (eth_macpmtcsr) on page 883 ). this bit is cleared when both bits[6:5], of this last register, are cleared due to a r ead operation to the et h_macpmtcsr register. bits 2:0 reserved RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 887/1317 ethernet mac interrupt mask register (eth_macimr) address offset: 0x003c reset value: 0x0000 0000 the eth_macimr register bits make it possible to mask the interrupt signal due to the corresponding event in the eth_macsr register. ethernet mac address 0 high register (eth_maca0hr) address offset: 0x0040 reset value: 0x0010 ffff the mac address 0 high register holds the upper 16 bits of the 6-byte first mac address of the station. note that the first da byte that is received on the mii interface corresponds to the ls byte (bits [7:0]) of the mac address low register. for example, if 0x1122 3344 5566 is received (0x11 is the first byte) on the m ii as the destination address, then the mac address 0 register [47:0] is compared with 0x6655 4433 2211. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved tstim reserved pmtim reserved rw rw bits 15:10 reserved bit 9 tstim: time stamp trigger interrupt mask when set, this bit disables the time stamp interrupt generation. bits 8:4 reserved bit 3 pmtim: pmt interrupt mask when set, this bit disables the assertion of t he interrupt signal due to the setting of the pmt status bit in eth_macsr. bits 2:0 reserved 313029282726252423222120191817161514131211109876543210 mo reserved maca0h 1 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bit 31 mo: always 1. bits 30:16 reserved bits 15:0 maca0h: mac address0 high [47:32] this field contains the upper 16 bits (47:32) of the 6-byte mac address0. this is used by the mac for filtering for received frames and for inserting the mac address in the transmit flow control (pause) frames. ethernet (eth): media access control (mac) with dma controller RM0033 888/1317 doc id 15403 rev 3 ethernet mac address 0 low register (eth_maca0lr) address offset: 0x0044 reset value: 0xffff ffff the mac address 0 low register holds the lower 32 bits of the 6-byte first mac address of the station. ethernet mac address 1 high register (eth_maca1hr) address offset: 0x0048 reset value: 0x0000 ffff the mac address 1 high register holds the upper 16 bits of the 6-byte second mac address of the station. 313029282726252423222120191817161514131211109876543210 maca0l rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:0 maca0l: mac address0 low [31:0] this field contains the lower 32 bits of the 6-byte mac address0. this is used by the mac for filtering for received frames and for inserting the mac address in the transmit flow control (pause) frames. 313029282726252423222120191817161514131211109876543210 ae sa mbc reserved maca1h rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bit 31 ae: address enable when this bit is set, the addre ss filters use the mac address1 for perfect filtering. when this bit is cleared, the address filters ig nore the address for filtering. bit 30 sa: source address when this bit is set, the mac address1[47:0] is used for comparison with the sa fields of the received frame. when this bit is cleared, the mac address1[47: 0] is used for comparison with the da fields of the received frame. bits 29:24 mbc: mask byte control these bits are mask control bits for comparison of each of the mac address1 bytes. when they are set high, the mac core does not compare the corresponding byte of received da/sa with the contents of the mac address1 registers. ea ch bit controls the masking of the bytes as follows: ? bit 29: eth_maca1hr [15:8] ? bit 28: eth_maca1hr [7:0] ? bit 27: eth_maca1lr [31:24] ? ? bit 24: eth_maca1lr [7:0] bits 23:16 reserved RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 889/1317 ethernet mac address1 low register (eth_maca1lr) address offset: 0x004c reset value: 0xffff ffff the mac address 1 low register holds the lower 32 bits of the 6-byte second mac address of the station. ethernet mac address 2 high register (eth_maca2hr) address offset: 0x0050 reset value: 0x0000 ffff the mac address 2 high register holds the upper 16 bits of the 6-byte second mac address of the station. bits 15:0 maca1h: mac address1 high [47:32] this field contains the upper 16 bits (4 7:32) of the 6-byte second mac address. 313029282726252423222120191817161514131211109876543210 maca1l rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:0 maca1l: mac address1 low [31:0] this field contains the lower 32 bits of the 6- byte mac address1. the content of this field is undefined until loaded by the applicati on after the initialization process. 313029282726252423222120191817161514131211109876543210 ae sa mbc reserved maca2h rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bit 31 ae: address enable when this bit is set, the addre ss filters use the mac address2 for perfect filtering. when reset, the address filters ignore the address for filtering. bit 30 sa: source address when this bit is set, the mac address 2 [47:0] is used for comparison with the sa fields of the received frame. when this bit is reset, the mac address 2 [47:0] is used for comparison with the da fields of the received frame. bits 29:24 mbc: mask byte control these bits are mask control bits for comparison of each of the mac address2 bytes. when set high, the mac core does not compare the co rresponding byte of received da/sa with the contents of the mac address 2 registers. each bi t controls the masking of the bytes as follows: ? bit 29: eth_maca2hr [15:8] ? bit 28: eth_maca2hr [7:0] ? bit 27: eth_maca2lr [31:24] ? ? bit 24: eth_maca2lr [7:0] ethernet (eth): media access control (mac) with dma controller RM0033 890/1317 doc id 15403 rev 3 ethernet mac address 2 low register (eth_maca2lr) address offset: 0x0054 reset value: 0xffff ffff the mac address 2 low register holds the lower 32 bits of the 6-byte second mac address of the station. ethernet mac address 3 high register (eth_maca3hr) address offset: 0x0058 reset value: 0x0000 ffff the mac address 3 high register holds the upper 16 bits of the 6-byte second mac address of the station. bits 23:16reserved bits 15:0 maca2h: mac address2 high [47:32] this field contains the upper 16 bits (47:32) of the 6-byte mac address2. 313029282726252423222120191817161514131211109876543210 maca2l rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:0 maca2l: mac address2 low [31:0] this field contains the lower 32 bits of the 6- byte second mac address2. the content of this field is undefined until loaded by the app lication after the initialization process. 313029282726252423222120191817161514131211109876543210 ae sa mbc reserved maca3h rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bit 31 ae: address enable when this bit is set, the address filters use the mac address3 for perfect filtering. when this bit is cleared, the address filters ig nore the address for filtering. bit 30 sa: source address when this bit is set, the mac address 3 [47:0] is used for comparison with the sa fields of the received frame. when this bit is cleared, the mac address 3[47:0] is used for comparison with the da fields of the received frame. RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 891/1317 ethernet mac address 3 low register (eth_maca3lr) address offset: 0x005c reset value: 0xffff ffff the mac address 3 low register holds the lower 32 bits of the 6-byte second mac address of the station. bits 29:24 mbc: mask byte control these bits are mask control bits for comparison of each of the mac address3 bytes. when these bits are set high, the mac core does not compare the corresponding byte of received da/sa with the contents of the mac address 3 regist ers. each bit controls the masking of the bytes as follows: ? bit 29: eth_maca3hr [15:8] ? bit 28: eth_maca3hr [7:0] ? bit 27: eth_maca3lr [31:24] ? ? bit 24: eth_maca3lr [7:0] bits 23:16 reserved bits 15:0 maca3h: mac address3 high [47:32] this field contains the upper 16 bits (47:32) of the 6-byte mac address3. 313029282726252423222120191817161514131211109876543210 maca3l rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:0 maca3l: mac address3 low [31:0] this field contains the lower 32 bits of the 6- byte second mac address3. the content of this field is undefined until loaded by the app lication after the initialization process. ethernet (eth): media access control (mac) with dma controller RM0033 892/1317 doc id 15403 rev 3 28.8.2 mmc regist er description ethernet mmc control register (eth_mmccr) address offset: 0x0100 reset value: 0x0000 0000 the ethernet mmc control register establishes the operating mode of the management counters. ethernet mmc receive interrupt register (eth_mmcrir) address offset: 0x0104 reset value: 0x0000 0000 the ethernet mmc receive interrupt register maintains the interrupts generated when receive statistic counters reach half their maximum values. (msb of the counter is set.) it is a 32-bit wide register. an interrupt bit is cleared when the respective mmc counter that 313029282726252423222120191817161514131211109876543210 reserved mcfhp mcp mcf ror csr cr rw rw rw rw rw rw bits 31:6 reserved bit 5 mcfhp: mmc counter full-half preset when mcfhp is low and bit4 is set, all mmc counters get preset to almost-half value. all frame-counters get preset to 0x7fff_fff0 (half - 16) when mcfhp is high and bit4 is set, all mmc counters get preset to almost-full value. all frame-counters get preset to 0xffff_fff 0 (full - 16) bit 4 mcp: mmc counter preset when set, all counters will be initialized or preset to almost full or almost half as per bit5 above. this bit will be cleared automatically after 1 clock cycle. this bit along with bit5 is useful for debugging and test ing the assertion of interrupts due to mmc counter becoming half-full or full. bit 3 mcf: mmc counter freeze when set, this bit freezes all the mmc counters to their current value. (none of the mmc counters are updated due to any transmitted or re ceived frame until this bit is cleared to 0. if any mmc counter is read with the reset on read bit set, then that counter is also cleared in this mode.) bit 2 ror: reset on read when this bit is set, the mmc counters is reset to zero after read (self-clearing after reset). the counters are cleared when the least signif icant byte lane (bits [7:0]) is read. bit 1 csr: counter stop rollover when this bit is set, the counter does not roll over to zero after it reaches the maximum value. bit 0 cr: counter reset when it is set, all counters are reset. this bit is cleared automati cally after 1 clock cycle. RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 893/1317 caused the interrupt is read. the least significant byte lane (bits [7:0]) of the respective counter must be read in order to clear the interrupt bit. ethernet mmc transmit interrupt register (eth_mmctir) address offset: 0x0108 reset value: 0x0000 0000 the ethernet mmc transmit interrupt register maintains the interrupts generated when transmit statistic counters reach half their maximum values. (msb of the counter is set.) it is a 32-bit wide register. an interrupt bit is cleared when the respective mmc counter that caused the interrupt is read. the least significant byte lane (bits [7:0]) of the respective counter must be read in order to clear the interrupt bit. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved rgufs reserved rfaes rfces reserved rc_r rc_r rc_r bits 31:18 reserved bit 17 rgufs: received good unicast frames status this bit is set when the received, good unicast frames, counter reaches half the maximum value. bits 16:7 reserved bit 6 rfaes: received frames alignment error status this bit is set when the received frames, with alignment error, counter reaches half the maximum value. bit 5 rfces: received frames crc error status this bit is set when the received frames, with crc error, counter reaches half the maximum value. bits 4:0 reserved 313029282726252423222120191817161514131211109876543210 reserved tgfs reserved tgfmscs tgfscs reserved rc_r rc_r rc_r bits 31:22 reserved bit 21 tgfs: transmitted good frames status this bit is set when the transmitted, good frames, counter reaches half the maximum value. bits 20:16 reserved ethernet (eth): media access control (mac) with dma controller RM0033 894/1317 doc id 15403 rev 3 bit 15 tgfmscs: transmitted good frames more single collision status this bit is set when the transmitted, good frames after more than a single collision, counter reaches half the maximum value. bit 14 tgfscs: transmitted good frames single collision status this bit is set when the transmitted, good frames after a single collision, counter reaches half the maximum value. bits 13:0 reserved RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 895/1317 ethernet mmc receive interrupt mask register (eth_mmcrimr) address offset: 0x010c reset value: 0x0000 0000 the ethernet mmc receive interrupt mask re gister maintains th e masks for interrupts generated when the receive statistic counters reach half their maximum value. (msb of the counter is set.) it is a 32-bit wide register. ethernet mmc transmit interrupt mask register (eth_mmctimr) address offset: 0x0110 reset value: 0x0000 0000 the ethernet mmc transmit interrupt mask re gister maintains th e masks for interrupts generated when the transmit statistic counters reach half their maximum value. (msb of the counter is set). it is a 32-bit wide register. 31302928272625242322212019181716151413121110987 6 5 43210 reserved rgufm reserved rfaem rfcem reserved rw rw rw bits 31:18 reserved bit 17 rgufm: received good unicast frames mask setting this bit masks the interrupt when the received, good uni cast frames, counter reaches half the maximum value. bits 16:7 reserved bit 6 rfaem: received frames alignment error mask setting this bit masks the interrupt when the re ceived frames, with alig nment error, counter reaches half the maximum value. bit 5 rfcem: received frame crc error mask setting this bit masks the interr upt when the received frames, wit h crc error, counter reaches half the maximum value. bits 4:0 reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved tgfm reserved tgfmscm tgfscm reserved rw rw rw bits 31:22 reserved bit 21 tgfm: transmitted good frames mask setting this bit masks the interrupt when the tr ansmitted, good frames, counter reaches half the maximum value. bits 20:16 reserved ethernet (eth): media access control (mac) with dma controller RM0033 896/1317 doc id 15403 rev 3 ethernet mmc transmitted good frames after a single collision counter register (eth_mmctgfsccr) address offset: 0x014c reset value: 0x0000 0000 this register contains the num ber of successfully transmitted frames after a single collision in half-duplex mode. ethernet mmc transmitted good frames after more than a single collision counter register (eth_mmctgfmsccr) address offset: 0x0150 reset value: 0x0000 0000 this register contains the number of successfully transmitted frames after more than a single collision in half-duplex mode. bit 15 tgfmscm: transmitted good frames more single collision mask setting this bit masks the interrupt when the tr ansmitted good frames after more than a single collision counter reaches half the maximum value. bit 14 tgfscm: transmitted good frames single collision mask setting this bit masks the interrupt when the tr ansmitted good frames after a single collision counter reaches half the maximum value. bits 13:0 reserved 313029282726252423222120191817161514131211109876543210 tgfscc rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr bits 31:0 tgfscc: transmitted good frames single collision counter transmitted good frames after a single collision counter. 313029282726252423222120191817161514131211109876543210 tgfmscc rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr bits 31:0 tgfmscc: transmitted good frames more single collision counter transmitted good frames after more than a single collision counter RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 897/1317 ethernet mmc transmitted good frames counter register (eth_mmctgfcr) address offset: 0x0168 reset value: 0x0000 0000 this register contains the number of good frames transmitted. ethernet mmc received frames with crc error counter register (eth_mmcrfcecr) address offset: 0x0194 reset value: 0x0000 0000 this register contains the number of frames received with crc error. ethernet mmc received frames with alignment error counter register (eth_mmcrfaecr) address offset: 0x0198 reset value: 0x0000 0000 this register contains the number of frames received with alignment (dribble) error. 313029282726252423222120191817161514131211109876543210 tgfc rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr bits 31:0 tgfc: transmitted good frames counter 313029282726252423222120191817161514131211109876543210 rfcec rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr bits 31:0 rfcec: received frames crc error counter received frames with crc error counter 313029282726252423222120191817161514131211109876543210 rfaec rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr bits 31:0 rfaec: received frames alignment error counter received frames with alignment error counter ethernet (eth): media access control (mac) with dma controller RM0033 898/1317 doc id 15403 rev 3 mmc received good unicast frames counter register (eth_mmcrgufcr) address offset: 0x01c4 reset value: 0x0000 0000 this register contains the number of good unicast frames received. 28.8.3 ieee 1588 time stamp registers this section describes the registers required to support precision network clock synchronization functions und er the ieee 158 8 standard. ethernet ptp time stamp control register (eth_ptptscr) address offset: 0x0700 reset value: 0x0000 00002000 this register controls the time stamp generation and update logic. 313029282726252423222120191817161514131211109876543210 rgufc rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr bits 31:0 rgufc: received good unicast frames counter 313029282726252423222120191817161514131211109876543210 reserved tspffmae tscnt tssmrme tsseme tssipv4fe tssipv6fe tssptpoefe tsptppsv2e tsssr tssarfe reserved ttsaru tsite tsstu tssti tsfcu tse rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:19 reserved bit 18 tspffmae: time stamp ptp frame filtering mac address enable when set, this bit uses the mac address (except for mac address 0) to filter the ptp frames when ptp is sent directly over ethernet. bits 17:16 tscnt : time stamp clock node type the following are the available types of clock node: 00: ordinary clock 01: boundary clock 10: end-to-end transparent clock 11: peer-to-peer transparent clock bit 15 tssmrme : time stamp snapshot for message relevant to master enable when this bit is set, the snapshot is taken for messages relevant to the master node only. when this bit is cleared the snapshot is taken for messages relevant to the slave node only. this is valid only for the ordinary clock and boundary clock nodes. bit 14 tsseme : time stamp snapshot for event message enable when this bit is set, the time stamp snaps hot is taken for event messages only (sync, delay_req, pdelay_req or pdelay_resp). when this bit is cleared the snapshot is taken for all other messages except for announce, management and signaling. RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 899/1317 bit 13 tssipv4fe : time stamp snapshot for ipv4 frames enable when this bit is set, the time stamp snapshot is taken for ipv4 frames. bit 12 tssipv6fe : time stamp snapshot for ipv6 frames enable when this bit is set, the time stamp snapshot is taken for ipv6 frames. bit 11 tssptpoefe : time stamp snapshot for ptp over ethernet frames enable when this bit is set, the time stamp snapshot is taken for frames which have ptp messages in ethernet frames (ptp over ethernet) also. by default snapshots are taken for udp-ipethernet ptp packets. bit 10 tsptppsv2e : time stamp ptp packet snooping for version2 format enable when this bit is set, the ptp packets are sn ooped using the version 2 format. when the bit is cleared, the ptp packets are sn ooped using the version 1 format. note: ieee 1588 version 1 and version 2 formats as indi cated in ieee st andard 1588-2008 (revision of ieee std. 1588-2002). bit 9 tsssr : time stamp subsecond rollover: digital or binary rollover control when this bit is set, the time stamp low re gister rolls over when the subsecond counter reaches the value 0x3b9a c9ff (999 999 999 in decimal), and increments the time stamp (high) seconds. when this bit is cleared, the rollover value of the subsecond register reaches 0x7fff ffff. the subsecond increment has to be programmed correctly depending on the ptp?s reference clock frequency and this bit value. bit 8 tssarfe: time stamp snapshot for all received frames enable when this bit is set, the time stamp snapshot is enabled for all frames received by the core. bits 7:6 reserved bit 5 tsaru: time stamp addend register update when this bit is set, the time stamp addend r egister?s contents are updated to the ptp block for fine correction. this bit is cleared when the update is complete. this register bit must be read as zero before you can set it. bit 4 tsite: time stamp interrupt trigger enable when this bit is set, a time stamp interrupt is generated when the system time becomes greater than the value written in the target time register. when the time stamp trigger interrupt is generated, this bit is cleared. bit 3 tsstu: time stamp syst em time update when this bit is set, the system time is up dated (added to or subtra cted from) with the value specified in the time stamp high update and ti me stamp low update r egisters. both the tsstu and tssti bits must be read as zero befo re you can set this bit. once the update is completed in hardware, this bit is cleared. bit 2 tssti: time stamp system time initialize when this bit is set, the system time is initializ ed (overwritten) with th e value specified in the time stamp high update and time stamp low update registers. this bit must be read as zero before you can set it. when initialization is complete, this bit is cleared. bit 1 tsfcu: time stamp fine or coarse update when set, this bit indicates that the system time stamp is to be updated using the fine update method. when cleared, it indicates the system ti me stamp is to be updated using the coarse method. ethernet (eth): media access control (mac) with dma controller RM0033 900/1317 doc id 15403 rev 3 the table below indicates the messages for which a snapshot is taken depending on the clock, enable master and enable snapshot for event message register settings. ethernet ptp subsecond increment register (eth_ptpssir) address offset: 0x0704 reset value: 0x0000 0000 this register contains the 8-bit value by wh ich the subsecond register is incremented. in coarse update mode (tsfcu bit in eth_ptptscr), the value in this register is added to the system time every clock cycle of hclk. in fi ne update mode, the value in this register is added to the system time whenever the accumulator gets an overflow. ethernet ptp time stamp high register (eth_ptptshr) address offset: 0x0708 bit 0 tse: time stamp enable when this bit is set, time stamping is enabled for transmit and receive frames. when this bit is cleared, the time stamp function is suspended and time stamps are not added for transmit and receive frames. because the maintained system time is suspended, you must always initialize the time stamp feature (system ti me) after setting this bit high. table 146. time stamp snapshot dependency on registers bits tscnt (bits 17:16) tssmrme (bit 15) (1) 1. n/a = not applicable. tsseme (bit 14) messages for which snapshots are taken 00 or 01 x (2) 2. x = don?t care. 0 sync, follow_up, delay_req, delay_resp 00 or 01 1 1 delay_req 00 or 01 0 1 sync 10 n/a 0 sync, follow_up, delay_req, delay_resp 10 n/a 1 sync, follow_up 11 n/a 0 sync, follow_up, delay_req, delay_resp, pdelay_req, pdelay_resp 11 n/a 1 sync, pdelay_req, pdelay_resp 313029282726252423222120191817161514131211109876543210 reserved stssi rw rw rw rw rw rw rw rw bits 31:8 reserved bits 7:0 stssi: system time subsecond increment the value programmed in this register is added to the contents of the subsecond value of the system time in every update. for example, to achieve 20 ns accuracy, the value is: 20 / 0.467 = ~ 43 (or 0x2a). RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 901/1317 reset value: 0x0000 0000 this register contains the most significant (h igher) 32 time bits. this read-only register contains the seconds system time value. the time stamp high register, along with time stamp low register, indicates the current value of the system time maintained by the mac. though it is updated on a continuous basis. 313029282726252423222120191817161514131211109876543210 sts rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr bits 31:0 sts: system time second the value in this field indicates the current valu e in seconds of the system time maintained by the core. ethernet (eth): media access control (mac) with dma controller RM0033 902/1317 doc id 15403 rev 3 ethernet ptp time stamp low register (eth_ptptslr) address offset: 0x070c reset value: 0x0000 0000 this register contains the least significant (lower) 32 time bits. this read-only register contains the subsecond system time value. ethernet ptp time stamp high update register (eth_ptptshur) address offset: 0x0710 reset value: 0x0000 0000 this register contains the most significant (higher) 32 bits of the time to be written to, added to, or subtracted from the system time value. the time stamp high update register, along with the time stamp update low register, initializes or updates the system time maintained by the mac. you have to write both of these registers before setting the tssti or tsstu bits in the time stamp control register. 313029282726252423222120191817161514131211109876543210 stpns stss r rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr bit 31 stpns: system time positive or negative sign this bit indicates a positive or negative time value. when set, the bit indicates that time representation is negative. when cleared, it in dicates that time representation is positive. because the system time should always be positive, this bit is normally zero. bits 30:0 stss: system time subseconds the value in this field has the subsecond ti me representation, with 0.46 ns accuracy. 313029282726252423222120191817161514131211109876543210 tsus rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:0 tsus: time stamp update second the value in this field indicate s the time, in seconds, to be initialized or added to the system time. RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 903/1317 ethernet ptp time stamp low update register (eth_ptptslur) address offset: 0x0714 reset value: 0x0000 0000 this register contains the least significant (lower) 32 bits of the time to be written to, added to, or subtracted from the system time value. ethernet ptp time stamp addend register (eth_ptptsar) address offset: 0x0718 reset value: 0x0000 0000 this register is used by the software to readjust the clock frequency linearly to match the master clock frequency. this regi ster value is used only when the system time is configured for fine update mode (tsfcu bit in eth_ptptscr). this register content is added to a 32-bit accumulator in every clock cycle and the system time is updated whenever the accumulator overflows. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tsupns tsuss rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bit 31 tsupns: time stamp update positive or negative sign this bit indicates positive or negative time value. when set, the bit indicates that time representation is negative. when cleared, it i ndicates that time representation is positive. when tssti is set (system time initialization) this bit should be zero. if this bit is set when tsstu is set, the value in the time stamp update registers is subtracted from the system time. otherwise it is added to the system time. bits 30:0 tsuss: time stamp update subseconds the value in this field indicates the subsecond time to be initialized or added to the system time. this value has an accuracy of 0.46 ns (in other words, a value of 0x0000_0001 is 0.46 ns). 313029282726252423222120191817161514131211109876543210 tsa rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:0 tsa: time stamp addend this register indicates the 32-bit time value to be added to the accumulator register to achieve time synchronization. ethernet (eth): media access control (mac) with dma controller RM0033 904/1317 doc id 15403 rev 3 ethernet ptp target time high register (eth_ptptthr) address offset: 0x071c reset value: 0x0000 0000 this register contains the higher 32 bits of time to be compared with the system time for interrupt event generation. the target time high register, along with target time low register, is used to schedule an interrupt event (tsaru bit in eth_ptptscr) wh en the system time exceeds the value programmed in these registers. ethernet ptp target time low register (eth_ptpttlr) address offset: 0x0720 reset value: 0x0000 0000 this register contains the lower 32 bits of time to be compared with the system time for interrupt event generation. ethernet ptp time stamp status register (eth_ptptssr) address offset: 0x0728 reset value: 0x0000 0000 this register contains the time stamp status register. 313029282726252423222120191817161514131211109876543210 ttsh rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:0 ttsh: target time stamp high this register stores the time in seconds. wh en the time stamp value matches or exceeds both target time stamp registers, the mac, if enabled, generates an interrupt. 313029282726252423222120191817161514131211109876543210 ttsl rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:0 ttsl: target time stamp low this register stores the time in (signed) nanoseconds. when the value of the time stamp matches or exceeds both target time stamp re gisters, the mac, if enabled, generates an interrupt. 313029282726252423222120191817161514131211109876543210 reserved tsttr tsso ro ro bits 31:2 reserved RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 905/1317 ethernet ptp pps control register (eth_ptpppscr) address offset: 0x072c reset value: 0x0000 0000 this register controls t he frequency of the pps output. 28.8.4 dma register description this section defines the bits for each dma register. non-32 bit accesses are allowed as long as the address is word-aligned. bit 1 tsttr : time stamp target time reached when set, this bit indicates that the value of the system time is greater than or equal to the value specified in the target time high and low registers bit 0 tsso : time stamp second overflow when set, this bit indicates that the second value of the time stamp has overflowed beyond 0xffff ffff. 313029282726252423222120191817161514131211109876543210 reserved tsttr tsso ro ro bits 31:4 reserved bits 3:0 ppsfreq : pps frequency selection the pps output frequency is set to 2 ppsfreq hz. 0000: 1 hz with a pulse width of 125 ms for binary rollover and, of 100 ms for digital rollover 0001: 2 hz with 50% duty cycle for binary ro llover (digital roll over not recommended) 0010: 4 hz with 50% duty cycle for binary ro llover (digital roll over not recommended) 0011: 8 hz with 50% duty cycle for binary ro llover (digital roll over not recommended) 0100: 16 hz with 50% duty cycle for binary rollover (digital rollover not recommended) ... 1111: 32768 hz with 50% duty cycl e for binary rollover (dig ital rollover not recommended) note: if digital rollover is used (tsssr=1, bit 9 in eth_ptptscr), it is recommended not to use the pps output with a frequency other than 1 hz. otherwise, with digital rollover, the pps output has irregular waveforms at higher frequencies (though its average frequency will always be correct during any one-second window). ethernet (eth): media access control (mac) with dma controller RM0033 906/1317 doc id 15403 rev 3 ethernet dma bus mode register (eth_dmabmr) address offset: 0x1000 reset value: 0x0000 2101 the bus mode register establishes the bus operating modes for the dma. 313029282726252423222120191817161514131211109876543210 reserved mb aab fpm usp rdp fb rtpr pbl edfe dsl da sr rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rs 313029282726252423222120191817161514131211109876543210 reserved aab fpm usp rdp fb rtpr pbl reserved dsl da sr rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rs bits 31:267 reserved bit 26 mb: mixed burst when this bit is set high and the fb bit is low, the ahb master interface starts all bursts of a length greater than 16 with incr (undefined burst). when this bit is cleared, it reverts to fixed burst transfers (incrx and single) for burst lengths of 16 and below. bit 25 aab: address-aligned beats when this bit is set high and the fb bit equals 1, the ahb interface generates all bursts aligned to the start address ls bits. if the fb bit equals 0, the first burst (accessing the data buffer?s start address) is not aligned, but subs equent bursts are aligned to the address. bit 24 fpm: 4xpbl mode when set high, this bit multiplies the pbl value programmed (bits [22:17] and bits [13:8]) four times. thus the dma transfers data in a maximu m of 4, 8, 16, 32, 64 and 128 beats depending on the pbl value. bit 23 usp: use separate pbl when set high, it configures the rxdma to use the value configured in bits [22:17] as pbl while the pbl value in bits [13:8] is applicable to txdma operations only. when this bit is cleared, the pbl value in bits [13:8] is applicable for both dma engines. bits 22:17 rdp: rx dma pbl these bits indicate the maximum number of b eats to be transferred in one rxdma transaction. this is the maximum value that is used in a single block read/writ e operation. the rxdma always attempts to burst as specified in rdp eac h time it starts a burs t transfer on the host bus. rdp can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. any other value results in undefined behavior. these bits are valid and applicable only when usp is set high. bit 16 fb: fixed burst this bit controls whether the ahb master interf ace performs fixed burst transfers or not. when set, the ahb uses only single, incr4, incr8 or incr16 during start of normal burst transfers. when reset, the ahb uses si ngle and incr burst transfer operations. RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 907/1317 ethernet dma transmit poll demand register (eth_dmatpdr) address offset: 0x1004 reset value: 0x0000 0000 this register is used by the application to instruct the dma to poll the transmit descriptor list. the transmit poll demand register enables the transmit dma to check whether or not the current descriptor is owned by dma. the trans mit poll demand command is given to wake up the txdma if it is in suspend mode. the txdma can go into suspend mode due to an underflow error in a transmitted frame or due to the unavailability of descriptors owned by bits 15:14 rtpr: rx tx priority ratio rxdma requests are given priority over txdma requests in the following ratio: 00: 1:1 01: 2:1 10: 3:1 11: 4:1 this is valid only when the da bit is cleared. bits 13:8 pbl: programmable burst length these bits indicate the maximum number of be ats to be transferred in one dma transaction. this is the maximum value that is used in a si ngle block read/write operation. the dma always attempts to burst as specified in pbl each time it starts a burst transfer on the host bus. pbl can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. any other value results in undefined behavior. when usp is set, this pbl value is applicable for txdma transactions only. the pbl values have the following limitations: ? the maximum number of beats (pbl) possible is limited by the size of the tx fifo and rx fifo. ? the fifo has a constraint that the maximum beat supported is half the depth of the fifo. ? if the pbl is common for both transmit an d receive dma, the minimum rx fifo and tx fifo depths must be considered. ? do not program out-of-range pbl values, because the syst em may not behave properly. bit 7 edfe: enhanced descriptor format enable when this bit is set, the enhanced descriptor format is enabled and the descriptor size is increased to 32 bytes (8 dwords). this is re quired when time stamping is activated (tse=1, eth_ptptscr bit 0) or if ipv4 checksum offl oad is activated (ipco=1, eth_maccr bit 10). bit 7 reserved bits 6:2 dsl: descriptor skip length this bit specifies the number of words to skip between two unchained descriptors. the address skipping starts from the end of current de scriptor to the start of next descriptor. when dsl value equals zero, the descriptor table is taken as contiguous by the dma, in ring mode. bit 1 da: dma arbitration 0: round-robin with rx:tx priority given in bits [15:14] 1: rx has priority over tx bit 0 sr: software reset when this bit is set, the mac dma controller resets all mac subsystem internal registers and logic. it is cleared autom atically after the reset operation has completed in all of the core clock domains. read a 0 value in this bit before re-programming any register of the core. ethernet (eth): media access control (mac) with dma controller RM0033 908/1317 doc id 15403 rev 3 transmit dma. you can issue this command anytime and the txdma resets it once it starts re-fetching the current descriptor from host memory. ehernet dma receive poll demand register (eth_dmarpdr) address offset: 0x1008 reset value: 0x0000 0000 this register is used by the application to inst ruct the dma to poll the receive descriptor list. the receive poll demand register enables the receive dma to check for new descriptors. this command is given to wake up the rxdma from suspend state. the rxdma can go into suspend state only due to the unavailability of de scriptors owned by it. ethernet dma receive descriptor list address register (eth_dmardlar) address offset: 0x100c reset value: 0x0000 0000 the receive descriptor list address register points to the start of the receive descriptor list. the descriptor lists reside in the stm32f 20x and stm32f21x's physical memory space and must be word-aligned. the dma internally converts it to bus-width aligned address by making the corresponding ls bits low. writing to the eth_dmardlar register is permitted only when reception is stopped. when stopped, the eth_dmardlar register must be written to before the receive start command is given. 313029282726252423222120191817161514131211109876543210 tpd rw_wt bits 31:0 tpd: transmit poll demand when these bits are written with any value, the dma reads the current descriptor pointed to by the eth_dmachtdr register. if that descriptor is not available (owned by host), transmission returns to the suspend state and eth_dmasr regi ster bit 2 is asserted. if the descriptor is available, transmission resumes. 313029282726252423222120191817161514131211109876543210 rpd rw_wt bits 31:0 rpd: receive poll demand when these bits are written with any value, t he dma reads the current descriptor pointed to by the eth_dmachrdr register. if that descriptor is not available (owned by host), reception returns to the suspended state and eth_dmasr register bit 7 is not asserted. if the descriptor is available, the receive dma returns to active state. 313029282726252423222120191817161514131211109876543210 srl rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 909/1317 ethernet dma transmit descriptor list address register (eth_dmatdlar) address offset: 0x1010 reset value: 0x0000 0000 the transmit descriptor list address register points to the start of the transmit descriptor list. the descriptor lists reside in the stm32f 20x and stm32f21x's physical memory space and must be word-aligned. the dma internally converts it to bus-width-aligned address by taking the corresponding lsb to low. writing to the eth_dmatdlar register is permitted only when transmission has stopped. once transmission has stopped, the eth_dmatdlar register can be written before the transmission start command is given. ethernet dma status register (eth_dmasr) address offset: 0x1014 reset value: 0x0000 0000 the status register contains all the status bits that the dma reports to the application. the eth_dmasr register is usually read by the software driver during an interrupt service routine or polling. most of the fields in this register cause the host to be interrupted. the eth_dmasr register bits are not cleared when read. writing 1 to (unreserved) bits in eth_dmasr register[16:0] clears them and writing 0 has no effect. each field (bits [16:0]) can be masked by masking the appropriate bit in the eth_dmaier register. bits 31:0 srl: start of receive list this field contains the base address of the firs t descriptor in the receive descriptor list. the lsb bits [1/2/3:0] for 32/64/128-bit bus width) are internally ignored and taken as all-zero by the dma. hence these lsb bits are read only. 313029282726252423222120191817161514131211109876543210 stl rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:0 stl: start of transmit list this field contains the base address of the first descriptor in the transmit descriptor list. the lsb bits [1/2/3:0] for 32/64/128-bit bus width) are internally ignored and taken as all-zero by the dma. hence these lsb bits are read-only. 313029282726252423222120191817161514131211109876543210 reserved tsts pmts mmcs reserved ebs tps rps nis ais ers fbes reserved ets rwts rpss rbus rs tus ros tjts tbus tpss ts rrr rrrrrrrrr rc- w1 rc- w1 rc- w1 rc- w1 rc- w1 rc- w1 rc- w1 rc- w1 rc- w1 rc- w1 rc- w1 rc- w1 rc- w1 rc- w1 rc- w1 bits 31:30 reserved bit 29 tsts: time stamp trigger status this bit indicates an interrupt event in the mac core's time stamp generator block. the software must read the mac core?s status register, clearing its source (bit 9), to reset this bit to 0. when this bit is high an interrupt is generated if enabled. ethernet (eth): media access control (mac) with dma controller RM0033 910/1317 doc id 15403 rev 3 bit 28 pmts: pmt status this bit indicates an event in the mac core?s pmt. the software must read the corresponding registers in the mac core to get the exact cause of interrupt and clear its so urce to reset this bit to 0. the interrupt is generated when this bit is high if enabled. bit 27 mmcs: mmc status this bit reflects an event in the mmc of the mac core. the software must read the corresponding registers in the mac core to get the exact cause of interrupt and clear the source of interrupt to make this bit as 0. the interrupt is generated when this bit is high if enabled. bit 26 reserved bits 25:23 ebs: error bits status these bits indicate the type of error that caused a bus error (error response on the ahb interface). valid only with the fatal bus error bit (eth_dmasr register [13]) set. this field does not generate an interrupt. bit 23 1 error during data transfer by txdma 0 error during data transfer by rxdma bit 24 1 error during read transfer 0 error during write transfer bit 25 1 error during descriptor access 0 error during data buffer access bits 22:20 tps: transmit process state these bits indicate the transmit dma fsm state. this field does not generate an interrupt. 000: stopped; reset or stop transmit command issued 001: running; fetching transmit transfer descriptor 010: running; waiting for status 011: running; reading data from host memory buffer and queuing it to transmit buffer (tx fifo) 100, 101: reserved for future use 110: suspended; transmit descriptor unavailable or transmit buffer underflow 111: running; closing transmit descriptor bits 19:17 rps: receive process state these bits indicate the receive dma fsm state. this field does not generate an interrupt. 000: stopped: reset or st op receive command issued 001: running: fetching receive transfer descriptor 010: reserved for future use 011: running: waiting for receive packet 100: suspended: receive descriptor unavailable 101: running: closing receive descriptor 110: reserved for future use 111: running: transferring the receive packet data from receive buffer to host memory RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 911/1317 bit 16 nis: normal interrupt summary the normal interrupt summary bit value is the logical or of the following when the corresponding interrupt bits are enabled in the eth_dmaier register: ? eth_dmasr [0]: transmit interrupt ? eth_dmasr [2]: transmit buffer unavailable ? eth_dmasr [6]: receive interrupt ? eth_dmasr [14]: early receive interrupt only unmasked bits affect the normal interrupt summary bit. this is a sticky bit and it must be cleared (by writing a 1 to this bit) each time a corresponding bit that causes nis to be set is cleared. bit 15 ais: abnormal interrupt summary the abnormal interrupt summary bit value is the logical or of the following when the corresponding interrupt bits are enabled in the eth_dmaier register: ? eth_dmasr [1]:transmit process stopped ? eth_dmasr [3]:transmit jabber timeout ? eth_dmasr [4]: receive fifo overflow ? eth_dmasr [5]: transmit underflow ? eth_dmasr [7]: receive buffer unavailable ? eth_dmasr [8]: receive process stopped ? eth_dmasr [9]: receive watchdog timeout ? eth_dmasr [10]: early transmit interrupt ? eth_dmasr [13]: fatal bus error only unmasked bits affect the abnormal interrupt summary bit. this is a sticky bit and it must be cleared each time a corresponding bit that causes ais to be set is cleared. bit 14 ers: early receive status this bit indicates that the dma had filled the firs t data buffer of the packet. receive interrupt eth_dmasr [6] automatically clears this bit. bit 13 fbes: fatal bus error status this bit indicates that a bus error occurred, as detailed in [25:23]. when this bit is set, the corresponding dma engine disables all its bus accesses. bits 12:11 reserved bit 10 ets: early transmit status this bit indicates that the frame to be transmi tted was fully transferred to the transmit fifo. bit 9 rwts: receive watchdog timeout status this bit is asserted when a frame with a length greater than 2 048 bytes is received. bit 8 rpss: receive process stopped status this bit is asserted when the receive process enters the stopped state. bit 7 rbus: receive buffer unavailable status this bit indicates that the next descriptor in the receive list is owned by the host and cannot be acquired by the dma. receive process is suspended. to resume processing receive descriptors, the host should change the ownership of the descriptor and issue a receive poll demand command. if no receive poll demand is issued, receive process resumes when the next recognized incoming frame is received. et h_dmasr [7] is set only when the previous receive descriptor was owned by the dma. ethernet (eth): media access control (mac) with dma controller RM0033 912/1317 doc id 15403 rev 3 ethernet dma operation mode register (eth_dmaomr) address offset: 0x1018 reset value: 0x0000 0000 the operation mode register establishes the transmit and receive operating modes and commands. the eth_dmaomr register should be the last csr to be written as part of dma initialization. bit 6 rs: receive status this bit indicates the completion of the frame re ception. specific frame status information has been posted in the descriptor. reception remains in the running state. bit 5 tus: transmit underflow status this bit indicates that the transmit buffer had an underflow during frame transmission. transmission is suspended and an underflow error tdes0[1] is set. bit 4 ros: receive overflow status this bit indicates that the receive buffer had an overflow during frame reception. if the partial frame is transferred to the application, t he overflow status is set in rdes0[11]. bit 3 tjts: transmit jabber timeout status this bit indicates that the transmit jabber time r expired, meaning that the transmitter had been excessively active. the transmission process is abo rted and placed in the stopped state. this causes the transmit jabber timeout tdes0[14] flag to be asserted. bit 2 tbus: transmit buffer unavailable status this bit indicates that the next descriptor in the transmit list is owned by the host and cannot be acquired by the dma. transmission is suspended. bits [22:20] explain the transmit process state transitions. to resume processing trans mit descriptors, the host should change the ownership of the bit of the descriptor and then issue a transmit poll demand command. bit 1 tpss: transmit process stopped status this bit is set when the transmission is stopped. bit 0 ts: transmit status this bit indicates that frame transmission is fini shed and tdes1[31] is set in the first descriptor. 313029282726252423222120191817161514131211109876543210 reserved dtcefd rsf dfrf reserved tsf ftf reserved ttc st reserved fef fugf reserved rtc osf sr reserved rw rw rw rw rs rw rw rw rw rw rw rw rw rw rw bits 31:27 reserved bit 26 dtcefd: dropping of tcp/ip checksum error frames disable when this bit is set, the core does not drop frames that only have errors detected by the receive checksum offload engine. such frames do not have any errors (including fcs error) in the ethernet frame received by the mac but ha ve errors in the encapsulated payload only. when this bit is cleared, all error fr ames are dropped if the fef bit is reset. bit 25 rsf: receive store and forward when this bit is set, a frame is read from the rx fifo after the complete frame has been written to it, ignoring rtc bits. when this bit is cleared, the rx fifo operates in cut-through mode, subject to the threshold specified by the rtc bits. RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 913/1317 bit 24 dfrf: disable flushing of received frames when this bit is set, the rxdma does not flush any frames due to the unavailability of receive descriptors/buffers as it does normally when this bit is cleared. (see receive process suspended on page 860 ) bits 23:22 reserved bit 21 tsf: transmit store and forward when this bit is set, transmission starts when a full frame resides in the transmit fifo. when this bit is set, the ttc values specified by th e eth_dmaomr register bits [16:14] are ignored. when this bit is cleared, the ttc values spec ified by the eth_dmaomr register bits [16:14] are taken into account. this bit should be changed only when transmission is stopped. bit 20 ftf: flush transmit fifo when this bit is set, the transmit fifo controller logic is reset to its default values and thus all data in the tx fifo are lost/flushe d. this bit is cleared internally when the flushing operation is complete. the operation mode register should no t be written to until this bit is cleared. bits 19:17 reserved bits 16:14 ttc: transmit threshold control these three bits control the threshold level of the transmit fifo. transm ission starts when the frame size within the transmit fifo is larger th an the threshold. in addit ion, full frames with a length less than the threshold are also transmitted. these bits are used only when the tsf bit (bit 21) is cleared. 000: 64 001: 128 010: 192 011: 256 100: 40 101: 32 110: 24 111: 16 bit 13 st: start/stop transmission when this bit is set, transmission is placed in the running state, and the dma checks the transmit list at the current position for a frame to be transmitted. descriptor acquisition is attempted either from the current position in the list, which is the transmit list base address set by the eth_dmatdlar register, or from t he position retained when transmission was stopped previously. if the current descriptor is not owned by the dma, transmission enters the suspended state and the transmit buffer unavaila ble bit (eth_dmasr [2]) is set. the start transmission command is effective only when tr ansmission is stopped. if the command is issued before setting the dma eth_dmatdlar r egister, the dma behavi or is unpredictable. when this bit is cleared, the transmission process is placed in the stopped state after completing the transmission of the current frame. the next descriptor position in the transmit list is saved, and becomes the current positi on when transmission is restarted. the stop transmission command is effective only when the transmission of the current frame is complete or when the transmission is in the suspended state. bits 12:8 reserved ethernet (eth): media access control (mac) with dma controller RM0033 914/1317 doc id 15403 rev 3 bit 7 fef: forward error frames when this bit is set, all frames except runt error frames are forwarded to the dma. when this bit is cleared, the rx fifo drops fram es with error status (crc error, collision error, giant frame, watchdog timeout, overflow). however, if the frame?s start byte (write) pointer is already transferred to the read controller side (in threshold mode), then the frames are not dropped. the rx fifo drops the error frames if that frame's start byte is not transferred (output) on the ari bus. bit 6 fugf: forward undersized good frames when this bit is set, the rx fifo forwards und ersized frames (frames with no error and length less than 64 bytes) including pad-bytes and crc). when this bit is cleared, the rx fifo drops al l frames of less than 64 bytes, unless such a frame has already been transferred due to lower value of receive threshold (e.g., rtc = 01). bit 5 reserved bits 4:3 rtc: receive threshold control these two bits control the threshold level of the receive fifo. transfer (request) to dma starts when the frame size within the receive fifo is larger than the threshold. in addition, full frames with a length less than the threshold are transferred automatically. note: note that value of 11 is not applicable if the configured receive fifo size is 128 bytes. note: these bits are valid only when the rsf bit is zero, and are ignored when the rsf bit is set to 1. 00: 64 01: 32 10: 96 11: 128 bit 2 osf: operate on second frame when this bit is set, this bit instructs the dm a to process a second frame of transmit data even before status for first frame is obtained. bit 1 sr: start/stop receive when this bit is set, the receive process is pl aced in the running state. the dma attempts to acquire the descriptor from the receive list and processes incoming frames. descriptor acquisition is attempted from the current position in the list, which is the address set by the dma eth_dmardlar register or the position retained when the receive process was previously stopped. if no descriptor is owned by the dma, reception is suspended and the receive buffer unavailable bit (eth_dmasr [7]) is set. the start receive command is effective only when reception has stopped. if the command was issued before setting the dma eth_dmardlar register, the dm a behavior is unpredictable. when this bit is cleared, rxdma operation is stopped after the transfer of the current frame. the next descriptor position in the receive list is saved and becomes the current position when the receive process is restarted. the stop re ceive command is effective only when the receive process is in either the running (wai ting for receive packet) or the suspended state. bit 0 reserved RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 915/1317 ethernet dma interrupt enable register (eth_dmaier) address offset: 0x101c reset value: 0x0000 0000 the interrupt enable register enables the interrupts reported by eth_dmasr. setting a bit to 1 enables a corresponding interrupt. after a hardware or software reset, all interrupts are disabled. 313029282726252423222120191817161514131211109876543210 reserved nise aise erie fbeie reserved etie rwtie rpsie rbuie rie tuie roie tjtie tbuie tpsie tie rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:17 reserved bit 16 nise: normal interrupt summary enable when this bit is set, a normal interrupt is enabled. when this bit is cleared, a normal interrupt is disabled. this bit enables the following bits: ? eth_dmasr [0]: transmit interrupt ? eth_dmasr [2]: transmit buffer unavailable ? eth_dmasr [6]: receive interrupt ? eth_dmasr [14]: early receive interrupt bit 15 aise: abnormal interrupt summary enable when this bit is set, an abnormal interrupt is enabled. when this bit is cleared, an abnormal interrupt is disabled. this bit enables the following bits: ? eth_dmasr [1]: transmit process stopped ? eth_dmasr [3]: transmit jabber timeout ? eth_dmasr [4]: receive overflow ? eth_dmasr [5]: transmit underflow ? eth_dmasr [7]: receive buffer unavailable ? eth_dmasr [8]: receive process stopped ? eth_dmasr [9]: receive watchdog timeout ? eth_dmasr [10]: early transmit interrupt ? eth_dmasr [13]: fatal bus error bit 14 erie: early receive interrupt enable when this bit is set with the normal interrupt summary enable bit (eth_dmaier register[16]), the early receive interrupt is enabled. when this bit is cleared, the early receive interrupt is disabled. bit 13 fbeie: fatal bus error interrupt enable when this bit is set with the abnormal interrupt summary enable bit (eth_dmaier register[15]), the fatal bus error interrupt is enabled. when this bit is cleared, the fatal bus error enable interrupt is disabled. bits 12:11 reserved bit 10 etie: early transmit interrupt enable when this bit is set with the abnormal interrupt summary enable bit (eth_dmaier register [15]), the early transmit interrupt is enabled. when this bit is cleared, the early transmit interrupt is disabled. ethernet (eth): media access control (mac) with dma controller RM0033 916/1317 doc id 15403 rev 3 the ethernet interrupt is generated only when the tsts or pmts bits of the dma status register is asserted with their corresponding interrupt are unmasked, or when the nis/ais status bit is asserted and the corresponding interrupt enable bits (nise/aise) are enabled. bit 9 rwtie: receive watchdog timeout interrupt enable when this bit is set with the abnormal interrupt summary enable bit (eth_dmaier register[15]), the receive watchd og timeout interrupt is enabled. when this bit is cleared, the receive watchdog timeout interrupt is disabled. bit 8 rpsie: receive process stopped interrupt enable when this bit is set with the abnormal interrupt summary enable bit (eth_dmaier register[15]), the receive stopped interrupt is enabled. when this bit is cleared, the receive stopped interrupt is disabled. bit 7 rbuie: receive buffer unavailable interrupt enable when this bit is set with the abnormal interrupt summary enable bit (eth_dmaier register[15]), the receive buffer unavailable interrupt is enabled. when this bit is cleared, the receive buffer unavailable interrupt is disabled. bit 6 rie: receive interrupt enable when this bit is set with the normal interrupt summary enable bit (eth_dmaier register[16]), the receive interrupt is enabled. when this bit is cleared, the receive interrupt is disabled. bit 5 tuie: underflow interrupt enable when this bit is set with the abnormal interrupt summary enable bit (eth_dmaier register[15]), the transmit underflow interrupt is enabled. when this bit is cleared, the underflow interrupt is disabled. bit 4 roie: overflow interrupt enable when this bit is set with the abnormal interrupt summary enable bit (eth_dmaier register[15]), the receive overflow interrupt is enabled. when this bit is cleared, the overflow interrupt is disabled. bit 3 tjtie: transmit jabber timeout interrupt enable when this bit is set with the abnormal interrupt summary enable bit (eth_dmaier register[15]), the transmit jabber timeout interrupt is enabled. when this bit is cleared, the transmit jabber timeout interrupt is disabled. bit 2 tbuie: transmit buffer unavailable interrupt enable when this bit is set with the normal interrupt summary enable bit (eth_dmaier register[16]), the transmit buffer unavailable interrupt is enabled. when this bit is cleared, the transmit buffer unavailable interrupt is disabled. bit 1 tpsie: transmit process stopped interrupt enable when this bit is set with the abnormal interrupt summary enable bit (eth_dmaier register[15]), the transmission stopped interrupt is enabled. when this bit is cleared, the transmission stopped interrupt is disabled. bit 0 tie: transmit interrupt enable when this bit is set with the normal interrupt summary enable bit (eth_dmaier register[16]), the transmit interrupt is enabled. when this bit is cleared, the tr ansmit interrupt is disabled. RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 917/1317 ethernet dma missed frame and buffer overflow counter register (eth_dmamfbocr) address offset: 0x1020 reset value: 0x0000 0000 the dma maintains two counters to track the number of missed frames during reception. this register reports the current value of the counter. the counter is used for diagnostic purposes. bits [15:0] indicate missed frames due to the stm32f20x and stm32f21x buffer being unavailable (no receive descriptor was available). bits [27:17] indicate missed frames due to rx fifo overflow conditions and runt frames (good frames of less than 64 bytes). ethernet dma receive status watchdog timer register (eth_dmarswtr) address offset: 0x1024 reset value: 0x0000 0000 this register, when written with a non-zero value, enables the watchdog timer for the receive status (rs, eth_dmasr[6]). 313029282726252423222120191817161514131211109876543210 reserved ofoc mfa omfc mfc rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r rc_ r bits 31:29 reserved bit 28 ofoc: overflow bit for fifo overflow counter bits 27:17 mfa: missed frames by the application indicates the number of frames missed by the application bit 16 omfc: overflow bit for missed frame counter bits 15:0 mfc: missed frames by the controller indicates the number of frames missed by the co ntroller due to the host receive buffer being unavailable. this counter is incremented each time the dma discards an incoming frame. 313029282726252423222120191817161514131211109876543210 reserved rswtc rw rw rw rw rw rw rw rw bits 31:8 reserved bits 7:0 rswtc: receive status (rs) watchdog timer count indicates the number of hclk clock cycles mult iplied by 256 for which the watchdog timer is set. the watchdog timer gets triggered with the programmed value after the rxdma completes the transfer of a frame for which the rs status bit is not set due to the setting of rdes1[31] in the corresponding descriptor. wh en the watchdog timer runs out, the rs bit is set and the timer is stopped. the watchdog timer is reset when the rs bit is set high due to automatic setting of rs as per rdes1[31] of any received frame. ethernet (eth): media access control (mac) with dma controller RM0033 918/1317 doc id 15403 rev 3 ethernet dma current host transmit descriptor register (eth_dmachtdr) address offset: 0x1048 reset value: 0x0000 0000 the current host transmit descriptor register points to the start address of the current transmit descriptor read by the dma. 313029282726252423222120191817161514131211109876543210 htdap rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr bits 31:0 htdap: host transmit descriptor address pointer cleared on reset. pointer updated by dma during operation. RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 919/1317 ethernet dma current host receive descriptor register (eth_dmachrdr) address offset: 0x104c reset value: 0x0000 0000 the current host receive descriptor register points to the start address of the current receive descriptor read by the dma. ethernet dma current host transmit buffer address register (eth_dmachtbar) address offset: 0x1050 reset value: 0x0000 0000 the current host transmit buffer address register points to the current transmit buffer address being read by the dma. ethernet dma current host receive buffer address register (eth_dmachrbar) address offset: 0x1054 reset value: 0x0000 0000 the current host receive buffer address register points to the current receive buffer address being read by the dma. 313029282726252423222120191817161514131211109876543210 hrdap rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr bits 31:0 hrdap: host receive descriptor address pointer cleared on reset. pointer updated by dma during operation. 313029282726252423222120191817161514131211109876543210 htbap rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr bits 31:0 htbap: host transmit buffer address pointer cleared on reset. pointer updated by dma during operation. 313029282726252423222120191817161514131211109876543210 hrbap rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr bits 31:0 hrbap: host receive buffer address pointer cleared on reset. pointer updated by dma during operation. ethernet (eth): media access control (mac) with dma controller RM0033 920/1317 doc id 15403 rev 3 28.8.5 ethernet register maps table 147 gives the eth register map and reset values. table 147. ethernet register map and reset values offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 eth_maccr reserved cstf eserved wd jd reserved ifg csd reserved fes rod lm dm ipco rd reserved apcs bl dc te re reserved reset value 0 00 0000 000000 00 0000 0x04 eth_macff r ra reserved hpf saf pcf bfd pa m daif hm hu pm reset value 0 00000 000000 0x08 eth_macht hr hth[31:0] reset value 00000000000000000000000000 000000 0x0c eth_macht lr htl[31:0] reset value 00000000000000000000000000 000000 0x10 eth_macmii ar reserved pa m r cr m w m b reset value 0000000000 000000 0x14 eth_macmii dr reserved md reset value 0000000000 000000 0x18 eth_macfc r pt reserved zqpd reserved plt upfd rfce tfce fcb/bpa reset value 0000000000000000 0 000000 0x1c eth_macvl antr reserved vlantc vlanti reset value 00000000000 000000 0x28 eth_macrw uffr frame filter reg0\frame filter reg1\frame filter reg2\frame filter reg3\frame filter reg4\...\frame filter reg7 reset value 0 0x2c eth_macpm tcsr wffrpr reserved gu reserved wfr mpr reserved wfe mpe pd reset value 0 0 0 0 000 0x34 eth_macdb gr reserved tff tfnegu reserved tfwa tfrs mtp mtfcs mmtea reserved rffl reserved rfrcs rfwra reserved msfrwcs mmrpea reset value 0 0 0000000 00 0 00 000 0x38 eth_macsr reserved tsts reserved mmcts mmcrs mmcs pmts reserved reset value 00000 0x3c eth_macim r reserved tstim reserved pmtim reserved reset value 00 0x40 eth_maca0 hr mo reserved maca0h reset value 10000000000000001111111111 111111 0x44 eth_maca0 lr maca0l reset value 11111111111111111111111111 111111 0x48 eth_maca1 hr ae sa mbc[6:0] reserved maca1h reset value 00000000 1111111111 111111 0x4c eth_maca1 lr maca1l reset value 11111111111111111111111111 111111 RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 921/1317 0x50 eth_maca2 hr ae sa mbc reserved maca2h reset value 00000000 1111111111 111111 0x54 eth_maca2 lr maca2l reset value 11111111111111111111111111 111111 0x58 eth_maca3 hr ae sa mbc reserved maca3h reset value 00000000 1111111111 111111 0x5c eth_maca3 lr maca3l reset value 11111111111111111111111111 111111 0x100 eth_mmccr reserved mcfhp mcp mcf ror csr cr reset value 000000 0x104 eth_mmcri r reserved rgufs reserved rfaes rfces reserved reset value 0 0 0 0x108 eth_mmcti r reserved tgfs reserved tgfmscs tgfscs reserved reset value 0 0 0 0x10c eth_mmcri mr reserved rgufm reserved rfaem rfcem reserved reset value 0 0 0 0x110 eth_mmcti mr reserved tgfm reserved tgfmscm tgfscm reserved reset value 0 0 0 0x14c eth_mmctg fsccr tgfscc reset value 00000000000000000000000000 000000 0x150 eth_mmctg fmsccr tgfmscc reset value 00000000000000000000000000 000000 0x168 eth_mmctg fcr tgfc reset value 00000000000000000000000000 000000 0x194 eth_mmcrf cecr rfcec reset value 00000000000000000000000000 000000 0x198 eth_mmcrf aecr rfaec reset value 00000000000000000000000000 000000 0x1c4 eth_mmcr gufcr rgufc reset value 00000000000000000000000000 000000 0x700 eth_ptpts cr reserved tspffmae tscnt tssmrme tsseme tssipv4fe tssipv6fe tssptpoefe tsptppsv2e tsssr tssarfe reserved ttsaru tsite tsstu tssti tsfcu tse reset value 00000100000 000000 0x704 eth_ptpssi r reserved stssi reset value 00 000000 0x708 eth_ptpts hr sts[31:0] reset value 00000000000000000000000000 000000 table 147. ethernet register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ethernet (eth): media access control (mac) with dma controller RM0033 922/1317 doc id 15403 rev 3 0x70c eth_ptptsl r stpns stss reset value 00000000000000000000000000 000000 0x710 eth_ptpts hur tsus reset value 00000000000000000000000000 000000 0x714 eth_ptptsl ur tsupns tsuss reset value 00000000000000000000000000 000000 0x718 eth_ptpts ar tsa reset value 00000000000000000000000000 000000 0x71c eth_ptptt hr ttsh reset value 00000000000000000000000000 000000 0x720 eth_ptpttl r ttsl reset value 00000000000000000000000000 000000 0x728 eth_ptpts sr reserved tsttr tsso reset value 00 0x1000 eth_dmabm r reserved mb aab fpm usp rdp fb rtpr pbl edfe dsl da sr reset value 000000000100000000100 000001 0x1004 eth_dmatp dr tpd reset value 00000000000000000000000000 000000 0x1008 eth_dmarp dr rpd reset value 00000000000000000000000000 000000 0x100c eth_dmard lar srl reset value 00000000000000000000000000 000000 0x1010 eth_dmatd lar stl reset value 00000000000000000000000000 000000 0x1014 eth_dmasr reserved tsts pmts mmcs reserved ebs tps rps nis ais ers fbes reserved ets rwts rpss rbus rs tus ros tjts tbus tpss ts reset value 000 0000000000000 00000 000000 0x1018 eth_dmaom r reserved dtcefd rsf dfrf reserved tsf ftf reserved ttc st reserved fef fugf reserved rtc osf sr reserved reset value 000 00 0000 00 0000 0x101c eth_dmaie r reserved nise aise erie fbeie reserved etie rwtie rpsie rbuie rie tuie roie tjtie tbuie tpsie tie reset value 0000 00000 000000 0x1020 eth_dmamf bocr reserved ofoc mfa omfc mfc reset value 00000000000000000000000 000000 0x1024 eth_dmars wtr reserved rswtc reset value 00 000000 0x1048 eth_dmach tdr htdap reset value 00000000000000000000000000 000000 0x104c eth_dmach rdr hrdap reset value 00000000000000000000000000 000000 0x1050 eth_dmach tbar htbap reset value 00000000000000000000000000 000000 table 147. ethernet register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RM0033 ethernet (eth): media access control (mac) with dma controller doc id 15403 rev 3 923/1317 refer to table 1 on page 50 for the register boundary addresses. 0x1054 eth_dmach rbar hrbap reset value 00000000000000000000000000 000000 table 147. ethernet register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 usb on-the-go full-speed (otg_fs) RM0033 924/1317 doc id 15403 rev 3 29 usb on-the-go full-speed (otg_fs) 29.1 otg_fs introduction portions copyright (c) 2004, 2005 synopsys, inc. all rights reserved. used with permission. this section presents the architecture and the programming model of the otg_fs controller. the following acronyms are used throughout the section: references are made to the following documents: usb on-the-go supplement, revision 1.3 universal serial bus revision 2.0 specification the otg_fs is a dual-role device (drd) controller that supports both device and host functions and is fully compliant with the on-the-go supplement to the usb 2.0 specification . it can also be configured as a host-only or device-only controller, fully compliant with the usb 2.0 specification. in host mode, the otg_fs supports full-speed (fs, 12 mbits/s) and low-speed (ls, 1.5 mbits/s) transfers whereas in device mode, it only supports full-speed (fs, 12 mbits/s) transfers. the otg_fs supports both hnp and srp. the only external device required is a charge pump for v bus in host mode. fs full-speed ls low-speed mac media access controller otg on-the-go pfc packet fifo controller phy physical layer usb universal serial bus utmi usb 2.0 transceiver ma crocell interface (utmi) RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 925/1317 29.2 otg_fs main features the main features can be divided into three categories: general, host-mode and device- mode features. 29.2.1 general features the otg_fs interface general features are the following: it is usb-if certified to the univer sal serial bus specification rev 2.0 it includes full support (phy) for the optional on-the-go (otg) protocol detailed in the on-the-go supplement rev 1.3 specification ? integrated support for a-b device identification (id line) ? integrated support for host negotiation protocol (hnp) and session request protocol (srp) ? it allows host to turn v bus off to conserve battery power in otg applications ? it supports otg monitoring of v bus levels with internal comparators ? it supports dynamic host-peripheral switch of role it is software-configurable to operate as: ? srp capable usb fs peripheral (b-device) ? srp capable usb fs/ls host (a-device) ? usb on-the-go full-spee d dual role device it supports fs sof and ls keep-alives with ? sof pulse pad connectivity ? sof pulse internal connection to timer2 (tim2) ? configurable framing period ? configurable end of frame interrupt it includes power saving features such as system stop during usb suspend, switch-off of clock domains internal to the digital core, phy and dfifo power management it features a dedicated ram of 1.25 kbytes with advanced fifo control: ? configurable partitioning of ram space into different fifos for flexible and efficient use of ram ? each fifo can hold multiple packets ? dynamic memory allocation ? configurable fifo sizes that are not powers of 2 to allow the use of contiguous memory locations it guarantees max usb bandwidth for up to one frame (1ms) without system intervention usb on-the-go full-speed (otg_fs) RM0033 926/1317 doc id 15403 rev 3 29.2.2 host-mode features the otg_fs interface main features and requirements in host-mode are the following: external charge pump for v bus voltage generation. up to 8 host channels (pipes): each channel is dynamically reconfigurable to allocate any type of usb transfer. built-in hardware scheduler holding: ? up to 8 interrupt plus isochronous transfer requests in the periodic hardware queue ? up to 8 control plus bulk transfer requests in the non-periodic hardware queue management of a shared rx fifo, a periodic tx fifo and a nonperiodic tx fifo for efficient usage of the usb data ram. 29.2.3 peripheral-mode features the otg_fs interface main features in peripheral-mode are the following: 1 bidirectional control endpoint0 3 in endpoints (eps) configurable to support bulk, interrupt or isochronous transfers 3 out endpoints configurable to support bulk, interrupt or isochronous transfers management of a shared rx fifo and a tx-out fifo for efficient usage of the usb data ram management of up to 4 dedicated tx-in fifos (one for each active in ep) to put less load on the application support for the soft disconnect feature. RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 927/1317 29.3 otg_fs functional description figure 348. block diagram 29.3.1 otg full-speed core the usb otg fs receives the 48 mhz 0.25% clock from the reset and clock controller (rcc), via an external quartz. the usb clock is used for driving the 48 mhz domain at full- speed (12 mbit/s) and must be enabled prior to configuring the otg fs core. the cpu reads and writes from/to the otg fs core registers through the ahb peripheral bus. it is informed of usb events through the single usb otg interrupt line described in section 29.15: otg_fs interrupts . the cpu submits data over the usb by writing 32-bit words to dedicated otg_fs locations (push registers). the data are then automatically stored into tx-data fifos configured within the usb data ram. there is one tx-fifo push register for each in-endpoint (peripheral mode) or out-channel (host mode). the cpu receives the data from the usb by reading 32-bit words from dedicated otg_fs addresses (pop registers). the data are then automatically retrieved from a shared rx-fifo configured within the 1.25 kb usb data ram. there is one rx-fifo pop register for each out-endpoint or in-channel. the usb protocol layer is driven by the serial interface engine (sie) and serialized over the usb by the full-/low-speed transceiver module within the on-chip physical layer (phy). 29.3.2 full-speed otg phy the embedded full-speed otg phy is controlled by the otg fs core and conveys usb control & data signals through the full-speed subset of the utmi+ bus (utmifs). it provides dp dm id v bu s otg f s phy u s b2.0 otg f s core utmif s 1.25 k b yte s u s b d a t a fifo s ahb peripher a l power& clock ctrl u s b interr u pt u s b d us pend u s b clock a t 4 8 mhz cortex-m 3 s y s tem clock dom a in u s b clock dom a in univer sa l s eri a l bus ram bus a i17106 usb on-the-go full-speed (otg_fs) RM0033 928/1317 doc id 15403 rev 3 the physical support to usb connectivity. the full-speed otg phy includes the following components: fs/ls transceiver module used by both host and device. it directly drives transmission and reception on the single-ended usb lines. integrated id pull-up resistor used to sample the id line for a/b device identification. dp/dm integrated pull-up and pull-down resistors controlled by the otg_fs core depending on the current role of the device. as a peripheral, it enables the dp pull-up resistor to signal full-speed peripheral connections as soon as v bus is sensed to be at a valid level (b-session valid). in host mode, pull-down resistors are enabled on both dp/dm. pull-up and pull-down resistors are dynamically switched when the device?s role is changed via the host negotiation protocol (hnp). pull-up/pull-down resistor ecn circuit. the dp pull-up consists of 2 resistors controlled separately from the otg_fs as per the resistor engineering change notice applied to usb rev2.0. the dynamic trimming of the dp pull-up strength allows for better noise rejection and tx/rx signal quality. v bus sensing comparators with hysteresis used to detect v bus valid, a-b session valid and session-end voltage thresholds. they are used to drive the session request protocol (srp), detect valid startup and end-of-session conditions, and constantly monitor the v bus supply during usb operations. v bus pulsing method circuit used to charge/discharge v bus through resistors during the srp (weak drive). caution: to guarantee a correct operation for the usb otg fs peripheral, the ahb frequency should be higher than 14.2 mhz. 29.4 otg dual role device (drd) figure 349. otg a-b device connection 1. external voltage regulator only needed when building a v bus powered device 2. stmps2141str needed only if the application has to support a v bus powered device. a basic power switch can be used if 5 v are available on the application board. 3. v dd range is between 2 v and 3.6 v. 3 4 - & x 3 4 - & x 3 4 - 0 3 3 4 2 # u r r e n t l i m i t e d p o w e r d i s t r i b u t i o n s w i t c h 6 $ $ 6 " 5 3 $ 0 6 3 3 0 ! 0 ! 0 ! 5 3 " m i c r o ! " c o n n e c t o r $ - ' 0 ) / ) 2 1 ' 0 ) / % . / v e r c u r r e n t 6 0 w r 6 t o 6 $ $ v o l t a g e r e g u l a t o r 6 $ $ ) $ 0 ! / 3 # ? ) . / 3 # ? / 5 4 a i RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 929/1317 29.4.1 id line detection the host or peripheral (the default) role is assumed depending on the id input pin. the id line status is determined on plugging in the usb, depending on which side of the usb cable is connected to the micro-ab receptacle. if the b-side of the usb cable is connected with a floating id wire, the integrated pull-up resistor detects a high id level and the default peripheral role is confirmed. in this configuration the otg_fs complies with the standard fsm described by section 6.8.2: on-the-go b-device of the on-the-go specification rev1.3 supplement to the usb2.0. if the a-side of the usb cable is connected with a grounded id, the otg_fs issues an id line status change interrupt (cidschg bit in otg_fs_gintsts) for host software initialization, and auto matically switches to the host role. in this configuration the otg_fs complies with the standard fsm described by section 6.8.1: on-the-go a- device of the on-the-go specification rev1.3 supplement to the usb2.0. 29.4.2 hnp dual role device the hnp capable bit in the global usb configuration register (hnpcap bit in otg_fs_ gusbcfg) enables the otg_fs core to dynamically change its role from a-host to a- peripheral and vice-versa, or from b-peripheral to b-host and vice-versa according to the host negotiation protocol (hnp). the current device status can be read by the combined values of the connector id status bit in the global otg control and status register (cidsts bit in otg_fs_gotgctl) and the current mode of operation bit in the global interrupt and status register (cmod bit in otg_fs_gintsts). the hnp program model is described in detail in section 29.17: otg_fs programming model . 29.4.3 srp dual role device the srp capable bit in the global usb configuration register (srpcap bit in otg_fs_gusbcfg) enables the otg_fs core to switch off the generation of v bus for the a-device to save power. note that the a-device is always in charge of driving v bus regardless of the host or peripheral role of the otg_fs. the srp a/b-device program model is described in detail in section 29.17: otg_fs programming model . usb on-the-go full-speed (otg_fs) RM0033 930/1317 doc id 15403 rev 3 29.5 usb peripheral this section gives the functional description of the otg_fs in the usb peripheral mode. the otg_fs works as an usb peripheral in the following circumstances: otg b-peripheral ? otg b-device default state if b-side of usb cable is plugged in otg a-peripheral ? otg a-device state after the hnp switches the otg_fs to its peripheral role b-device ? if the id line is present, functional and connected to the b-side of the usb cable, and the hnp-capable bit in the global usb configuration register (hnpcap bit in otg_fs_gusbcfg) is cleared (see on-the-go rev1.3 par. 6.8.3). peripheral only (see figure 350: usb peripheral-only connection ) ? the force device mode bit in the global usb configuration register (fdmod in otg_fs_gusbcfg) is set to 1, forcing the otg_fs core to work as a usb peripheral-only (see on-the-go rev1.3 par. 6.8.3). in this case, the id line is ignored even if present on the usb connector. note: 1 to build a bus-powered device implementation in case of the b-device or peripheral-only configuration, an external regulator has to be added that generates the v dd chip-supply from v bus . 2the v bus pin can be freed by disabling the v bus sensing option. this is done by setting the novbussens bit in the otg_fs_gccfg register. in this case the v bus is considered internally to be always at v bus valid level (5 v). figure 350. usb peripheral-only connection 1. use a regulator to build a bus-powered device. 2. v dd range between 2 v and 3.6 v. 29.5.1 srp-capable peripheral the srp capable bit in the global usb configuration register (srpcap bit in otg_fs_gusbcfg) enables the otg_fs to support the session request protocol (srp). 3 4 - & x 3 4 - & x 6 t o 6 $ $ 6 o l a t g e r e g u l a t o r 6 $ $ 6 " 5 3 $ 0 6 3 3 0 ! 0 ! 0 ! 5 3 " 3 t d " c o n n e c t o r $ - / 3 # ? ) . / 3 # ? / 5 4 a i RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 931/1317 in this way, it allows the remote a-de vice to save power by switching off v bus while the usb session is suspended. the srp peripheral mode program model is described in detail in the b-device session request protocol section. 29.5.2 peripheral states powered state the v bus input detects the b-session valid voltage by which the usb peripheral is allowed to enter the powered state (see usb2.0 par9.1). the otg_fs then automatically connects the dp pull-up resistor to signal full-speed device connection to the host and generates the session request interrupt (srqint bit in otg_fs_gintsts) to notify the powered state. the v bus input also ensures that valid v bus levels are supplied by the host during usb operations. if a drop in v bus below b-session valid happens to be detected (for instance because of a power disturbance or if the host port has been switched off), the otg_fs automatically disconnects and the session end detected (sedet bit in otg_fs_gotgint) interrupt is generated to notify that the otg_fs has exited the powered state. in the powered state, the otg_fs expects to receive some reset signaling from the host. no other usb operation is possible. when a reset signaling is received the reset detected interrupt (usbrst in otg_fs_gintsts) is generated. when the reset signaling is complete, the enumeration done interrup t (enumdne bit in otg_fs_gintsts) is generated and the otg_fs enters the default state. soft disconnect the powered state can be exited by software with the soft disconnect feature. the dp pull- up resistor is removed by setting the soft disconnect bit in the device control register (sdis bit in otg_fs_dctl), causing a device disconnect detection interrupt on the host side even though the usb cable was not really removed from the host port. default state in the default state the otg_fs expects to receive a set_address command from the host. no other usb operation is possible . when a valid set_address command is decoded on the usb, the application writes the corresponding number into the device address field in the device configuration register (dad bit in otg_fs_dcfg). the otg_fs then enters the address state and is ready to answer host transactions at the configured usb address. suspended state the otg_fs peripheral constantly monitors th e usb activity. after counting 3 ms of usb idleness, the early suspend interrupt (esusp bit in otg_fs_gintsts) is issued, and confirmed 3 ms later, if appropriate, by the suspend interrupt (usbsusp bit in otg_fs_gintsts). the device suspend bit is then automatically set in the device status register (suspsts bit in otg_fs_dsts) and the otg_fs enters the suspended state. the suspended state may optionally be exited by the device itself. in this case the application sets the remote wakeup signaling bit in the device control register (wkupint bit in otg_fs_dctl) and clears it after 1 to 15 ms. usb on-the-go full-speed (otg_fs) RM0033 932/1317 doc id 15403 rev 3 when a resume signaling is detected from the host, the resume interrupt (rwusig bit in otg_fs_gintsts) is generated and the devi ce suspend bit is automatically cleared. 29.5.3 peripheral endpoints the otg_fs core instantiates the following usb endpoints: control endpoint 0: ? bidirectional and handles control messages only ? separate set of registers to handle in and out transactions ? proper control (otg_fs_diepctl0/otg_fs_doepctl0), transfer configuration (otg_fs_dieptsiz0/otg_fs_dieptsiz0), and status-interrupt (otg_fs_diepintx/)otg_fs_doepint0) registers. the available set of bits inside the control and transfer size registers slightly differs from that of other endpoints 3 in endpoints ? each of them can be configured to support the isochronous, bulk or interrupt transfer type ? each of them has proper control (otg_fs_diepctl x ), transfer configuration (otg_fs_dieptsiz x ), and status-interrupt (otg_fs_diepint x ) registers ? the device in endpoints common interrupt mask register (otg_fs_diepmsk) is available to enable/disable a single kind of endpoint interrupt source on all of the in endpoints (ep0 included) ? support for incomplete isochronous in transfer interrupt (iisoixfr bit in otg_fs_gintsts), asserted when there is at least one isochronous in endpoint on which the transfer is not completed in the current frame. this interrupt is asserted along with the end of periodic frame interrupt (otg_fs_gintsts/eopf). 3 out endpoints ? each of them can be configured to support the isochronous, bulk or interrupt transfer type ? each of them has a proper control (otg_fs_doepctl x ), transfer configuration (otg_fs_doeptsiz x ) and status-interrupt (otg_fs_doepint x ) register ? device out endpoints common interrupt mask register (otg_fs_doepmsk) is available to enable/disable a single kind of endpoint interrupt source on all of the out endpoints (ep0 included) ? support for incomplete isochronous out transfer interrupt (incompisoout bit in otg_fs_gintsts), asserted when t here is at least one isochronous out endpoint on which the transfer is not completed in the current frame. this interrupt is asserted along with the end of periodic frame interrupt (otg_fs_gintsts/eopf). RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 933/1317 endpoint control the following endpoint controls are available to the application through the device endpoint- x in/out control register (diepctl x /doepctl x ): ? endpoint enable/disable ? endpoint activate in current configuration ? program usb transfer type (isochronous, bulk, interrupt) ? program supported packet size ? program tx-fifo number associated with the in endpoint ? program the expected or transmitted data0/data1 pid (bulk/interrupt only) ? program the even/odd frame during which the transaction is received or transmitted (isochronous only) ? optionally program the nak bit to always negative-acknowledge the host regardless of the fifo status ? optionally program the stall bit to alwa ys stall host tokens to that endpoint ? optionally program the snoop mode for out endpoint not to check the crc field of received data endpoint transfer the device endpoint- x transfer size registers (dieptsiz x /doeptsiz x ) allow the application to program the transfer size parameters and read the transfer status. programming must be done before setting the endpoint enable bit in the endpoint control register. once the endpoint is enabled, these fields are read- only as the otg fs core updates them with the current transfer status. the following transfer parameters can be programmed: transfer size in bytes number of packets that constitute the overall transfer size endpoint status/interrupt the device endpoint- x interrupt registers (diepint x /dopepint x) indicate the status of an endpoint with respect to usb- and ahb-related events. the application must read these registers when the out endpoint interrupt bit or the in endpoint interrupt bit in the core interrupt register (oepint bit in otg_fs_gintsts or iepint bit in otg_fs_gintsts, respectively) is set. before the application can read these registers, it must first read the device all endpoints interrupt (otg_fs_daint) register to get the exact endpoint number for the device endpoint- x interrupt register. the application must clear the appropriate bit in this register to clear the corresponding bits in the daint and gintsts registers usb on-the-go full-speed (otg_fs) RM0033 934/1317 doc id 15403 rev 3 the peripheral core provides the following status checks and interrupt generation: transfer completed interrupt, indicating that data transfer was completed on both the application (ahb) and usb sides setup stage has been done (control-out only) associated transmit fifo is half or completely empty (in endpoints) nak acknowledge has been transmitted to the host (isochronous-in only) in token received when tx-fifo was empty (bulk-in/interrupt-in only) out token received when endpoint was not yet enabled babble error condition has been detected endpoint disable by application is effective endpoint nak by application is effective (isochronous-in only) more than 3 back-to-back setup packets were received (control-out only) timeout condition detected (control-in only) isochronous out packet has been dropped, without generating an interrupt 29.6 usb host this section gives the functional description of the otg_fs in the usb host mode. the otg_fs works as a usb host in the following circumstances: otg a-host ? otg a-device default state when the a-side of the usb cable is plugged in otg b-host ? otg b-device after hnp switching to the host role a-device ? if the id line is present, functional and connected to the a-side of the usb cable, and the hnp-capable bit is cleared in the global usb configuration register (hnpcap bit in otg_fs_gusbcfg). integrated pull-down resistors are automatically set on the dp/dm lines. host only (see figure figure 351: usb host-only connection ). ? the force host mode bit in the global usb configuration register (fhmod bit in otg_fs_gusbcfg) forces the otg_fs core to work as a usb host-only. in this case, the id line is ignored even if present on the usb connector. integrated pull- down resistors are automatically set on the dp/dm lines. note: 1 on-chip 5 v v bus generation is not supported. for this reason, a charge pump or, if 5 v are available on the application board, a basic power switch must be added externally to drive the 5 v v bus line. the external charge pump can be driven by any gpio output. this is required for the otg a-host, a-device and host-only configurations. 2the v bus input ensures that valid v bus levels are supplied by the charge pump during usb operations while the charge pump overcurrent output can be input to any gpio pin configured to generate port interrupts. the overcurrent isr must promptly disable the v bus generation. 3the v bus pin can be freed by disabling the v bus sensing option. this is done by setting the novbussens bit in the otg_fs_gccfg register. in this case the v bus is considered internally to be always at v bus valid level (5 v). RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 935/1317 figure 351. usb host-only connection 1. stmps2141str needed only if the application has to support a v bus powered device. a basic power switch can be used if 5 v are available on the application board. 2. v dd range is between 2 v and 3.6 v. 29.6.1 srp-capable host srp support is available through the srp capable bit in the global usb configuration register (srpcap bit in otg_fs_gusbcfg). with the srp feature enabled, the host can save power by switching off the v bus power while the usb session is suspended. the srp host mode program model is described in detail in the a-device session request protocol ) section. 29.6.2 usb host states host port power on-chip 5 v v bus generation is not supported. for this reason, a charge pump or, if 5 v are available on the application board, a basic power switch, must be added externally to drive the 5 v v bus line. the external charge pump can be driven by any gpio output. when the application decides to power on v bus using the chosen gpio, it must also set the port power bit in the host port control and status register (ppwr bit in otg_fs_hprt). v bus valid the v bus input ensures that valid v bus levels are supplied by the charge pump during usb operations. any unforeseen v bus voltage drop below the v bus valid threshold (4.25 v) leads to an otg interrupt triggered by the session end detected bit (sedet bit in otg_fs_gotgint). the application is then required to remove the v bus power and clear the port power bit. the charge pump overcurrent flag can also be used to prevent electrical damage. connect the overcurrent flag output from the charge pump to any gpio input and configure it to generate a port interrupt on the active level. the overcurrent isr must promptly disable the v bus generation and clear the port power bit. 3 4 - & x 3 4 - & x 3 4 - 0 3 3 4 2 # u r r e n t l i m i t e d p o w e r d i s t r i b u t i o n s w i t c h 6 $ $ 6 " 5 3 $ 0 6 3 3 0 ! 0 ! 0 ! 5 3 " 3 t d ! c o n n e c t o r $ - ' 0 ) / ) 2 1 ' 0 ) / % . / v e r c u r r e n t 6 0 w r / 3 # ? ) . / 3 # ? / 5 4 a i usb on-the-go full-speed (otg_fs) RM0033 936/1317 doc id 15403 rev 3 host detection of a peripheral connection even if usb peripherals or b-devices can be attached at any time, the otg_fs will not detect any bus connection until v bus is no longer sensed at a valid level (5 v). when v bus is at a valid level and a remote b-device is attached, the otg_fs core issues a host port interrupt triggered by the device connected bit in the host port control and status register (pcdet bit in otg_fs_hprt). host detection of peripheral a disconnection the peripheral disconnection event triggers th e disconnect detected interrupt (discint bit in otg_fs_gintsts). host enumeration after detecting a peripheral connection the host must start the enumeration process by sending usb reset and configuration commands to the new peripheral. before starting to drive a usb reset, the application waits for the otg interrupt triggered by the debounce done bit (dbcdne bit in otg_fs_g otgint), which indicates that the bus is stable again after the electrical debounce caused by the attachment of a pull-up resistor on dp (fs) or dm (ls). the application drives a usb reset signaling (single-ended zero) over the usb by keeping the port reset bit set in the host port control and status register (prst bit in otg_fs_hprt) for a minimum of 10 ms and a maximum of 20 ms. the application takes care of the timing count and then of clearing the port reset bit. once the usb reset sequence has completed, the host port interrupt is triggered by the port enable/disable change bit (penchng bit in otg_fs_hprt). this informs the application that the speed of the enumerated peripheral can be read from the port speed field in the host port control and status register (pspd bit in otg_fs_hprt) and that the host is starting to drive sofs (fs) or keep alives (ls). the host is now ready to complete the peripheral enumeration by sending peripheral configuration commands. host suspend the application decides to suspend the usb acti vity by setting the port suspend bit in the host port control and status register (psusp bit in otg_fs_hprt). the otg_fs core stops sending sofs and enters the suspended state. the suspended state can be optionally exited on the remote device?s initiative (remote wakeup). in this case the remote wakeup interrupt (wkupint bit in otg_fs_gintsts) is generated upon detection of a remote wakeup signaling, the port resume bit in the host port control and status register (pres bit in otg_fs_hprt) self-sets, and resume signaling is automatically driven over the usb. the application must time the resume window and then clear the port resume bit to exit the suspended state and restart the sof. if the suspended state is exited on the host initiative, the application must set the port resume bit to start resume signaling on the host port, time the resume window and finally clear the port resume bit. 29.6.3 host channels the otg_fs core instantiates 8 host channels. each host channel supports an usb host transfer (usb pipe). the host is not able to support more than 8 transfer requests at the RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 937/1317 same time. if more than 8 transfer requests are pending from the application, the host controller driver (hcd) must re-allocate channels when they become available from previous duty, that is, after receiving the transfer completed and channel halted interrupts. each host channel can be configured to support in/out and any type of periodic/nonperiodic transaction. each host channel makes us of proper control (hcchar x ), transfer configuration (hctsiz x ) and status/interrupt (hcint x ) registers with associated mask (hcintmsk x ) registers. host channel control the following host channel controls are available to the application through the host channel- x characteristics register (hcchar x ): ? channel enable/disable ? program the fs/ls speed of target usb peripheral ? program the address of target usb peripheral ? program the endpoint number of target usb peripheral ? program the transfer in/out direction ? program the usb transfer type (control, bulk, interrupt, isochronous) ? program the maximum packet size (mps) ? program the periodic transfer to be executed during odd/even frames host channel transfer the host channel transfer size registers (hctsiz x ) allow the application to program the transfer size parameters, and read the transfer status. programming must be done before setting the channel enable bit in the host channel characteristics register. once the endpoint is enabled the packet count field is read-only as the otg fs core updates it according to the current transfer status. the following transfer parameters can be programmed: ? transfer size in bytes ? number of packets making up the overall transfer size ? initial data pid host channel status/interrupt the host channel- x interrupt register (hcint x ) indicates the status of an endpoint with respect to usb- and ahb-related events. the application must read these register when the host channels interrupt bit in the core interrupt register (hcint bit in otg_fs_gintsts) is set. before the application can read these registers, it must first read the host all channels interrupt (hcaint) register to get the exact channel number for the host channel-x interrupt register. the application must clear the appropriate bit in this register to clear the usb on-the-go full-speed (otg_fs) RM0033 938/1317 doc id 15403 rev 3 corresponding bits in the haint and gintsts registers. the mask bits for each interrupt source of each channel are also available in the otg_fs_hcintmsk-x register. the host core provides the following status checks and interrupt generation: ? transfer completed interrupt, indicating that the data transfer is complete on both the application (ahb) and usb sides ? channel has stopped due to transfer completed, usb transaction error or disable command from the application ? associated transmit fifo is half or completely empty (in endpoints) ? ack response received ? nak response received ? stall response received ? usb transaction error due to crc failure, timeout, bit stuff error, false eop ? babble error ?frame overrun ? data toggle error 29.6.4 host scheduler the host core features a built-in hardware scheduler which is able to autonomously re-order and manage the usb transaction requests posted by the application. at the beginning of each frame the host executes the periodic (isochronous and interrupt) transactions first, followed by the nonperiodic (control and bulk) transactions to achieve the higher level of priority granted to the isochronous and interr upt transfer types by the usb specification. the host processes the usb transactions through request queues (one for periodic and one for nonperiodic). each request queue can hold up to 8 entries. each entry represents a pending transaction request from the application, and holds the in or out channel number along with other information to perform a transaction on the usb. the order in which the requests are written to the queue determines the sequence of the transactions on the usb interface. at the beginning of each frame, the host processes the periodic request queue first, followed by the nonperiodic request queue. the host issues an incomplete periodic transfer interrupt (ipxfr bit in otg_fs_gintsts) if an isochronous or interrupt transaction scheduled for the current frame is still pending at the end of the cu rrent frame. the otg hs core is fully responsible for the management of the periodic and nonperiodic request queues.the periodic transmit fifo and queue status register (hptxsts) and nonperiodic transmit fifo and queue status register (hnptxsts) are read-only registers which can be used by the application to read the status of each request queue. they contain: the number of free entries currently available in the periodic (nonperiodic) request queue (8 max) free space currently available in the periodic (nonperiodic) tx-fifo (out-transactions) in/out token, host channel number and other status information. as request queues can hold a maximum of 8 entries each, the application can push to schedule host transactions in advance with respec t to the moment they physically reach the sb for a maximum of 8 pending periodic transactions plus 8 pending nonperiodic transactions. to post a transaction request to the host scheduler (queue) the application must check that there is at least 1 entry available in the periodic (nonperiodic) request queue by reading the RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 939/1317 ptxqsav bits in the otg_fs_hnptxsts register or nptqxsav bits in the otg_fs_hnptxsts register. 29.7 sof trigger figure 352. sof connectivity the otg fs core provides means to monitor, track and configure sof framing in the host and peripheral, as well as an sof pulse output connectivity feature. such utilities are especially useful for adaptiv e audio clock generation techniques, where the audio peripheral needs to synchronize to the is ochronous stream provided by the pc, or the host needs to trim its framing rate according to the requirements of the audio peripheral. 29.7.1 host sofs in host mode the number of phy clocks occurring between the generation of two consecutive sof (fs) or keep-alive (ls) tokens is programmable in the host frame interval register (hfir), thus providing application control over the sof framing period. an interrupt is generated at any start of frame (sof bit in oth_fs_gintsts). the current frame number and the time remaining until the next sof are tracked in the host frame number register (hfnum). an sof pulse signal, generated at any sof starting token and with a width of 12 system clock cycles, can be made available externally on the sof pin using the sofouten bit in the global control and configuration register. the sof pulse is also internally connected to the input trigger of timer 2 (tim2), so that the input capture feature, the output compare feature and the timer can be triggered by the sof pulse. the tim2 connection is enabled through the itr1_rmp bits of tim2_or register. 29.7.2 peripheral sofs in device mode, the start of frame interrupt is generated each time an sof token is received on the usb (sof bit in oth_fs_gintsts). the corresponding frame number can be read from the device status register (fnsof bit in otg_fs_dsts). an sof pulse signal with a width of 12 system clock cycles is also generated and can be made available externally on the sof pin by using the sof output enable bit in the global control and configuration 3 4 - & x 3 4 - & x 6 " 5 3 $ 6 3 3 0 ! 0 ! 0 ! 5 3 " m i c r o ! " c o n n e c t o r $ ) $ 4 ) - ) 4 2 3 / & p u l s e 3 / & g e n 0 ! 0 ! 3 / & p u l s e o u t p u t t o e x t e r n a l a u d i o c o n t r o l a i usb on-the-go full-speed (otg_fs) RM0033 940/1317 doc id 15403 rev 3 register (sofouten bit in otg_fs_gccfg). th e sof pulse signal is also internally connected to the tim2 input trigger, so that the input capture feature, the output compare feature and the timer can be triggered by the sof pulse. the tim2 connection is enabled through the itr1_rmp bits the tim2 option register (tim2_or). the end of periodic frame interrupt (gintsts/eop f) is used to notify the application when 80%, 85%, 90% or 95% of the time frame interval elapsed depending on the periodic frame interval field in the device configuration register (pfivl bit in otg_fs_dcfg). this feature can be used to determine if all of the isochronous traffic for that frame is complete. 29.8 power options the power consumption of the otg phy is controlled by three bits in the general core configuration register: phy power down (gccfg/pwrdwn) it switches on/off the full-speed transceiver module of the phy. it must be preliminarily set to allow any usb operation. a-v bus sensing enable (gccfg/vbusasen) it switches on/off the v bus comparators associated with a-device operations. it must be set when in a-device (usb host) mode and during hnp. b-v bus sensing enable (gccfg/vbusasen) it switches on/off the v bus comparators associated with b-device operations. it must be set when in b-device (usb peripheral) mode and during hnp. power reduction techniques are available while in the usb suspended state, when the usb session is not yet valid or the device is disconnected. stop phy clock (stppclk bit in otg_fs_pcgcctl) when setting the stop phy clock bit in the clock gating control register, most of the 48 mhz clock domain internal to the otg full-speed core is switched off by clock gating. the dynamic power consumption due to the usb clock switching activity is cut even if the 48 mhz clock input is kept running by the application most of the transceiver is also disabled, and only the part in charge of detecting the asynchronous resume or remote wakeup event is kept alive. gate hclk (gatehclk bit in otg_fs_pcgcctl) when setting the gate hclk bit in the clock gating control register, most of the system clock domain internal to the otg_fs core is switched off by clock gating. only the register read and write interface is kept alive. the dynamic power consumption due to the usb clock switching activity is cut even if the system clock is kept running by the application for other purposes. usb system stop when the otg_fs is in the usb suspended state, the application may decide to drastically reduce the overall power consumption by a complete shut down of all the clock sources in the system. usb system stop is activated by first setting the stop phy clock bit and then configuring the system deep sleep mode in the power control system module (pwr). the otg_fs core automatically reactivates both system and usb clocks by asynchronous detection of remote wakeup (as an host) or resume (as a device) signaling on the usb. RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 941/1317 to save dynamic power, the usb data fifo is clocked only when accessed by the otg_fs core. 29.9 dynamic update of the otg_fs_hfir register the usb core embeds a dynamic trimming cap ability of micro-sof fr aming period in host mode allowing to synchronize an external device with the micro-sof frames. when the otg_hs_hfir register is changed within a current micro-sof frame, the sof period correction is applied in the next frame as described in figure 353 . figure 353. updating otg_fs_hfir dynamically 29.10 usb data fifos the usb system features 1.25 kbyte of dedicated ram with a sophisticated fifo control mechanism. the packet fifo controller module in the otg_fs core organizes ram space into tx-fifos into which the application pushes the data to be temporarily stored before the usb transmission, and into a single rx fifo where the data received from the usb are temporarily stored before retrieval (popped) by the application. the number of instructed fifos and how these are architectured inside the ram depends on the device?s role. in peripheral mode an additional tx-fifo is inst ructed for each active in endpoint. any fifo size is software configured to better meet the application requirements. x x x x , a t e n c y 3 / & r e l o a d / 4 ' ? & 3 ? ( & ) 2 w r i t e v a l u e & r a m e t i m e r / l d / 4 ' ? & 3 ? ( ) & 2 v a l u e p e r i o d s / 4 ' ? & 3 ? ( ) & 2 v a l u e p e r i o d s ( ) & 2 w r i t e l a t e n c y . e w / 4 ' ? & 3 ? ( ) & 2 v a l u e p e r i o d s / 4 ' ? & 3 ? ( & ) 2 a i usb on-the-go full-speed (otg_fs) RM0033 942/1317 doc id 15403 rev 3 29.11 peripheral fifo architecture figure 354. device -mode fifo address mapping and ahb fi fo access mapping 29.11.1 peripheral rx fifo the otg peripheral uses a single receive fifo that receives the data directed to all out endpoints. received packets are stacked back-to-back until free space is available in the rx-fifo. the status of the received packet (which contains the out endpoint destination number, the byte count, the data pid and the validity of the received data) is also stored by the core on top of the data payload. when no more space is available, host transactions are nacked and an interrupt is received on the addressed endpoint. the size of the receive fifo is configured in the receive fifo size register (grxfsiz). the single receive fifo architectu re makes it more efficient for the usb peripheral to fill in the receive ram buffer: all out endpoints share the same ram buffer (shared fifo) the otg fs core can fill in the receive fifo up to the limit for any host sequence of out tokens the application keeps receiving the rx-fifo non-empty interrupt (rxflvl bit in otg_fs_gintsts) as long as there is at least one packet available for download. it reads the packet information from the receive status read and pop register (grxstsp) and finally pops data off the receive fifo by reading from the endpoint-related pop address. in endpoint tx fifo #n dfifo push access from ahb any out endpoint dfifo pop access from ahb dedicated tx fifo #n control (optional) dedicated tx fifo #1 control (optional) rx fifo control in endpoint tx fifo #1 dfifo push access from ahb mac pop mac pop mac push single data fifo tx fifo #n packet tx fifo #0 packet dieptxf2[31:16] dieptxfx[15:0] dieptxf2[15:0] dieptxf1[31:16] dieptxf1[15:0] gnptxfsiz[31:16] ai15611 in endpoint tx fifo #0 dfifo push access from ahb dedicated tx fifo #0 control (optional) mac pop tx fifo #1 packet rx packets (rx start address fixed to 0) . . . . . . . . . gnptxfsiz[15:0] grxfsiz[31:16] a1 = 0 RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 943/1317 29.11.2 peripheral tx fifos the core has a dedicated fifo for each in endpoint. the application configures fifo sizes by writing the non periodic transmit fifo size register (otg_fs_tx0fsiz) for in endpoint0 and the device in endpoint transmit fifox registers (dieptxfx) for in endpoint-x. 29.12 host fifo architecture figure 355. host-mode fifo address mapping and ahb fifo access mapping 29.12.1 host rx fifo the host uses one receiver fifo for all periodic and nonperiodic transactions. the fifo is used as a receive buffer to hold the received data (payload of the received packet) from the usb until it is transferred to the system memory. packets received from any remote in endpoint are stacked back-to-back until free space is available. the status of each received packet with the host channel destination, byte count, data pid and validity of the received data are also stored into the fifo. the size of the receive fifo is configured in the receive fifo size register (grxfsiz). the single receive fifo architectu re makes it highly efficient fo r the usb host to fill in the receive data buffer: all in configured host channels share the same ram buffer (shared fifo) the otg fs core can fill in the receive fifo up to the limit for any sequence of in tokens driven by the host software the application receives the rx fifo not-empty interrupt as long as there is at least one packet available for download. it reads the packet information from the receive status read and pop register and finally pops the data off the receive fifo. any periodic channel dfifo push access from ahb any channel dfifo pop access from ahb periodic tx fifo control (optional) non-periodic tx fifo control rx fifo control any non-periodic channel dfifo push access from ahb mac pop mac pop mac push single data fifo periodic tx packets periodic tx packets rx packets hptxfsiz[31:16] hptxfsiz[15:0] nptxfsiz[31:16] nptxfsiz[15:0] rxfsiz[31:16] rx start address fixed to 0 a1 = 0 ai15610 usb on-the-go full-speed (otg_fs) RM0033 944/1317 doc id 15403 rev 3 29.12.2 host tx fifos the host uses one transmit fifo for all non- periodic (control and bulk) out transactions and one transmit fifo for all periodic (isochronous and interrupt) out transactions. fifos are used as transmit buffers to hold the data (payload of the transmit packet) to be transmitted over the usb. the size of the periodic (nonperiodic) tx fifo is configured in the host periodic (nonperiodic) transmit fifo size (hptxfsiz/hnptxfsiz) register. the two tx fifo implementation derives from the higher priority granted to the periodic type of traffic over the usb frame. at the beginning of each frame, the built-in host scheduler processes the periodic request queue first, followed by the nonperiodic request queue. the two transmit fifo architecture provides the usb host with separate optimization for periodic and nonperiodic transmit data buffer management: all host channels configured to support per iodic (nonperiodic) transactions in the out direction share the same ram buffer (shared fifos) the otg fs core can fill in the periodic (no nperiodic) transmit fifo up to the limit for any sequence of out tokens driven by the host software the otg_fs core issues the periodic tx fifo empty interrupt (ptxfe bit in otg_fs_gintsts) as long as the periodic tx-fifo is half or completely empty, depending on the value of the periodic tx-fifo empty level bit in the ahb configuration register (ptxfelvl bit in otg_fs_gahbcfg). the application can push the transmission data in advance as long as free space is available in both the periodic tx fifo and the periodic request queue. the host periodic transmit fifo and queue status register (hptxsts) can be read to know how much space is available in both. otg_fs core issues the non periodic tx fifo empty interrupt (nptxfe bit in otg_fs_gintsts) as long as the nonperiodic tx fifo is half or completely empty depending on the non periodic tx fifo empty level bit in the ahb configuration register (txfelvl bit in otg_fs_gahbcfg). the application can push the transmission data as long as free space is available in both the nonperiodic tx fifo and nonperiodic request queue. the host nonperiodic transmit fifo and queue status register (hnptxsts) can be read to know how much space is available in both. 29.13 fifo ram allocation 29.13.1 device mode receive fifo ram allocation: the application should allocate ram for setup packets: 10 locations must be reserved in the receive fifo to receive setup packets on control endpoint. the core does not use these locations, which are reserved for setup packets, to write any other data. one location is to be allocated for global out nak. status information is written to the fifo along with each received packet. therefore, a minimum space of (largest packet size / 4) + 1 must be allocated to receive packets. if multiple isochronous endpoints are enabled, then at least two (largest packet size / 4) + 1 spaces must be allocated to receive back-to-back packets. typically, two (largest packet size / 4) + 1 spaces are recommended so that when the previous packet is being transferred to the cpu, the usb can receive the subsequent packet. along with the last packet for each endpoint, transfer complete status information is also pushed to the fifo. typically, one location for each out endpoint is recommended. RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 945/1317 transmit fifo ram allocation: the minimum ram space required for each in endpoint transmit fifo is the maximum packet size for that particular in endpoint. note: more space allocated in the transmit in endpoint fifo results in better performance on the usb. 29.13.2 host mode receive fifo ram allocation status information is written to the fifo along with each received packet. therefore, a minimum space of (largest packet size / 4) + 1 must be allocated to receive packets. if multiple isochronous channels are enabled, then at least two (largest packet size / 4) + 1 spaces must be allocated to receive back-to-back packets. typically, two (largest packet size / 4) + 1 spaces are recommended so that when the previous packet is being transferred to the cpu, the usb can receive the subsequent packet. along with the last packet in the host channel, transfer complete status information is also pushed to the fifo. so one location must be allocated for this. transmit fifo ram allocation the minimum amount of ram required for the host non-periodic transmit fifo is the largest maximum packet size among all supported non-periodic out channels. typically, two largest packet sizes worth of space is recommended, so that when the current packet is under transfer to the usb, the cpu can get the next packet. the minimum amount of ram required for host periodic transmit fifo is the largest maximum packet size out of all the supported periodic out channels. if there is at least one isochronous out endpoint, then the space must be at least two times the maximum packet size of that channel. note: more space allocated in the transmit non-periodic fifo results in better performance on the usb. 29.14 usb system performance best usb and system performance is achieved owing to the large ram buffers, the highly configurable fifo sizes, the quick 32-bit fifo access through ahb push/pop registers and, especially, the advanced fifo control mechanism. indeed, this mechanism allows the usb on-the-go full-speed (otg_fs) RM0033 946/1317 doc id 15403 rev 3 otg_fs to fill in the available ram space at best regardless of the current usb sequence. with these features: the application gains good margins to calibrate its intervention in order to optimize the cpu bandwidth usage: ? it can accumulate large amounts of transmission data in advance compared to when they are effectively sent over the usb ? it benefits of a large time margin to download data from the single receive fifo the usb core is able to maintain its full ope rating rate, that is to provide maximum full- speed bandwidth with a great margin of autonomy versus application intervention: ? it has a large reserve of transmission data at its disposal to autonomously manage the sending of data over the usb ? it has a lot of empty space available in the receive buffer to autonomously fill it in with the data coming from the usb as the otg_fs core is able to fill in the 1. 25 kbyte ram buffer very efficiently, and as 1.25 kbyte of transmit/receive data is more than enough to cover a full speed frame, the usb system is able to withstand the maximum full-speed data rate for up to one usb frame (1 ms) without any cpu intervention. 29.15 otg_fs interrupts when the otg_fs controller is operating in one mode, either device or host, the application must not access registers from the other mode. if an illegal access occurs, a mode mismatch interrupt is generated and reflected in the core interrupt register (mmis bit in the otg_fs_gintsts register). when the core switches from one mode to the other, the registers in the new mode of operation must be reprogrammed as they would be after a power-on reset. figure 356 shows the interrupt hierarchy. RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 947/1317 figure 356. interrupt hierarchy 1. the core interrupt register bits are shown in otg_fs core interrupt register (otg_fs_gintsts) on page 962 . 31 30 29 28 27 26 25 24 23 20 19 18 17:10 9 8 7:3 2 1 0 and or interrupt global interrupt mask (bit 0) ahb configuration register core interrupt mask register otg interrupt register core interrupt register (1) device in/out endpoint interrupt registers 0 to 3 device all endpoints interrupt register 16:9 out endpoints 3:0 in endpoints interrupt sources host port control and status register host all channels interrupt register host channels interrupt mask registers 0 to 7 host all channels interrupt mask register host channels interrupt registers 0 to 7 22 21 device all endpoints interrupt mask register device in/out endpoints common interrupt mask register ai15616b usb on-the-go full-speed (otg_fs) RM0033 948/1317 doc id 15403 rev 3 29.16 otg_fs control and status registers by reading from and writing to the control and status registers (csrs) through the ahb slave interface, the application controls the otg_fs controller. these registers are 32 bits wide, and the addresses are 32-bit block aligned. csrs are classified as follows: core global registers host-mode registers host global registers host port csrs host channel-specific registers device-mode registers device global registers device endpoint-specific registers power and clock-gating registers data fifo (dfifo) access registers only the core global, power and clock-gating, data fifo access, and host port control and status registers can be accessed in both host and device modes. when the otg_fs controller is operating in one mode, either device or host, the application must not access registers from the other mode. if an illegal ac cess occurs, a mode mismatch interrupt is generated and reflected in the core interrupt register (mmis bit in the otg_fs_gintsts register). when the core switches from one mode to the other, the registers in the new mode of operation must be reprogrammed as they would be after a power-on reset. RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 949/1317 29.16.1 csr memory map the host and device mode registers occupy different addresses. all registers are implemented in the ahb clock domain. figure 357. csr memory map 1. x = 3 in device mode and x = 7 in host mode. global csr map these registers are available in both host and device modes. 0000h core glo ba l c s r s (1 k b yte) 0400h ho s t mode c s r s (1 k b yte) 0 8 00h device mode c s r s (1.5 k b yte) 0e00h power a nd clock g a ting c s r s (0.5 k b yte) 1000h device ep 0/ho s t ch a nnel 0 fifo (4 k b yte) 2000h device ep1/ho s t ch a nnel 1 fifo (4 k b yte) 3 000h device ep (x ? 1) (1) /ho s t ch a nnel (x ? 1) (1) fifo (4 k b yte) device ep x (1) /ho s t ch a nnel x (1) fifo (4 k b yte) re s erved dfifo p us h/pop to thi s region 2 0000h 3 ffffh direct a cce ss to d a t a fifo ram for de bu gging (12 8 k b yte) dfifo de bu g re a d/ write to thi s region a i15615 b table 148. core global control and status registers (csrs) acronym address offset register name otg_fs_gotgctl 0x000 otg_fs control and status regi ster (otg_fs_gotgctl) on page 953 otg_fs_gotgint 0x004 otg_fs interrupt register (otg_fs_gotgint) on page 955 otg_fs_gahbcfg 0x008 otg_fs ahb configuration register (otg_fs_gahbcfg) on page 957 otg_fs_gusbcfg 0x00c otg_fs usb configuration register (otg_fs_gusbcfg) on page 958 otg_fs_grstctl 0x010 otg_fs reset register (otg_fs_grstctl) on page 960 usb on-the-go full-speed (otg_fs) RM0033 950/1317 doc id 15403 rev 3 host-mode csr map these registers must be programmed every time the core changes to host mode. otg_fs_gintsts 0x014 otg_fs core interrupt register (otg_fs_gintsts) on page 962 otg_fs_gintmsk 0x018 otg_fs interrupt mask register (otg_fs_gintmsk) on page 966 otg_fs_grxstsr 0x01c otg_fs receive status debug read/otg status read and pop registers (otg_fs_grxstsr/otg_f s_grxstsp) on page 969 otg_fs_grxstsp 0x020 otg_fs_grxfsiz 0x024 otg_fs receive fifo size register (otg_fs_grxfsiz) on page 970 otg_fs_hnptxfsiz/ otg_fs_dieptxf0 (1) 0x028 otg_fs host non-periodic transmit fifo size register (otg_fs_hnptxfsiz)/endpoint 0 transmit fifo size (otg_fs_dieptxf0) otg_fs_hnptxsts 0x02c otg_fs non-periodic transmit fifo/queue status register (otg_fs_hnptxsts) on page 971 otg_fs_gccfg 0x038 otg_fs general core configuration register (otg_fs_gccfg) on page 972 otg_fs_cid 0x03c otg_fs core id register (otg_fs_cid) on page 973 otg_fs_hptxfsiz 0x100 otg_fs host periodic transmit fifo size register (otg_fs_hptxfsiz) on page 973 otg_fs_dieptxfx 0x104 0x124 ... 0x138 otg_fs device in endpoint transmit fifo size register (otg_fs_dieptxfx) (x = 1..3, wher e x is the fifo_number) on page 975 1. the general rule is to use otg_fs_hnptxfsiz for host mode and otg_fs_dieptxf0 for device mode. table 148. core global control and status registers (csrs) (continued) acronym address offset register name table 149. host-mode control and status registers (csrs) acronym offset address register name otg_fs_hcfg 0x400 otg_fs host configuration re gister (otg_fs_hcfg) on page 975 otg_fs_hfir 0x404 otg_fs host frame interval register (otg_fs_hfir) on page 976 otg_fs_hfnum 0x408 otg_fs host frame number/fra me time remaining register (otg_fs_hfnum) on page 977 otg_fs_hptxsts 0x410 otg_fs_host periodic transmit fifo/queue status register (otg_fs_hptxsts) on page 977 otg_fs_haint 0x414 otg_fs host all channels interrupt register (otg_fs_haint) on page 978 otg_fs_haintmsk 0x418 otg_fs host all channels interrupt mask register (otg_fs_haintmsk) on page 979 RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 951/1317 device-mode csr map these registers must be programmed every time the core changes to device mode. otg_fs_hprt 0x440 otg_fs host port control and status register (otg_fs_hprt) on page 979 otg_fs_hccharx 0x500 0x520 ... 0x6e0h otg_fs host channel-x characteristics register (otg_fs_hccharx) (x = 0..7, where x = channel_number) on page 982 otg_fs_hcintx 508h otg_fs host channel-x interrupt register (otg_fs_hcintx) (x = 0..7, where x = channel_number) on page 983 otg_fs_hcintmskx 50ch otg_fs host channel-x interrupt mask register (otg_fs_hcintmskx) (x = 0..7, where x = channel_number) on page 984 otg_fs_hctsizx 510h otg_fs host channel-x transfer size register (otg_fs_hctsizx) (x = 0..7, where x = channel_number) on page 985 table 149. host-mode control and status registers (csrs) (continued) acronym offset address register name table 150. device-mode control and status registers acronym offset address register name otg_fs_dcfg 0x800 otg_fs device configuration r egister (otg_fs_dcfg) on page 986 otg_fs_dctl 0x804 otg_fs device control register (otg_fs_dctl) on page 987 otg_fs_dsts 0x808 otg_fs device status regist er (otg_fs_dsts) on page 988 otg_fs_diepmsk 0x810 otg_fs device in endpoint common interrupt mask register (otg_fs_diepmsk) on page 989 otg_fs_doepmsk 0x814 otg_fs device out endpoint common interrupt mask register (otg_fs_doepmsk) on page 990 otg_fs_daint 0x818 otg_fs device all endpoints interrupt register (otg_fs_daint) on page 991 otg_fs_daintmsk 0x81c otg_fs all endpoints interrupt mask register (otg_fs_daintmsk) on page 992 otg_fs_dvbusdis 0x828 otg_fs device v bus discharge time register (otg_fs_dvbusdis) on page 992 otg_fs_dvbuspulse 0x82c otg_fs device v bus pulsing time register (otg_fs_dvbuspulse) on page 993 otg_fs_diepempmsk 0x834 otg_fs device in endpoint fifo empty interrupt mask register: (otg_fs_diepempmsk) on page 993 otg_fs_diepctl0 0x900 otg_fs device control in endpoint 0 control register (otg_fs_diepctl0 ) on page 994 usb on-the-go full-speed (otg_fs) RM0033 952/1317 doc id 15403 rev 3 data fifo (dfifo) access register map these registers, available in both host and device modes, are used to read or write the fifo space for a specific endpoint or a channel, in a given direction. if a host channel is of type in, the fifo can only be read on the channel. similarly, if a host channel is of type out, the fifo can only be written on the channel. otg_fs_diepctlx 0x920 0x940 ... 0xae0 otg device endpoint-x control register (otg_fs_diepctlx) (x = 1..3, where x = endpoint_number) on page 995 otg_fs_diepintx 0x908 otg_fs device endpoint-x interrupt register (otg_fs_diepintx) (x = 0..3, where x = endpoint_number) on page 1002 otg_fs_dieptsiz0 0x910 otg_fs device in endpoint 0 transfer size register (otg_fs_dieptsiz 0) on page 1004 otg_fs_dtxfstsx 0x918 otg_fs device in endpoint transmit fifo status register (otg_fs_dtxfstsx) (x = 0..3, where x = endpoint_number) on page 1007 otg_fs_dieptsizx 0x930 0x950 ... 0xaf0 otg_fs device out endpoint-x transfer size register (otg_fs_doeptsizx) (x = 1..3, where x = endpoint_number) on page 1007 otg_fs_doepctl0 0xb00 otg_fs device control out endpoint 0 control register (otg_fs_doepctl0) on page 998 otg_fs_doepctlx 0xb20 0xb40 ... 0xcc0 0xce0 0xcfd otg device endpoint-x control register (otg_fs_diepctlx) (x = 1..3, where x = endpoint_number) on page 995 otg_fs_doepintx 0xb08 otg_fs device endpoint-x interrupt register (otg_fs_diepintx) (x = 0..3, where x = endpoint_number) on page 1002 otg_fs_doeptsizx 0xb10 otg_fs device out endpoint-x transfer size register (otg_fs_doeptsizx) (x = 1..3, where x = endpoint_number) on page 1007 table 150. device-mode control and status registers (continued) acronym offset address register name RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 953/1317 power and clock gating csr map there is a single register for power and clock gating. it is available in both host and device modes. 29.16.2 otg_fs global registers these registers are available in both host and device modes, and do not need to be reprogrammed when switching between these modes. bit values in the register descriptions are expressed in binary unless otherwise specified. otg_fs control and status register (otg_fs_gotgctl) address offset: 0x000 reset value: 0x0000 0800 the otg_fs_gotgctl register controls the behavior and reflects the status of the otg function of the core. table 151. data fifo (dfifo) access register map fifo access register section address range access device in endpoint 0/host out channel 0: dfifo write access device out endpoint 0/host in channel 0: dfifo read access 0x1000?0x1ffc w r device in endpoint 1/host out channel 1: dfifo write access device out endpoint 1/host in channel 1: dfifo read access 0x2000?0x2ffc w r ... ... ... device in endpoint x (1) /host out channel x (1) : dfifo write access device out endpoint x (1) /host in channel x (1) : dfifo read access 1. where x is 3 in device mode and 7 in host mode. 0xx000h?0xxffch w r table 152. power and clock gating control and status registers register name acronym offset address: 0xe00?0xfff power and clock gating control register pcgcr 0xe00-0xe04 reserved 0xe05?0xfff 313029282726252423222120191817161514131211109876543210 reserved bsvld asvld dbct cidsts reserved dhnpen hshnpen hnprq hngscs reserved srq srqscs rrrr rwrwrwr rwr bits 31:20 reserved usb on-the-go full-speed (otg_fs) RM0033 954/1317 doc id 15403 rev 3 bit 19 bsvld: b-session valid indicates the device mo de transceiver status. 0: b-session is not valid. 1: b-session is valid. in otg mode, you can use this bit to determin e if the device is c onnected or disconnected. note: only accessible in device mode. bit 18 asvld: a-session valid indicates the host mode transceiver status. 0: a-session is not valid 1: a-session is valid note: only accessible in host mode. bit 17 dbct: long/short debounce time indicates the debounce time of a detected connection. 0: long debounce time, used for physical connections (100 ms + 2.5 s) 1: short debounce time, used for soft connections (2.5 s) note: only accessible in host mode. bit 16 cidsts: connector id status indicates the connector id status on a connect event. 0: the otg_fs controller is in a-device mode 1: the otg_fs controller is in b-device mode note: accessible in both device and host modes. bits 15:12 reserved bit 11 dhnpen: device hnp enabled the application sets this bit when it successfully receives a setfeature.sethnpenable command from the connected usb host. 0: hnp is not enabled in the application 1: hnp is enabled in the application note: only accessible in device mode. bit 10 hshnpen: host set hnp enable the application sets this bit when it has successfully enabled hnp (using the setfeature.sethnpenable command) on the connected device. 0: host set hnp is not enabled 1: host set hnp is enabled note: only accessible in host mode. bit 9 hnprq: hnp request the application sets this bit to initiate an hnp request to the connected usb host. the application can clear this bit by writing a 0 wh en the host negotiation success status change bit in the otg_fs_gotgint register (hnsschg bit in otg_fs_gotgint) is set. the core clears this bit when the hnsschg bit is cleared. 0: no hnp request 1: hnp request note: only accessible in device mode. RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 955/1317 otg_fs interrupt register (otg_fs_gotgint) address offset: 0x04 reset value: 0x0000 0000 the application reads this register whenever there is an otg interrupt and clears the bits in this register to clear the otg interrupt. bit 8 hngscs: host negotiation success the core sets this bit when host negotiation is successful. the core clears this bit when the hnp request (hnprq) bit in this register is set. 0: host negotiation failure 1: host negotiation success note: only accessible in device mode. bits 7:2 reserved bit 1 srq: session request the application sets this bit to initiate a session request on the usb. the application can clear this bit by writing a 0 when the host negotiation success status change bit in the otg_fs_gotgint register (hnsschg bit in otg_fs_gotgint) is set. the core clears this bit when the hnsschg bit is cleared. if you use the usb 1.1 full-speed serial transceiver interface to initiate the session request, the application must wait until v bus discharges to 0.2 v, after the b- session valid bit in this register (bsvld bit in otg_fs_gotgctl) is cleared. th is discharge time varies between different phys and can be obtained from the phy vendor. 0: no session request 1: session request note: only accessible in device mode. bit 0 srqscs: session request success the core sets this bit when a session request initiation is successful. 0: session request failure 1: session request success note: only accessible in device mode. 313029282726252423222120191817161514131211109876543210 reserved dbcdne adtochg hngdet reserved hnsschg srsschg reserved sedet res. rc_ w1 rc_ w1 rc_ w1 rc_ w1 rc_ w1 rc_ w1 bits 31:20 reserved. bit 19 dbcdne: debounce done the core sets this bit when the debounce is completed after the device connect. the application can start driving usb reset after seeing this interrupt. this bit is only valid when the hnp capable or srp capable bit is set in the otg_fs_gusbcfg register (hnpcap bit or srpcap bit in otg_fs_g usbcfg, respectively). note: only accessible in host mode. usb on-the-go full-speed (otg_fs) RM0033 956/1317 doc id 15403 rev 3 bit 18 adtochg: a-device timeout change the core sets this bit to indica te that the a-device has timed out while waiting for the b-device to connect. note: accessible in both device and host modes. bit 17 hngdet: host negotiation detected the core sets this bit when it detects a host negotiation request on the usb. note: accessible in both device and host modes. bits 16:10 reserved. bit 9 hnsschg: host negotiation success status change the core sets this bit on the success or failure of a usb host negotiation request. the application must read the host negotiation success bit of the otg_fs_gotgctl register (hngscs in otg_fs_gotgctl) to check for success or failure. note: accessible in both device and host modes. bits 7:3 reserved. bit 8 srsschg: session request success status change the core sets this bit on the success or fail ure of a session request. the application must read the session request success bi t in the otg_fs_gotgctl register (srqscs bit in otg_fs_gotgctl) to check for success or failure. note: accessible in both device and host modes. bit 2 sedet: session end detected the core sets this bit to indicate that the level of the voltage on v bus is no longer valid for a b- peripheral session when v bus < 0.8 v. bits 1:0 reserved. RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 957/1317 otg_fs ahb configuration register (otg_fs_gahbcfg) address offset: 0x008 reset value: 0x0000 0000 this register can be used to configure the core after power-on or a change in mode. this register mainly contains ahb system-related configuration parameters. do not change this register after the initial programming. the application must program this register before starting any transactions on either the ahb or the usb. 313029282726252423222120191817161514131211109876543210 reserved ptxfelvl txfelvl reserved gintmsk rw rw rw bits 31:20 reserved. bit 8 ptxfelvl: periodic txfifo empty level indicates when the periodic txfifo empty inte rrupt bit in the otg_fs_gintsts register (ptxfe bit in otg_fs_gintsts) is triggered. 0: ptxfe (in otg_fs_gintsts) in terrupt indicates that the periodic txfifo is half empty 1: ptxfe (in otg_fs_gintsts) in terrupt indicates that the periodic txfifo is completely empty note: only accessible in host mode. bit 7 txfelvl: txfifo empty level in device mode, this bit indicates when in en dpoint transmit fifo empty interrupt (txfe in otg_fs_diepintx.) is triggered. 0: the txfe (in otg_fs_diepintx) interrupt indi cates that the in endpoint txfifo is half empty 1: the txfe (in otg_fs_diepintx) interrupt indicates that the in endpoint txfifo is completely empty in host mode, this bit indicates when the nonperiodic tx fifo empty interrupt (nptxfe bit in otg_fs_gintsts) is triggered: 0: the nptxfe (in otg_fs_gintsts) interrupt indicates that the nonperiodic tx fifo is half empty 1: the nptxfe (in otg_fs_gintsts) interrupt indicates that the nonperiodic tx fifo is completely empty bits 6:1 reserved. bit 0 gintmsk: global interrupt mask the application uses this bit to mask or unmask the interrupt line assertion to itself. irrespective of this bit?s setting, the interrupt status registers are updated by the core. 0: mask the interrupt assertion to the application. 1: unmask the interrupt assertion to the application. note: accessible in both device and host modes. usb on-the-go full-speed (otg_fs) RM0033 958/1317 doc id 15403 rev 3 otg_fs usb configuration register (otg_fs_gusbcfg) address offset: 0x00c reset value: 0x0000 0a00 this register can be used to configure the core after power-on or a changing to host mode or device mode. it contains usb and usb-phy related configuration parameters. the application must program this register before starting any transactions on either the ahb or the usb. do not make changes to this register after the initial programming. 313029282726252423222120191817161514131211109876543210 ctxpkt fdmod fhmod reserved trdt hnpcap srpcap physel reserved tocal rw rw rw rw r/rw r/rw wo rw bits 31:20 reserved. bit 31 ctxpkt: corrupt tx packet this bit is for debug purposes only. never set this bit to 1. note: accessible in both device and host modes. bit 30 fdmod: force device mode writing a 1 to this bit forces the core to devi ce mode irrespective of the otg_fs_id input pin. 0: normal mode 1: force device mode after setting the force bit, the application must wait at least 25 ms before the change takes effect. note: accessible in both device and host modes. bit 29 fhmod: force host mode writing a 1 to this bit forces the core to hos t mode irrespective of the otg_fs_id input pin. 0: normal mode 1: force host mode after setting the force bit, the application must wait at least 25 ms before the change takes effect. note: accessible in both device and host modes. bits 28:14 reserved bits 13:10 trdt: usb turnaround time sets the turnaround time in phy clocks. to calculate the value of trdt, use the following formula: trdt = 4 ahb clock + 1 phy clock examples: 1. if ahb clock = 72 mhz (phy clock is 48), the trdt is set to 9. 2. if ahb clock = 48 mhz (phy clock is 48), the trdt is set to 5. note: only accessible in device mode. bit 9 hnpcap: hnp-capable the application uses this bit to control the otg_fs controller?s hnp capabilities. 0: hnp capability is not enabled. 1: hnp capability is enabled. note: accessible in both device and host modes. RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 959/1317 bit 8 srpcap: srp-capable the application uses this bit to control the otg_ fs controller?s srp capabilities. if the core operates as a non-srp-capable b-device, it cannot request the connected a-device (host) to activate v bus and start a session. 0: srp capability is not enabled. 1: srp capability is enabled. note: accessible in both device and host modes. bit 7 physel: full speed serial transceiver select this bit is always 1 with write-only access. bits [6:3] reserved bits [2:0] tocal: fs timeout calibration the number of phy clocks that t he application programs in this field is added to the full-speed interpacket timeout duration in the core to account for any additional delays introduced by the phy. this can be required, because the delay introduced by the phy in generating the line state condition can vary from one phy to another. the usb standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. the application must program this field based on t he speed of enumeration. the number of bit times added per phy clock is 0.25 bit times. usb on-the-go full-speed (otg_fs) RM0033 960/1317 doc id 15403 rev 3 otg_fs reset register (otg_fs_grstctl) address offset: 0x10 reset value: 0x2000 0000 the application uses this register to reset various hardware features inside the core. 313029282726252423222120191817161514131211109876543210 ahbidl reserved txfnum txfflsh rxfflsh reserved fcrst hsrst csrst r rw rs rs rs rs rs bit 31 ahbidl: ahb master idle indicates that the ahb master state machine is in the idle condition. note: accessible in both device and host modes. bits 30:11 reserved bits 10:6 txfnum: txfifo number this is the fifo number that must be flushed us ing the txfifo flush bit. this field must not be changed until the core clears the txfifo flush bit. 00000: ? non-periodic txfifo flush in host mode ? tx fifo 0 flush in device mode 00001: ? periodic txfifo flush in host mode ? txfifo 1 flush in device mode 00010: txfifo 2 flush in device mode ... 00101: txfifo 15 flush in device mode 10000: flush all the transmit fifos in device or host mode. note: accessible in both device and host modes. bit 5 txfflsh: txfifo flush this bit selectively flushes a single or all transmit fifos, but cannot do so if the core is in the midst of a transaction. the application must write this bit only after c hecking that the core is neither writing to the txfifo nor reading from the txfifo . verify using these registers: read?nak effective interrupt ensures the core is not reading from the fifo write?ahbidl bit in otg_fs_grstctl ensures the core is not writing anything to the fifo. note: accessible in both device and host modes. bit 4 rxfflsh: rxfifo flush the application can flush the entire rxfifo using this bit, but must first ensure that the core is not in the middle of a transaction. the application must only write to this bit after c hecking that the core is neither reading from the rxfifo nor writing to the rxfifo. the application must wait until the bit is cleare d before performing any other operations. this bit requires 8 clocks (slowest of phy or ahb clock) to clear. note: accessible in both device and host modes. RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 961/1317 bit 3 reserved bit 2 fcrst: host frame counter reset the application writes this bit to reset the frame number counter inside the core. when the frame counter is reset, the subsequent sof sent out by the core has a frame number of 0. note: only accessible in host mode. bit 1 hsrst: hclk soft reset the application uses this bit to flush the contro l logic in the ahb clock domain. only ahb clock domain pipelines are reset. fifos are not flushed with this bit. all state machines in the ahb clock domain are reset to the idle state after terminating the transactions on the ahb, following the protocol. csr control bits used by the ahb cloc k domain state machines are cleared. to clear this interrupt, status mask bits that control the interrupt status and are generated by the ahb clock domain state machine are cleared. because interrupt status bits are not cleared, the application can get the status of any core events that occurred after it set this bit. this is a self-clearing bit that the core clears af ter all necessary logic is reset in the core. this can take several clocks, depending on the core?s current state. note: accessible in both device and host modes. bit 0 csrst: core soft reset resets the hclk and pclk domains as follows: clears the interrupts and all the csr register bits except for the following bits: ? rstpdmodl bit in otg_fs_pcgcctl ? gayehclk bit in otg_fs_pcgcctl ? pwrclmp bit in otg_fs_pcgcctl ? stppclk bit in otg_fs_pcgcctl ? fslspcs bit in otg_fs_hcfg ? dspd bit in otg_fs_dcfg all module state machines (except for the ahb slave unit) are reset to the idle state, and all the transmit fifos and the receive fifo are flushed. any transactions on the ahb master are terminated as soon as possible, after completing the last data phase of an ahb transfer. any tran sactions on the usb are terminated immediately. the application can write to this bit any time it wants to reset the core. this is a self-clearing bit and the core clears this bit after all the necessary logic is reset in the core, which can take several clocks, depending on the current state of the core. once this bit has been cleared, the software must wait at least 3 phy clocks befo re accessing the phy do main (synchronization delay). the software must also check that bit 31 in this register is set to 1 (ahb master is idle) before starting any operation. typically, the software reset is used during software development and also when you dynamically change the phy sele ction bits in the above listed usb configuration registers. when you change the phy, the corresponding clock for the phy is selected and used in the phy domain. once a new clock is selected, the phy domain has to be reset for proper operation. note: accessible in both device and host modes. usb on-the-go full-speed (otg_fs) RM0033 962/1317 doc id 15403 rev 3 otg_fs core interrupt register (otg_fs_gintsts) address offset: 0x014 reset value: 0x0400 0020 this register interrupts the application for system-level events in the current mode (device mode or host mode). some of the bits in this register are valid only in host mode, while others are valid in device mode only. this register also indicates the current mode. to clear the interrupt status bits of the rc_w1 type, the application must write 1 into the bit. the fifo status interrupts are read-only; once software reads from or writes to the fifo while servicing these interrupts, fifo interrupt conditions are cleared automatically. the application must clear the otg_fs_gintsts register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization. 313029282726252423222120191817161514131211109876543210 wkuint srqint discint cidschg reserved ptxfe hcint hprtint reserved ipxfr/incompisoout iisoixfr oepint iepint reserved eopf isoodrp enumdne usbrst usbsusp esusp reserved goutnakeff ginakeff nptxfe rxflvl sof otgint mmis cmod rc_w1 rrr res.rc_w1rr rc_w1 rrrr rc_w1 r rc_w1 r bit 31 wkupint: resume/remote wakeup detected interrupt in device mode, this interrupt is asserted when a resume is detected on the usb. in host mode, this interrupt is asserted when a remote wakeup is detected on the usb. note: accessible in both device and host modes. bit 30 srqint: session request/new session detected interrupt in host mode, this interrupt is asserted when a session request is detected from the device. in device mode, this interrupt is asserted when v bus is in the valid range for a b-peripheral device. accessible in both device and host modes. bit 29 discint: disconnect detected interrupt asserted when a device disconnect is detected. note: only accessible in host mode. bit 28 cidschg: connector id status change the core sets this bit when there is a change in connector id status. note: accessible in both device and host modes. bit 27 reserved bit 26 ptxfe: periodic txfifo empty asserted when the periodic transmit fifo is eit her half or completely empty and there is space for at least one entry to be written in the period ic request queue. the half or completely empty status is determined by the periodic txfifo empty level bit in the otg_fs_gahbcfg register (ptxfelvl bit in otg_fs_gahbcfg). note: only accessible in host mode. RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 963/1317 bit 25 hcint: host channels interrupt the core sets this bit to indicate that an interrupt is pending on one of the channels of the core (in host mode). the application must read the otg_fs_haint register to determine the exact number of the channel on which the interrupt occurred, and then read the corresponding otg_fs_hcintx register to determine the exact cause of the interrupt. the application must clear the appropriate status bit in the ot g_fs_hcintx register to clear this bit. note: only accessible in host mode. bit 24 hprtint: host port interrupt the core sets this bit to indicate a change in port status of one of the otg_fs controller ports in host mode. the application must read the otg_fs_hprt register to determine the exact event that caused this interrupt. the applicati on must clear the appropriate status bit in the otg_fs_hprt register to clear this bit. note: only accessible in host mode. bits 23:22 reserved bit 21 ipxfr: incomplete periodic transfer in host mode, the core sets this interrupt bit when there are incomplete periodic transactions still pending, which are scheduled for the current frame. incompisoout: incomplete isochronous out transfer in device mode, the core sets this interrupt to indicate that there is at least one isochronous out endpoint on which the transfer is not comple ted in the current frame. this interrupt is asserted along with the end of periodic frame interrupt (eopf) bit in this register. bit 20 iisoixfr: incomplete isochronous in transfer the core sets this interrupt to indicate that there is at least one isochronous in endpoint on which the transfer is not completed in the current frame. this interrupt is asserted along with the end of periodic frame interrupt (eopf) bit in this register. note: only accessible in device mode. bit 19 oepint: out endpoint interrupt the core sets this bit to indica te that an interrupt is pending on one of the out endpoints of the core (in device mode). the application must read the otg_fs_daint register to determine the exact number of the out endpoint on which the interrupt occurred, and then read the corresponding otg_fs_doepintx regist er to determine the exact cause of the interrupt. the application must clear the ap propriate status bit in the corresponding otg_fs_doepintx register to clear this bit. note: only accessible in device mode. bit 18 iepint: in endpoint interrupt the core sets this bit to indicate that an interrupt is pending on one of the in endpoints of the core (in device mode). the application must read the otg_fs_daint register to determine the exact number of the in endpoint on which the interrupt occurred, and then read the corresponding otg_fs_diepintx register to det ermine the exact cause of the interrupt. the application must clear the appropriate stat us bit in the corresponding otg_fs_diepintx register to clear this bit. note: only accessible in device mode. bits 17:16 reserved bit 15 eopf: end of periodic frame interrupt indicates that the period specified in the peri odic frame interval field of the otg_fs_dcfg register (pfivl bit in otg_fs_dcfg) has been reached in the current frame. note: only accessible in device mode. usb on-the-go full-speed (otg_fs) RM0033 964/1317 doc id 15403 rev 3 bit 14 isoodrp: isochronous out packet dropped interrupt the core sets this bit when it fails to wr ite an isochronous out packet into the rxfifo because the rxfifo does not have enough space to accommodate a maximum size packet for the isochronous out endpoint. note: only accessible in device mode. bit 13 enumdne: enumeration done the core sets this bit to indicate that speed enumeration is complete. the application must read the otg_fs_dsts register to obtain the enumerated speed. note: only accessible in device mode. bit 12 usbrst: usb reset the core sets this bit to indicate that a reset is det ected on the usb. note: only accessible in device mode. bit 11 usbsusp: usb suspend the core sets this bit to indi cate that a suspend was detected on the usb. the core enters the suspended state when there is no activity on the data lines for a period of 3 ms. note: only accessible in device mode. bit 10 esusp: early suspend the core sets this bit to indicate that an idle state has been detected on the usb for 3 ms. note: only accessible in device mode. bits 9:8 reserved bit 7 gonakeff: global out nak effective indicates that the set global out nak bit in the otg_fs_dctl register (sgonak bit in otg_fs_dctl), set by the application, has taken effect in the core. this bit can be cleared by writing the clear global out nak bit in the otg_fs_dctl register (cgonak bit in otg_fs_dctl). note: only accessible in device mode. bit 6 ginakeff: global in non-periodic nak effective indicates that the set global non-periodic in nak bit in the otg_fs_dctl register (sginak bit in otg_fs_dctl), set by the application, has taken effect in the core. that is, the core has sampled the global in nak bit set by the applicat ion. this bit can be cleared by clearing the clear global non-periodic in nak bit in the otg_fs_dctl register (cginak bit in otg_fs_dctl). this interrupt does not necessarily mean that a nak handshake is sent out on the usb. the stall bit takes precedence over the nak bit. note: only accessible in device mode. bit 5 nptxfe: non-periodic txfifo empty this interrupt is asserted when the non-periodic tx fifo is either half or completely empty, and there is space for at least one entry to be writ ten to the non-periodic transmit request queue. the half or completely empty status is determi ned by the non-periodic txfifo empty level bit in the otg_fs_gahbcfg register (txfelvl bit in otg_fs_gahbcfg). note: accessible in host mode only. bit 4 rxflvl: rxfifo non-empty indicates that there is at least one pa cket pending to be read from the rxfifo. note: accessible in both host and device modes. RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 965/1317 bit 3 sof: start of frame in host mode, the core sets this bit to indi cate that an sof (fs), or keep-alive (ls) is transmitted on the usb. the ap plication must write a 1 to this bit to clear the interrupt. in device mode, in the core sets this bit to indicate that an sof token has been received on the usb. the application can read the device status register to get the current frame number. this interrupt is seen only when the core is operating in fs. note: accessible in both host and device modes. bit 2 otgint: otg interrupt the core sets this bit to indi cate an otg protocol event. the application must read the otg interrupt status (otg_fs_gotgint) register to determine the exact event that caused this interrupt. the application must clear the appr opriate status bit in the otg_fs_gotgint register to clear this bit. note: accessible in both host and device modes. bit 1 mmis: mode mismatch interrupt the core sets this bit when the application is trying to access: a host mode register, when the core is operating in device mode a device mode register, when the core is operating in host mode the register access is completed on the ahb with an okay response, but is ignored by the core internally and does not affect the operation of the core. note: accessible in both host and device modes. bit 0 cmod: current mode of operation indicates the current mode. 0: device mode 1: host mode note: accessible in both host and device modes. usb on-the-go full-speed (otg_fs) RM0033 966/1317 doc id 15403 rev 3 otg_fs interrupt mask register (otg_fs_gintmsk) address offset: 0x018 reset value: 0x0000 0000 this register works with the core interrupt register to interrupt the application. when an interrupt bit is masked, the interrupt associated with that bit is not generated. however, the core interrupt (otg_fs_gintsts) register bit corresponding to that interrupt is still set. 313029282726252423222120191817161514131211109876543210 wuim srqim discint cidschgm reserved ptxfem hcim prtim reserved ipxfrm/iisooxfrm iisoixfrm oepint iepint epmism reserved eopfm isoodrpm enumdnem usbrst usbsuspm esuspm reserved gonakeffm ginakeffm nptxfem rxflvlm sofm otgint mmism reserved rwrwrwrw rwrw r rwrwrwrwrw rwrwrwrwrwrw rwrwrwrwrwrwrw bit 31 wuim: resume/remote wakeup detected interrupt mask 0: masked interrupt 1: unmasked interrupt note: accessible in both host and device modes. bit 30 srqim: session request/new session detected interrupt mask 0: masked interrupt 1: unmasked interrupt note: accessible in both host and device modes. bit 29 discint: disconnect detected interrupt mask 0: masked interrupt 1: unmasked interrupt note: only accessible in device mode. bit 28 cidschgm: connector id status change mask 0: masked interrupt 1: unmasked interrupt note: accessible in both host and device modes. bit 27 reserved bit 26 ptxfem: periodic txfifo empty mask 0: masked interrupt 1: unmasked interrupt note: only accessible in host mode. bit 25 hcim: host channels interrupt mask 0: masked interrupt 1: unmasked interrupt note: only accessible in host mode. bit 24 prtim: host port interrupt mask 0: masked interrupt 1: unmasked interrupt note: only accessible in host mode. RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 967/1317 bits 23:22 reserved bit 21 ipxfrm: incomplete periodic transfer mask 0: masked interrupt 1: unmasked interrupt note: only accessible in host mode. iisooxfrm: incomplete isochronous out transfer mask 0: masked interrupt 1: unmasked interrupt note: only accessible in device mode. bit 20 iisoixfrm: incomplete isochronous in transfer mask 0: masked interrupt 1: unmasked interrupt note: only accessible in device mode. bit 19 oepint: out endpoints interrupt mask 0: masked interrupt 1: unmasked interrupt note: only accessible in device mode. bit 18 iepint: in endpoints interrupt mask 0: masked interrupt 1: unmasked interrupt note: only accessible in device mode. bit 17 epmism: endpoint mismatch interrupt mask 0: masked interrupt 1: unmasked interrupt note: only accessible in device mode. bit 16 reserved bit 15 eopfm: end of periodic frame interrupt mask 0: masked interrupt 1: unmasked interrupt note: only accessible in device mode. bit 14 isoodrpm: isochronous out packet dropped interrupt mask 0: masked interrupt 1: unmasked interrupt note: only accessible in device mode. bit 13 enumdnem: enumeration done mask 0: masked interrupt 1: unmasked interrupt note: only accessible in device mode. bit 12 usbrst: usb reset mask 0: masked interrupt 1: unmasked interrupt note: only accessible in device mode. usb on-the-go full-speed (otg_fs) RM0033 968/1317 doc id 15403 rev 3 bit 11 usbsuspm: usb suspend mask 0: masked interrupt 1: unmasked interrupt note: only accessible in device mode. bit 10 esuspm: early suspend mask 0: masked interrupt 1: unmasked interrupt note: only accessible in device mode. bits 9:8 reserved. bit 7 gonakeffm: global out nak effective mask 0: masked interrupt 1: unmasked interrupt note: only accessible in device mode. bit 6 ginakeffm: global non-periodic in nak effective mask 0: masked interrupt 1: unmasked interrupt note: only accessible in device mode. bit 5 nptxfem: non-periodic txfifo empty mask 0: masked interrupt 1: unmasked interrupt note: only accessible in host mode. bit 4 rxflvlm: receive fifo non-empty mask 0: masked interrupt 1: unmasked interrupt note: accessible in both device and host modes. bit 3 sofm: start of frame mask 0: masked interrupt 1: unmasked interrupt note: accessible in both device and host modes. bit 2 otgint: otg interrupt mask 0: masked interrupt 1: unmasked interrupt note: accessible in both device and host modes. bit 1 mmism: mode mismatch interrupt mask 0: masked interrupt 1: unmasked interrupt note: accessible in both device and host modes. bit 0 reserved RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 969/1317 otg_fs receive status debug read/otg status read and pop registers (otg_fs_grxstsr/otg_fs_grxstsp) address offset for read: 0x01c address offset for pop: 0x020 reset value: 0x0000 0000 a read to the receive status debug read register returns the contents of the top of the receive fifo. a read to the receive status read and pop register additionally pops the top data entry out of the rxfifo. the receive status contents must be interpreted differently in host and device modes. the core ignores the receive status pop/read when the receive fifo is empty and returns a value of 0x0000 0000. the application must only pop the receive status fifo when the receive fifo non-empty bit of the core interrupt register (rxflvl bit in otg_fs_gintsts) is asserted. host mode: 313029282726252423222120191817161514131211109876543210 reserved pktsts dpid bcnt chnum rr r r bits 31:21 reserved bits 20:17 pktsts: packet status indicates the status of the received packet 0010: in data packet received 0011: in transfer completed (triggers an interrupt) 0101: data toggle error (triggers an interrupt) 0111: channel halted (triggers an interrupt) others: reserved bits 16:15 dpid: data pid indicates the data pid of the received packet 00: data0 10: data1 01: data2 11: mdata bits 14:4 bcnt: byte count indicates the byte count of the received in data packet. bits 3:0 chnum: channel number indicates the channel number to which the current received packet belongs. usb on-the-go full-speed (otg_fs) RM0033 970/1317 doc id 15403 rev 3 device mode: otg_fs receive fifo size register (otg_fs_grxfsiz) address offset: 0x024 reset value: 0x0000 0200 the application can program the ram size that must be allocated to the rxfifo. 313029282726252423222120191817161514131211109876543210 reserved frmnum pktsts dpid bcnt epnum rrr r r bits 31:25 reserved bits 24:21 frmnum: frame number this is the least significant 4 bits of the fram e number in which the packet is received on the usb. this field is supported only when isochronous out endpoints are supported. bits 20:17 pktsts: packet status indicates the status of the received packet 0001: global out nak (triggers an interrupt) 0010: out data packet received 0011: out transfer completed (triggers an interrupt) 0100: setup transaction completed (triggers an interrupt) 0110: setup data packet received others: reserved bits 16:15 dpid: data pid indicates the data pid of the received out data packet 00: data0 10: data1 01: data2 11: mdata bits 14:4 bcnt: byte count indicates the byte count of the received data packet. bits 3:0 epnum: endpoint number indicates the endpoint number to which the current received packet belongs. 313029282726252423222120191817161514131211109876543210 reserved rxfd r/rw bits 31:16 reserved bits 15:0 rxfd: rxfifo depth this value is in terms of 32-bit words. minimum value is 16 maximum value is 256 the power-on reset value of this register is specified as the largest rx data fifo depth. RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 971/1317 otg_fs host non-periodic transmit fifo size register (otg_fs_hnptxfsiz)/endpoint 0 transmit fifo size (otg_fs_dieptxf0) address offset: 0x028 reset value: 0x0000 0200 host mode device mode otg_fs non-periodic transmit fifo/queue status register (otg_fs_hnptxsts) address offset: 0x02c reset value: 0x0008 0200 note: in device mode, this register is not valid. this read-only register contains the free spac e information for the non-periodic txfifo and the non-periodic transmit request queue. 313029282726252423222120191817161514131211109876543210 nptxfd/tx0fd nptxfsa/tx0fsa r/rw r/rw bits 31:16 nptxfd: non-periodic txfifo depth this value is in terms of 32-bit words. minimum value is 16 maximum value is 256 bits 15:0 nptxfsa: non-periodic transmit ram start address this field contains the memory start ad dress for non-periodic transmit fifo ram. bits 31:16 tx0fd: endpoint 0 txfifo depth this value is in terms of 32-bit words. minimum value is 16 maximum value is 256 bits 15:0 tx0fsa: endpoint 0 transmit ram start address this field contains the memory start ad dress for the endpoint 0 transmit fifo ram. 313029282726252423222120191817161514131211109876543210 reserved nptxqtop nptqxsav nptxfsav rr r bit 31 reserved usb on-the-go full-speed (otg_fs) RM0033 972/1317 doc id 15403 rev 3 otg_fs general core configuration register (otg_fs_gccfg) address offset: 0x038 reset value: 0x0000 0000 bits 30:24 nptxqtop: top of the non-periodic transmit request queue entry in the non-periodic tx request queue that is currently being processed by the mac. bits [30:27]: channel/endpoint number bits [26:25]: ? 00: in/out token ? 01: zero-length transmit packet (device in/host out) ? 11: channel halt command bit [24]: terminate (last entry for selected channel/endpoint) bits 23:16 nptqxsav: non-periodic transmit request queue space available indicates the amount of free space available in the non-periodic transmit request queue. this queue holds both in and out requests in host mode. device mode has only in requests. 00: non-periodic transmit request queue is full 01: dx1 location available 10: dx2 locations available bxn : dx n locations available (0 n dx8) others: reserved bits 15:0 nptxfsav: non-periodic txfifo space available indicates the amount of free space available in the non-periodic txfifo. values are in terms of 32-bit words. 00: non-periodic txfifo is full 01: dx1 word available 10: dx2 words available 0xn: dx n words available (where 0 n dx256) others: reserved 313029282726252423222120191817161514131211109876543210 reserved sofouten vbusbsen vbusasen reserved .pwrdwn reserved rw rw rw rw RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 973/1317 otg_fs core id register (otg_fs_cid) address offset: 0x03c reset value:0x0000 1100 this is a read only register containing the product id. otg_fs host periodic transmit fifo size register (otg_fs_hptxfsiz) address offset: 0x100 reset value: 0x0200 0600 bits 31:22 reserved bit 21 novbussens : v bus sensing disable option when this bit is set, v bus is considered internally to be always at v bus valid level (5 v). this option removes the need for a dedicated v bus pad, and leave this pad free to be used for other purposes such as a shared functionality. v bus connection can be remapped on another general purpose input pad and monitored by software. this option is only suitable for host-only or device-only applications. 0: v bus sensing available by hardware 1: v bus sensing not available by hardware. bit 20 sofouten: sof output enable 0: sof pulse not available on pad 1: sof pulse available on pad bit 19 vbusbsen: enable the v bus sensing ?b? device 0: v bus sensing ?b? disabled 1: v bus sensing ?b? enabled bit 18 vbusasen: enable the v bus sensing ?a? device 0: v bus sensing ?a? disabled 1: v bus sensing ?a? enabled bit 17 reserved bit 16 pwrdwn: power down used to activate the transceiver in transmission/reception 0: power down active 1: power down deactivated (?transceiver active?) bits 15:0 reserved. 313029282726252423222120191817161514131211109876543210 product_id rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:0 product_id: product id field application-programmable id field. usb on-the-go full-speed (otg_fs) RM0033 974/1317 doc id 15403 rev 3 313029282726252423222120191817161514131211109876543210 ptxfsiz ptxsa r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w bits 31:16 ptxfd: host periodic txfifo depth this value is in terms of 32-bit words. minimum value is 16 bits 15:0 ptxsa: host periodic txfifo start address the power-on reset value of this register is the sum of the largest rx data fifo depth and largest non-periodic tx data fifo depth. RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 975/1317 otg_fs device in endpoint transmit fifo size register (otg_fs_dieptxfx) (x = 1..3, where x is the fifo_number) address offset: 0x104 + (fifo_number ? 1) 0x04 reset value: 0x02000400 29.16.3 host-mode registers bit values in the register descriptions are expressed in binary unless otherwise specified. host-mode registers affect the operation of the core in the host mode. host mode registers must not be accessed in device mode, as the results are undefined. host mode registers can be categorized as follows: otg_fs host configuration register (otg_fs_hcfg) address offset: 0x400 reset value: 0x0000 0000 this register configures the core after power-on. do not make changes to this register after initializing the host. 313029282726252423222120191817161514131211109876543210 ineptxfd ineptxsa r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w bits 31:16 ineptxfd: in endpoint txfifo depth this value is in terms of 32-bit words. minimum value is 16 the power-on reset value of this register is s pecified as the largest in endpoint fifo number depth. bits 15:0 ineptxsa: in endpoint fifox transmit ram start address this field contains the memory start address for in endpoint transmit fifox. 313029282726252423222120191817161514131211109876543210 reserved fslss fslspcs rrwrw bits 31:3 reserved bit 2 fslss: fs- and ls-only support the application uses this bit to control the co re?s enumeration speed. using this bit, the application can make the core enumerate as an fs host, even if the connected device supports hs traffic. do not make changes to this field after initial programming. 1: fs/ls-only, even if the connect ed device can support hs (read-only) usb on-the-go full-speed (otg_fs) RM0033 976/1317 doc id 15403 rev 3 otg_fs host frame interval register (otg_fs_hfir) address offset: 0x404 reset value: 0x0000 ea60 this register stores the frame interval information for the current speed to which the otg_fs controller has enumerated. bits 1:0 fslspcs: fs/ls phy clock select when the core is in fs host mode 01: phy clock is running at 48 mhz others: reserved when the core is in ls host mode 00: reserved 01: select 48 mhz phy clock frequency 10: select 6 mhz phy clock frequency 11: reserved note: the fslspcs must be set on a connection event according to the speed of the connected device (after changing this bit, a software reset must be performed). 313029282726252423222120191817161514131211109876543210 reserved frivl rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:16 reserved bits 15:0 frivl: frame interval the value that the application programs to th is field specifies the interval between two consecutive sofs (fs) or keep-alive tokens (ls). this field contains the number of phy clocks that constitute the required frame interval. the application can write a value to this register only after the port enable bit of the ho st port control and status register (pena bit in otg_fs_hprt) has been set. if no value is prog rammed, the core calculates the value based on the phy clock specified in the fs/ls phy clock select field of the host configuration register (fslspcs in otg_fs_hcfg). do not ch ange the value of this field after the initial configuration. 1 ms (phy clock frequency) RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 977/1317 otg_fs host frame number/frame time remaining register (otg_fs_hfnum) address offset: 0x408 reset value: 0x0000 3fff this register indicates the current frame number. it also indicates the time remaining (in terms of the number of phy clocks) in the current frame. otg_fs_host periodic transmit fifo/queue status register (otg_fs_hptxsts) address offset: 0x410 reset value: 0x0008 0100 this read-only register contains the free space information for the periodic txfifo and the periodic transmit request queue. 313029282726252423222120191817161514131211109876543210 ftrem frnum rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr bits 31:16 ftrem: frame time remaining indicates the amount of time remaining in the cu rrent frame, in terms of phy clocks. this field decrements on each phy clock. when it reaches zero, this field is reloaded with the value in the frame interval register and a new sof is transmitted on the usb. bits 15:0 frnum: frame number this field increments when a new sof is transmitt ed on the usb, and is cleared to 0 when it reaches 0x3fff. 313029282726252423222120191817161514131211109876543210 ptxqtop ptxqsav ptxfsavl rrrrrrrrrrrrrrrrrwrwrwrwrwrwrwrwrwrwrwrwrwrwrwrw bits 31:24 ptxqtop: top of the periodic transmit request queue this indicates the entry in the periodic tx re quest queue that is currently being processed by the mac. this register is used for debugging. bit [31]: odd/even frame ? 0: send in even frame ? 1: send in odd frame bits [30:27]: channel/endpoint number bits [26:25]: type ? 00: in/out ? 01: zero-length packet ? 11: disable channel command bit [24]: terminate (last entry for the selected channel/endpoint) usb on-the-go full-speed (otg_fs) RM0033 978/1317 doc id 15403 rev 3 otg_fs host all channels interrupt register (otg_fs_haint) address offset: 0x414 reset value: 0x0000 000 when a significant event occurs on a channel, the host all channels interrupt register interrupts the application using the host channels interrupt bit of the core interrupt register (hcint bit in otg_fs_gintsts). this is shown in figure 356 . there is one interrupt bit per channel, up to a maximum of 16 bits. bits in this register are set and cleared when the application sets and clears bits in the corresponding host channel-x interrupt register. bits 23:16 ptxqsav: periodic transmit request queue space available indicates the number of free locations available to be written in the periodic transmit request queue. this queue holds both in and out requests. 00: periodic transmit request queue is full 01: dx1 location available 10: dx2 locations available bxn: dxn locations available (0 dxn 8) others: reserved bits 15:0 ptxfsavl: periodic transmit data fifo space available indicates the number of free locations availabl e to be written to in the periodic txfifo. values are in terms of 32-bit words 0000: periodic txfifo is full 0001: dx1 word available 0010: dx2 words available bxn: dxn words available (where 0 dxn ptxfd) others: reserved 313029282726252423222120191817161514131211109876543210 reserved haint rrrrrrrrrrrrrrrr bits 31:16 reserved bits 15:0 haint: channel interrupts one bit per channel: bit 0 for channel 0, bit 15 for channel 15 RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 979/1317 otg_fs host all channels interrupt mask register (otg_fs_haintmsk) address offset: 0x418 reset value: 0x0000 0000 the host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. there is one interrupt mask bit per channel, up to a maximum of 16 bits. otg_fs host port control and status register (otg_fs_hprt) address offset: 0x440 reset value: 0x0000 0000 this register is available only in host mode. currently, the otg host supports only one port. a single register holds usb port-related information such as usb reset, enable, suspend, resume, connect status, and test mode for each port. it is shown in figure 356 . the rc_w1 bits in this register can trigger an interrupt to the application through the host port interrupt bit of the core interrupt register (hprtint bit in otg_fs_gintsts). on a port interrupt, the application must read this register and clear the bit that caused the interrupt. for the rc_w1 bits, the application must write a 1 to the bit to clear the interrupt. 313029282726252423222120191817161514131211109876543210 reserved haintm rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:16 reserved bits 15:0 haintm: channel interrupt mask 0: masked interrupt 1: unmasked interrupt one bit per channel: bit 0 for channel 0, bit 15 for channel 15 313029282726252423222120191817161514131211109876 5 43210 reserved pspd ptctl ppwr plsts reserved prst psusp pres pocchng poca penchng pena pcdet pcsts r r rw rw rw rw rw r r rw rs rw rc_ w1 r rc_ w1 rc_ w0 rc_ w1 r bits 31:19 reserved bits 18:17 pspd: port speed indicates the speed of the device attached to this port. 01: full speed 10: low speed 11: reserved usb on-the-go full-speed (otg_fs) RM0033 980/1317 doc id 15403 rev 3 bits 16:13 ptctl: port test control the application writes a nonzero value to this field to put the port into a test mode, and the corresponding pattern is signaled on the port. 0000: test mode disabled 0001: test_j mode 0010: test_k mode 0011: test_se0_nak mode 0100: test_packet mode 0101: test_force_enable others: reserved bit 12 ppwr: port power the application uses this field to control power to this port, and the core clears this bit on an overcurrent condition. 0: power off 1: power on bits 11:10 plsts: port line status indicates the current logic level usb data lines bit [10]: logic level of otg_fs_fs_dp bit [11]: logic level of otg_fs_fs_dm bit 9 reserved bit 8 prst: port reset when the application sets this bit, a reset seque nce is started on this port. the application must time the reset period and clear this bit after the reset sequence is complete. 0: port not in reset 1: port in reset the application must leave this bit set for a minimum duration of at least 10 ms to start a reset on the port. the application can leave it set fo r another 10 ms in addition to the required minimum duration, before clearing the bit, even though there is no maximum limit set by the usb standard. bit 7 psusp: port suspend the application sets this bit to put this port in suspend mode. the core only stops sending sofs when this is set. to stop the phy clock, the application must set the port clock stop bit, which asserts the suspend input pin of the phy. the read value of this bit reflects the current su spend status of the port. this bit is cleared by the core after a remote wakeup signal is detected or the application sets the port reset bit or port resume bit in this register or the re sume/remote wakeup detected interrupt bit or disconnect detected interrupt bit in the core interrupt register (wkuint or discint in otg_fs_gintsts, respectively). 0: port not in suspend mode 1: port in suspend mode RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 981/1317 bit 6 pres: port resume the application sets this bit to drive resume signaling on the port. the core continues to drive the resume signal until the application clears this bit. if the core detects a usb remote wakeup sequence, as indicated by the port resume/remote wakeup detected interrupt bit of the core interrupt register (wkuint bit in otg_fs_gintsts), the core starts driving resu me signaling without application intervention and clears this bit when it detects a disconnect condition. the read value of this bit indicates whether the core is currently driving resume signaling. 0: no resume driven 1: resume driven bit 5 pocchng: port overcurrent change the core sets this bit when the status of the port overcurrent active bit (bit 4) in this register changes. bit 4 poca: port overcurrent active indicates the overcurrent condition of the port. 0: no overcurrent condition 1: overcurrent condition bit 3 penchng: port enable/disable change the core sets this bit when the status of t he port enable bit [2] in this register changes. bit 2 pena: port enable a port is enabled only by the core after a reset sequence, and is disabled by an overcurrent condition, a disconnect condition, or by the app lication clearing this bit. the application cannot set this bit by a register write. it can only clear it to disable the port. this bit does not trigger any interrupt to the application. 0: port disabled 1: port enabled bit 1 pcdet: port connect detected the core sets this bit when a device connection is detected to trigge r an interrupt to the application using the host port interrupt bit in the core interrupt register (hprtint bit in otg_fs_gintsts). the application must write a 1 to this bit to clear the interrupt. bit 0 pcsts: port connect status 0: no device is attached to the port 1: a device is attached to the port usb on-the-go full-speed (otg_fs) RM0033 982/1317 doc id 15403 rev 3 otg_fs host channel-x characteristics register (otg_fs_hccharx) (x = 0..7, where x = channel_number) address offset: 0x500 + (channel_number 0x20) reset value: 0x0000 0000 313029282726252423222120191817161514131211109876543210 chena chdis oddfrm dad mcnt eptyp lsdev reserved epdir epnum mpsiz rs rs rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bit 31 chena: channel enable this field is set by the application and cleared by the otg host. 0: channel disabled 1: channel enabled bit 30 chdis: channel disable the application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. the application must wait for the channel disabled interrupt before treating the channel as disabled. bit 29 oddfrm: odd frame this field is set (reset) by the application to indicate that the otg host must perform a transfer in an odd frame. this field is applicable for only periodic (isochronous and interrupt) transactions. 0: even frame 1: odd frame bits 28:22 dad: device address this field selects the specific device serving as the data source or sink. bits 21:20 mcnt: multicount this field indicates to the host the number of tr ansactions that must be executed per frame for this periodic endpoint. for non-periodic transfers, this field is not used 00: reserved. this field yields undefined results 01: 1 transaction 10: 2 transactions per frame to be issued for this endpoint 11: 3 transactions per frame to be issued for this endpoint note: this field must be set to at least 01. bits 19:18 eptyp: endpoint type indicates the transfer type selected. 00: control 01: isochronous 10: bulk 11: interrupt bit 17 lsdev: low-speed device this field is set by the application to indicate that this channel is communicating to a low- speed device. bit 16 reserved RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 983/1317 otg_fs host channel-x interrupt register (otg_fs_hcintx) (x = 0..7, where x = channel_number) address offset: 0x508 + (channel_number 0x20) reset value: 0x0000 0000 this register indicates the status of a channel with respect to usb- and ahb-related events. it is shown in figure 356 . the application must read this register when the host channels interrupt bit in the core interrupt register ( hcint bit in otg_fs_gin tsts) is set. before the application can read this register, it must first read the host all channels interrupt (otg_fs_haint) register to get the exact channel number for the host channel-x interrupt register. the application must clear the appropriate bit in this register to clear the corresponding bits in the otg_fs_haint and otg_fs_gintsts registers. bit 15 epdir: endpoint direction indicates whether the transaction is in or out. 0: out 1: in bits 14:11 epnum: endpoint number indicates the endpoint number on the device serving as the data source or sink. bits 10:0 mpsiz: maximum packet size indicates the maximum packet size of the associated endpoint. 313029282726252423222120191817161514131211109876543210 reserved dterr frmor bberr txerr reserved ack nak stall reserved chh xfrc rc_ w1 rc_ w1 rc_ w1 rc_ w1 rc_ w1 rc_ w1 rc_ w1 rc_ w1 rc_ w1 bits 31:11 reserved bit 10 dterr: data toggle error bit 9 frmor: frame overrun bit 8 bberr: babble error bit 7 txerr: transaction error indicates one of the following errors occurred on the usb. crc check failure timeout bit stuff error false eop bit 6 reserved bit 5 ack: ack response received/transmitted interrupt bit 4 nak: nak response received interrupt bit 3 stall: stall response received interrupt usb on-the-go full-speed (otg_fs) RM0033 984/1317 doc id 15403 rev 3 otg_fs host channel-x interrupt mask register (otg_fs_hcintmskx) (x = 0..7, where x = channel_number) address offset: 0x50c + (channel_number 0x20) reset value: 0x0000 0000 this register reflects the mask for each channel status described in the previous section. bit 2 reserved bit 1 chh: channel halted indicates the transfer completed abnormally either because of any usb transaction error or in response to disable request by the application. bit 0 xfrc: transfer completed transfer completed normally without any errors. 313029282726252423222120191817161514131211109876543210 reserved dterrm frmorm bberrm txerrm nyet ackm nakm stallm reserved chhm xfrcm rw rw rw rw rw rw rw rw rw rw bits 31:11 reserved bit 10 dterrm: data toggle error mask 0: masked interrupt 1: unmasked interrupt bit 9 frmorm: frame overrun mask 0: masked interrupt 1: unmasked interrupt bit 8 bberrm: babble error mask 0: masked interrupt 1: unmasked interrupt bit 7 txerrm: transaction error mask 0: masked interrupt 1: unmasked interrupt bit 6 nyet: response received interrupt mask 0: masked interrupt 1: unmasked interrupt bit 5 ackm: ack response received/transmitted interrupt mask 0: masked interrupt 1: unmasked interrupt bit 4 nakm: nak response received interrupt mask 0: masked interrupt 1: unmasked interrupt bit 3 stallm: stall response received interrupt mask 0: masked interrupt 1: unmasked interrupt RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 985/1317 otg_fs host channel-x transfer size register (otg_fs_hctsizx) (x = 0..7, where x = channel_number) address offset: 0x510 + (channel_number 0x20) reset value: 0x0000 0000 bit 2 reserved bit 1 chhm: channel halted mask 0: masked interrupt 1: unmasked interrupt bit 0 xfrcm: transfer completed mask 0: masked interrupt 1: unmasked interrupt 313029282726252423222120191817161514131211109876543210 reserved dpid pktcnt xfrsiz rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bit 31 reserved bits 30:29 dpid: data pid the application programs this fiel d with the type of pid to use for the initial transaction. the host maintains this field for the rest of the transfer. 00: data0 01: data2 10: data1 11: mdata (non-control)/setup (control) bits 28:19 pktcnt: packet count this field is programmed by the application with the expected number of packets to be transmitted (out) or received (in). the host decrements this count on every successf ul transmission or reception of an out/in packet. once this count reaches zero, the application is interrupted to indicate normal completion. bits 18:0 xfrsiz: transfer size for an out, this field is the number of data bytes the host sends during the transfer. for an in, this field is the buffer size that the application has reserved for the transfer. the application is expected to program this field as an integer multiple of the maximum packet size for in transactions (periodic and non-periodic). usb on-the-go full-speed (otg_fs) RM0033 986/1317 doc id 15403 rev 3 29.16.4 device-mode registers otg_fs device configuration register (otg_fs_dcfg) address offset: 0x800 reset value: 0x0220 0000 this register configures the core in device mode after power-on or after certain control commands or enumeration. do not make changes to this register after initial programming. 313029282726252423222120191817161514131211109876543210 reserved pfivl dad reserved nzlsohsk dspd rw rw rw rw rw rw rw rw rw rw rw bits 31:13 reserved bits 12:11 pfivl: periodic frame interval indicates the time within a frame at which the application must be notified using the end of periodic frame interrupt. this can be used to determine if all the isochronous traffic for that frame is complete. 00: 80% of the frame interval 01: 85% of the frame interval 10: 90% of the frame interval 11: 95% of the frame interval bits 10:4 dad: device address the application must program this field after every setaddress control command. bit 3 reserved bit 2 nzlsohsk: non-zero-length status out handshake the application can use this field to select the handshake the core sends on receiving a nonzero-length data packet during the out tran saction of a control transfer?s status stage. 1: send a stall handshake on a nonzero-length status out transaction and do not send the received out packet to the application. 0: send the received out packet to the applic ation (zero-length or nonzero-length) and send a handshake based on the nak and stall bits for the endpoint in the device endpoint control register. bits 1:0 dspd: device speed indicates the speed at which the application requires the core to enumerate, or the maximum speed the application can support. however, the actual bus speed is determined only after the chirp sequence is completed, and is based on th e speed of the usb host to which the core is connected. 00: reserved 01: reserved 10: reserved 11: full speed (usb 1.1 transceiver clock is 48 mhz) RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 987/1317 otg_fs device control register (otg_fs_dctl) address offset: 0x804 reset value: 0x0000 0000 313029282726252423222120191817161514131211109876543210 reserved poprgdne cgonak sgonak cginak sginak tctl gonsts ginsts sdis rwusig rwwwwwrwrwrwr rrwrw bits 31:12 reserved bit 11 poprgdne: power-on programming done the application uses this bit to indicate that re gister programming is completed after a wakeup from power down mode. bit 10 cgonak: clear global out nak a write to this field clears the global out nak. bit 9 sgonak: set global out nak a write to this field sets the global out nak. the application uses this bit to send a nak handshake on all out endpoints. the application must set the this bit only after making sure that the global out nak effective bit in the core interrupt register (gonakeff bit in otg_fs_gintsts) is cleared. bit 8 cginak: clear global in nak a write to this field clears the global in nak. bit 7 sginak: set global in nak a write to this field sets the global non-periodic in nak.the application uses this bit to send a nak handshake on all non-periodic in endpoints. the application must set this bit only after making sure that the global in nak effective bit in the core interrupt regist er (ginakeff bit in otg_fs_gintsts) is cleared. bits 6:4 tctl: test control 000: test mode disabled 001: test_j mode 010: test_k mode 011: test_se0_nak mode 100: test_packet mode 101: test_force_enable others: reserved bit 3 gonsts: global out nak status 0: a handshake is sent based on the fifo status and the nak and stall bit settings. 1: no data is written to the rxfifo, irresp ective of space availability. sends a nak handshake on all packets, except on setup transactions. all isochronous out packets are dropped. usb on-the-go full-speed (otg_fs) RM0033 988/1317 doc id 15403 rev 3 table 153 contains the minimum duration (according to device state) for which the soft disconnect (sdis) bit must be set for the usb host to detect a device disconnect. to accommodate clock jitter, it is recommended that the application add some extra delay to the specified minimum duration. otg_fs device status register (otg_fs_dsts) address offset: 0x808 reset value: 0x0000 0010 this register indicates the status of the core with respect to usb-related events. it must be read on interrupts from the device all interrupts (otg_fs_daint) register. bit 2 ginsts: global in nak status 0: a handshake is sent out based on the data availability in the transmit fifo. 1: a nak handshake is sent out on all non-periodic in endpoints, irrespective of the data availability in the transmit fifo. bit 1 sdis: soft disconnect the application uses this bit to signal the usb otg core to perform a soft disconnect. as long as this bit is set, the host does not see that the device is connected, and the device does not receive signals on the usb. the core sta ys in the disconnected st ate until the application clears this bit. 0: normal operation. when this bit is cleared after a soft disconnect, the core generates a device connect event to the usb host. when the device is reconnected, the usb host restarts device enumeration. 1: the core generates a device disconnect event to the usb host. bit 0 rwusig: remote wakeup signaling when the application sets this bit, the core initiates remote signaling to wake up the usb host. the application must set this bit to instruct the core to exit the suspend state. as specified in the usb 2.0 specification, the application must clear this bit 1 ms to 15 ms after setting it. table 153. minimum duration for soft disconnect operating speed device state minimum duration full speed suspended 1 ms + 2.5 s full speed idle 2.5 s full speed not idle or suspended (performing transactions) 2.5 s 313029282726252423222120191817161514131211109876543210 reserved fnsof reserved eerr enumspd suspsts rrrrrrrrrrrrrr rrrr bits 31:22 reserved bits 21:8 fnsof: frame number of the received sof bits 7:4 reserved RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 989/1317 otg_fs device in endpoint common interrupt mask register (otg_fs_diepmsk) address offset: 0x810 reset value: 0x0000 0000 this register works with each of the otg_fs_diepintx registers for all endpoints to generate an interrupt per in endpoint. the in endpoint interrupt for a specific status in the otg_fs_diepintx register can be masked by writing to the corresponding bit in this register. status bits are masked by default. bit 3 eerr: erratic error the core sets this bit to report any erratic errors. due to erratic errors, the otg_fs controller goes into suspended state and an interrupt is generated to the application with early suspend bit of the otg_fs_gintsts register (esusp bit in otg_fs_gintsts). if the early suspend is asserted due to an erratic error, the application can only perform a soft disconnect recover. bits 2:1 enumspd: enumerated speed indicates the speed at which the otg_fs co ntroller has come up after speed detection through a chirp sequence. 01: reserved 10: reserved 11: full speed (phy clock is running at 48 mhz) others: reserved bit 0 suspsts: suspend status in device mode, this bit is set as long as a suspend condition is detected on the usb. the core enters the suspended state when t here is no activity on the usb data lines for a period of 3 ms. the core comes out of the suspend: ? when there is an activity on the usb data lines ? when the application writes to the remote wakeup signaling bit in the otg_fs_dctl register (rwusig bit in otg_fs_dctl). 313029282726252423222120191817161514131211109876543210 reserved inepnem inepnmm ittxfemsk tom reserved epdm xfrcm rw rw rw rw rw rw bits 31:7 reserved bit 6 inepnem: in endpoint nak effective mask 0: masked interrupt 1: unmasked interrupt bit 5 inepnmm: in token received with ep mismatch mask 0: masked interrupt 1: unmasked interrupt bit 4 ittxfemsk: in token received when txfifo empty mask 0: masked interrupt 1: unmasked interrupt usb on-the-go full-speed (otg_fs) RM0033 990/1317 doc id 15403 rev 3 otg_fs device out endpoint common interrupt mask register (otg_fs_doepmsk) address offset: 0x814 reset value: 0x0000 0000 this register works with each of the otg_fs_doepintx registers for all endpoints to generate an interrupt per out endpoint. the out endpoint interrupt for a specific status in the otg_fs_doepintx register can be masked by writing into the corresponding bit in this register. status bits are masked by default. bit 3 tom: timeout condition mask (non-isochronous endpoints) 0: masked interrupt 1: unmasked interrupt bit 2 reserved bit 1 epdm: endpoint disabled interrupt mask 0: masked interrupt 1: unmasked interrupt bit 0 xfrcm: transfer completed interrupt mask 0: masked interrupt 1: unmasked interrupt 313029282726252423222120191817161514131211109876543210 reserved otepdm stupm reserved epdm xfrcm rw rw rw rw bits 31:5 reserved bit 4 otepdm: out token received when endpoint disabled mask applies to control out endpoints only. 0: masked interrupt 1: unmasked interrupt bit 3 stupm: setup phase done mask applies to control endpoints only. 0: masked interrupt 1: unmasked interrupt bit 2 reserved bit 1 epdm: endpoint disabled interrupt mask 0: masked interrupt 1: unmasked interrupt bit 0 xfrcm: transfer completed interrupt mask 0: masked interrupt 1: unmasked interrupt RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 991/1317 otg_fs device all endpoints interrupt register (otg_fs_daint) address offset: 0x818 reset value: 0x0000 0000 when a significant event occurs on an endpoint, a otg_fs_daint register interrupts the application using the device out endpoints interrupt bit or device in endpoints interrupt bit of the otg_fs_gintsts register (oepint or iepint in otg_fs_gintsts, respectively). there is one interrupt bit per endpoint, up to a maximum of 16 bits for out endpoints and 16 bits for in endpoints. for a bidirectional endpoint, the corresponding in and out interrupt bits are used. bits in this register are set and cleared when the application sets and clears bits in the corres ponding device endpoint-x interrupt register (otg_fs_diepintx/otg_fs_doepintx). 313029282726252423222120191817161514131211109876543210 oepint iepint rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr bits 31:16 oepint: out endpoint interrupt bits one bit per out endpoint: bit 16 for out endpoint 0, bit 18 for out endpoint 3. bits 15:0 iepint: in endpoint interrupt bits one bit per in endpoint: bit 0 for in endpoint 0, bit 3 for endpoint 3. usb on-the-go full-speed (otg_fs) RM0033 992/1317 doc id 15403 rev 3 otg_fs all endpoints interrupt mask register (otg_fs_daintmsk) address offset: 0x81c reset value: 0x0000 0000 the otg_fs_daintmsk register works with the device endpoint interrupt register to interrupt the application when an event occurs on a device endpoint. however, the otg_fs_daint register bit correspondi ng to that interrupt is still set. otg_fs device v bus discharge time register (otg_fs_dvbusdis) address offset: 0x0828 reset value: 0x0000 17d7 this register specifies the v bus discharge time after v bus pulsing during srp. 313029282726252423222120191817161514131211109876543210 oepm iepm rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:16 oepm: out ep interrupt mask bits one per out endpoint: bit 16 for out ep 0, bit 18 for out ep 3 0: masked interrupt 1: unmasked interrupt bits 15:0 iepm: in ep interrupt mask bits one bit per in endpoint: bit 0 for in ep 0, bit 3 for in ep 3 0: masked interrupt 1: unmasked interrupt 313029282726252423222120191817161514131211109876543210 reserved vbusdt rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:16 reserved bits 15:0 vbusdt: device v bus discharge time specifies the v bus discharge time after v bus pulsing during srp. this value equals: v bus discharge time in phy clocks / 1 024 depending on your v bus load, this value may need adjusting. RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 993/1317 otg_fs device v bus pulsing time register (otg_fs_dvbuspulse) address offset: 0x082c reset value: 0x0000 05b8 this register specifies the v bus pulsing time during srp. otg_fs device in endpoint fifo empty interrupt mask register: (otg_fs_diepempmsk) address offset: 0x834 reset value: 0x0000 0000 this register is used to control the in endpoint fifo empty interrupt generation (txfe_otg_fs_diepintx). 313029282726252423222120191817161514131211109876543210 reserved dvbusp rw rw rw rw rw rw rw rw rw rw rw rw bits 31:12 reserved bits 11:0 dvbusp: device v bus pulsing time specifies the v bus pulsing time during srp. this value equals: v bus pulsing time in phy clocks / 1 024 313029282726252423222120191817161514131211109876543210 reserved ineptxfem rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:16 reserved bits 15:0 ineptxfem: in ep tx fifo empty interrupt mask bits these bits act as mask bits for otg_fs_diepintx. txfe interrupt one bit per in endpoint: bit 0 for in endpoint 0, bit 3 for in endpoint 3 0: masked interrupt 1: unmasked interrupt usb on-the-go full-speed (otg_fs) RM0033 994/1317 doc id 15403 rev 3 otg_fs device control in endpoint 0 control register (otg_fs_diepctl0) address offset: 0x900 reset value: 0x0000 0000 this section describes the otg_fs_diepctl0 register. nonzero control endpoints use registers for endpoints 1?3. 313029282726252423222120191817161514131211109876543210 epena epdis reserved snak cnak txfnum stall reserved eptyp naksts reserved usbaep reserved mpsiz r r w w rw rw rw rw rs r r r r rw rw bit 31 epena: endpoint enable the application sets this bit to start transmitting data on the endpoint 0. the core clears this bit before setting any of the following interrupts on this endpoint: ? endpoint disabled ? transfer completed bit 30 epdis: endpoint disable the application sets this bit to stop transmitti ng data on an endpoint, even before the transfer for that endpoint is complete. the application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. the core clears this bit before setting the endpoint disabled interrupt. the application must set this bit only if endpoint enable is already set for this endpoint. bits 29:28 reserved bit 27 snak: set nak a write to this bit sets the nak bit for the endpoint. using this bit, the application can control the transmission of nak handshakes on an endpoint. the core can also set this bit for an endpoint after a setup packet is received on that endpoint. bit 26 cnak: clear nak a write to this bit clears the nak bit for the endpoint. bits 25:22 txfnum: txfifo number this value is set to the fifo number that is assigned to in endpoint 0. bit 21 stall: stall handshake the application can only set this bit, and the core clears it when a setup token is received for this endpoint. if a nak bit, a global in nak or global out nak is set along with this bit, the stall bit takes priority. bit 20 reserved bits 19:18 eptyp: endpoint type hardcoded to ?00? for control. RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 995/1317 otg device endpoint-x control register (otg_fs_diepctlx) (x = 1..3, where x = endpoint_number) address offset: 0x900 + (endpoint_number 0x20) reset value: 0x0000 0000 the application uses this register to control th e behavior of each logical endpoint other than endpoint 0. bit 17 naksts: nak status indicates the following: 0: the core is transmitting non-nak handshakes based on the fifo status 1: the core is transmitting nak handshakes on this endpoint. when this bit is set, either by the application or core, the core stops transmitting data, even if there are data available in the txfifo. irrespective of this bit?s setting, the core always responds to setup data packets with an ack handshake. bit 16 reserved bit 15 usbaep: usb active endpoint this bit is always set to 1, indicating that control endpoint 0 is always active in all configurations and interfaces. bits 14:2 reserved bits 1:0 mpsiz: maximum packet size the application must program this field with t he maximum packet size for the current logical endpoint. 00: 64 bytes 01: 32 bytes 10: 16 bytes 11: 8 bytes 313029282726252423222120191817161514131211109876543210 epena epdis soddfrm sd0pid/sevnfrm snak cnak txfnum stall reserved eptyp naksts eonum/dpid usbaep reserved mpsiz rsrswwwwrwrwrwrw rw/ rs rw rw r r rw rw rw rw rw rw rw rw rw rw rw rw bit 31 epena: endpoint enable the application sets this bit to start transmitting data on an endpoint. the core clears this bit before setting any of the following interrupts on this endpoint: ? setup phase done ? endpoint disabled ? transfer completed usb on-the-go full-speed (otg_fs) RM0033 996/1317 doc id 15403 rev 3 bit 30 epdis: endpoint disable the application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. the app lication must wait for the endpoint disabled interrupt before treating the endpoint as disabled. the core clears this bit before setting the endpoint disabled interrupt. the application must set this bit only if endpoint enable is already set for this endpoint. bit 29 soddfrm: set odd frame applies to isochronous in and out endpoints only. writing to this field sets the even /odd frame (eonum) field to odd frame. bit 28 sd0pid: set data0 pid applies to interrupt/bulk in endpoints only. writing to this field sets the endpoint data pid (dpid) field in this register to data0. sevnfrm: set even frame applies to isochronous in endpoints only. writing to this field sets the even/odd frame (eonum) field to even frame. bit 27 snak: set nak a write to this bit sets the nak bit for the endpoint. using this bit, the application can control the transmission of nak handshakes on an endpoint. the core can also set this bit for out endpoints on a transfer completed interrupt, or after a setup is received on the endpoint. bit 26 cnak: clear nak a write to this bit clears the nak bit for the endpoint. bits 25:22 txfnum: txfifo number these bits specify the fifo nu mber associated with this endpoint. each active in endpoint must be programmed to a separate fifo number. this field is valid only for in endpoints. bit 21 stall: stall handshake applies to non-control, non-isochronous in endpoints only (access type is rw). the application sets this bit to stall all tokens from the usb host to this endpoint. if a nak bit, global in nak, or global out nak is set along with this bit, the stall bit takes priority. only the application can clear this bit, never the core. applies to control endpoints only (access type is rs). the application can only set this bit, and the core clears it, when a setup token is received for this endpoint. if a nak bit, global in nak, or global out nak is set along with this bit, the stall bit takes priority. irrespective of this bit?s setting, the core always responds to setup data packets with an ack handshake. bit 20 reserved bits 19:18 eptyp: endpoint type this is the transfer type supported by this logical endpoint. 00: control 01: isochronous 10: bulk 11: interrupt RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 997/1317 bit 17 naksts: nak status it indicates the following: 0: the core is transmitting non-nak handshakes based on the fifo status. 1: the core is transmitting nak handshakes on this endpoint. when either the application or the core sets this bit: for non-isochronous in endpoints: the core st ops transmitting any data on an in endpoint, even if there are data av ailable in the txfifo. for isochronous in endpoints: the core sends out a zero-length data packet, even if there are data available in the txfifo. irrespective of this bit?s sett ing, the core always responds to setup data packets with an ack handshake. bit 16 eonum: even/odd frame applies to isochronous in endpoints only. indicates the frame number in which the core transmits/receives isochronous data for this endpoint. the application must program the even /odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the sevnfrm and soddfrm fields in this register. 0: even frame 1: odd frame dpid: endpoint data pid applies to interrupt/bulk in endpoints only. contains the pid of the packet to be received or transmitted on this endpoint. the application must program the pid of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. the ap plication uses the sd0pid register field to program either data0 or data1 pid. 0: data0 1: data1 bit 15 usbaep: usb active endpoint indicates whether this endpoint is active in t he current configuration and interface. the core clears this bit for all endpoints (other than ep 0) after detecting a usb reset. after receiving the setconfiguration and setinterface comman ds, the application must program endpoint registers accordingly and set this bit. bits 14:11 reserved bits 10:0 mpsiz: maximum packet size the application must program this field with the maximum packet size for the current logical endpoint. this value is in bytes. usb on-the-go full-speed (otg_fs) RM0033 998/1317 doc id 15403 rev 3 otg_fs device control out endpoint 0 control register (otg_fs_doepctl0) address offset: 0xb00 reset value: 0x0000 8000 this section describes the otg_fs_doepctl0 register. nonzero control endpoints use registers for endpoints 1?3. 313029282726252423222120191817161514131211109876543210 epena epdis reserved snak cnak reserved stall snpm eptyp naksts reserved usbaep reserved mpsiz w r w w rs rw r r r r r r bit 31 epena: endpoint enable the application sets this bit to start transmitting data on endpoint 0. the core clears this bit before setting any of the following interrupts on this endpoint: ? setup phase done ? endpoint disabled ? transfer completed bit 30 epdis: endpoint disable the application cannot disable control out endpoint 0. bits 29:28 reserved bit 27 snak: set nak a write to this bit sets the nak bit for the endpoint. using this bit, the application can control the transmission of nak handshakes on an endpoint. the core can also set this bit on a transfer completed interrupt, or after a setup is received on the endpoint. bit 26 cnak: clear nak a write to this bit clears the nak bit for the endpoint. bits 25:22 reserved bit 21 stall: stall handshake the application can only set this bit, and the core clears it, when a setup token is received for this endpoint. if a nak bit or global out nak is set along with this bit, the stall bit takes priority. irrespective of this bit?s setting, the core always responds to setup data packets with an ack handshake. bit 20 snpm: snoop mode this bit configures the endpoint to snoop mode . in snoop mode, the core does not check the correctness of out packets before transferring them to application memory. bits 19:18 eptyp: endpoint type hardcoded to 2?b00 for control. RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 999/1317 otg_fs device endpoint-x control register (otg_fs_doepctlx) (x = 1..3, where x = endpoint_number) address offset for out endpoints: 0xb00 + (endpoint_number 0x20) reset value: 0x0000 0000 the application uses this register to control th e behavior of each logical endpoint other than endpoint 0. bit 17 naksts: nak status indicates the following: 0: the core is transmitting non-nak h andshakes based on the fifo status. 1: the core is transmitting nak handshakes on this endpoint. when either the application or the core sets this bit, the core stops receiv ing data, even if there is space in the rxfifo to accommodate the inco ming packet. irrespective of this bit?s setting, the core always responds to setup data packets with an ack handshake. bit 16 reserved bit 15 usbaep: usb active endpoint this bit is always set to 1, indicating that a control endpoint 0 is always active in all configurations and interfaces. bits 14:2 reserved bits 1:0 mpsiz: maximum packet size the maximum packet size for control out endpoint 0 is the same as what is programmed in control in endpoint 0. 00: 64 bytes 01: 32 bytes 10: 16 bytes 11: 8 bytes 313029282726252423222120191817161514131211109876543210 epena epdis soddfrm/sd1pid sd0pid/sevnfrm snak cnak reserved stall snpm eptyp naksts eonum/dpid usbaep reserved mpsiz rsrswwww rw/ rs rw rw rw r r rw rw rw rw rw rw rw rw rw rw rw rw bit 31 epena: endpoint enable applies to in and out endpoints. the application sets this bit to start transmitting data on an endpoint. the core clears this bit before setting any of the following interrupts on this endpoint: ? setup phase done ? endpoint disabled ? transfer completed usb on-the-go full-speed (otg_fs) RM0033 1000/1317 doc id 15403 rev 3 bit 30 epdis: endpoint disable the application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. the application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. the core clears this bit before setting the endpoint disabled interrupt. the application must set this bit only if endpoint enable is already set for this endpoint. bit 29 sd1pid: set data1 pid applies to interrupt/bulk in and out endpoints only. writing to this field sets the endpoint data pid (dpid) field in this register to data1. soddfrm: set odd frame applies to isochronous in and out endpoints only. writing to this field sets the even/odd frame (eonum) field to odd frame. bit 28 sd0pid: set data0 pid applies to interrupt/bulk out endpoints only. writing to this field sets the endpoint data pid (dpid) field in this register to data0. sevnfrm: set even frame applies to isochronous out endpoints only. writing to this field sets the even/odd frame (eonum) field to even frame. bit 27 snak: set nak a write to this bit sets the nak bit for the endpoint. using this bit, the application can control the transmission of nak handshakes on an endpoint. the core can also set this bit for out endpoints on a transfer completed interrupt, or after a setup is received on the endpoint. bit 26 cnak: clear nak a write to this bit clears the nak bit for the endpoint. bits 25:22 reserved bit 21 stall: stall handshake applies to non-control, non-isochronous out endpoints only (access type is rw). the application sets this bit to stall all tokens from the usb host to this endpoint. if a nak bit, global in nak, or global out nak is set along with this bit, the stall bit takes priority. only the application can clear this bit, never the core. applies to control endpoints only (access type is rs). the application can only set this bit, and the core clears it, when a setup token is received for this endpoint. if a nak bit, global in nak, or global out nak is set along with this bit, the stall bit takes priority. irrespective of this bit?s setting, the core always responds to setup data packets with an ack handshake. bit 20 snpm: snoop mode this bit configures the endpoint to snoop mode . in snoop mode, the core does not check the correctness of out packets before transferring them to application memory. bits 19:18 eptyp: endpoint type this is the transfer type supported by this logical endpoint. 00: control 01: isochronous 10: bulk 11: interrupt RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 1001/1317 bit 17 naksts: nak status indicates the following: 0: the core is transmitting non-nak handshakes based on the fifo status. 1: the core is transmitting nak handshakes on this endpoint. when either the application or the core sets this bit: the core stops receiving any data on an out endpoint, even if there is space in the rxfifo to accommodat e the incoming packet. irrespective of this bit?s setting, the core always responds to setup data packets with an ack handshake. bit 16 eonum: even/odd frame applies to isochronous in and out endpoints only. indicates the frame number in which the core transmits/receives isochronous data for this endpoint. the application must program the even/ odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the sevnfrm and soddfrm fields in this register. 0: even frame 1: odd frame dpid: endpoint data pid applies to interrupt/bulk out endpoints only. contains the pid of the packet to be received or transmitted on this endpoint. the application must program the pid of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. the application uses the sd0pid register field to program either data0 or data1 pid. 0: data0 1: data1 bit 15 usbaep: usb active endpoint indicates whether this endpoint is active in t he current configuration and interface. the core clears this bit for all endpoints (other than ep 0) after detecting a usb reset. after receiving the setconfiguration and setinterface comman ds, the application must program endpoint registers accordingly and set this bit. bits 14:11 reserved bits 10:0 mpsiz: maximum packet size the application must program this field with the maximum packet size for the current logical endpoint. this value is in bytes. usb on-the-go full-speed (otg_fs) RM0033 1002/1317 doc id 15403 rev 3 otg_fs device endpoint-x interrupt register (otg_fs_diepintx) (x = 0..3, where x = endpoint_number) address offset: 0x908 + (endpoint_number 0x20) reset value: 0x0000 0080 this register indicates the status of an endpoint with respect to usb- and ahb-related events. it is shown in figure 356 . the application must read this register when the in endpoints interrupt bit of the core interrupt register (iepint in otg_fs_gintsts) is set. before the application can read this register, it must first read the device all endpoints interrupt (otg_fs_daint) register to get the exact endpoint number for the device endpoint-x interrupt register. the application must clear the appropriate bit in this register to clear the corresponding bits in the otg_fs_daint and otg_fs_gintsts registers. 313029282726252423222120191817161514131211109876543210 reserved txfe inepne reserved ittxfe toc reserved epdisd xfrc r rc_ w1 /rw rc_ w1 rc_ w1 rc_ w1 rc_ w1 bits 31:8 reserved bit 7 txfe: transmit fifo empty this interrupt is asserted when the txfifo for th is endpoint is either half or completely empty. the half or completely empty status is dete rmined by the txfifo empty level bit in the otg_fs_gahbcfg register (txf elvl bit in otg_fs_gahbcfg). bit 6 inepne: in endpoint nak effective this bit can be cleared when the application clears the in endpoint nak by writing to the cnak bit in otg_fs_diepctlx. this interrupt indicates that the core has sampled the nak bit set (either by the application or by the core). the interrupt indicates that the in endpoint nak bit set by the application has taken effect in the core. this interrupt does not guarantee that a nak handshake is sent on the usb. a stall bit takes priority over a nak bit. bit 5 reserved bit 4 ittxfe: in token received when txfifo is empty applies to non-periodic in endpoints only. indicates that an in token was received when the associated txfifo (periodic/non-periodic) was empty. this interrupt is asserted on the endpoint for which the in token was received. bit 3 toc: timeout condition applies only to control in endpoints. indicates that the core has detected a timeout condition on the usb for the last in token on this endpoint. bit 2 reserved. bit 1 epdisd: endpoint disabled interrupt this bit indicates that the endpoint is disabled per the application?s request. RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 1003/1317 otg_fs device endpoint-x interrupt register (otg_fs_doepintx) (x = 0..3, where x = endpoint_number) address offset: 0xb08 + (endpoint_number 0x20) reset value: 0x0000 0080 this register indicates the status of an endpoint with respect to usb- and ahb-related events. it is shown in figure 356 . the application must read this register when the out endpoints interrupt bit of the otg_fs_gintsts register (oepint bit in otg_fs_gintsts) is set. before the application can read this register, it must first read the otg_fs_daint register to get the exact endpoint number for the otg_fs_doepintx register. the application must clear the appropriate bit in this register to clear the corresponding bits in the otg_fs_daint and otg_fs_gintsts registers. bit 0 xfrc: transfer completed interrupt this field indicates that the programmed transfer is complete on the ahb as well as on the usb, for this endpoint. 313029282726252423222120191817161514131211109876543210 reserved reserved b2bstup reserved otepdis stup reserved epdisd xfrc rc_ w1 /rw rc_ w1 rc_ w1 rc_ w1 rc_ w1 bits 31:7 reserved bit 6 b2bstup: back-to-back setup packets received applies to control out endpoint only. this bit indicates that the core has received more than three back-to-back setup packets for this particular endpoint. bit 5 reserved bit 4 otepdis: out token received when endpoint disabled applies only to control out endpoints. indicates that an out token was received when the endpoint was not yet enabled. this interrupt is asserted on the endpoint for which the out token was received. bit 3 stup: setup phase done applies to control out endpoint only. indicates that the setup phase for the control endpoint is complete and no more back-to- back setup packets were received for the current control transfer. on this interrupt, the application can decode the received setup data packet. bit 2 reserved bit 1 epdisd: endpoint disabled interrupt this bit indicates that the endpoint is disabled per the application?s request. bit 0 xfrc: transfer completed interrupt this field indicates that the programmed transfer is complete on the ahb as well as on the usb, for this endpoint. usb on-the-go full-speed (otg_fs) RM0033 1004/1317 doc id 15403 rev 3 otg_fs device in endpoint 0 transfer size register (otg_fs_dieptsiz0) address offset: 0x910 reset value: 0x0000 0000 the application must modify this register before enabling endpoint 0. once endpoint 0 is enabled using the endpoint enable bit in the device control endpoint 0 control registers (epena in otg_fs_diepctl0), the core modifies this register. the application can only read this register once the core has cleared the endpoint enable bit. nonzero endpoints use the registers for endpoints 1?3. 313029282726252423222120191817161514131211109876543210 reserved pktcnt reserved xfrsiz rw rw rw rw rw rw rw rw rw bits 31:21 reserved bits 20:19 pktcnt: packet count indicates the total number of usb packets that constitute the transfer size amount of data for endpoint 0. this field is decremented every time a packet (m aximum size or short packet) is read from the txfifo. bits 18:7 reserved bits 6:0 xfrsiz: transfer size indicates the transfer size in bytes for endpoint 0. the core interrupts the application only after it has exhausted the transfer size amount of data. the transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. the core decrements this field every time a packet from the external memory is written to the txfifo. RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 1005/1317 otg_fs device out endpoint 0 transfer size register (otg_fs_doeptsiz0) address offset: 0xb10 reset value: 0x0000 0000 the application must modify this register before enabling endpoint 0. once endpoint 0 is enabled using the endpoint enable bit in the otg_fs_doepctl0 registers (epena bit in otg_fs_doepctl0), the core modifies this register. the application can only read this register once the core has cleared the endpoint enable bit. nonzero endpoints use the registers for endpoints 1?3. 313029282726252423222120191817161514131211109876543210 reserved stupc nt reserved pktcnt reserved xfrsiz rw rw rw rw rw rw rw rw rw rw bit 31 reserved bits 30:29 stupcnt: setup packet count this field specifies the number of back-to-back setup data packets the endpoint can receive. 01: 1 packet 10: 2 packets 11: 3 packets bits 28:20 reserved bit 19 pktcnt: packet count this field is decremented to zero afte r a packet is written into the rxfifo. bits 18:7 reserved bits 6:0 xfrsiz: transfer size indicates the transfer size in bytes for endpoint 0. the core interrupts the application only after it has exhausted the transfer size amount of data. the transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. the core decrements this field every time a packe t is read from the rxfi fo and written to the external memory. usb on-the-go full-speed (otg_fs) RM0033 1006/1317 doc id 15403 rev 3 otg_fs device endpoint-x transfer size register (otg_fs_dieptsizx) (x = 1..3, where x = endpoint_number) address offset: 0x910 + (endpoint_number 0x20) reset value: 0x0000 0000 the application must modify this register before enabling the endpoint. once the endpoint is enabled using the endpoint enable bit in th e otg_fs_diepctlx registers (epena bit in otg_fs_diepctlx), the core modifies this re gister. the application can only read this register once the core has cleared the endpoint enable bit. 313029282726252423222120191817161514131211109876543210 reserved mcnt pktcnt xfrsiz rw/ r/r w rw/ r/r w rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bit 31 reserved bits 30:29 mcnt: multi count for periodic in endpoints, this field indicates the number of packets that must be transmitted per frame on the usb. the core uses this field to calculate the data pid for isochronous in endpoints. 01: 1 packet 10: 2 packets 11: 3 packets bit 28:19 pktcnt: packet count indicates the total number of usb packets that constitute the transfer size amount of data for this endpoint. this field is decremented every time a packet (maximum size or short packet) is read from the txfifo. bits 18:0 xfrsiz: transfer size this field contains the transfer size in bytes for the current endpoint. the core only interrupts the application after it has exhausted the transfer si ze amount of data. the transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. the core decrements this field every time a packet from the external memory is written to the txfifo. RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 1007/1317 otg_fs device in endpoint transmit fifo status register (otg_fs_dtxfstsx) (x = 0..3, where x = endpoint_number) address offset for in endpoints: 0x918 + (endpoint_number 0x20) this read-only register contains the free space information for the device in endpoint txfifo. otg_fs device out endpoint-x transfer size register (otg_fs_doeptsizx) (x = 1..3, where x = endpoint_number) address offset: 0xb10 + (endpoint_number 0x20) reset value: 0x0000 0000 the application must modify this register before enabling the endpoint. once the endpoint is enabled using endpoint enable bit of th e otg_fs_doepctlx registers (epena bit in otg_fs_doepctlx), the core modifies this register. the application can only read this register once the core has cleared the endpoint enable bit. 313029282726252423222120191817161514131211109876543210 reserved ineptfsav rrrrrrrrrrrrrrrr 31:16 reserved 15:0 ineptfsav: in endpoint txfifo space available indicates the amount of free space available in the endpoint txfifo. values are in terms of 32-bit words: 0x0: endpoint txfifo is full 0x1: 1 word available 0x2: 2 words available 0xn: n words available others: reserved 3130 29282726252423222120191817161514131211109876543210 reserved rxdpid/s tupcnt pktcnt xfrsiz rw/r/ rw rw/r/ rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bit 31 reserved bits 30:29 rxdpid: received data pid applies to isochronous out endpoints only. this is the data pid received in the last packet for this endpoint. 00: data0 01: data2 10: data1 11: mdata usb on-the-go full-speed (otg_fs) RM0033 1008/1317 doc id 15403 rev 3 29.16.5 otg_fs power and cl ock gating control register (otg_fs_pcgcctl) address offset: 0xe00 reset value: 0x0000 0000 this register is available in host and device modes. stupcnt: setup packet count applies to control out endpoints only. this field specifies the number of back-to-ba ck setup data packets the endpoint can receive. 01: 1 packet 10: 2 packets 11: 3 packets bit 28:19 pktcnt: packet count indicates the total number of usb packets that constitute the transfer size amount of data for this endpoint. this field is decremented every time a packet (maximum size or short packet) is written to the rxfifo. bits 18:0 xfrsiz: transfer size this field contains the transfer size in bytes for the current endpoint. the core only interrupts the application after it has exhausted the transfer si ze amount of data. the transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. the core decrements this field every time a pack et is read from the rxfifo and written to the external memory. 3130 29282726252423222120191817161514131211109876543210 reserved physusp reserved gatehclk stppclk rw rw rw bit 31:5 reserved bit 4 physusp: phy suspended indicates that the phy has been suspended. th is bit is updated once the phy is suspended after the application has set the stppclk bit (bit 0). bits 3:2 reserved bit 1 gatehclk: gate hclk the application sets this bit to gate hclk to modules other than the ahb slave and master and wakeup logic when the usb is suspended or the session is not valid. the application clears this bit when the usb is resumed or a new session starts. bit 0 stppclk: stop phy clock the application sets this bit to stop the phy cl ock when the usb is suspended, the session is not valid, or the device is disconnected. the application clears this bit when the usb is resumed or a new session starts. RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 1009/1317 29.16.6 otg_fs register map the table below gives the usb otg register map and reset values. table 154. otg_fs register map and reset values offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x000 otg_fs_got gctl reserved bsvld asvld dbct cidsts reserved dhnpen hshnpen hnprq hngscs reserved srq srqscs reset value 0 0 0 1 0 0 0 0 0 0 0x004 otg_fs_got gint reserved dbcdne adtochg hngdet reserved hnsschg srsschg reserved sedet res. reset value 0 0 0 0 0 0 0x008 otg_fs_gah bcfg reserved ptxfelvl txfelvl reserved gintmsk reset value 00 0 0x00c otg_fs_gus bcfg ctxpkt fdmod fhmod reserved trdt hnpcap srpcap physel reserved tocal reset value 0101001 000 0x010 otg_fs_grst ctl ahbidl reserved txfnum txfflsh rxfflsh reserved fcrst hsrst csrst reset value 1 000 0000000 0x014 otg_fs_gint sts wkuint srqint discint cidschg reserved ptxfe hcint hprtint reserved ipxfr/inco mpisoout iisoixfr oepint iepint reserved eopf isoodrp enumdne usbrst usbsusp esusp reserved goutnakeff ginakeff nptxfe rxflvl sof otgint mmis cmod reset value 0000 1 00 0000 000000 00100000 0x018 otg_fs_gint msk wuim srqim discint cidschgm reserved ptxfem hcim prtim reserved ipxfrm/iisooxfrm iisoixfrm oepint iepint epmism reserved eopfm isoodrpm enumdnem usbrst usbsuspm esuspm reserved gonakeffm ginakeffm nptxfem rxflvlm sofm otgint mmism reserved reset value 0000 000 00000 000000 0000000 0x01c otg_fs_grxs tsr (host mode) reserved pktsts dpid bcnt chnum reset value 0000 000000000000000 otg_fs_grxs tsr (device mode) reserved frmnum pktsts dpid bcnt epnum reset value 0000000000000000000000000 0x020 otg_fs_grxs tsr (host mode) reserved pktsts dpid bcnt chnum reset value 0000 000000000000000 otg_fs_grxs tspr (device mode) reserved frmnum pktsts dpid bcnt epnum reset value 0000000000000000000000000 0x024 otg_fs_grxf siz reserved rxfd reset value 0000001000000000 usb on-the-go full-speed (otg_fs) RM0033 1010/1317 doc id 15403 rev 3 0x028 otg_fs_hnpt xfsiz/ otg_fs_diep txf0 nptxfd/tx0fd nptxfsa/tx0fsa reset value 00000000000000000000001000000000 0x02c otg_fs_hnpt xsts res. nptxqtop nptqxsav nptxfsav reset value 0000000000001000000001000000000 0x038 otg_fs_ gccfg reserved novbussens sofouten vbusbsen vbusasen reserved .pwrdwn reserved reset value 0 0 0 0 0 0x03c otg_fs_cid product_id reset value 00000000000000000001000100000000 0x100 otg_fs_hptx fsiz ptxfsiz ptxsa reset value 00000111011010000001000000100100 0x104 otg_fs_diep txf1 ineptxfd ineptxsa reset value 00000010000000000000010000000000 0x108 otg_fs_diep txf2 ineptxfd ineptxsa reset value 00000010000000000000010000000000 0x10c otg_fs_diep txf3 ineptxfd ineptxsa reset value 00000010000000000000010000000000 0x400 otg_fs_hcfg reserved fslss fslspcs reset value 000 0x404 otg_fs_hfir reserved frivl reset value 1110101001100000 0x408 otg_fs_hfnu m ftrem frnum reset value 00000000000000000011111111111111 0x410 otg_fs_hptx sts ptxqtop ptxqsav ptxfsavl reset value 0 0 0 0 0 0 0 0yyyyyyyyyyyyyyyyyyyyyyyy 0x414 otg_fs_hain t reserved haint reset value 0000000000000000 0x418 otg_fs_hain tmsk reserved haintm reset value 0000000000000000 0x440 otg_fs_hprt reserved pspd ptctl ppwr plsts reserved prst psusp pres pocchng poca penchng pena pcdet pcsts reset value 0000000000000000000 0x500 otg_fs_hcc har0 chena chdis oddfrm dad mcnt eptyp lsdev reserved epdir epnum mpsiz reset value 000000000000000 0000000000000000 0x520 otg_fs_hcc har1 chena chdis oddfrm dad mcnt eptyp lsdev reserved epdir epnum mpsiz reset value 000000000000000 0000000000000000 0x540 otg_fs_hcc har2 chena chdis oddfrm dad mcnt eptyp lsdev reserved epdir epnum mpsiz reset value 000000000000000 0000000000000000 table 154. otg_fs register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 1011/1317 0x560 otg_fs_hcc har3 chena chdis oddfrm dad mcnt eptyp lsdev reserved epdir epnum mpsiz reset value 000000000000000 0000000000000000 0x580 otg_fs_hcc har4 chena chdis oddfrm dad mcnt eptyp lsdev reserved epdir epnum mpsiz reset value 000000000000000 0000000000000000 0x5a0 otg_fs_hcc har5 chena chdis oddfrm dad mcnt eptyp lsdev reserved epdir epnum mpsiz reset value 000000000000000 0000000000000000 0x5c0 otg_fs_hcc har6 chena chdis oddfrm dad mcnt eptyp lsdev reserved epdir epnum mpsiz reset value 000000000000000 0000000000000000 0x5e0 otg_fs_hcc har7 chena chdis oddfrm dad mcnt eptyp lsdev reserved epdir epnum mpsiz reset value 000000000000000 0000000000000000 0x508 otg_fs_hcin t0 reserved dterr frmor bberr txerr reserved ack nak stall reserved chh xfrc reset value 0000 000 00 0x528 otg_fs_hcin t1 reserved dterr frmor bberr txerr reserved ack nak stall reserved chh xfrc reset value 0000 000 00 0x548 otg_fs_hcin t2 reserved dterr frmor bberr txerr reserved ack nak stall reserved chh xfrc reset value 0000 000 00 0x568 otg_fs_hcin t3 reserved dterr frmor bberr txerr reserved ack nak stall reserved chh xfrc reset value 0000 000 00 0x588 otg_fs_hcin t4 reserved dterr frmor bberr txerr reserved ack nak stall reserved chh xfrc reset value 0000 000 00 0x5a8 otg_fs_hcin t5 reserved dterr frmor bberr txerr reserved ack nak stall reserved chh xfrc reset value 0000 000 00 0x5c8 otg_fs_hcin t6 reserved dterr frmor bberr txerr reserved ack nak stall reserved chh xfrc reset value 0000 000 00 0x5e8 otg_fs_hcin t7 reserved dterr frmor bberr txerr reserved ack nak stall reserved chh xfrc reset value 0000 000 00 0x50c otg_fs_hcin tmsk0 reserved dterrm frmorm bberrm txerrm nyet ackm nakm stallm reserved chhm xfrcm reset value 00000000 00 0x52c otg_fs_hcin tmsk1 reserved dterrm frmorm bberrm txerrm nyet ackm nakm stallm reserved chhm xfrcm reset value 00000000 00 table 154. otg_fs register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 usb on-the-go full-speed (otg_fs) RM0033 1012/1317 doc id 15403 rev 3 0x54c otg_fs_hcin tmsk2 reserved dterrm frmorm bberrm txerrm nyet ackm nakm stallm reserved chhm xfrcm reset value 00000000 00 0x56c otg_fs_hcin tmsk3 reserved dterrm frmorm bberrm txerrm nyet ackm nakm stallm reserved chhm xfrcm reset value 00000000 00 0x58c otg_fs_hcin tmsk4 reserved dterrm frmorm bberrm txerrm nyet ackm nakm stallm reserved chhm xfrcm reset value 00000000 00 0x5ac otg_fs_hcin tmsk5 reserved dterrm frmorm bberrm txerrm nyet ackm nakm stallm reserved chhm xfrcm reset value 00000000 00 0x5cc otg_fs_hcin tmsk6 reserved dterrm frmorm bberrm txerrm nyet ackm nakm stallm reserved chhm xfrcm reset value 00000000 00 0x5ec otg_fs_hcin tmsk7 reserved dterrm frmorm bberrm txerrm nyet ackm nakm stallm reserved chhm xfrcm reset value 00000000 00 0x510 otg_fs_hcts iz0 reserved dpid pktcnt xfrsiz reset value 0000000000000000000000000000000 0x530 otg_fs_hcts iz1 reserved dpid pktcnt xfrsiz reset value 0000000000000000000000000000000 0x550 otg_fs_hcts iz2 reserved dpid pktcnt xfrsiz reset value 0000000000000000000000000000000 0x570 otg_fs_hcts iz3 reserved dpid pktcnt xfrsiz reset value 0000000000000000000000000000000 0x590 otg_fs_hcts iz4 reserved dpid pktcnt xfrsiz reset value 0000000000000000000000000000000 0x5b0 otg_fs_hcts iz5 reserved dpid pktcnt xfrsiz reset value 0000000000000000000000000000000 0x5d0 otg_fs_hcts iz6 reserved dpid pktcnt xfrsiz reset value 0000000000000000000000000000000 0x5f0 otg_fs_hcts iz7 reserved dpid pktcnt xfrsiz reset value 0000000000000000000000000000000 0x800 otg_fs_dcfg reserved pfivl dad reserved nzlsohsk dspd reset value 000000000 000 table 154. otg_fs register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 1013/1317 0x804 otg_fs_dctl reserved poprgdne cgonak sgonak cginak sginak tctl gonsts ginsts sdis rwusig reset value 000000000000 0x808 otg_fs_dsts reserved fnsof reserved eerr enumspd suspsts reset value 00000000000000 0000 0x810 otg_fs_diep msk reserved inepnem inepnmm ittxfemsk tom reserved epdm xfrcm reset value 0000 00 0x814 otg_fs_doep msk reserved otepdm stupm reserved epdm xfrcm reset value 00 00 0x818 otg_fs_dain t oepint iepint reset value 00000000000000000000000000000000 0x81c otg_fs_dain tmsk oepm iepm reset value 00000000000000000000000000000000 0x828 otg_fs_dvbu sdis reserved vbusdt reset value 0001011111010111 0x82c otg_fs_dvbu spulse reserved dvbusp reset value 010110111000 0x834 otg_fs_diep empmsk reserved ineptxfem reset value 0000000000000000 0x900 otg_fs_diep ctl0 epena epdis reserved snak cnak txfnum stall reserved epty p naksts reserved usbaep reserved mpsi z reset value 00 0000000 000 1 00 0x918 tg_fs_dtxfs ts0 reserved ineptfsav reset value 0000001000000000 0x920 otg_fs_diep ctl1 epena epdis soddfrm/sd1pid sd0pid/sevnfrm snak cnak txfnum stall reserved eptyp naksts eonum/dpid usbaep reserved mpsiz reset value 00000000000 00000 00000000000 0x938 tg_fs_dtxfs ts1 reserved ineptfsav reset value 0000001000000000 0x940 otg_fs_diep ctl2 epena epdis soddfrm sd0pid/sevnfrm snak cnak txfnum stall reserved eptyp naksts eonum/dpid usbaep reserved mpsiz reset value 00000000000 00000 00000000000 0x958 tg_fs_dtxfs ts2 reserved ineptfsav reset value 0000001000000000 table 154. otg_fs register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 usb on-the-go full-speed (otg_fs) RM0033 1014/1317 doc id 15403 rev 3 0x960 otg_fs_diep ctl3 epena epdis soddfrm sd0pid/sevnfrm snak cnak txfnum stall reserved eptyp naksts eonum/dpid usbaep reserved mpsiz reset value 00000000000 00000 00000000000 0x978 tg_fs_dtxfs ts3 reserved ineptfsav reset value 0000001000000000 0xb00 otg_fs_doep ctl0 epena epdis reserved snak cnak reserved stall snpm epty p naksts reserved usbaep reserved mpsi z reset value 0 0 0 0 0 0 0 0 0 1 0 0 0xb20 otg_fs_doep ctl1 epena epdis soddfrm sd0pid/sevnfrm snak cnak reserved stall snpm eptyp naksts eonum/dpid usbaep reserved mpsiz reset value 000000 0000000 00000000000 0xb40 otg_fs_doep ctl2 epena epdis soddfrm sd0pid/sevnfrm snak cnak reserved stall snpm eptyp naksts eonum/dpid usbaep reserved mpsiz reset value 000000 0000000 00000000000 0xb60 otg_fs_doep ctl3 epena epdis soddfrm sd0pid/sevnfrm snak cnak reserved stall snpm eptyp naksts eonum/dpid usbaep reserved mpsiz reset value 000000 0000000 00000000000 0x908 otg_fs_diepi nt0 reserved txfe inepne reserved ittxfe toc reserved epdisd xfrc reset value 10 00 00 0x928 otg_fs_diepi nt1 reserved txfe inepne reserved ittxfe toc reserved epdisd xfrc reset value 10 00 00 0x948 otg_fs_diepi nt2 reserved txfe inepne reserved ittxfe toc reserved epdisd xfrc reset value 10 00 00 0x968 otg_fs_diepi nt3 reserved txfe inepne reserved ittxfe toc reserved epdisd xfrc reset value 10 00 00 0xb08 otg_fs_doep int0 reserved reserved b2bstup reserved otepdis stup reserved epdisd xfrc reset value 00000 0xb28 otg_fs_doep int1 reserved reserved b2bstup reserved otepdis stup reserved epdisd xfrc reset value 00000 table 154. otg_fs register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 1015/1317 refer to table 1 on page 50 for the register boundary addresses. 29.17 otg_fs programming model 29.17.1 core initialization the application must perform the core initialization sequence. if the cable is connected during power-up, the current mode of operation bit in the otg_fs_gintsts (cmod bit in otg_fs_gintsts) reflects the mode. the otg_fs controller enters host mode when an ?a? plug is connected or device mode when a ?b? plug is connected. 0xb48 otg_fs_doep int2 reserved reserved b2bstup reserved otepdis stup reserved epdisd xfrc reset value 00000 0xb68 otg_fs_doep int3 reserved reserved b2bstup reserved otepdis stup reserved epdisd xfrc reset value 00000 0x910 otg_fs_diep tsiz0 reserved pktc nt reserved xfrsiz reset value 00 0000000 0x930 otg_fs_diep tsiz1 reserved mcnt pktcnt xfrsiz reset value 0000000000000000000000000000000 0x950 otg_fs_diep tsiz2 reserved mcnt pktcnt xfrsiz reset value 0000000000000000000000000000000 0x970 otg_fs_diep tsiz3 reserved mcnt pktcnt xfrsiz reset value 0000000000000000000000000000000 0xb10 otg_fs_doep tsiz0 reserved stup cnt reserved pktcnt reserved xfrsiz reset value 00 0 0000000 0xb30 otg_fs_doep tsiz1 reserved rxdpid/ stupcnt pktcnt xfrsiz reset value 0000000000000000000000000000000 0xb50 otg_fs_doep tsiz2 reserved rxdpid/ stupcnt pktcnt xfrsiz reset value 0000000000000000000000000000000 0xb70 otg_fs_doep tsiz3 reserved rxdpid/ stupcnt pktcnt xfrsiz reset value 0000000000000000000000000000000 0xe00 otg_fs_pcg cctl reserved physusp reserved gatehclk stppclk reset value table 154. otg_fs register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 usb on-the-go full-speed (otg_fs) RM0033 1016/1317 doc id 15403 rev 3 this section explains the initialization of the otg_fs controller after power-on. the application must follow the init ialization sequence irrespective of host or device mode operation. all core global registers are initialized according to the core?s configuration: 1. program the following fields in the otg_fs_gahbcfg register: ? global interrupt mask bit gintmsk = 1 ? rxfifo non-empty (rxflvl bit in otg_fs_gintsts) ? periodic txfifo empty level 2. program the following fields in the otg_fs_gusbcfg register: ? hnp capable bit ? srp capable bit ? fs timeout calibration field ? usb turnaround time field 3. the software must unmask the following bits in the otg_fs_gintmsk register: otg interrupt mask mode mismatch interrupt mask 4. the software can read the cmod bit in otg_fs_gintsts to determine whether the otg_fs controller is operating in host or device mode. RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 1017/1317 29.17.2 host initialization to initialize the core as host, the app lication must perform the following steps: 1. program the hprtint in the otg_fs_gintmsk register to unmask 2. program the otg_fs_hcfg register to select full-speed host 3. program the ppwr bit in otg_fs_hprt to 1. this drives v bus on the usb. 4. wait for the pcdet interrupt in otg_fs_hprt0. this indicates that a device is connecting to the port. 5. program the prst bit in otg_fs_hprt to 1. this starts the reset process. 6. wait at least 10 ms for the reset process to complete. 7. program the prst bit in otg_fs_hprt to 0. 8. wait for the penchng interrupt in otg_fs_hprt. 9. read the pspd bit in otg_fs_hprt to get the enumerated speed. 10. program the hfir register with a value corresponding to the selected phy clock 1 11. program the fslspcs field in the otg_fs_hcfg register following the speed of the device detected in step 9. if fslspcs has been changed a port reset must be performed. 12. program the otg_fs_grxfsiz register to select the size of the receive fifo. 13. program the otg_fs_hnptxfsiz register to select the size and the start address of the non-periodic transmit fifo for non-periodic transactions. 14. program the otg_fs_hptxfsiz register to select the size and start address of the periodic transmit fifo for periodic transactions. to communicate with devices, the system software must initialize and enable at least one channel. 29.17.3 device initialization the application must perform the following steps to initialize the core as a device on power- up or after a mode change from host to device. 1. program the following fields in the otg_fs_dcfg register: ? device speed ? non-zero-length status out handshake 2. program the otg_fs_gintmsk register to unmask the following interrupts: ? usb reset ? enumeration done ? early suspend ? usb suspend ?sof 3. program the vbusbsen bit in the otg_fs_gccfg regist er to enable v bus sensing in ?b? device mode and supply the 5 volts across the pull-up resistor on the dp line. 4. wait for the usbrst interrupt in otg_fs_gintsts. it indicates that a reset has been detected on the usb that lasts for about 10 ms on receiving this interrupt. wait for the enumdne interrupt in otg_fs_gintsts. this interrupt indicates the end of reset on the usb. on receiving this interrupt, the application must read the otg_fs_dsts usb on-the-go full-speed (otg_fs) RM0033 1018/1317 doc id 15403 rev 3 register to determine the enumeration speed and perform the steps listed in endpoint initialization on enumeration completion on page 1035 . at this point, the device is ready to accept sof packets and perform control transfers on control endpoint 0. 29.17.4 host programming model channel initialization the application must initialize one or more channels before it can communicate with connected devices. to initialize and enable a channel, the application must perform the following steps: 1. program the otg_fs_gintmsk register to unmask the following: 2. channel interrupt ? non-periodic transmit fifo empty for out transactions (applicable when operating in pipelined transaction-level with the packet count field programmed with more than one). ? non-periodic transmit fifo half-empty for out transactions (applicable when operating in pipelined transaction-level with the packet count field programmed with more than one). 3. program the otg_fs_haintmsk register to unmask the selected channels? interrupts. 4. program the otg_fs_hcintmsk register to unmask the transaction-related interrupts of interest given in the host channel interrupt register. 5. program the selected channel?s otg_fs_hctsizx register with the total transfer size, in bytes, and the expected number of packets, including short packets. the application must program the pid field with the initial data pid (to be used on the first out transaction or to be expected from the first in transaction). 6. program the otg_fs_hccharx register of the selected channel with the device?s endpoint characteristics, such as type, speed, direction, and so forth. (the channel can be enabled by setting the channel enable bit to 1 only when the application is ready to transmit or receive any packet). halting a channel the application can disable any channel by programming the otg_fs_hccharx register with the chdis and chena bits set to 1. this enables the otg_fs host to flush the posted requests (if any) and generates a channel halted interrupt. the application must wait for the chh interrupt in otg_fs_hcintx before reallo cating the channel for other transactions. the otg_fs host does not interrupt the transaction that has already been started on the usb. before disabling a channel, the application must ensure that there is at least one free space available in the non-periodic request queue (when disabling a non-periodic channel) or the periodic request queue (when disabling a pe riodic channel). the application can simply flush the posted requests when the request queue is full (before disabling the channel), by programming the otg_fs_hccharx register with the chdis bit set to 1, and the chena bit cleared to 0. the application is expected to disable a channel on any of the following conditions: RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 1019/1317 1. when an stall, txerr, bberr or dterr in terrupt in otg_fs_ hcintx is received for an in or out channel. the application must be able to receive other interrupts (dterr, nak, data, txerr) for the sa me channel before receiving the halt. 2. when a discint (disconnect device) in terrupt in otg_fs_gintsts is received. (the application is expected to disable all enabled channels). 3. when the application aborts a transfer before normal completion. operational model the application must initialize a channel before communicating to the connected device. this section explains the sequence of operati on to be performed for different types of usb transactions. writing the transmit fifo the otg_fs host automatically writes an entry (out request) to the periodic/non- periodic request queue, along with the last dword write of a packet. the application must ensure that at least one free space is available in the periodic/non-periodic request queue before starting to write to the transmit fifo. the application must always write to the transmit fifo in dwords. if the packet size is non-dword aligned, the application must use padding. the otg_fs host determines the actual packet size based on the programmed maximum packet size and transfer size. figure 358. transmit fifo write task mp s : m a xim u m p a cket s ize s t a rt a i1567 3b w a it for nptxfe/ptxfe interr u pt in otg_f s _gint s t s re a d gnptx s t s /hptxf s iz regi s ter s for a v a il ab le fifo a nd qu e u e s p a ce s 1 mp s or lp s fifo s p a ce a v a il ab le? write 1 p a cket d a t a to tr a n s mit fifo more p a cket s to s end? done no no ye s ye s lp s : l as t p a cket s ize usb on-the-go full-speed (otg_fs) RM0033 1020/1317 doc id 15403 rev 3 reading the receive fifo the application must ignore all packet statuses other than in data packet (bx0010). figure 359. receive fifo read task bulk and control out/setup transactions a typical bulk or control out/setup pipelined transaction-level operation is shown in figure 360 . see channel 1 (ch_1). two bulk out packets are transmitted. a control rxflvl interrupt ? read the received packet from the receive fifo read otg_fs_grxstsp pktsts 0b0010? yes yes unmask rxflvl interrupt bcnt > 0? no mask rxflvl interrupt yes unmask rxflvl interrupt no no start ai15674 RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 1021/1317 setup transaction operates in the same way but has only one packet. the assumptions are: ? the application is attempting to send two maximum-packet-size packets (transfer size = 1, 024 bytes). ? the non-periodic transmit fifo can hold two packets (128 bytes for fs). ? the non-periodic request queue depth = 4. normal bulk and control out/setup operations the sequence of operations in (channel 1) is as follows: a) initialize channel 1 b) write the first packet for channel 1 c) along with the last word write, the core writes an entry to the non-periodic request queue d) as soon as the non-periodic queue becomes non-empty, the core attempts to send an out token in the current frame e) write the second (last) packet for channel 1 f) the core generates the xfrc interrup t as soon as the last transaction is completed successfully g) in response to the xfrc interrupt, de-allocate the channel for other transfers h) handling non-ack responses usb on-the-go full-speed (otg_fs) RM0033 1022/1317 doc id 15403 rev 3 figu re 36 0. norma l b u lk/cont r o l out/setup a nd b u lk /cont r o l in t r ans a c t ions the ch ann el- s p e cif i c int e r r up t ser v ice r o u t in e f o r b u lk and con t rol o u t / setup tr ans a c t ions i s s h o w n in the f o llo w i ng code samples . i n te rrup t se r v i c e r o u t i n e f o r b u lk / c ont r o l out/ setup a nd b u lk /c ont r o l i n tr ans act i ons a) bu lk/con tr ol out/ setup unmask (nak/txerr/stall/x frc) if ( xf rc ) { reset error count mask ack a c k ho s t a p p lic a t io n d e v ic e ah b usb o u t d a t a 0 m p s 1 mps 1 mps write_tx _fifo (ch_1) init_reg(ch_1) set _ch_en (ch_2) init_reg(ch_2) write_tx _fifo (ch_1) set _ch_en (ch_2) ch_2 ch _ 2 ch _ 1 ch _ 1 de-allocate (ch_1) i n ch_2 ch _ 2 ch _ 2 ch _ 1 a c k o u t set _ch_en (ch_2) n o n - pe r i o d ic r e q u e s t qu e u e assume that this queue can hold 4 entries. 4 1 6 a c k d a t a 0 i n a c k read_rx_sts read_rx_fifo 1 mps set _ch_en (ch_2) 1 mps read_rx_stsre ad_rx_fifo read_rx_sts disable (ch_2) 1 2 3 4 5 6 7 de-allocate (ch_2) chh interrupt r ch_2 2 3 5 7 8 9 12 13 read_rx_sts 10 11 d a t a 1 m p s d a t a 1 ai15675 rxflvl interrupt xfrc interrupt rxflvl interrupt rxflvl interrupt rxflvl interrupt xfrc interrupt RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 1023/1317 de-allocate channel } else if ( stall ) { transfer done = 1 unmask chh disable channel } else if ( nak or txerr ) { rewind buffer pointers unmask chh disable channel if ( txerr ) { increment error count unmask ack } else { reset error count } } else if ( chh ) { mask chh if (transfer done or (error_count == 3)) { de-allocate channel } else { re-initialize channel } } else if ( ack ) { reset error count mask ack } the application is expected to write the data packets into the transmit fifo as and when the space is available in the tr ansmit fifo and the request queue. the application can make use of the nptxfe interrupt in otg_fs_gintsts to find the transmit fifo space. b) bulk/control in unmask (txerr/xfrc/bberr/stall/dterr) if ( xfrc ) { reset error count unmask chh disable channel usb on-the-go full-speed (otg_fs) RM0033 1024/1317 doc id 15403 rev 3 reset error count mask ack } else if ( txerr or bberr or stall ) { unmask chh disable channel if ( txerr ) { increment error count unmask ack } } else if ( chh ) { mask chh if (transfer done or (error_count == 3)) { de-allocate channel } else { re-initialize channel } } else if ( ack ) { reset error count mask ack } else if ( dterr ) { reset error count } the application is expected to write the requ ests as and when the request queue space is available and until the xfrc interrupt is received. bulk and control in transactions a typical bulk or control in pipelined tr ansaction-level operation is shown in figure 361 . see channel 2 (ch_2). the assumptions are: ? the application is attempting to receive two maximum-packet-size packets (transfer size = 1 024 bytes). ? the receive fifo can contain at least one maximum-packet-size packet and two status words per packet (72 bytes for fs). ? the non-periodic request queue depth = 4. RM0033 usb on-the-go full-speed (otg_fs) d o c id 154 03 re v 3 1 025 /13 1 7 fi gu re 36 1. bul k / c o n tr ol in tra n sa ct io ns the se que nce of ope r a t i o n s is as f o llo ws: a) initializ e channel 2. b) s e t the c h ena bit in hcch ar2 to wr ite an in request to the non-per iodic request que ue . c) th e co re a tte m p t s t o s e n d a n i n t o k e n af te r c o m p let i ng t h e cu rr e n t ou t t r ansaction. d) the cor e g ene r a t e s an rxf l vl int e r r up t as soo n as t he re ceiv ed pa c k e t is wr it t en t o th e re ce iv e fi fo . e) in r e spo n se t o th e rxf l vl in te rr u p t , ma sk t he rxfl vl in t e rr upt and r e a d t he rece iv e d pa c k e t st at us to det er mine t h e n u mb er o f b y t e s re ce iv ed, t hen r e a d th e receiv e fifo accordingly . f o llo wing th is , u n m a sk th e rxfl vl in te rr u p t . a c k ho s t a p p lic a t io n d e v ic e ah b usb o u t d a t a 0 m p s 1 mps 1 mps write_tx _fifo (ch_1) init_reg(ch_1) set _ch_en (ch_2) init_reg(ch_2) write_tx _fifo (ch_1) set _ch_en (ch_2) ch_2 ch _ 2 ch _ 1 ch _ 1 de-allocate (ch_1) i n ch_2 ch _ 2 ch _ 2 ch _ 1 a c k o u t set _ch_en (ch_2) n o n - pe r i o d ic r e q u e s t qu e u e assume that this queue can hold 4 entries. 4 1 6 a c k d a t a 0 i n a c k read_rx_sts read_rx_fifo 1 mps set _ch_en (ch_2) 1 mps read_rx_stsre ad_rx_fifo read_rx_sts disable (ch_2) 1 2 3 4 5 6 7 de-allocate (ch_2) chh interrupt r ch_2 2 3 5 7 8 9 12 13 read_rx_sts 10 11 d a t a 1 m p s d a t a 1 ai15675 rxflvl interrupt xfrc interrupt rxflvl interrupt rxflvl interrupt rxflvl interrupt xfrc interrupt usb on-the-go full-speed (otg_fs) RM0033 1026/1317 doc id 15403 rev 3 f) the core generates the rxflvl interrupt for the transfer completion status entry in the receive fifo. g) the application must read and ignore the receive packet status when the receive packet status is not an in data packet (pktsts in grxstsr 0b0010). h) the core generates the xfrc interrupt as soon as the receive packet status is read. i) in response to the xfrc interrupt, disable the channel and stop writing the otg_fs_hcchar2 register for further requests. the core writes a channel disable request to the non-periodic request queue as soon as the otg_fs_hcchar2 register is written. j) the core generates the rxflvl interrupt as soon as the halt status is written to the receive fifo. k) read and ignore the receive packet status. l) the core generates a chh interrupt as soon as the halt status is popped from the receive fifo. m) in response to the chh interrupt, de-allocate the channel for other transfers. n) handling non-ack responses control transactions setup, data, and status stages of a control transfer must be performed as three separate transfers. setup-, data- or status-stage out transactions are performed similarly to the bulk out transactions explained previously. data- or status-stage in transactions are performed similarly to the bulk in transactions explained previously. for all three stages, the application is expected to set the eptyp field in otg_fs_hcchar1 to control. during the setu p stage, the application is expected to set the pid field in otg_fs_hctsiz1 to setup. interrupt out transactions a typical interrupt out operation is shown in figure 362 . the assumptions are: ? the application is attempting to send one packet in every frame (up to 1 maximum packet size), starting with the odd frame (transfer size = 1 024 bytes) ? the periodic transmit fifo can hold one packet (1 kb) ? periodic request queue depth = 4 the sequence of operations is as follows: a) initialize and enable channel 1. the application must set the oddfrm bit in otg_fs_hcchar1. b) write the first packet for channel 1. c) along with the last word write of each packet, the otg_fs host writes an entry to the periodic request queue. d) the otg_fs host attempts to send an out token in the next (odd) frame. e) the otg_fs host generates an xfrc interrupt as soon as the last packet is transmitted successfully. f) in response to the xfrc interrupt, reinitialize the channel for the next transfer. RM0033 usb on-the-go full-speed (otg_fs) d o c id 154 03 re v 3 1 027 /13 1 7 figu re 36 2. norma l int e rru pt out/in t rans a c t ions int e rrupt s e r v ice r o ut ine f o r int e rrupt o u t/in tra n sa ct ions a) in te rr u p t o u t unmask (nak/txerr/stall/x frc/frmor) if ( xf rc ) { reset erro r count mask ack de-allocat e channel } else if ( stall or frmor ) { mask ack unmask chh ho s t a p p lic a t io n d evi ce ah b u s b o u t d a t a 0 m p s 1 mp s 1 mps wr i t e _ t x _ f i f o ( c h_1 ) i n i t _r eg ( c h_1) s e t _ c h_en ( c h_2) i n i t _r eg( c h _ 2 ) write_tx_fifo (ch_1) i n o u t d a t a 1 m p s per i odi c r e q u es t q u eue a s s u m e th a t th i s q u e u e c an ho l d 4 en t r i e s . 1 5 d a t a 0 i n rxflvl interrupt 1 mps r ead _r x _ s t s r ead _r x _ f i f o read_rx_sts 1 2 3 4 6 2 3 6 7 8 9 od d (m i c ro ) fr a m e even (micro) frame i n i t _r eg ( c h_1) s e t _ c h_en ( c h_2) i n i t _r eg( c h _ 2 ) write_tx_fifo (ch_1) i n i t _r eg ( c h_1) 1 mps d a t a 1 5 4 a c k a c k a c k ch _ 1 ch _ 2 ch _ 2 ch _ 1 ai15676 rxflvl interrupt xfrc interrupt xfrc interrupt xfrc interrupt usb on-the-go full-speed (otg_fs) RM0033 1028/1317 doc id 15403 rev 3 disable channel if ( stall ) { transfer done = 1 } } else if ( nak or txerr ) { rewind buffer pointers reset error count mask ack unmask chh disable channel } else if ( chh ) { mask chh if (transfer done or (error_count == 3)) { de-allocate channel } else { re-initialize channel (in next b_interval - 1 frame) } } else if ( ack ) { reset error count mask ack } the application uses the nptxfe interrupt in otg_fs_gintsts to find the transmit fifo space. b) interrupt in unmask (nak/txerr/xfrc/bberr/stall/frmor/dterr) if ( xfrc ) { reset error count mask ack if (otg_fs_hctsizx.pktcnt == 0) { de-allocate channel } else { transfer done = 1 unmask chh disable channel RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 1029/1317 } } else if ( stall or frmor or nak or dterr or bberr ) { mask ack unmask chh disable channel if ( stall or bberr ) { reset error count transfer done = 1 } else if (! frmor ) { reset error count } } else if ( txerr ) { increment error count unmask ack unmask chh disable channel } else if ( chh ) { mask chh if (transfer done or (error_count == 3)) { de-allocate channel } else re-initialize channel (in next b_interval - 1 /frame) } } else if ( ack ) { reset error count mask ack } usb on-the-go full-speed (otg_fs) RM0033 1030/1317 doc id 15403 rev 3 interrupt in transactions the assumptions are: ? the application is attempting to receive one packet (up to 1 maximum packet size) in every frame, starting with odd (transfer size = 1 024 bytes). ? the receive fifo can hold at least one maximum-packet-size packet and two status words per packet (1 031 bytes). ? periodic request queue depth = 4. normal interrupt in operation the sequence of operations is as follows: a) initialize channel 2. the applic ation must set the oddfrm bit in otg_fs_hcchar2. b) set the chena bit in otg_fs_hcchar2 to write an in request to the periodic request queue. c) the otg_fs host writes an in request to the periodic request queue for each otg_fs_hcchar2 register write with the chena bit set. d) the otg_fs host attempts to send an in token in the next (odd) frame. e) as soon as the in packet is received and written to the receive fifo, the otg_fs host generates an rxflvl interrupt. f) in response to the rxflvl interrupt, read the received packet status to determine the number of bytes received, then read the receive fifo accordingly. the application must mask the rxflvl interrupt before reading the receive fifo, and unmask after reading the entire packet. g) the core generates the rxflvl interrupt for the transfer completion status entry in the receive fifo. the application must read and ignore the receive packet status when the receive packet status is not an in data packet (pktsts in grxstsr 0b0010). h) the core generates an xfrc interrupt as soon as the receive packet status is read. i) in response to the xfrc interrupt, read the pktcnt field in otg_fs_hctsiz2. if the pktcnt bit in otg_fs_hctsiz2 is not equal to 0, disable the channel before re-initializing the channel for the next transfer, if any). if pktcnt bit in otg_fs_hctsiz2 = 0, reinitialize the channel for the next transfer. this time, the application must reset the oddf rm bit in otg_fs_hcchar2. RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 1031/1317 isochronous out transactions a typical isochronous out operation is shown in figure 363 . the assumptions are: ? the application is attempting to send one packet every frame (up to 1 maximum packet size), starting with an odd frame. (transfer size = 1 024 bytes). ? the periodic transmit fifo can hold one packet (1 kb). ? periodic request queue depth = 4. the sequence of operations is as follows: a) initialize and enable channel 1. the application must set the oddfrm bit in otg_fs_hcchar1. b) write the first packet for channel 1. c) along with the last word write of each packet, the otg_fs host writes an entry to the periodic request queue. d) the otg_fs host attempts to send the out token in the next frame (odd). e) the otg_fs host generates the xfrc interrupt as soon as the last packet is transmitted successfully. f) in response to the xfrc interrupt, reinitialize the channel for the next transfer. g) handling non-ack responses usb on-the-go full-speed (otg_fs) RM0033 1032/1317 doc id 15403 rev 3 figu re 36 3. norma l isoc h r on ous out / in t r an sac tions int e rrupt s e r v ice r o ut ine f o r is oc hr onous o ut/in tra n s a c t i ons code sa mple : i s o c h r o nou s o u t unmask (frmor/xfrc) if ( xf rc ) { de-allocat e channel } else if ( frmor ) { unmask chh disable channel } ho s t a p p lic a t io n d evi ce ah b usb o u t d a t a 0 m p s 1 mps 1 mp s write_tx_fifo (ch_1) init_reg(ch_1) set_ch_en (ch_2) init_reg(ch_2) wr i t e _ t x _ f i f o ( c h_1 ) i n o u t d a t a 1 m p s periodic request queue assume that this queue can hold 4 entries. 1 5 d a t a 0 i n rxflvl interrupt 1 mps read_rx_sts read_rx_fifo read_rx_sts 1 2 3 4 6 2 3 6 7 8 9 od d (m i c ro ) fr a m e even (micro) frame i n i t _r eg ( c h_1) set_ch_en (ch_2) init_reg(ch_2) wr i t e _ t x _ f i f o ( c h_1 ) i n i t _r eg ( c h_1) 1 mps d a t a 1 5 4 a c k a c k a c k ch _ 1 ch _ 2 ch _ 2 ch _ 1 ai15676 rxflvl interrupt xfrc interrupt xfrc interrupt xfrc interrupt RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 1033/1317 else if ( chh ) { mask chh de-allocate channel } code sample: isochronous in unmask (txerr/xfrc/frmor/bberr) if ( xfrc or frmor ) { if ( xfrc and (otg_fs_hctsizx.pktcnt == 0)) { reset error count de-allocate channel } else { unmask chh disable channel } } else if ( txerr or bberr ) { increment error count unmask chh disable channel } else if ( chh ) { mask chh if (transfer done or (error_count == 3)) { de-allocate channel } else { re-initialize channel } } usb on-the-go full-speed (otg_fs) RM0033 1034/1317 doc id 15403 rev 3 isochronous in transactions the assumptions are: ? the application is attempting to receive one packet (up to 1 maximum packet size) in every frame starting with the next odd frame (transfer size = 1 024 bytes). ? the receive fifo can hold at least one maximum-packet-size packet and two status word per packet (1 031 bytes). ? periodic request queue depth = 4. the sequence of operations is as follows: a) initialize channel 2. the applic ation must set the oddfrm bit in otg_fs_hcchar2. b) set the chena bit in otg_fs_hcchar2 to write an in request to the periodic request queue. c) the otg_fs host writes an in request to the periodic request queue for each otg_fs_hcchar2 register write with the chena bit set. d) the otg_fs host attempts to send an in token in the next odd frame. e) as soon as the in packet is received and written to the receive fifo, the otg_fs host generates an rxflvl interrupt. f) in response to the rxflvl interrupt, read the received packet status to determine the number of bytes received, then read the receive fifo accordingly. the application must mask the rxflvl interrupt before reading the receive fifo, and unmask it after reading the entire packet. g) the core generates an rxflvl interrupt for the transfer completion status entry in the receive fifo. this time, the application must read and ignore the receive packet status when the receive packet status is not an in data packet (pktsts bit in otg_fs_grxstsr 0b0010). h) the core generates an xfrc interrupt as soon as the receive packet status is read. i) in response to the xfrc interrupt, read the pktcnt field in otg_fs_hctsiz2. if pktcnt 0 in otg_fs_hctsiz2, disable the channel before re-initializing the channel for the next transfer, if any. if pktcnt = 0 in otg_fs_hctsiz2, reinitialize the channel for the next transfer. this time, the application must reset the oddfrm bit in otg_fs_hcchar2. selecting the queue depth choose the periodic and non-periodic request queue depths carefully to match the number of periodic/non-periodic endpoints accessed. the non-periodic request queue depth affects the performance of non-periodic transfers. the deeper the queue (along with sufficient fifo size), the more often the core is able to pipeline non-periodic transfers. if the queue size is small, the core is able to put in new requests only when the queue space is freed up. the core?s periodic request queue depth is critical to perform periodic transfers as scheduled. select the periodic queue depth, based on the number of periodic transfers scheduled in a microframe. if the periodic request queue depth is smaller than the periodic transfers scheduled in a microframe, a frame overrun condition occurs. handling babble conditions otg_fs controller handles two cases of babble: packet babble and port babble. packet babble occurs if the device sends more data than the maximum packet size for RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 1035/1317 the channel. port babble occurs if the core continues to receive data from the device at eof2 (the end of frame 2, which is very close to sof). when otg_fs controller detects a packet babble, it stops writing data into the rx buffer and waits for the end of packet (eop). when it detects an eop, it flushes already written data in the rx buffer and generates a babble interrupt to the application. when otg_fs controller detects a port babble, it flushes the rxfifo and disables the port. the core then generates a port disabled interrupt (hprtint in otg_fs_gintsts, penchng in otg_fs_hprt). on receiving this interrupt, the application must determine that this is not due to an overcurrent condition (another cause of the port disabled interrupt) by checking poca in otg_fs_hprt, then perform a soft reset. the core does not send any more tokens after it has detected a port babble condition. 29.17.5 device programming model endpoint initialization on usb reset 1. set the nak bit for all out endpoints ? snak = 1 in otg_fs_doepctlx (for all out endpoints) 2. unmask the following interrupt bits ? inep0 = 1 in otg_fs_daintmsk (control 0 in endpoint) ? outep0 = 1 in otg_fs_daintmsk (control 0 out endpoint) ?stup=1 in doepmsk ? xfrc = 1 in doepmsk ? xfrc = 1 in diepmsk ? toc = 1 in diepmsk 3. set up the data fifo ram for each of the fifos ? program the otg_fs_grxfsiz register, to be able to receive control out data and setup data. if thresholding is not enabled, at a minimum, this must be equal to 1 max packet size of control endpoint 0 + 2 words (for the status of the control out data packet) + 10 words (for setup packets). ? program the otg_fs_tx0fsiz register (depending on the fifo number chosen) to be able to transmit control in data. at a minimum, this must be equal to 1 max packet size of control endpoint 0. 4. program the following fields in the endpoint-specific registers for control out endpoint 0 to receive a setup packet ? stupcnt = 3 in otg_fs_doeptsiz0 (to receive up to 3 back-to-back setup packets) at this point, all initia lization required to receive setup packets is done. endpoint initialization on enumeration completion 1. on the enumeration done interrupt (enumdne in otg_fs_gintsts), read the otg_fs_dsts register to determine the enumeration speed. 2. program the mpsiz field in otg_fs_diepctl0 to set the maximum packet size. this step configures control endpoint 0. the maximum packet size for a control endpoint depends on the enumeration speed. usb on-the-go full-speed (otg_fs) RM0033 1036/1317 doc id 15403 rev 3 at this point, the device is ready to receive sof packets and is configured to perform control transfers on control endpoint 0. endpoint initialization on setaddress command this section describes what the application must do when it receives a setaddress command in a setup packet. 1. program the otg_fs_dcfg register with the device address received in the setaddress command 1. program the core to send out a status in packet endpoint initialization on setconfiguration/setinterface command this section describes what the application must do when it receives a setconfiguration or setinterface command in a setup packet. 1. when a setconfiguration command is received, the application must program the endpoint registers to configure them with the characteristics of the valid endpoints in the new configuration. 2. when a setinterface command is received, the application must program the endpoint registers of the endpoints affected by this command. 3. some endpoints that were active in the prior configuration or alternate setting are not valid in the new configuration or alternate setting. these invalid endpoints must be deactivated. 4. unmask the interrupt for each active endpoint and mask the interrupts for all inactive endpoints in the otg_fs_daintmsk register. 5. set up the data fifo ram for each fifo. 6. after all required endpoints are configured; the application must program the core to send a status in packet. at this point, the device core is configured to receive and transmit any type of data packet. endpoint activation this section describes the steps required to activate a device endpoint or to configure an existing device endpoint to a new type. 1. program the characteristics of the required endpoint into the following fields of the otg_fs_diepctlx register (for in or bidirectional endpoints) or the otg_fs_doepctlx register (for out or bidirectional endpoints). ? maximum packet size ? usb active endpoint = 1 ? endpoint start data toggle (for interrupt and bulk endpoints) ? endpoint type ? txfifo number 2. once the endpoint is activated, the core st arts decoding the tokens addressed to that endpoint and sends out a valid handshake for each valid token received for the endpoint. endpoint deactivation this section describes the steps required to deactivate an existing endpoint. RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 1037/1317 1. in the endpoint to be deactivated, clear the usb active endpoint bit in the otg_fs_diepctlx register (for in or bidirectional endpoints) or the otg_fs_doepctlx register (for out or bidirectional endpoints). 2. once the endpoint is deactivated, the core ignores tokens addressed to that endpoint, which results in a timeout on the usb. note: 1 the application must meet the following conditions to set up the device core to handle traffic: nptxfem and rxflvlm in the otg_fs_gintmsk register must be cleared. 29.17.6 operational model setup and out data transfers this section describes the internal data flow and application-level operations during data out transfers and setup transactions. packet read this section describes how to read packets (out data and setup packets) from the receive fifo. 1. on catching an rxflvl interrupt (otg_fs_gintsts register), the application must read the receive status pop register (otg_fs_grxstsp). 2. the application can mask the rxflvl interrupt (in otg_fs_gintsts) by writing to rxflvl = 0 (in otg_fs_gintmsk), until it has read the packet from the receive fifo. 3. if the received packet?s byte count is not 0, the byte count amount of data is popped from the receive data fifo and stored in memory. if the received packet byte count is 0, no data is popped from the receive data fifo. 4. the receive fifo?s packet status readout indicates one of the following: a) global out nak pattern: pktsts = global out nak, bcnt = 0x000, epnum = don?t care (0x0), dpid = don?t care (0b00). these data indicate that the global out nak bit has taken effect. b) setup packet pattern: pktsts = setup, bcnt = 0x008, epnum = control ep num, dpid = d0. these data indicate that a setup packet for the specified endpoint is now available for reading from the receive fifo. c) setup stage done pattern: pktsts = setup stage done, bcnt = 0x0, epnum = control ep num, dpid = don?t care (0b00). these data indicate that the setup stage for the specified endpoint has completed and the data stage has started. after this entry is popped from the receive fifo, the core asserts a setup interrupt on the specified control out endpoint. d) data out packet pattern: pktsts = dataout, bcnt = size of the received data out packet (0 bcnt 1 024), epnum = epnum on which the packet was received, dpid = actual data pid. e) data transfer completed pattern: pktsts = data out transfer done, bcnt = 0x0, epnum = out ep num on which the data transfer is complete, dpid = don?t care (0b00). these data indicate that an out data transfer for the specified out endpoint has usb on-the-go full-speed (otg_fs) RM0033 1038/1317 doc id 15403 rev 3 completed. after this entry is popped from the receive fifo, the core asserts a transfer completed interrupt on the specified out endpoint. 5. after the data payload is popped from the receive fifo, the rxflvl interrupt (otg_fs_gintsts) must be unmasked. 6. steps 1?5 are repeated every time the application detects assertion of the interrupt line due to rxflvl in otg_fs_gintsts. readin g an empty receive fifo can result in undefined core behavior. figure 364 provides a flowchart of the above procedure. figure 364. receive fifo packet read setup transactions this section describes how the core handles setup packets and the application?s sequence for handling setup transactions. application requirements 1. to receive a setup packet, the stupcn t field (otg_fs_doeptsizx) in a control out endpoint must be programmed to a non-zero value. when the application programs the stupcnt field to a non-zero value, the core receives setup packets and writes them to the rece ive fifo, irrespective of the nak status and epena bit setting in otg_fs_doepctlx. the stupcnt field is decremented every time the control endpoint receives a setup packet. if the stupcnt field is not programmed to a proper value before receiving a setup packet, the core still receives the setup packet and decrements the stupcnt field, but the application may not be able to word_cnt = bcnt[11:2] + c ( bcnt[1] | bcnt[1]) rcv_out_pkt() rd_data = rd_reg (otg_fs_grxstsp); mem[0: word_cnt ? 1] = rd_rxfifo(rd_data.epnum, word_cnt) n rd_data.bcnt = 0 wait until rxflvl in otg_fs_gintstsg packet store in memory y a i15677 b RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 1039/1317 determine the correct number of setup packets received in the setup stage of a control transfer. ? stupcnt = 3 in otg_fs_doeptsizx 2. the application must always allocate some extra space in the receive data fifo, to be able to receive up to three setup packets on a control endpoint. ? the space to be reserved is 10 words. three words are required for the first setup packet, 1 word is required for the setup stage done word and 6 words are required to store two extra setup packets among all control endpoints. ? 3 words per setup packet are required to store 8 bytes of setup data and 4 bytes of setup status (setup packet pattern). the core reserves this space in the receive data. ? fifo to write setup data only, and never uses this space for data packets. 3. the application must read the 2 words of the setup packet from the receive fifo. 4. the application must read and discard the setup stage done word from the receive fifo. internal data flow 5. when a setup packet is received, the core writes the received data to the receive fifo, without checking for available space in the receive fifo and irrespective of the endpoint?s nak and stall bit settings. ? the core internally sets the in nak and out nak bits for the control in/out endpoints on which the setup packet was received. 6. for every setup packet received on the usb, 3 words of data are written to the receive fifo, and the stupcnt field is decremented by 1. ? the first word contains control information used internally by the core ? the second word contains the first 4 bytes of the setup command ? the third word contains the last 4 bytes of the setup command 7. when the setup stage changes to a data in/out stage, the core writes an entry (setup stage done word) to the receive fifo, indicating the completion of the setup stage. 8. on the ahb side, setup packets are emptied by the application. 9. when the application pops the setup stage done word from the receive fifo, the core interrupts the application with an stup interrupt (otg_fs_doepintx), indicating it can process the received setup packet. ? the core clears the endpoint enable bit for control out endpoints. application programming sequence 1. program the otg_fs_doeptsizx register. ? stupcnt = 3 2. wait for the rxflvl interrupt (otg_fs_gintsts) and empty the data packets from the receive fifo. 3. assertion of the stup interrupt (otg_fs_doepintx) marks a successful completion of the setup data transfer. ? on this interrupt, the application must read the otg_fs_doeptsizx register to determine the number of setup packets received and process the last received setup packet. usb on-the-go full-speed (otg_fs) RM0033 1040/1317 doc id 15403 rev 3 figure 365. processing a setup packet handling more than three back-to-back setup packets per the usb 2.0 specification, normally, during a setup packet error, a host does not send more than three back-to-back setup packets to the same endpoint. however, the usb 2.0 specification does not limit the number of back-to-back setup packets a host can send to the same endpoint. when this condition occurs, the otg_fs controller generates an interrupt (b2bstup in otg_fs_doepintx). setting the global out nak internal data flow: 1. when the application sets the global out nak (sgonak bit in otg_fs_dctl), the core stops writing data, except setup packets, to the receive fifo. irrespective of the space availability in the receive fifo, no n-isochronous out tokens receive a nak handshake response, and the core ignores isochronous out data packets 2. the core writes the global out nak pattern to the receive fifo. the application must reserve enough receive fifo space to write this data pattern. 3. when the application pops the global out nak pattern word from the receive fifo, the core sets the gonakeff interrupt (otg_fs_gintsts). 4. once the application detects this interrupt, it can assume that the core is in global out nak mode. the application can clear this interrupt by clearing the sgonak bit in otg_fs_dctl. application programming sequence wait for stup in otg_fs_doepintx rem_supcnt = rd_reg(doeptsizx) setup_cmd[31:0] = mem[4 ? 2 * rem_supcnt] setup_cmd[63:32] = mem[5 ? 2 * rem_supcnt] ctrl-rd/wr/2 stage find setup cmd type write 2-stage read setup_np_in_pkt status in phase rcv_out_pkt data out phase setup_np_in_pkt data in phase ai15678 RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 1041/1317 1. to stop receiving any kind of data in the receive fifo, the application must set the global out nak bit by programming the following field: ? sgonak = 1 in otg_fs_dctl 2. wait for the assertion of the gonakeff interrupt in otg_fs_gintsts. when asserted, this interrupt indicates that the core has stopped receiving any type of data except setup packets. 3. the application can receive valid out packets after it has set sgonak in otg_fs_dctl and before the core asserts the gonakeff interrupt (otg_fs_gintsts). 4. the application can temporarily mask this interrupt by writing to the ginakeffm bit in the otg_fs_gintmsk register. ? ginakeffm = 0 in the otg_fs_gintmsk register 5. whenever the application is ready to exit the global out nak mode, it must clear the sgonak bit in otg_fs_dctl. this also clears the gonakeff interrupt (otg_fs_gintsts). ? otg_fs_dctl = 1 in cgonak 6. if the application has masked this interrupt earlier, it must be unmasked as follows: ? ginakeffm = 1 in gintmsk disabling an out endpoint the application must use this sequence to disable an out endpoint that it has enabled. application programming sequence: 1. before disabling any out endpoint, the application must enable global out nak mode in the core. ? sgonak = 1 in otg_fs_dctl 2. wait for the gonakeff in terrupt (otg_fs_gintsts) 3. disable the required out endpoint by programming the following fields: ? epdis = 1 in otg_fs_doepctlx ? snak = 1 in otg_fs_doepctlx 4. wait for the epdisd in terrupt (otg_fs_doepintx), wh ich indicates that the out endpoint is completely disabled. when the epdisd interrupt is asserted, the core also clears the following bits: ? epdis = 0 in otg_fs_doepctlx ? epena = 0 in otg_fs_doepctlx 5. the application must clear the global out nak bit to start receiving data from other non-disabled out endpoints. ? sgonak = 0 in otg_fs_dctl generic non-isochronous out data transfers this section describes a regular non-isochronous out data transfer (control, bulk, or interrupt). application requirements: usb on-the-go full-speed (otg_fs) RM0033 1042/1317 doc id 15403 rev 3 1. before setting up an out transfer, the application must allocate a buffer in the memory to accommodate all data to be received as part of the out transfer. 2. for out transfers, the transfer size field in the endpoint?s transfer size register must be a multiple of the maximum packet size of the endpoint, adjusted to the word boundary. ? transfer size[epnum] = n (mpsiz[epnum] + 4 ? (mpsiz[epnum] mod 4)) ? packet count[epnum] = n ? n > 0 3. on any out endpoint interrupt, the applic ation must read the endpoint?s transfer size register to calculate the size of the payload in the memory. the received payload size can be less than the programmed transfer size. ? payload size in memory = application programmed initial transfer size ? core updated final transfer size ? number of usb packets in which this payload was received = application programmed initial packet count ? core updated final packet count internal data flow: 1. the application must set the transfer size and packet count fields in the endpoint- specific registers, clear the nak bit, and enable the endpoint to receive the data. 2. once the nak bit is cleared, the core starts receiving data and writes it to the receive fifo, as long as there is space in the receive fifo. for every data packet received on the usb, the data packet and its status are written to the receive fifo. every packet (maximum packet size or short packet) written to the receive fifo decrements the packet count field for that endpoint by 1. ? out data packets received with bad data crc are flushed from the receive fifo automatically. ? after sending an ack for the packet on the usb, the core discards non- isochronous out data packets that the host, which cannot detect the ack, re- sends. the application does not detect multiple back-to-back data out packets on the same endpoint with the same data pid. in this case the packet count is not decremented. ? if there is no space in the receive fifo, isochronous or non-isochronous data packets are ignored and not written to the receive fifo. additionally, non- isochronous out tokens receive a nak handshake reply. ? in all the above three cases, the packet count is not decremented because no data are written to the receive fifo. 3. when the packet count becomes 0 or when a short packet is received on the endpoint, the nak bit for that endpoint is set. once the nak bit is set, the isochronous or non- isochronous data packets are ignored and not written to the receive fifo, and non- isochronous out tokens receive a nak handshake reply. 4. after the data are written to the receive fifo, the application reads the data from the receive fifo and writes it to external memory, one packet at a time per endpoint. 5. at the end of every packet write on the ahb to external memory, the transfer size for the endpoint is decremented by the size of the written packet. RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 1043/1317 6. the out data transfer completed pattern for an out endpoint is written to the receive fifo on one of the following conditions: ? the transfer size is 0 and the packet count is 0 ? the last out data packet written to the receive fifo is a short packet (0 packet size < maximum packet size) 7. when either the application pops this entry (out data transfer completed), a transfer completed interrupt is generated for the endpoint and the endpoint enable is cleared. application programming sequence: 1. program the otg_fs_doeptsizx register for the transfer size and the corresponding packet count. 2. program the otg_fs_doepctlx register with the endpoint characteristics, and set the epena and cnak bits. ? epena = 1 in otg_fs_doepctlx ? cnak = 1 in otg_fs_doepctlx 3. wait for the rxflvl interrupt (in otg_fs_gintsts) and empty the data packets from the receive fifo. ? this step can be repeated many times, depending on the transfer size. 4. asserting the xfrc interrupt (otg_fs_doepintx) marks a successful completion of the non-isochronous out data transfer. 5. read the otg_fs_doeptsizx register to determine the size of the received data payload. generic isochronous out data transfer this section describes a regular isochronous out data transfer. application requirements: 1. all the application requirements for non-isochronous out data transfers also apply to isochronous out data transfers. 2. for isochronous out data transfers, the transfer size and packet count fields must always be set to the number of maximum-packet-size packets that can be received in a single frame and no more. isochronous out data transfers cannot span more than 1 frame. 3. the application must read all isochronous out data packets from the receive fifo (data and status) before the end of the periodic frame (eopf interrupt in otg_fs_gintsts). 4. to receive data in the following frame, an isochronous out endpoint must be enabled after the eopf (otg_fs_gintsts) and before the sof (otg_fs_gintsts). internal data flow: 1. the internal data flow for isochronous out endpoints is the same as that for non- isochronous out endpoints, but for a few differences. 2. when an isochronous out endpoint is enabled by setting the endpoint enable and clearing the nak bits, the even/odd frame bit must also be set appropriately. the core receives data on an isochronous out endpoint in a particular frame only if the following condition is met: ? eonum (in otg_fs_doepctlx) = soffn[0] (in otg_fs_dsts) 3. when the application completely reads an isochronous out data packet (data and status) from the receive fifo, the core updates the rxdpid field in usb on-the-go full-speed (otg_fs) RM0033 1044/1317 doc id 15403 rev 3 otg_fs_doeptsizx with the data pid of the last isochronous out data packet read from the receive fifo. application programming sequence: 1. program the otg_fs_doeptsizx register for the transfer size and the corresponding packet count 2. program the otg_fs_doepctlx register with the endpoint characteristics and set the endpoint enable, clearnak, and even/odd frame bits. ? epena = 1 ?cnak=1 ? eonum = (0: even/1: odd) 3. wait for the rxflvl interrupt (in otg_fs_gintsts) and empty the data packets from the receive fifo ? this step can be repeated many times, depending on the transfer size. 4. the assertion of the xfrc interrupt (in otg_fs_doepintx) marks the completion of the isochronous out data transfer. this inte rrupt does not necessarily mean that the data in memory are good. 5. this interrupt cannot always be detected for isochronous out transfers. instead, the application can detect the iisooxfrm interrupt in otg_fs_gintsts. 6. read the otg_fs_doeptsizx register to determine the size of the received transfer and to determine the validity of the data received in the frame. the application must treat the data received in memory as valid only if one of the following conditions is met: ? rxdpid = d0 (in otg_fs_doeptsizx) and the number of usb packets in which this payload was received = 1 ? rxdpid = d1 (in otg_fs_doeptsizx) and the number of usb packets in which this payload was received = 2 ? rxdpid = d2 (in otg_fs_doeptsizx) and the number of usb packets in which this payload was received = 3 the number of usb packets in which this payload was received = application programmed initial packet count ? core updated final packet count the application can discard invalid data packets. incomplete isochronous out data transfers this section describes the application prog ramming sequence when isochronous out data packets are dropped inside the core. internal data flow: 1. for isochronous out endpoints, the xfrc interrupt (in otg_fs_doepintx) may not always be asserted. if the core drops isochronous out data packets, the application could fail to detect the xfrc interrupt (otg_fs_doepintx) under the following circumstances: ? when the receive fifo cannot accommodate the complete iso out data packet, the core drops the received iso out data ? when the isochronous out data packet is received with crc errors ? when the isochronous out token received by the core is corrupted ? when the application is very slow in reading the data from the receive fifo 2. when the core detects an end of periodic frame before transfer completion to all isochronous out endpoints, it asserts the incomplete isochronous out data interrupt RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 1045/1317 (iisooxfrm in otg_fs_gintsts), indicating that an xfrc interrupt (in otg_fs_doepintx) is not asserted on at least one of the isochronous out endpoints. at this point, the endpoint with the incomplete transfer remains enabled, but no active transfers remain in progress on this endpoint on the usb. application programming sequence: 1. asserting the iisooxfrm interrupt (otg_fs_gintsts) indicates that in the current frame, at least one isochronous out endpoint has an incomplete transfer. 2. if this occurs because isochronous out data is not completely emptied from the endpoint, the application must ensure that the application empties all isochronous out data (data and status) from the receive fifo before proceeding. ? when all data are emptied from the receive fifo, the application can detect the xfrc interrupt (otg_fs_doepintx). in this case, the application must re- enable the endpoint to receive isochronous out data in the next frame. 3. when it receives an iisooxfrm interrupt (in otg_fs_gintsts), the application must read the control registers of all isochronous out endpoints (otg_fs_doepctlx) to determine which endpoints had an incomplete transfer in the current microframe. an endpoint transfer is incomplete if both the following conditions are met: ? eonum bit (in otg_fs_doepctlx) = soffn[0] (in otg_fs_dsts) ? epena = 1 (in otg_fs_doepctlx) 4. the previous step must be performed before the sof interrupt (in otg_fs_gintsts) is detected, to ensure that the current frame number is not changed. 5. for isochronous out endpoints with incomplete transfers, the application must discard the data in the memory and disable the endpoint by setting the epdis bit in otg_fs_doepctlx. 6. wait for the epdis interrupt (in otg_fs_doepintx) and enable the endpoint to receive new data in the next frame. ? because the core can take some time to disable the endpoint, the application may not be able to receive the data in the next frame after receiving bad isochronous data. stalling a non-isochronous out endpoint this section describes how the application can stall a non-isochronous endpoint. 1. put the core in the global out nak mode. 2. disable the required endpoint ? when disabling the endpoint, instead of setting the snak bit in otg_fs_doepctl, set stal l = 1 (in otg_fs_doepctl). the stall bit always takes precedence over the nak bit. 3. when the application is ready to end the stall handshake for the endpoint, the stall bit (in otg_fs_doepctlx) must be cleared. 4. if the application is setting or clearing a stall for an endpoint due to a setfeature.endpoint halt or clearfeature.endpoint halt command, the stall bit must be set or cleared before the application sets up the status stage transfer on the control endpoint. usb on-the-go full-speed (otg_fs) RM0033 1046/1317 doc id 15403 rev 3 exam ples th is sect ion d e scr i b e s and d e p i ct s som e fu nd ame n t a l tr ansf e r t y pe s an d sce nar io s . bu lk out tr ansact i on fig u r e 36 6 d epict s th e r e cep t io n o f a sing le bu lk out dat a p a c k e t fr om th e usb t o t h e ahb a nd de scr i b e s t h e e v en ts in v o lv ed in t h e p r o c e s s . figu re 36 6. bulk out t rans a c t ion af t e r a set c o n f i gu r a t i on /se t i n t e r f ace comm and , t h e ap plicat ion init ializ e s a ll out en dp oint s b y setting cnak = 1 and epen a = 1 (in o t g_fs _doepctlx), and setting a suitab l e xfrsiz a n d pktcnt in th e o t g_ fs_d oep t si zx r e g iste r . 1. h o s t atte m p t s t o se nd d a t a (o ut to k e n) to a n en d p o i nt . 2 . when th e core re ce iv es t h e out t o k e n on t h e usb , it st or es t h e pac k e t in th e rxf i fo be ca use space is a v a ilab l e th er e . 3. af ter w r it ing t h e co m p le te p a c k e t in th e r xfifo , t h e c o r e th en a sse r t s th e rxfl vl int e r r up t ( i n o t g_ fs_g intsts) . 4 . on r e ce iv ing t he pktcnt n u mb er o f usb pac k e ts , th e co re int e r n a lly se ts t h e nak b i t f o r th is e n d p o in t to p r e v en t it fr o m re ce ivin g a n y m o r e pa c k e t s . 5 . the app lica t ion pr ocesses th e int e r r upt an d re ads th e da ta f r om t he rxfif o . 6 . when t h e app lica t ion ha s r ead all th e da ta ( e q u iv ale n t t o xfrsi z), th e core gen er a t e s an xfrc int e r r upt (in o t g_f s _doepi ntx) . 7 . the app lica t ion pr ocesses th e int e r r upt an d uses th e se tt in g of t h e xfrc int e r r up t bit (in o t g_ fs_doepi nt x) to d e t e r m ine t h a t t he in te nde d t r ansf e r i s comp let e . in it _ o u t _ e p ho s t de v i c e us b o u t a c k rxflvl intr i w r _ r e g (doeptsizx) wr_reg(doepctlx) 64 bytes o u t n a k xa ct _ 1 a p p lic a t ion xfrc i n t r d o e p c t l x . n a k = 1 pktcnt 0 xfrsiz = 0 r i d le u n t i l in t r rcv_out _pkt() idle until intr on n e w x f e r o r rx fi fo not em pt y 1 2 3 4 5 6 7 8 xfrsiz = 64 bytes pktcnt = 1 epena = 1 cnak = 1 ai15679b RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 1047/1317 in data transfers packet write this section describes how the application writes data packets to the endpoint fifo when dedicated transmit fifos are enabled. 1. the application can either choose the polling or the interrupt mode. ? in polling mode, the application monitors th e status of the endpoint transmit data fifo by reading the ot g_fs_dtxfstsx register, to determine if there is enough space in the data fifo. ? in interrupt mode, the application waits for the txfe interrupt (in otg_fs_diepintx) and then reads the otg_fs_dtxfstsx register, to determine if there is enough space in the data fifo. ? to write a single non-zero length data packet, there must be space to write the entire packet in the data fifo. ? to write zero length packet, the application must not look at the fifo space. 2. using one of the above mentioned methods, when the application determines that there is enough space to write a transmit packet, the application must first write into the endpoint control register, before writing the data into the data fifo. typically, the application, must do a read modify write on the otg_fs_diepctlx register to avoid modifying the contents of the register, except for setting the endpoint enable bit. the application can write multiple packets for the same endpoint into the transmit fifo, if space is available. for periodic in endpoints, the application must write packets only for one microframe. it can write packets for the next periodic transaction only after getting transfer complete for the previous transaction. setting in endpoint nak internal data flow: 1. when the application sets the in nak fo r a particular endpoint, the core stops transmitting data on the end point, irrespective of data availability in the endpoint?s transmit fifo. 2. non-isochronous in tokens receive a nak handshake reply ? isochronous in tokens receive a zero-data-length packet reply 3. the core asserts the inepne (in endpoint nak effective) interrupt in otg_fs_diepintx in response to the snak bit in otg_fs_diepctlx. 4. once this interrupt is seen by the application, the application can assume that the endpoint is in in nak mode. this interrupt can be cleared by the application by setting the cnak bit in otg_fs_diepctlx. application programming sequence: usb on-the-go full-speed (otg_fs) RM0033 1048/1317 doc id 15403 rev 3 1. to stop transmitting any data on a particular in endpoint, the application must set the in nak bit. to set this bit, the following field must be programmed. ? snak = 1 in otg_fs_diepctlx 2. wait for assertion of the inepne interr upt in otg_fs_diepintx. this interrupt indicates that the core has stopped transmitting data on the endpoint. 3. the core can transmit valid in data on the endpoint after the application has set the nak bit, but before the assertion of the nak effective interrupt. 4. the application can mask this interrupt te mporarily by writing to the inepnem bit in diepmsk. ? inepnem = 0 in diepmsk 5. to exit endpoint nak mode , the application must clear t he nak status bit (naksts) in otg_fs_diepctlx. this also clears the inepne interrupt (in otg_fs_diepintx). ? cnak = 1 in otg_fs_diepctlx 6. if the application masked this interrupt earlier, it must be unmasked as follows: ? inepnem = 1 in diepmsk in endpoint disable use the following sequence to disable a specif ic in endpoint that has been previously enabled. application programming sequence: 1. the application must stop writing data on the ahb for the in endpoint to be disabled. 2. the application must set the endpoint in nak mode. ? snak = 1 in otg_fs_diepctlx 3. wait for the inepne interrupt in otg_fs_diepintx. 4. set the following bits in the otg_fs_diepctlx register for the endpoint that must be disabled. ? epdis = 1 in otg_fs_diepctlx ? snak = 1 in otg_fs_diepctlx 5. assertion of the epdisd interrupt in otg_fs_diepintx indicates that the core has completely disabled the specified endpoint. along with the assertion of the interrupt, the core also clears the following bits: ? epena = 0 in otg_fs_diepctlx ? epdis = 0 in otg_fs_diepctlx 6. the application must read the otg_fs_dieptsizx register for the periodic in ep, to calculate how much data on the endpoint were transmitted on the usb. 7. the application must flush the data in the endpoint transmit fifo, by setting the following fields in the otg_fs_grstctl register: ? txfnum (in otg_fs_grstctl) = endpoint transmit fifo number ? txfflsh in (otg_fs_grstctl) = 1 the application must poll the otg_fs_grstctl register, until the txfflsh bit is cleared by the core, which indicates the end of flush operation. to transmit new data on this endpoint, the application can re-enable the endpoint at a later point. RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 1049/1317 generic non-periodic in data transfers application requirements: 1. before setting up an in transfer, the application must ensure that all data to be transmitted as part of the in transfer are part of a single buffer. 2. for in transfers, the transfer size field in the endpoint transfer size register denotes a payload that constitutes multiple maximum-packet-size packets and a single short packet. this short packet is transmitted at the end of the transfer. ? to transmit a few maximum-packet-size packets and a short packet at the end of the transfer: transfer size[epnum] = x mpsiz[epnum] + sp if (sp > 0), then packet count[epnum] = x + 1. otherwise, packet count[epnum] = x ? to transmit a single zero-length data packet: transfer size[epnum] = 0 packet count[epnum] = 1 ? to transmit a few maximum-packet-size packets and a zero-length data packet at the end of the transfer, the application must split the transfer into two parts. the first sends maximum-packet-size data pa ckets and the second sends the zero- length data packet alone. first transfer: transfer size[epnum] = x mpsiz[epnum]; packet count = n ; second transfer: transfer size[epnum] = 0; packet count = 1; 3. once an endpoint is enabled for data transfers, the core updates the transfer size register. at the end of the in transfer, the application must read the transfer size register to determine how much data posted in the transmit fifo have already been sent on the usb. 4. data fetched into transmit fifo = application-programmed initial transfer size ? core- updated final transfer size ? data transmitted on usb = (application-pr ogrammed initial packet count ? core updated final packet count) mpsiz[epnum] ? data yet to be transmitted on usb = (app lication-programmed initial transfer size ? data transmitted on usb) internal data flow: 1. the application must set the transfer size and packet count fields in the endpoint- specific registers and enable the endpoint to transmit the data. 2. the application must also write the required data to the transmit fifo for the endpoint. 3. every time a packet is written into the transmit fifo by the application, the transfer size for that endpoint is decremented by the packet size. the data is fetched from the memory by the application, until the transfer size for the endpoint becomes 0. after writing the data into the fifo, the ?number of packets in fifo? count is incremented (this is a 3-bit count, internally maintained by the core for each in endpoint transmit fifo. the maximum number of packets maintained by the core at any time in an in endpoint fifo is eight). for zero-length packets, a separate flag is set for each fifo, without any data in the fifo. 4. once the data are written to the transmit fifo, the core reads them out upon receiving an in token. for every non-isochronous in data packet transmitted with an ack usb on-the-go full-speed (otg_fs) RM0033 1050/1317 doc id 15403 rev 3 handshake, the packet count for the endpoint is decremented by one, until the packet count is zero. the packet count is not decremented on a timeout. 5. for zero length packets (indicated by an internal zero length flag), the core sends out a zero-length packet for the in token and decrements the packet count field. 6. if there are no data in the fifo for a received in token and the packet count field for that endpoint is zero, the core generates an ?in token received when txfifo is empty? (ittxfe) interrupt for the endpoint, provided that the endpoint nak bit is not set. the core responds with a nak handshake for non-isochronous endpoints on the usb. 7. the core internally rewinds the fifo pointers and no timeout interrupt is generated. 8. when the transfer size is 0 and the packet count is 0, the transfer complete (xfrc) interrupt for the endpoint is generated and the endpoint enable is cleared. application programming sequence: 1. program the otg_fs_dieptsizx register with the transfer size and corresponding packet count. 2. program the otg_fs_diepctlx register with the endpoint characteristics and set the cnak and epena (endpoint enable) bits. 3. when transmitting non-zero length data packet, the application must poll the o tg_fs_dtxfstsx register (where x is the fifo number associated with that endpoint) to determine whether there is enough space in the data fifo. the application can optionally use txfe (in otg_fs_diepintx) before writing the data. generic periodic in data transfers this section describes a typica l periodic in data transfer. application requirements: 1. application requirements 1, 2, 3, and 4 of generic non-periodic in data transfers on page 1049 also apply to periodic in data transfers, except for a slight modification of requirement 2. ? the application can only transmit multiples of maximum-packet-size data packets or multiples of maximum-packet-size packets, plus a short packet at the end. to transmit a few maximum-packet-size packets and a short packet at the end of the transfer, the following conditions must be met: transfer size[epnum] = x mpsiz[epnum] + sp (where x is an integer 0, and 0 sp < mpsiz[epnum]) if (sp > 0), packet count[epnum] = x + 1 otherwise, packet count[epnum] = x ; mcnt[epnum] = packet count[epnum] ? the application cannot transmit a zero-length data packet at the end of a transfer. it can transmit a single zero-length data pa cket by itself. to transmit a single zero- length data packet: ? transfer size[epnum] = 0 packet count[epnum] = 1 mcnt[epnum] = packet count[epnum] RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 1051/1317 2. the application can only schedule data transfers one frame at a time. ? (mcnt ? 1) mpsiz xfersiz mcnt mpsiz ? pktcnt = mcnt (in otg_fs_dieptsizx) ? if xfersiz < mcnt mpsiz, the last data packet of the transfer is a short packet. ? note that: mcnt is in otg_fs_dieptsizx, mpsiz is in otg_fs_diepctlx, pktcnt is in otg_fs_dieptsizx and xfersiz is in otg_fs_dieptsizx 3. the complete data to be transmitted in the frame must be written into the transmit fifo by the application, before the in token is received. even when 1 word of the data to be transmitted per frame is missing in the transmit fifo when the in token is received, the core behaves as when the fifo is empty. when the transmit fifo is empty: ? a zero data length packet would be transmitted on the usb for isochronous in endpoints ? a nak handshake would be transmitted on the usb for interrupt in endpoints internal data flow: 1. the application must set the transfer size and packet count fields in the endpoint- specific registers and enable the endpoint to transmit the data. 2. the application must also write the required data to the associated transmit fifo for the endpoint. 3. every time the application writes a packet to the transmit fifo, the transfer size for that endpoint is decremented by the packet size. the data are fetched from application memory until the transfer size for the endpoint becomes 0. 4. when an in token is received for a periodic endpoint, the core transmits the data in the fifo, if available. if the complete data payload (complete packet, in dedicated fifo mode) for the frame is not present in the fifo, then the core generates an in token received when txfifo empty interrupt for the endpoint. ? a zero-length data packet is transmitted on the usb for isochronous in endpoints ? a nak handshake is transmitted on the usb for interrupt in endpoints 5. the packet count for the endpoint is decremented by 1 under the following conditions: ? for isochronous endpoints, when a zero- or non-zero-length data packet is transmitted ? for interrupt endpoints, when an ack handshake is transmitted ? when the transfer size and packet count are both 0, the transfer completed interrupt for the endpoint is generated and the endpoint enable is cleared. 6. at the ?periodic frame interval? (controlled by pfivl in otg_fs_dcfg), when the core finds non-empty any of the isochronous in endpoint fifos scheduled for the current frame non-empty, the core generates an iisoixfr interrupt in otg_fs_gintsts. usb on-the-go full-speed (otg_fs) RM0033 1052/1317 doc id 15403 rev 3 application programming sequence: 1. program the otg_fs_diepctlx register with the endpoint characteristics and set the cnak and epena bits. 2. write the data to be transmitted in the next frame to the transmit fifo. 3. asserting the ittxfe interrupt (in otg_fs_diepintx) indicates that the application has not yet written all data to be transmitted to the transmit fifo. 4. if the interrupt endpoint is already enabled when this interrupt is detected, ignore the interrupt. if it is not enabled, enable the endpoint so that the data can be transmitted on the next in token attempt. 5. asserting the xfrc interrupt (in otg_fs_diepintx) with no ittxfe interrupt in otg_fs_diepintx indicates the successful completion of an isochronous in transfer. a read to the otg_fs_dieptsizx register must give transfer size = 0 and packet count = 0, indicating all data were transmitted on the usb. 6. asserting the xfrc interrupt (in otg_fs_diepintx), with or without the ittxfe interrupt (in otg_fs_diepintx), indicates the successful completion of an interrupt in transfer. a read to the otg_fs_dieptsizx register must give transfer size = 0 and packet count = 0, indicating all data were transmitted on the usb. 7. asserting the incomplete isochronous in transfer (iisoixfr) interrupt in otg_fs_gintsts with none of the aforementioned interrupts indicates the core did not receive at least 1 periodic in token in the current frame. incomplete isochronous in data transfers this section describes what the application must do on an incomplete isochronous in data transfer. internal data flow: 1. an isochronous in transfer is treated as in complete in one of the following conditions: a) the core receives a corrupted isochronous in token on at least one isochronous in endpoint. in this case, the application detects an incomplete isochronous in transfer interrupt (iisoixfr in otg_fs_gintsts). b) the application is slow to write the complete data payload to the transmit fifo and an in token is received before the complete data payload is written to the fifo. in this case, the application detects an in token received when txfifo empty interrupt in otg_fs_diepintx. the application can ignore this interrupt, as it eventually results in an incomplete isochro nous in transfer interrupt (iisoixfr in otg_fs_gintsts) at the end of periodic frame. the core transmits a zero-length data packet on the usb in response to the received in token. 2. the application must stop writing the data payload to the transmit fifo as soon as possible. 3. the application must set the nak bit and the disable bit for the endpoint. 4. the core disables the endpoint, clears the disable bit, and asserts the endpoint disable interrupt for the endpoint. RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 1053/1317 application programming sequence: 1. the application can ignore the in token received when txfifo empty interrupt in otg_fs_diepintx on any isochronous in endpoint, as it eventually results in an incomplete isochronous in transfer interrupt (in otg_fs_gintsts). 2. assertion of the incomplete isochronous in transfer interrupt (in otg_fs_gintsts) indicates an incomplete isochronous in trans fer on at least one of the isochronous in endpoints. 3. the application must read the endpoint control register for all isochronous in endpoints to detect endpoints with incomplete in data transfers. 4. the application must stop writing data to the periodic transmit fifos associated with these endpoints on the ahb. 5. program the following fields in the otg_fs_diepctlx register to disable the endpoint: ? snak = 1 in otg_fs_diepctlx ? epdis = 1 in otg_fs_diepctlx 6. the assertion of the endpoint disabled interrupt in otg_fs_diepintx indicates that the core has disabled the endpoint. ? at this point, the application must flush the data in the associated transmit fifo or overwrite the existing data in the fifo by enabling the endpoint for a new transfer in the next microframe. to flush the data, the application must use the otg_fs_grstctl register. stalling non-isochronous in endpoints this section describes how the application can stall a non-isochronous endpoint. application programming sequence: 1. disable the in endpoint to be stalled. set the stall bit as well. 2. epdis = 1 in otg_fs_diepctlx, when the endpoint is already enabled ? stall = 1 in otg_fs_diepctlx ? the stall bit always takes precedence over the nak bit 3. assertion of the endpoint disabled interrupt (in otg_fs_diepintx) indicates to the application that the core has disabled the specified endpoint. 4. the application must flush the non-periodic or periodic transmit fifo, depending on the endpoint type. in case of a non-periodic endpoint, the application must re-enable the other non-periodic endpoints that do not need to be stalled, to transmit data. 5. whenever the application is ready to end the stall handshake for the endpoint, the stall bit must be cleared in otg_fs_diepctlx. 6. if the application sets or clears a stall bit for an endpoint due to a setfeature.endpoint halt command or clearfeature.endpoint halt command, the stall bit must be set or cleared before the application sets up the status stage transfer on the control endpoint. special case: stalling the control out endpoint the core must stall in/out tokens if, during the data stage of a control transfer, the host sends more in/out tokens than are specified in the setup packet. in this case, the application must enable the ittxfe interrupt in otg_fs_diepintx and the otepdis interrupt in otg_fs_doepintx during the data stage of the control transfer, after the core has transferred the amount of data specified in the setup packet. then, when the usb on-the-go full-speed (otg_fs) RM0033 1054/1317 doc id 15403 rev 3 application receives this interrupt, it must set the stall bit in the corresponding endpoint control register, and clear this interrupt. 29.17.7 worst case response time when the otg_fs controller acts as a device, there is a worst case response time for any tokens that follow an isochronous out. this worst case response time depends on the ahb clock frequency. the core registers are in the ahb domain, and the core does not accept another token before updating these register values. the worst case is for any token following an isochronous out, because for an isochronous transaction, there is no handshake and the next token could come sooner. this worst case value is 7 phy clocks when the ahb clock is the same as the phy clock. when the ahb clock is faster, this value is smaller. if this worst case condition occurs, the core responds to bulk/interrupt tokens with a nak and drops isochronous and setup tokens. the ho st interprets this as a timeout condition for setup and retries the setup packet. for isochronous transfers, the incomplete isochronous in transfer interrupt (iisoixfr) and incomplete isochronous out transfer interrupt (iisooxfr) inform the application that isochronous in/out packets were dropped. choosing the value of trdt in otg_fs_gusbcfg the value in trdt (otg_fs_gusbcfg) is the time it takes for the mac, in terms of phy clocks after it has received an in token, to get the fifo status, and thus the first data from the pfc block. this time involves the synchronization delay between the phy and ahb clocks. the worst case delay for this is when the ahb clock is the same as the phy clock. in this case, the delay is 5 clocks. once the mac receives an in token, this information (token received) is synchronized to the ahb clock by the pfc (the pfc runs on the ahb clock). the pfc then reads the data from the spram and writes them into the dual clock source buffer. the mac then reads the data out of the source buffer (4 deep). if the ahb is running at a higher frequency than the phy, the application can use a smaller value for trdt (in otg_fs_gusbcfg). figure 367 has the following signals: tkn_rcvd: token received information from mac to pfc dynced_tkn_rcvd: doubled sync tkn_rcvd, from pclk to hclk domain spr_read: read to spram spr_addr: address to spram spr_rdata: read data from spram srcbuf_push: push to the source buffer srcbuf_rdata: read data from the source buffer. data seen by mac the application can use the following formula to calculate the value of trdt: 4 ahb clock + 1 phy clock = (2 clock sy nc + 1 clock memory address + 1 clock memory data from sync ram) + (1 phy clock (next phy clock mac can sample the 2 clock fifo outputs) RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 1055/1317 figure 367. trdt max timing case 29.17.8 otg programming model the otg_fs controller is an otg device s upporting hnp and srp. when the core is connected to an ?a? plug, it is referred to as an a-device. when the core is connected to a ?b? plug it is referred to as a b-device. in host mode, the otg_fs controller turns off v bus to conserve power. srp is a method by which the b-device signals the a-device to turn on v bus power. a device must perform both data-line pulsing and v bus pulsing, but a host can detect either data-line pulsing or v bus pulsing for srp. hnp is a method by which the b- device negotiates and switches to host role. in negotiated mode after hnp, the b-device suspends the bus and reverts to the device role. a-device session request protocol the application must set the srp-capable bit in the core usb configuration register. this enables the otg_fs controller to detect srp as an a-device. 12345678 0ns 50ns 100ns 150ns 200ns hclk pclk tkn_rcvd dsynced_tkn_rcvd spr_read spr_addr spr_rdata srcbuf_push srcbuf_rdata 5 clocks d1 a1 d1 ai15680 usb on-the-go full-speed (otg_fs) RM0033 1056/1317 doc id 15403 rev 3 figure 368. a-device srp 1. drv_vbus = v bus drive signal to the phy vbus_valid = v bus valid signal from phy a_valid = a-peripheral v bus level signal to phy d+ = data plus line d- = data minus line 1. to save power, the application suspends and turns off port power when the bus is idle by writing the port suspend and port power bits in the host port control and status register. 2. phy indicates port power off by deasserting the vbus_valid signal. 3. the device must detect se0 for at least 2 ms to start srp when v bus power is off. 4. to initiate srp, the device turns on its data line pull-up resistor for 5 to 10 ms. the otg_fs controller detects data-line pulsing. 5. the device drives v bus above the a-device session valid (2.0 v minimum) for v bus pulsing. the otg_fs controller interrupts the application on detecting srp. the session request detected bit is set in global interrupt status register (srqint set in otg_fs_gintsts). 6. the application must service the session request detected interrupt and turn on the port power bit by writing the port power bit in the host port control and status register. the phy indicates port power-on by asserting the vbus_valid signal. 7. when the usb is powered, the device connects, completing the srp process. ai15681 drv_vbus vbus_valid a_valid d+ d- suspend v bus pulsing data line pulsing connect 1 6 2 5 3 47 low RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 1057/1317 b-device session request protocol the application must set the srp-capable bit in the core usb configuration register. this enables the otg_fs controller to initiate srp as a b-device. srp is a means by which the otg_fs controller can request a new session from the host. figure 369. b-device srp 1. vbus_valid = v bus valid signal from phy b_valid = b-peripheral valid session to phy dischrg_vbus = discharge signal to phy sess_end = session end signal to phy chrg_vbus = charge v bus signal to phy dp = data plus line dm = data minus line 1. to save power, the host suspends and turns off port power when the bus is idle. the otg_fs controller sets the early suspend bit in the core interrupt register after 3 ms of bus idleness. following this, the otg_ fs controller sets the usb suspend bit in the core interrupt register. the otg_fs controller informs the phy to discharge v bus . 2. the phy indicates the session?s end to the de vice. this is the initial condition for srp. the otg_fs controller requires 2 ms of se0 before initiating srp. for a usb 1.1 full-speed serial transceiver, the application must wait until v bus discharges to 0.2 v afte r bsvld (in otg_fs_gotgctl ) is deasserted. this a i156 8 2 vbu s _valid b_valid di s chrg_vbu s s e ss _end dp dm chrg_vbu s sus pend d a t a line p u l s ing connect v bu s p u l s ing 1 6 2 3 4 5 8 7 low usb on-the-go full-speed (otg_fs) RM0033 1058/1317 doc id 15403 rev 3 discharge time can be obtained from the transceiver vendor and varies from one transceiver to another. 3. the usb otg core informs the phy to speed up v bus discharge. 4. the application init iates srp by writing the session re quest bit in the otg control and status register. the otg_fs controller perform data-line pulsing followed by v bus pulsing. 5. the host detects srp from either the data-line or v bus pulsing, and turns on v bus . the phy indicates v bus power-on to the device. 6. the otg_fs controller performs v bus pulsing. the host starts a new session by turning on v bus , indicating srp success. the otg_fs controller interrupts the application by setting the session request success status change bit in the otg interrupt status register. the application reads the session request success bit in the otg control and status register. 7. when the usb is powered, the otg_fs controller connects, completing the srp process. a-device host negotiation protocol hnp switches the usb host role from the a-device to the b-device. the application must set the hnp-capable bit in the core usb configuration register to enable the otg_fs controller to perform hnp as an a-device. figure 370. a-device hnp 1. dppulldown = signal from core to phy to enable/ disable the pull-down on the dp line inside the phy. dmpulldown = signal from core to phy to enable/di sable the pull-down on the dm line inside the phy. 1. the otg_fs controller sends the b-device a setfeature b_hnp_enable descriptor to enable hnp support. the b-device?s ack response indicates that the b-device supports hnp. the application must set hos t set hnp enable bit in the otg control a i156 83 otg core dp dm dppulldown dmpulldown ho s t device ho s t 1 sus pend 2 3 45 re s et 6 tr a ffic 7 8 connect tr a ffic RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 1059/1317 and status register to indicate to the otg_fs controller that the b-device supports hnp. 2. when it has finished using the bus, the application suspends by writing the port suspend bit in the host port control and status register. 3. when the b-device observes a usb suspend, it disconnects, indicating the initial condition for hnp. the b-device initiates hnp only when it must swit ch to the host role; otherwise, the bus continues to be suspended. the otg_fs controller sets the host negotiation detected interrupt in the otg interrupt status register, indicating the start of hnp. the otg_fs controller deasserts the dm pull down and dm pull down in the phy to indicate a device role. the phy enables the otg_fs_dp pull-up resistor to indicate a connect for b-device. the application must read the current mode bit in the otg control and status register to determine device mode operation. 4. the b-device detects the connection, issues a usb reset, and enumerates the otg_fs controller for data traffic. 5. the b-device continues the host role, initiating traffic, and suspends the bus when done. the otg_fs controller sets the early suspend bit in the core interrupt register after 3 ms of bus idleness. following this, the otg_ fs controller sets the usb suspend bit in the core interrupt register. 6. in negotiated mode, the otg_fs controller detects the suspend, disconnects, and switches back to the host role. the otg_fs controller asserts the dm pull down and dm pull down in the phy to indicate its assumption of the host role. 7. the otg_fs controller sets the connector id status change interrupt in the otg interrupt status register. the application must read the connector id status in the otg control and status register to determine the otg_fs controller operation as an a- device. this indicates the completion of hnp to the application. the application must read the current mode bit in the otg control and status register to determine host mode operation. 8. the b-device connects, completing the hnp process. b-device host negotiation protocol hnp switches the usb host role from b-device to a-device. the application must set the hnp-capable bit in the core usb configuration register to enable the otg_fs controller to perform hnp as a b-device. usb on-the-go full-speed (otg_fs) RM0033 1060/1317 doc id 15403 rev 3 figure 371. b-device hnp 1. dppulldown = signal from core to phy to enable/ disable the pull-down on the dp line inside the phy. dmpulldown = signal from core to phy to enable/di sable the pull-down on the dm line inside the phy. 1. the a-device sends the setfeature b_hnp_enable descriptor to enable hnp support. the otg_fs controller?s ack response indicates that it supports hnp. the application must set the device hnp enable bit in the otg control and status register to indicate hnp support. the application sets the hnp request bit in the otg control and status register to indicate to the otg_fs co ntroller to initiate hnp. 2. when it has finished using the bus, the a-device suspends by writing the port suspend bit in the host port control and status register. the otg_fs controller sets the early suspend bit in the core interrupt register after 3 ms of bus idleness. following this, the otg_ fs controller sets the usb suspend bit in the core interrupt register. the otg_fs controller disconnects and the a-device detects se0 on the bus, indicating hnp. the otg_fs controller assert s the dp pull down and dm pull down in the phy to indicate its assumption of the host role. the a-device responds by activating its otg_fs_dp pull-up resistor within 3 ms of detecting se0. the otg_fs controller detects this as a connect. the otg_fs controller sets the host negotiation success status change interrupt in the otg interrupt status register, indicating the hnp status. the application must read the host negotiation success bit in the otg control and status register to determine host a i156 8 4 otg core dp dm dppulldown dmpulldown ho s t device device 1 sus pend 2 3 45 re s et 6 tr a ffic 7 8 connect tr a ffic RM0033 usb on-the-go full-speed (otg_fs) doc id 15403 rev 3 1061/1317 negotiation success. the application must read the current mode bit in the core interrupt register (otg_fs_gintsts) to determine host mode operation. 3. the application sets the reset bit (prst in otg_fs_hprt) and the otg_fs controller issues a usb reset and enumerates the a-device for data traffic. 4. the otg_fs controller continues the host role of initiating traffic, and when done, suspends the bus by writing the port suspend bit in the host port control and status register. 5. in negotiated mode, when the a-device detects a suspend, it disconnects and switches back to the host role. the otg_fs controller deasserts the dp pull down and dm pull down in the phy to indicate the assumption of the device role. 6. the application must read the current mode bit in the core interrupt (otg_fs_gintsts) register to determine the host mode operation. 7. the otg_fs controller connects, completing the hnp process. usb on-the-go high-speed (otg_hs) RM0033 1062/1317 doc id 15403 rev 3 30 usb on-the-go high-speed (otg_hs) 30.1 otg_hs introduction portions copyright (c) 2004, 2005 synopsys, inc. all rights reserved. used with permission. this section presents the architecture and the programming model of the otg_hs controller. the following acronyms are used throughout the section: references are made to the following documents: usb on-the-go supplement, revision 1.3 universal serial bus revision 2.0 specification the otg_hs is a dual-role device (drd) controller that supports both peripheral and host functions and is fully compliant with the on-the-go supplement to the usb 2.0 specification . it can also be configured as a host-only or peripheral-only controller, fully compliant with the usb 2.0 specification. in host mode, the otg_hs supports high-speed (hs, 480 mbits/s), full-speed (fs, 12 mbits/s) and low-speed (ls, 1.5 mbits/s) transfers whereas in peripheral mode, it only supports high-speed (hs, 480mbits/s) and full-speed (fs, 12 mbits/s) transfers. the otg_hs supports both hnp and srp. the only external device required is a charge pump for vbus in otg mode. fs full-speed hs high-speed ls low-speed usb universal serial bus otg on-the-go phy physical layer mac media access controller pfc packet fifo controller utmi usb transceiver macrocell interface ulpi utmi+ low pin interface RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1063/1317 30.2 otg_hs main features the main features can be divided into three categories: general, host-mode and peripheral- mode features. 30.2.1 general features the otg_hs interface main features are the following: it is usb-if certified in compliance with the universal serial bus revision 2.0 specification it supports 3 phy interfaces ? an on-chip full-speed phy ?an i 2 c interface for external full-speed i 2 c phy ? an ulpi interface for external high-speed phy. it supports the host negotiation protocol (hnp) and the session request protocol (srp) it allows the host to turn v bus off to save power in otg applications, with no need for external components it allows to monitor v bus levels using internal comparators it supports dynamic host-peripheral role switching it is software-configurable to operate as: ? an srp-capable usb hs/fs peripheral (b-device) ? an srp-capable usb hs/fs/low-speed host (a-device) ? an usb otg fs dual-role device it supports hs/fs sofs as well as low-speed (ls) keep-alive tokens with: ? sof pulse pad output capability ? sof pulse internal connection to timer 2 (tim2) ? configurable framing period ? configurable end-of-frame interrupt it embeds an internal dma with shareholding support and software selectable ahb burst type in dma mode it has power saving features such as system clock stop during us b suspend, switching off of the digital core internal clock domains, phy and dfifo power management it features a dedicated 4-kbyte data ram with advanced fifo management: ? the memory partition can be configured into different fifos to allow flexible and efficient use of ram ? each fifo can contain multiple packets ? memory allocation is performed dynamically ? the fifo size can be configured to values that are not powers of 2 to allow the use of contiguous memory locations it ensures a maximum usb bandwidth of up to one frame without application intervention usb on-the-go high-speed (otg_hs) RM0033 1064/1317 doc id 15403 rev 3 30.2.2 host-mode features the otg_hs interface features in host mode are the following: it requires an external charge pump to generate v bus it has up to 12 host channels (pipes), each channel being dynamically reconfigurable to support any kind of usb transfer it features a built-in hardware scheduler holding: ? up to 8 interrupt plus isochronous transfer requests in the periodic hardware queue ? up to 8 control plus bulk transfer requests in the nonperiodic hardware queue it manages a shared rx fifo, a periodic tx fifo, and a nonperiodic tx fifo for efficient usage of the usb data ram it features dynamic trimmi ng capability of sof frami ng period in host mode. 30.2.3 peripheral-mode features the otg_hs interface main features in peripheral mode are the following: it has 1 bidirectional control endpoint 0 it has 5 in endpoints (ep) configurable to support bulk, interrupt or isochronous transfers it has 5 out endpoints configurable to supp ort bulk, interrupt or isochronous transfers it manages a shared rx fifo and a tx-out fifo for efficient usage of the usb data ram it manages up to 6 dedicated tx-in fifos (one for each in-configured ep) to reduce the application load it features soft disconnect capability RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1065/1317 30.3 otg_hs functional description figure 372 shows the otg_hs interface block diagram. figure 372. usb otg interface block diagram 1. the usb dma cannot directly address the internal flash memory. 30.3.1 high-speed otg phy the usb otg hs core embeds an ulpi interface to connect an external hs phy. 30.3.2 external full-speed otg phy using the i2 c interface the usb otg hs core embeds an i 2 c interface allowing to connect an external fs phy. 30.3.3 embedded full-speed otg phy the full-speed otg phy includes the following components: fs/ls transceiver module used by both host and device. it directly drives transmission and reception on the single-ended usb lines. integrated id pull-up resistor used to sample the id line for a/b device identification. dp/dm integrated pull-up and pull-down resistors controlled by the otg_hs core depending on the current role of the device. as a peripheral, it enables the dp pull-up resistor to signal full-speed peripheral connections as soon as v bus is sensed to be at a valid level (b-session valid). in host mode, pull-down resistors are enabled on both ! ( " m a s t e r i n t e r f a c e ! ( " s l a v e i n t e r f a c e # 0 5 - e m o r y 0 e r i p h e r a l 0 e r i p h e r a l 5 , 0 ) i n t e r f a c e 5 , 0 ) 0 ( 9 5 3 " $ a t a & ) & / s i n g l e p o r t 2 ! - 3 0 2 ! - $ a t a & ) & / 2 ! - i n t e r f a c e ) n t e r r u p t ! ( " a p p l i c a t i o n b u s 5 3 " / 4 ' ( 3 c o r e a i b usb on-the-go high-speed (otg_hs) RM0033 1066/1317 doc id 15403 rev 3 dp/dm. pull-up and pull-down resistors are dynamically switched when the peripheral role is changed via the host negotiation protocol (hnp). pull-up/pull-down resistor ecn circuit the dp pull-up consists of 2 resistors controlled separately from the otg_hs as per the resistor engineering change notice applied to usb rev2.0. the dynamic trimming of the dp pull-up strength allows to achieve a better noise rejection and tx/rx signal quality. v bus sensing comparators with hysteresis us ed to detect vbus_va lid, a-b session valid and session-end voltage thresholds. they are used to drive the session request protocol (srp), detect valid startup and end-of-session conditions, and constantly monitor the v bus supply during usb operations. v bus pulsing method circuit used to charge/discharge v bus through resistors during the srp (weak drive). caution: to guarantee a correct operation for the usb otg hs peripheral, the ahb frequency should be higher than 30 mhz. 30.4 otg dual-role device 30.4.1 id line detection the host or peripheral (the default) role depends on the level of the id input line. it is determined when the usb cable is plugged in and depends on which side of the usb cable is connected to the micro-ab receptacle: if the b-side of the usb cable is connected with a floating id wire, the integrated pull-up resistor detects a high id level and the default peripheral role is confirmed. in this configuration the otg_hs conforms to the fsm standard described in section 6.8.2. on-the-go b-device of the usb on-the-go supplement, revision 1.3. if the a-side of the usb cable is connect ed with a grounded id, the otg_hs issues an id line status change interrupt (cidschg bit in the otg_hs_gintsts register) for host software initialization, and automatically switches to host role. in this configuration the otg_hs conforms to the fsm standard described by section 6.8.1: on-the-go a- device of the usb on-the-go supplement, revision 1.3. 30.4.2 hnp dual role device the hnp capable bit in the global usb configuration register (hnpcap bit in the otg_hs_ gusbcfg register) configures the otg_hs core to dynamically change from a-host to a- device role and vice-versa, or from b-device to b-host role and vice-versa, according to the host negotiation protocol (hnp). the current device status is defined by the combination of the connector id status bit in the global otg control and status register (cidsts bit in otg_hs_gotgctl) and the current mode of operation bit in the global interrupt and status register (cmod bit in otg_hs_gintsts). the hnp programming model is described in detail in section 30.13: otg_hs programming model . 30.4.3 srp dual-role device the srp capable bit in the global usb configuration register (srpcap bit in otg_hs_gusbcfg) configures the otg_hs core to switch v bus off for the a-device in RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1067/1317 order to save power. the a-device is always in charge of driving v bus regardless of the otg_hs role (host or peripheral). the srp a/b-device program model is described in detail in section 30.13: otg_hs programming model . 30.5 usb functional description in peripheral mode the otg_hs operates as an usb peripheral in the following circumstances: otg b-device otg b-device default state if the b-side of usb cable is plugged in otg a-device otg a-device state after the hnp switches the otg_hs to peripheral role b-device if the id line is present, functional and connected to the b-side of the usb cable, and the hnp-capable bit in the global usb configuration register (hnpcap bit in otg_hs_gusbcfg) is cleared (see on-the-go specification revision 1.3 section 6.8.3). peripheral only (see figure 350: usb peripheral-only connection ) the force peripheral mode bit in the global usb configuration register (fdmod in otg_hs_gusbcfg) is set to 1, forcing the otg_hs core to operate in usb peripheral-only mode (see on-the-go specification revision 1.3 section 6.8.3). in this case, the id line is ignored even if it is available on the usb connector. note: to build a bus-powered device architecture in the b-device or peripheral-only configuration, an external regulator must be added to generate the v dd supply voltage from v bus . 30.5.1 srp-capable peripheral the srp capable bit in the global usb configuration register (srpcap bit in otg_hs_gusbcfg) configures the otg_hs to support the session request protocol (srp). as a result, it allows the remote a-device to save power by switching v bus off when the usb session is suspended. the srp peripheral mode program model is described in detail in section : b-device session request protocol . 30.5.2 peripheral states powered state the v bus input detects the b-session valid voltage used to put the usb peripheral in the powered state (see usb2.0 specification se ction 9.1). the otg_hs then automatically connects the dp pull-up resistor to signal full-speed device connection to the host, and generates the session request interrupt (srqint bit in otg_hs_gintsts) to notify the powered state. the v bus input also ensures that valid v bus levels are supplied by the host during usb operations. if v bus drops below the b-session valid voltage (for example because power disturbances occurred or the host port has been switched off), the otg_hs automatically disconnects and the session end detected (sedet bit in otg_hs_gotgint) interrupt is generated to notify that the otg_hs has exited the powered state. usb on-the-go high-speed (otg_hs) RM0033 1068/1317 doc id 15403 rev 3 in powered state, the otg_hs expects a reset from the host. no other usb operations are possible. when a reset is received, t he reset detected interrupt (usbrst in otg_hs_gintsts) is generated. when the reset is complete, the enumeration done interrupt (enumdne bit in otg_hs_gintsts) is generated and the otg_hs enters the default state. soft disconnect the powered state can be exited by software by using the soft disconnect feature. the dp pull-up resistor is removed by setting the soft disconnect bit in the device control register (sdis bit in otg_hs_dctl), thus generating a device disconnect detection interrupt on the host side even though the usb cable was not really unplugged from the host port. default state in default state the otg_hs expects to receive a set_ad dress command from the host. no other usb operations ar e possible. when a valid set_address command is decoded on the usb, the application writes the corresponding number into the device address field in the device configuration register (dad bit in otg_hs_dcfg). the otg_hs then enters the address state and is ready to answer host transactions at the configured usb address. suspended state the otg_hs peripheral constantly monitors the usb activity. when the usb remains idle for 3 ms, the early suspend interrupt (esusp bit in otg_hs_gintsts) is issued. it is confirmed 3 ms later, if appr opriate, by generating a su spend interrupt (usbsusp bit in otg_hs_gintsts). the device suspend bit is th en automatically set in the device status register (suspsts bit in otg_hs_dsts) and the otg_hs enters the suspended state. the device can also exit from the suspended state by itself. in this case the application sets the remote wakeup signaling bit in the device control register (wkupint bit in otg_hs_dctl) and clears it after 1 to 15 ms. when a resume signaling is detected from the host, the resume interrupt (rwusig bit in otg_hs_gintsts) is generated and the devi ce suspend bit is automatically cleared. 30.5.3 peripheral endpoints the otg_hs core instantiates the following usb endpoints: control endpoint 0 this endpoint is bidirectional and handles control messages only. it has a separate set of registers to handle in and out transactions, as well as dedicated control (otg_hs_diepctl0/otg_hs_doepctl0), transfer configuration (otg_hs_dieptsiz0/otg_hs_dieptsi z0), and status-interrupt RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1069/1317 (otg_hs_diepintx/)otg_hs_do epint0) registers. the bits available inside the control and transfer size registers slightly differ from other endpoints. 5 in endpoints ? they can be configured to support the isochronous, bulk or interrupt transfer type. ? they feature dedicated control (otg_hs_diepctlx), transfer configuration (otg_hs_dieptsizx), and status-interrupt (otg_hs_diepintx) registers. ? the device in endpoints common interrupt mask register (otg_hs_diepmsk) allows to enable/disable a single endpoint interrupt source on all of the in endpoints (ep0 included). ? they support incomplete isochronous in transfer interrupt (iisoixfr bit in otg_hs_gintsts). this interrupt is asserted when there is at least one isochronous in endpoint for which the transfer is not completed in the current frame. this interrupt is asserted along with the end of periodic frame interrupt (otg_hs_gintsts/eopf). 5 out endpoints ? they can be configured to support the isochronous, bulk or interrupt transfer type. ? they feature dedicated control (otg_hs_doepctlx), transfer configuration (otg_hs_doeptsizx) and status-interrupt (otg_hs_doepintx) registers. ? the device out endpoints common interrupt mask register (otg_hs_doepmsk) allows to enable/disable a single endpoint interrupt source on all out endpoints (ep0 included). ? they support incomplete isochronous out transfer interrupt (incompisoout bit in otg_hs_gintsts). this interrupt is asserted when there is at least one isochronous out endpoint on which the transfer is not completed in the current frame. this interrupt is asserted along with the end of periodic frame interrupt (otg_hs_gintsts/eopf). endpoint controls the following endpoint controls are available through the device endpoint-x in/out control register (diepctlx/doepctlx): endpoint enable/disable endpoint activation in current configuration program the usb transfer type (isochronous, bulk, interrupt) program the supported packet size program the tx-fifo number associated with the in endpoint program the expected or transmitted data0/data1 pid (bulk/interrupt only) program the even/odd frame during which the transaction is received or transmitted (isochronous only) optionally program the nak bit to always send a negative acknowledge to the host regardless of the fifo status optionally program the stall bit to always stall host tokens to that endpoint optionally program the snoop mode for out endpoint where the received data crc is not checked usb on-the-go high-speed (otg_hs) RM0033 1070/1317 doc id 15403 rev 3 endpoint transfer the device endpoint-x transfer size registers (dieptsizx/doeptsizx) allow the application to program the transfer size parameters and read the transfer status. the programming operation must be performed before setting the endpoint enable bit in the endpoint control register. once the endpoint is enabled, these fields are read-only as the otg fs core updates them with the current transfer status. the following transfer parameters can be programmed: transfer size in bytes number of packets constituting the overall transfer size. endpoint status/interrupt the device endpoint-x interrup t registers (diepintx/dopepintx) indicate the status of an endpoint with respect to usb- and ahb-related events. the application must read these registers when the out endpoint interrupt bit or the in endpoint interrupt bit in the core interrupt register (oepint bit in otg_hs_gintsts or iepint bit in otg_hs_gintsts, respectively) is set. before the application can read these registers, it must first read the device all endpoints interrupt register (otg_hs_daint) to get the exact endpoint number for the device endpoint-x interrupt register. the application must clear the appropriate bit in this register to clear the corresponding bits in the daint and gintsts registers. the peripheral core provides the following status checks and interrupt generation: transfer completed interrupt, indicating that data transfer has completed on both the application (ahb) and usb sides setup stage done (control-out only) associated transmit fifo is half or completely empty (in endpoints) nak acknowledge transmitted to the host (isochronous-in only) in token received when tx-fifo was empty (bulk-in/interrupt-in only) out token received when endpoint was not yet enabled babble error condition detected endpoint disable by application is effective endpoint nak by application is effective (isochronous-in only) more than 3 back-to-back setup packets received (control-out only) timeout condition detected (control-in only) isochronous out packet dropped without generating an interrupt RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1071/1317 30.6 usb functional description on host mode this section gives the functional description of the otg_hs in the usb host mode. the otg_hs works as a usb host in the following circumstances: otg a-host otg a-device default state when the a-side of the usb cable is plugged in otg b-host otg b-device after hnp switching to the host role a-device if the id line is present, functional and connected to the a-side of the usb cable, and the hnp-capable bit is cleared in the global usb configuration register (hnpcap bit in otg_hs_gusbcfg). integrated pull-down resistors are automatically set on the dp/dm lines. host only ( figure 351: usb host-only connection ). the force host mode bit in the global u sb configuration register (fhmod bit in otg_hs_gusbcfg) forces the otg_hs core to operate in usb host-only mode. in this case, the id line is ignored even if it is available on the usb connector. integrated pull-down resistors are automatically set on the otg_hs_fs_dp/otg_hs_fs_dm lines. note: 1 on-chip 5 v v bus generation is not supported. as a result, a charge pump or a basic power switch (if a 5 v supply is available on the application board) must be added externally to drive the 5 v v bus line. the external charge pump can be driven by any gpio output. this is required for the otg a-host, a-de vice and host-only configurations. 2the v bus input ensures that valid v bus levels are supplied by the charge pump during usb operations while the charge pump overcurrent output can be input to any gpio pin configured to generate port interrupts. the overcurrent isr must promptly disable the v bus generation. 30.6.1 srp-capable host srp support is available through the srp capable bit in the global usb configuration register (srpcap bit in otg_hs_gusbcfg). when the srp feature is enabled, the host can save power by switching off the v bus power while the usb session is suspended. the srp host mode program model is described in detail in section : a-device session request protocol . 30.6.2 usb host states host port power on-chip 5 v v bus generation is not supported. as a result, a charge pump or a basic power switch (if a 5 v supply voltage is available on the application board) must be added externally to drive the 5 v v bus line. the external charge pump can be driven by any gpio output. when the application powers on v bus through the selected gpio, it must also set the port power bit in the host port control and status register (ppwr bit in otg_hs_hprt). usb on-the-go high-speed (otg_hs) RM0033 1072/1317 doc id 15403 rev 3 v bus valid the v bus input ensures that valid v bus levels are supplied by the charge pump during usb operations. any unforeseen v bus voltage drop below the v bus valid threshold (4.25 v) generates an otg interrupt triggered by the session end detected bit (sedet bit in otg_hs_gotgint). the application must then switch the v bus power off and clear the port power bit. the charge pump overcurrent flag can also be used to prevent electrical damage. connect the overcurrent flag output from the charge pump to any gpio input, and configure it to generate a port interrupt on the active level. the overcurrent isr must promptly disable the v bus generation and clear the port power bit. detection of peripheral connection by the host even if usb peripherals or b-devices can be attached at any time, the otg_hs does not detect a bus connection until the end of the v bus sensing (v bus over 4.75 v). when v bus is at a valid level and a remote b-device is attached, the otg_hs core issues a host port interrupt triggered by the device connected bit in the host port control and status register (pcdet bit in otg_hs_hprt). detection of peripheral disconnection by the host the peripheral disconnection event triggers th e disconnect detected interrupt (discint bit in otg_hs_gintsts). host enumeration after detecting a peripheral connection, the host must start the enumeration process by issuing an usb reset and configuration commands to the new peripheral. before sending an usb reset, the application waits for the otg interrupt triggered by the debounce done bit (dbcdne bit in otg_hs_g otgint), which indica tes that the bus is stable again after the electrical debounce caused by the attachment of a pull-up resistor on otg_hs_fs_dp (full speed) or otg_hs_fs_dm (low speed). the application issues an usb reset (single-ended zero) via the usb by keeping the port reset bit set in the host port control and status register (prst bit in otg_hs_hprt) for a minimum of 10 ms and a maximum of 20 ms. the application monitors the time and then clears the port reset bit. once the usb reset sequence has completed, the host port interrupt is triggered by the port enable/disable change bit (penchng bit in ot g_hs_hprt) to inform the application that the speed of the enumerated peripheral can be read from the port speed field in the host port control and st atus register (pspd bit in otg_hs_hpr t), and that the host is starting to drive sofs (full speed) or keep-alive tokens (low speed). the host is then ready to complete the peripheral enumeration by sending peripheral configuration commands. host suspend the application can decide to suspend the usb activity by setting the port suspend bit in the host port control and status register (psusp bit in otg_hs_hprt). the otg_hs core stops sending sofs and enters the suspended state. the suspended state can be exited on the remote device initiative (remote wakeup). in this case the remote wakeup interrupt (wkupint bit in otg_hs_gintsts) is generated upon detection of a remote wakeup event, the port resume bit in the host port control and status RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1073/1317 register (pres bit in otg_hs_hprt) is set, and a resume signaling is automatically issued on the usb. the application must monitor the resume window duration, and then clear the port resume bit to exit the suspended state and restart the sof. if the suspended state is exited on the host initiative, the application must set the port resume bit to start resume signaling on the host port, monitor the resume window duration and then clear the port resume bit. 30.6.3 host channels the otg_hs core instantiates 12 host channels. each host channel supports an usb host transfer (usb pipe). the host is not able to support more than 8 transfer requests simultaneously. if more than 8 transfer requests are pending from the application, the host controller driver (hcd) must re-allocate channels when they become available, that is, after receiving the transfer completed and channel halted interrupts. each host channel can be configured to support in/out and any type of periodic/nonperiodic transaction. each hos t channel has dedicated control (hccharx), transfer configuration (hctsizx) and status/interrupt (hcintx) registers with associated mask (hcintmskx) registers. host channel controls the following host channel controls are available through the host channel-x characteristics register (hccharx): channel enable/disable program the hs/fs/ls speed of target usb peripheral program the address of target usb peripheral program the endpoint number of target usb peripheral program the transfer in/out direction program the usb transfer type (control, bulk, interrupt, isochronous) program the maximum packet size (mps) program the periodic transfer to be executed during odd/even frames host channel transfer the host channel transfer size registers (hctsizx) allow the application to program the transfer size parameters, and read the transfer status. the programming operation must be performed before setting the channel enable bit in the host channel characteristics register. once the endpoint is enabled, the packet count field is read-only as the otg hs core updates it according to the current transfer status. the following transfer parameters can be programmed: transfer size in bytes number of packets constituting the overall transfer size initial data pid host channel status/interrupt the host channel-x interrupt register (hcintx) indicates the status of an endpoint with respect to usb- and ahb-related events. the application must read these register when the host channels interrupt bit in the core interrupt register (hcint bit in otg_hs_gintsts) is usb on-the-go high-speed (otg_hs) RM0033 1074/1317 doc id 15403 rev 3 set. before the application can read these registers, it must first read the host all channels interrupt (hcaint) register to get the exact channel number for the host channel-x interrupt register. the application must clear the appropriate bit in this register to clear the corresponding bits in the haint and gintsts registers. the mask bits for each interrupt source of each channel are also available in the otg_hs_hcintmsk-x register. the host core provides the following status checks and interrupt generation: transfer completed interrupt, indicating that the data transfer is complete on both the application (ahb) and usb sides channel stopped due to transfer completed, usb transaction error or disable command from the application associated transmit fifo half or completely empty (in endpoints) ack response received nak response received stall response received usb transaction error due to crc failure, timeout, bit stuff error, false eop babble error frame overrun data toggle error 30.6.4 host scheduler the host core features a built-in hardware scheduler which is able to autonomously re-order and manage the usb the transaction requests posted by the application. at the beginning of each frame the host executes the periodic (isochronous and interrupt) transactions first, followed by the nonperiodic (control and bulk) transactions to achieve the higher level of priority granted to the isochronous and interr upt transfer types by the usb specification. the host processes the usb transactions through request queues (one for periodic and one for nonperiodic). each request queue can hold up to 8 entries. each entry represents a pending transaction request from the application, and holds the in or out channel number along with other information to perform a transaction on the usb. the order in which the requests are written to the queue determines the sequence of the transactions on the usb interface. at the beginning of each frame, the host processes the periodic request queue first, followed by the nonperiodic request queue. the host issues an incomplete periodic transfer interrupt (ipxfr bit in otg_hs_gintsts) if an isochronous or interrupt transaction scheduled for the current frame is still pending at the end of the cu rrent frame. the otg hs core is fully responsible for the management of the periodic and nonperiodic request queues.the periodic transmit fifo and queue status register (hptxsts) and nonperiodic transmit fifo and queue status register (hnptxsts) are read-only registers which can be used by the application to read the status of each request queue. they contain: the number of free entries currently available in the periodic (nonperiodic) request queue (8 max) free space currently available in the periodic (nonperiodic) tx-fifo (out-transactions) in/out token, host channel number and other status information. as request queues can hold a maximum of 8 entries each, the application can push to schedule host transactions in advance with respec t to the moment they physically reach the RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1075/1317 usb for a maximum of 8 pending periodic transactions plus 8 pending nonperiodic transactions. to post a transaction request to the host scheduler (queue) the application must check that there is at least 1 entry available in the periodic (nonperiodic) request queue by reading the ptxqsav bits in the otg_hs_hnptxsts register or nptqxsav bits in the otg_hs_hnptxsts register. 30.7 sof trigger the otg fs core allows to monitor, track and configure sof framing in the host and peripheral. it also features an sof pulse output connectivity. these capabilities are pa rticularly useful to implement adaptive audio clock generation techniques, where the audio peripheral needs to synchronize to the isochronous stream provided by the pc, or the host needs trimming its framing rate according to the requirements of the audio peripheral. 30.7.1 host sofs in host mode the number of phy clocks occurring between the generation of two consecutive sof (fs) or keep-alive (ls) tokens is programmable in the host frame interval register (otg_hs_hfir), thus providing application control over the sof framing period. an interrupt is generated at any start of frame (sof bit in otg_hs_gintsts). the current frame number and the time remaining until the next sof are tracked in the host frame number register (otg_hs_hfnum). an sof pulse signal is generated at any sof starting token and with a width of 12 system clock cycles. it can be made available externally on the sof pin using the sofouten bit in the global control and configuration register. the sof pulse is also internally connected to the input trigger of timer 2 (tim2), so that the input capture feature, the output compare feature and the timer can be triggered by the sof pulse. the tim2 connection is enabled through itr1_rmp bits of tim2_or register. sof trigger output to tim2 itr1 connection 30.7.2 peripheral sofs in peripheral mode, the start of frame interrupt is generated each time an sof token is received on the usb (sof bit in otg_hs_gintsts). the corresponding frame number s of p u l s e itr1 tim2 otg_h s _core s of o u tp u t p u l s e u s b micro-ab connector vbu s dp dm id a i16092 usb on-the-go high-speed (otg_hs) RM0033 1076/1317 doc id 15403 rev 3 can be read from the device status register (fnsof bit in otg_hs_dsts). an sof pulse signal with a width of 12 system clock cycles is also generated and ca n be made available externally on the sof pin by using the sof output enable bit in the global control and configuration register (sofouten bit in otg_hs_gccfg). the sof pulse signal is also internally connected to the tim2 input trigger, so that the input capture feature, the output compare feature and the timer can be triggered by the sof pulse (see figure ). the tim2 connection is enabled through itr1_rmp bits of tim2_or register. the end of periodic frame interrupt (gintsts/eop f) is used to notify the application when 80%, 85%, 90% or 95% of the time frame interval elapsed depending on the periodic frame interval field in the device configuratio n register (pfivl bit in otg_hs_dcfg). this feature can be used to determine if all of the isochronous traffic for that frame is complete. 30.8 usb_hs power modes the power consumption of the otg phy is controlled by three bits in the general core configuration register: phy power down (gccfg/pwrdwn) this bit switches on/off the phy full-speed transceiver module. it must be preliminarily set to allow any usb operation. a-vbus sensing enable (gccfg/vbusasen) this bit switches on/off the v bus comparators associated with a-device operations. it must be set when in a-device (usb host) mode and during hnp. b-vbus sensing enable (gccfg/vbusasen) this bit switches on/off the v bus comparators associated with b-device operations. it must be set when in b-device (usb peripheral) mode and during hnp. power reduction techniques are available in the usb suspended state, when the usb session is not yet valid or the device is disconnected. stop phy clock (stppclk bit in otg_hs_pcgcctl) ? when setting the stop phy clock bit in the clock gating control register, most of the clock domain internal to the otg high-speed core is switched off by clock gating. the dynamic power consumption due to the usb clock switching activity is cut even if the clock input is kept running by the application ? most of the transceiver is also disabled, and only the part in charge of detecting the asynchronous resume or remote wakeup event is kept alive. gate hclk (gatehclk bit in otg_hs_pcgcctl) when setting the gate hclk bit in the clock gating control register, most of the system clock domain internal to the otg_hs core is switched off by clock gating. only the register read and write interface is kept alive. the dynamic power consumption due to the usb clock switching activity is cut even if the system clock is kept running by the application for other purposes. usb system stop ? when the otg_hs is in usb suspended state, the application can decide to drastically reduce the overall power consumption by shutting down all the clock sources in the system. usb system stop is activated by first setting the stop phy RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1077/1317 clock bit and then configuring the system deep sleep mode in the powercontrol system module (pwr). ? the otg_hs core automatically reactivates both system and usb clocks by asynchronous detection of remote wakeup (as an host) or resume (as a device) signaling on the usb. 30.9 dynamic update of the otg_hs_hfir register the usb core embeds a dynamic trimming cap ability of micro-sof fr aming period in host mode allowing to synchronize an external device with the micro-sof frames. when the otg_hs_hfir register is changed within a current micro-sof frame, the sof period correction is applied in the next frame as described in figure 373 . figure 373. updating otg_hs_hfir dynamically 30.10 fifo ram allocation 30.10.1 peripheral mode receive fifo ram for receive fifo ram, the application sh ould allocate ram for setup packets: 10 locations must be reserved in the receive fifo to receive setup packets on control endpoints. these locations are reserved for setup packets and are not used by the core to write any other data. one location must be allocated for global out nak. status information are also written to the fifo along with each received packet. therefore, a minimum space of (largest packet size / 4) + 1 must be allocated to receive packets. if a high-bandwidth endpoint or multiple isochronous endpoints are enabled, at least two spaces of (largest packet size / 4) + 1 must be allotted to receive back-to-back packets. typically, two (largest packet size / 4) + 1 spaces are recommended so that when the previous packet is being transferred to ahb, the usb can receive the subsequent packet. along with each endpoints last packet, transfer complete status information are also pushed to the fifo. typically, one location for each out endpoint is recommended. x x x x x , a t e n c y 3 / & r e l o a d / 4 ' ? ( 3 ? ( & ) 2 w r i t e v a l u e & r a m e t i m e r / l d / 4 ' ? ( 3 ? ( ) & 2 v a l u e p e r i o d s / 4 ' ? ( 3 ? ( ) & 2 v a l u e p e r i o d s ( ) & 2 w r i t e l a t e n c y . e w / 4 ' ? ( 3 ? ( ) & 2 v a l u e p e r i o d s / 4 ' ? ( 3 ? ( & ) 2 a i b usb on-the-go high-speed (otg_hs) RM0033 1078/1317 doc id 15403 rev 3 transmit fifo ram for transmit fifo ram, the minimum ram space required for each in endpoint transmit fifo is the maximum packet size for this in endpoint. note: more space allocated in the transmit in endpoint fifo results in a better performance on the usb. 30.10.2 host mode receive fifo ram for receive fifo ram allocation, status information are written to the fifo along with each received packet. therefore, a minimum space of (largest packet size / 4) + 1 must be allocated to receive packets. if a high-bandwidth channel or multiple isochronous channels are enabled, at least two spaces of (largest packet size / 4) + 1 must be allocated to receive back-to-back packets. typically, two (largest packet size / 4) + 1 spaces are recommended so that when the previous packet is being transferred to ahb, the usb can receive the subsequent packet. along with each host channels last packet, transfer complete status information are also pushed to the fifo. as a consequence, one location must be allocated to store this data. transmit fifo ram for transmit fifo ram allocation, the minimum amount of ram required for the host nonperiodic transmit fifo is the largest maximum packet size for all supported nonperiodic out channels. typically, a space corresponding to two largest packet size is recommended, so that when the current packet is being transferred to the usb, the ahb can transmit the subsequent packet. the minimum amount of ram required for host periodic transmit fifo is the largest maximum packet size for all supported periodic out channels. if there is at least one high bandwidth isochronous out endpoint, then the space must be at least two times the maximum packet size for that channel. note: 1 more space allocated in the transmit nonperiodic fifo results in better performance on the usb. 2 when operating in dma mode, the dma address register for each host channel (hcdman) is stored in the spram (fifo). one location for each channel must be reserved for this. 30.11 otg_hs interrupts when the otg_hs controller is operating in one mode, either peripheral or host, the application must not access re gisters from the other mode. if an illegal access occurs, a mode mismatch interrupt is generated and reflected in the core interrupt register (mmis bit in the otg_hs_gintsts register). when the core switches from one mode to the other, the registers in the new mode of operation must be reprogrammed as they would be after a power-on reset. figure 374 shows the interrupt hierarchy. RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1079/1317 figure 374. interrupt hierarchy 1. the core interrupt register bits are shown in otg_hs core interrupt register (otg_hs_gintsts) on page 1096 . 3 1 3 0 29 2 8 27 26 25 24 2 3 20 19 1 8 17:10 9 8 7: 3 210 and or interr u pt glo ba l interr u pt m as k (bit 0) ahb config u r a tion regi s ter core interr u pt m as k regi s ter otg interr u pt regi s ter core interr u pt regi s ter (1) device in/out endpoint interr u pt regi s ter s 0 to 5 device a ll endpoint s interr u pt regi s ter 21:16 out endpoint s 5:0 in endpoint s interr u pt s o u rce s ho s t port control a nd s t a t us regi s ter ho s t a ll ch a nnel s interr u pt regi s ter ho s t ch a nnel s interr u pt m as k regi s ter s 0 to 11 ho s t a ll ch a nnel s interr u pt m as k regi s ter ho s t ch a nnel s interr u pt regi s ter s 0 to 11 22 21 device a ll endpoint s interr u pt m as k regi s ter device in/out endpoint s common interr u pt m as k regi s ter a i1609 3b or and device e a ch in/out endpoint interr u pt m as k regi s ter device e a ch endpoint interr u pt regi s ter 3 1:16 ep1out 15:0 ep1in device e a ch endpoint interr u pt m as k regi s ter endp_interr u pt[ 3 1:0] endp_m u lti_proc_intrpt usb on-the-go high-speed (otg_hs) RM0033 1080/1317 doc id 15403 rev 3 30.12 otg_hs control and status registers by reading from and writing to the control and status registers (csrs) through the ahb slave interface, the application controls the otg_hs controller. these registers are 32 bits wide, and the addresses are 32-bit block aligned. csrs are classified as follows: core global registers host-mode registers host global registers host port csrs host channel-specific registers device-mode registers device global registers device endpoint-specific registers power and clock-gating registers data fifo (dfifo) access registers only the core global, power and clock-gating, data fifo access, and host port control and status registers can be accessed in both host and peripheral modes. when the otg_hs controller is operating in one mode, either peripheral or host, the application must not access registers from the other mode. if an illegal a ccess occurs, a mode mismatch interrupt is generated and reflected in the core interrupt register (mmis bit in the otg_hs_gintsts register). when the core switches from one mode to the other, the registers in the new mode of operation must be reprogrammed as they would be after a power-on reset. 30.12.1 csr memory map the host and peripheral mode registers occupy different addresses. all registers are implemented in the ahb clock domain. RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1081/1317 figure 375. csr memory map 1. x = 5 in peripheral mode and x = 11 in host mode. global csr map these registers are available in both host and peripheral modes. 0000h core glo ba l c s r s (1 k b yte) 0400h ho s t mode c s r s (1 k b yte) 0 8 00h device mode c s r s (1.5 k b yte) 0e00h power a nd clock g a ting c s r s (0.5 k b yte) 1000h device ep 0/ho s t ch a nnel 0 fifo (4 k b yte) 2000h device ep1/ho s t ch a nnel 1 fifo (4 k b yte) 3 000h device ep (x ? 1) (1) /ho s t ch a nnel (x ? 1) (1) fifo (4 k b yte) device ep x (1) /ho s t ch a nnel x (1) fifo (4 k b yte) re s erved dfifo p us h/pop to thi s region 2 0000h 3 ffffh direct a cce ss to d a t a fifo ram for de bu gging (12 8 k b yte) dfifo de bu g re a d/ write to thi s region a i15615 b table 155. core global control and status registers (csrs) acronym address offset register name otg_hs_gotgctl 0x000 otg_hs control and status register (otg_hs_gotgctl) on page 1085 otg_hs_gotgint 0x004 otg_hs interrupt register (otg_hs_gotgint) on page 1087 otg_hs_gahbcfg 0x008 otg_hs ahb configuration register (otg_hs_gahbcfg) on page 1089 otg_hs_gusbcfg 0x00c otg_hs usb configuration register (otg_hs_gusbcfg) on page 1090 otg_hs_grstctl 0x010 otg_hs reset register (otg_hs_grstctl) on page 1093 otg_hs_gintsts 0x014 otg_hs core interrupt register (otg_hs_gintsts) on page 1096 otg_hs_gintmsk 0x018 otg_hs interrupt mask register (otg_hs_gintmsk) on page 1100 usb on-the-go high-speed (otg_hs) RM0033 1082/1317 doc id 15403 rev 3 host-mode csr map these registers must be programmed every time the core changes to host mode. otg_hs_grxstsr 0x01c otg_hs receive status debug read/ otg status read and pop registers (otg_hs_grxstsr/otg_hs_ grxstsp) on page 1103 otg_hs_grxstsp 0x020 otg_hs_grxfsiz 0x024 otg_hs receive fifo size register (otg_hs_grxfsiz) on page 1104 otg_hs_gnptxfsiz/ otg_hs_tx0fsiz 0x028 otg_hs nonperiodic transmit fifo size/endpoint 0 transmit fifo size register (otg_hs_gnptxfsiz/ otg_hs_tx0fsiz) on page 1105 otg_hs_gnptxsts 0x02c otg_hs nonperiodic transmit fifo/queue status register (otg_hs_gnptxsts) on page 1105 otg_hs_gccfg 0x038 otg_hs general core configuration register (otg_hs_gccfg) on page 1108 otg_hs_cid 0x03c otg_hs core id register (otg_hs_cid) on page 1109 otg_hs_hptxfsiz 0x100 otg_hs host periodic transmit fifo size register (otg_hs_hptxfsiz) on page 1109 otg_hs_dieptxfx 0x104 0x124 ... 0x13c otg_hs device in endpoint transmit fifo size register (otg_hs_dieptxfx) (x = 1..7, where x is the fifo_number) on page 1109 table 155. core global control and status registers (csrs) (continued) acronym address offset register name table 156. host-mode control and status registers (csrs) acronym offset address register name otg_hs_hcfg 0x400 otg_hs host configuration register (otg_hs_hcfg) on page 1110 otg_hs_hfir 0x404 otg_hs host frame interval register (otg_hs_hfir) on page 1111 otg_hs_hfnum 0x408 otg_hs host frame number/frame time remaining register (otg_hs_hfnum) on page 1111 otg_hs_hptxsts 0x410 otg_hs_host periodic transmit fifo/queue status register (otg_hs_hptxsts) on page 1112 otg_hs_haint 0x414 otg_hs host all channels interrupt register (otg_hs_haint) on page 1113 otg_hs_haintmsk 0x418 otg_hs host all channels interrupt mask register (otg_hs_haintmsk) on page 1113 otg_hs_hprt 0x440 otg_hs host port control and st atus register (otg_hs_hprt) on page 1114 RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1083/1317 device-mode csr map these registers must be programmed every time the core changes to peripheral mode. otg_hs_hccharx 0x500 0x520 ... 0x6e0 otg_hs host channel-x characteristics register (otg_hs_hccharx) (x = 0..11, where x = channel_number) on page 1116 otg_hs_hcspltx 0x504 otg_hs host channel-x split control register (otg_hs_hcspltx) (x = 0..11, where x = channel_number) on page 1118 otg_hs_hcintx 0x508 otg_hs host channel-x interrupt re gister (otg_hs_hcintx) (x = 0..11, where x = channel_number) on page 1119 otg_hs_hcintmskx 0x50c otg_hs host channel-x interrupt ma sk register (otg_hs_hcintmskx) (x = 0..11, where x = channel_number) on page 1120 otg_hs_hctsizx 0x510 otg_hs host channel-x transfer size register (otg_hs_hctsizx) (x = 0..11, where x = channel_number) on page 1121 otg_hs_hcdmax 0x514 otg_hs host channel-x dma address register (otg_hs_hcdmax) (x = 0..11, where x = channel_number) on page 1122 table 156. host-mode control and status registers (csrs) (continued) acronym offset address register name table 157. device-mode control and status registers acronym offset address register name otg_hs_dcfg 0x800 otg_hs device configuration register (otg_hs_dcfg) on page 1122 otg_hs_dctl 0x804 otg_hs device control register (otg_hs_dctl) on page 1124 otg_hs_dsts 0x808 otg_hs device status register (otg_hs_dsts) on page 1126 otg_hs_diepmsk 0x810 otg_hs device in endpoint common interrupt mask register (otg_hs_diepmsk) on page 1127 otg_hs_doepmsk 0x814 otg_hs device out endpoint common interrupt mask register (otg_hs_doepmsk) on page 1128 otg_hs_daint 0x818 otg_hs device all endpoints interrupt register (otg_hs_daint) on page 1129 otg_hs_daintmsk 0x81c otg_hs all endpoints interrupt mask register (otg_hs_daintmsk) on page 1129 otg_hs_dvbusdis 0x828 otg_hs device v bus discharge time register (otg_hs_dvbusdis) on page 1130 otg_hs_dvbuspulse 0x82c otg_hs device v bus pulsing time register (otg_hs_dvbuspulse) on page 1130 otg_hs_diepempmsk 0x834 otg_hs device in endpoint fifo empty interrupt mask register: (otg_hs_diepempmsk) on page 1132 usb on-the-go high-speed (otg_hs) RM0033 1084/1317 doc id 15403 rev 3 otg_hs_eachhint 0x838 otg_hs device each endpoint interrupt register (otg_hs_deachint) on page 1132 otg_hs_eachhintmsk 0x83c otg_hs device each endpoint interrupt register mask (otg_hs_deachintmsk) on page 1133 otg_hs_diepeachmsk1 0x840 otg_hs device each in endpoint-1 interrupt register (otg_hs_diepeachmsk1) on page 1133 otg_hs_doepeachmsk1 0x880 otg_hs device each out endpoint-1 interrupt register (otg_hs_doepeachmsk1) on page 1134 otg_hs_diepctlx 0x920 0x940 ... 0xae0 otg device endpoint-x control register (otg_hs_diepctlx) (x = 0..7, where x = endpoint_number) on page 1135 otg_hs_diepintx 0x908 otg_hs device endpoint-x interrupt register (otg_hs_diepintx) (x = 0..7, where x = endpoint_number) on page 1142 otg_hs_dieptsiz0 0x910 otg_hs device in endpoint 0 transfer size register (otg_hs_dieptsiz0) on page 1145 otg_hs_diepdmax 0x914 otg_hs device endpoint-x dma address register (otg_hs_diepdmax / otg_hs_d oepdmax) (x = 1..5, where x = endpoint_number) on page 1149 otg_hs_dtxfstsx 0x918 otg_hs device in endpoint tran smit fifo status register (otg_hs_dtxfstsx) (x = 0..5, where x = endpoint_number) on page 1148 otg_hs_dieptsizx 0x930 0x950 ... 0xaf0 otg_hs device endpoint-x transfer size register (otg_hs_doeptsizx) (x = 1..5, where x = endpoint_number) on page 1148 otg_hs_doepctl0 0xb00 otg_hs device control out endpoint 0 control register (otg_hs_doepctl0) on page 1138 otg_hs_doepctlx 0xb20 0xb40 ... 0xcc0 0xce0 0xcfd otg device endpoint-x control register (otg_hs_diepctlx) (x = 0..7, where x = endpoint_number) on page 1135 otg_hs_doepintx 0xb08 otg_hs device endpoint-x interrupt register (otg_hs_diepintx) (x = 0..7, where x = endpoint_number) on page 1142 otg_hs_doeptsizx 0xb10 otg_hs device endpoint-x transfer size register (otg_hs_doeptsizx) (x = 1..5, where x = endpoint_number) on page 1148 table 157. device-mode control and status registers (continued) acronym offset address register name RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1085/1317 data fifo (dfifo) access register map these registers, available in both host and peripheral modes, are used to read or write the fifo space for a specific endpoint or a channel , in a given direction. if a host channel is of type in, the fifo can only be read on the channel. similarly, if a host channel is of type out, the fifo can only be written on the channel. power and clock gating csr map there is a single register for power and clock gating. it is available in both host and peripheral modes. 30.12.2 otg_hs global registers these registers are available in both host and peripheral modes, and do not need to be reprogrammed when switching between these modes. bit values in the register descriptions are expressed in binary unless otherwise specified. otg_hs control and status register (otg_hs_gotgctl) address offset: 0x000 reset value: 0x0000 0800 the otg control and status register controls the behavior and reflects the status of the otg function of the core. table 158. data fifo (dfifo) access register map fifo access register section address range access device in endpoint 0/host out channel 0: dfifo write access device out endpoint 0/host in channel 0: dfifo read access 0x1000?0x1ffc w r device in endpoint 1/host out channel 1: dfifo write access device out endpoint 1/host in channel 1: dfifo read access 0x2000?0x2ffc w r ... ... ... device in endpoint x (1) /host out channel x (1) : dfifo write access device out endpoint x (1) /host in channel x (1) : dfifo read access 1. where x is 5 in peripheral mode and 11 in host mode. 0xx000h?0xxffch w r table 159. power and clock gating control and status registers register name acronym offset address: 0xe00?0xfff power and clock gating control register pcgcr 0xe00-0xe04 reserved 0xe05?0xfff usb on-the-go high-speed (otg_hs) RM0033 1086/1317 doc id 15403 rev 3 313029282726252423222120191817161514131211109876543210 reserved bsvld asvld dbct cidsts reserved dhnpen hshnpen hnprq hngscs reserved srq srqscs rrrr rwrwrwr rwr bits 31:20 reserved bit 19 bsvld: b-session valid indicates the peripheral mode transceiver status. 0: b-session is not valid. 1: b-session is valid. in otg mode, you can use this bit to determine if the device is connected or disconnected. note: only accessible in peripheral mode. bit 18 asvld: a-session valid indicates the host mode transceiver status. 0: a-session is not valid 1: a-session is valid note: only accessible in host mode. bit 17 dbct: long/short debounce time indicates the debounce time of a detected connection. 0: long debounce time, used for physical connections (100 ms + 2.5 s) 1: short debounce time, used for soft connections (2.5 s) note: only accessible in host mode. bit 16 cidsts: connector id status indicates the connector id status on a connect event. 0: the otg_hs controller is in a-device mode 1: the otg_hs controller is in b-device mode note: accessible in both peripheral and host modes. bits 15:12 reserved bit 11 dhnpen: device hnp enabled the application sets this bit when it successf ully receives a setfeature.sethnpenable command from the connected usb host. 0: hnp is not enabled in the application 1: hnp is enabled in the application note: only accessible in peripheral mode. bit 10 hshnpen: host set hnp enable the application sets this bit when it has successfully enabled hnp (using the setfeature.sethnpenable command) on the connected device. 0: host set hnp is not enabled 1: host set hnp is enabled note: only accessible in host mode. RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1087/1317 otg_hs interrupt register (otg_hs_gotgint) address offset: 0x04 reset value: 0x0000 0000 the application reads this register whenever there is an otg interrupt and clears the bits in this register to clear the otg interrupt. bit 9 hnprq: hnp request the application sets this bit to initiate an hnp request to the connected usb host. the application can clear this bit by writing a 0 when the host negotiation success status change bit in the otg interrupt register (hnsschg bit in otg_hs_gotgint) is set. the core clears this bit when the hnsschg bit is cleared. 0: no hnp request 1: hnp request note: only accessible in peripheral mode. bit 8 hngscs: host negotiation success the core sets this bit when host negotiation is successful. the core clears this bit when the hnp request (hnprq) bit in this register is set. 0: host negotiation failure 1: host negotiation success note: only accessible in peripheral mode. bits 7:2 reserved bit 1 srq: session request the application sets this bit to initiate a session request on the usb. the application can clear this bit by writing a 0 when the host negotiation success status change bit in the otg interrupt register (hnsschg bit in otg_hs_got gint) is set. the core clears this bit when the hnsschg bit is cleared. if you use the usb 1.1 full-speed serial transceiv er interface to initiate the session request, the application must wait until v bus discharges to 0.2 v, after the b-session valid bit in this register (bsvld bit in otg_hs_gotgctl) is cl eared. this discharge time varies between different phys and can be obtained from the phy vendor. 0: no session request 1: session request note: only accessible in peripheral mode. bit 0 srqscs: session request success the core sets this bit when a se ssion request initiation is successful. 0: session request failure 1: session request success note: only accessible in peripheral mode. 313029282726252423222120191817161514131211109876543210 reserved dbcdne adtochg hngdet reserved hnsschg srsschg reserved sedet res. rc_ w1 rc_ w1 rc_ w1 rc_ w1 rc_ w1 rc_ w1 usb on-the-go high-speed (otg_hs) RM0033 1088/1317 doc id 15403 rev 3 bits 31:20 reserved. bit 19 dbcdne: debounce done the core sets this bit when the debounce is completed after the device connect. the application can start driving usb reset after seeing this interrupt. this bit is only valid when the hnp capable or srp capable bit is set in the co re usb configuration register (hnpcap bit or srpcap bit in otg_hs_gusbcfg, respectively). note: only accessible in host mode. bit 18 adtochg: a-device timeout change the core sets this bit to indica te that the a-device has timed out while waiting for the b-device to connect. note: accessible in both peripheral and host modes. bit 17 hngdet: host negotiation detected the core sets this bit when it detects a host negotiation request on the usb. note: accessible in both peripheral and host modes. bits 16:10 reserved. bit 9 hnsschg: host negotiation success status change the core sets this bit on the success or failure of a usb host negotiation request. the application must read the host negotiation succe ss bit of the otg contro l and status register (hngscs in otg_hs_gotgctl) to check for success or failure. note: accessible in both peripheral and host modes. bits 7:3 reserved. bit 8 srsschg: session request success status change the core sets this bit on the success or fail ure of a session request. the application must read the session request success bit in the otg control and status register (srqscs bit in otg_hs_gotgctl) to check for success or failure. note: accessible in both peripheral and host modes. bit 2 sedet: session end detected the core sets this bit to indicate that the level of the voltage on v bus is no longer valid for a b- device session when v bus < 0.8 v. bits 1:0 reserved. RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1089/1317 otg_hs ahb configuration register (otg_hs_gahbcfg) address offset: 0x008 reset value: 0x0000 0000 this register can be used to configure the core after power-on or a change in mode. this register mainly contains ahb system-related configuration parameters. do not change this register after the initial programming. the application must program this register before starting any transactions on either the ahb or the usb. 313029282726252423222120191817161514131211109876543210 reserved ptxfelvl txfelvl reserved dmaen hbstlen gint rw rw rw rw bits 31:20 reserved. bit 8 ptxfelvl: periodic txfifo empty level indicates when the periodic txfifo empty interr upt bit in the core interrupt register (ptxfe bit in otg_hs_gintsts) is triggered. 0: ptxfe (in otg_hs_gintsts) interrupt indica tes that the periodic txfifo is half empty 1: ptxfe (in otg_hs_gintsts) interrupt indicate s that the periodic tx fifo is completely empty note: only accessible in host mode. bit 7 txfelvl: txfifo empty level in peripheral mode, this bit indicates when th e in endpoint transmit fifo empty interrupt (txfe in otg_hs_diepintx.) is triggered. 0: txfe (in otg_hs_diepintx) interrupt indi cates that the in endpoint txfifo is half empty 1: txfe (in otg_hs_diepintx) interrupt indicates that the in endpoint txfifo is completely empty note: only accessible in peripheral mode. bit 6 reserved bits5 dmaen: dma enable 0: the core operates in slave mode 1: the core operates in dma mode bits 4:1 hbstlen: burst length/type 0000 single 0001 incr 0011 incr4 0101 incr8 0111 incr16 others: reserved bit 0 gint: global interrupt mask this bit is used to mask or unmask the interrupt line assertion to the application. irrespective of this bit setting, the interrupt status registers are updated by the core. 0: mask the interrupt assertion to the application. 1: unmask the interrupt assertion to the application note: accessible in both peripheral and host modes. usb on-the-go high-speed (otg_hs) RM0033 1090/1317 doc id 15403 rev 3 otg_hs usb configuration register (otg_hs_gusbcfg) address offset: 0x00c reset value: 0x0000 0a00 this register can be used to configure the core after power-on or a changing to host mode or peripheral mode. it contains usb and usb-phy related configuration parameters. the application must program this register before starting any transactions on either the ahb or the usb. do not make changes to this register after the initial programming. 313029282726252423222120191817161514131211109876543210 ctxpkt fdmod fhmod reserved ulpiipd ptci pcci tsdps ulpievbusi ulpievbusd ulpicsm ulpiar ulpifsls reserved phylpcs reserved trdt hnpcap srpcap reserved tocal rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw r/rw r/rw rw bit 31 ctxpkt: corrupt tx packet this bit is for debug purposes only. never set this bit to 1. note: accessible in both peripheral and host modes. bit 30 fdmod: forced peripheral mode writing a 1 to this bit forces the core to peripheral mode irrespective of the otg_hs_id input pin. 0: normal mode 1: forced peripheral mode after setting the force bit, the application must wait at least 25 ms before the change takes effect. note: accessible in both peripheral and host modes. bit 29 fhmod: forced host mode writing a 1 to this bit forces the core to host mode irrespective of the otg_hs_id input pin. 0: normal mode 1: forced host mode after setting the force bit, the application must wait at least 25 ms before the change takes effect. note: accessible in both peripheral and host modes. bits 28:26 reserved bit 25 ulpiipd: ulpi interface protect disable this bit controls the circuitry built in the phy to protect the ulpi interface when the link tri- states stp and data. any pull-up or pull-down resistors employed by this feature can be disabled. please refer to the ulpi specification for more details. 0: enables the interface protection circuit 1: disables the interface protection circuit bit 24 ptci: indicator pass through this bit controls whether the complement output is qualified with the internal v bus valid comparator before being used in the v bus state in the rx cmd. please refer to the ulpi specification for more details. 0: complement output signal is qualified with the internal v bus valid comparator 1: complement output signal is not qualified with the internal v bus valid comparator RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1091/1317 bit 23 pcci: indicator complement this bit controls the phy to invert the exte rnalvbusindicator input signal, and generate the complement output. please refer to the ulpi specification for more details. 0: phy does not invert the externalvbusindicator signal 1: phy inverts externalvbusindicator signal bit 22 tsdps : termsel dline pulsing selection this bit selects utmi_termselect to drive the data line pulse during srp (session request protocol). 0: data line pulsing using utmi_txvalid (default) 1: data line pulsing using utmi_termsel bit 21 ulpievbusi: ulpi external v bus indicator this bit indicates to the ulpi phy to use an external v bus overcurrent indicator. 0: phy uses an internal v bus valid comparator 1: phy uses an external v bus valid comparator bit 20 ulpievbusd: ulpi external v bus drive this bit selects between internal or external supply to drive 5 v on v bus , in the ulpi phy. 0: phy drives v bus using internal charge pump (default) 1: phy drives v bus using external supply. bit 19 ulpicsm: ulpi clock suspendm this bit sets the clocksuspendm bit in the interf ace control register on the ulpi phy. this bit applies only in the serial and carkit modes. 0: phy powers down the internal clock during suspend 1: phy does not power down the internal clock bit 18 ulpiar: ulpi auto-resume this bit sets the autoresume bit in the interface control register on the ulpi phy. 0: phy does not use autoresume feature 1: phy uses autoresume feature bit 17 ulpifsls: ulpi fs/ls select the application uses this bit to select the fs/ls serial interface for the ulpi phy. this bit is valid only when the fs serial transceiver is selected on the ulpi phy. 0: ulpi interface 1: ulpi fs/ls serial interface bit 16 reserved bit 15 phylpcs: phy low-power clock select this bit selects either 480 mhz or 48 mhz (low-power) phy mode. in fs and ls modes, the phy can usually operate on a 48 mhz clock to save power. 0: 480 mhz internal pll clock 1: 48 mhz external clock in 480 mhz mode, the utmi interface operat es at either 60 or 30 mhz, depending on whether the 8- or 16-bit data width is select ed. in 48 mhz mode, the utmi interface operates at 48 mhz in fs and ls modes. bit 14 reserved usb on-the-go high-speed (otg_hs) RM0033 1092/1317 doc id 15403 rev 3 bits 13:10 trdt: usb turnaround time sets the turnaround time in phy clocks. the formula below gives the value of trdt: trdt = 4 ahb clock frequency+ 1 phy clock frequency. for example: if ahb clock frequency = 72 mhz (phy clock frequency = 48 mhz), the trdt must be set to 9. if ahb clock frequency = 48 mhz (phy clock frequency = 48 mhz), the trdt must be set to 5. note: only accessible in peripheral mode. bit 9 hnpcap: hnp-capable the application uses this bit to contro l the otg_hs controller?s hnp capabilities. 0: hnp capability is not enabled 1: hnp capability is enabled note: accessible in both peripheral and host modes. bit 8 srpcap: srp-capable the application uses this bit to control the otg_hs controller?s srp capabilities. if the core operates as a nonsrp-capable b-device, it cann ot request the connected a-device (host) to activate v bus and start a session. 0: srp capability is not enabled 1: srp capability is enabled note: accessible in both peripheral and host modes. bits 7:3 reserved. must be kept cleared. bits 2:0 tocal: fs timeout calibration the number of phy clocks that the application programs in this field is added to the full- speed interpacket timeout duration in the core to account for any additional delays introduced by the phy. this can be required, because the delay introduced by the phy in generating the line state condition can vary from one phy to another. the usb standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. the application must program this field based on th e speed of enumeration. the number of bit times added per phy clock is 0.25 bit times. RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1093/1317 otg_hs reset register (otg_hs_grstctl) address offset: 0x010 reset value: 0x2000 0000 the application uses this register to reset various hardware features inside the core. 313029282726252423222120191817161514131211109876543210 ahbidl dmareq reserved txfnum txfflsh rxfflsh reserved fcrst hsrst csrst rr rw rs rs rs rs rs bit 31 ahbidl: ahb master idle indicates that the ahb master state machine is in the idle condition. note: accessible in both peripheral and host modes. bit 30 dmareq: dma request signal this bit indicates that the dma request is in progress. used for debug. bits 29:11 reserved bits 10:6 txfnum: txfifo number this is the fifo number that must be flushed using the txfifo flush bit. this field must not be changed until the core clears the txfifo flush bit. 00000: ? nonperiodic txfifo flush in host mode ? tx fifo 0 flush in peripheral mode 00001: ? periodic txfifo flush in host mode ? txfifo 1 flush in peripheral mode 00010: txfifo 2 flush in peripheral mode ... 00101: txfifo 15 flush in peripheral mode 10000: flush all the transmit fifos in peripheral or host mode. note: accessible in both peripheral and host modes. bit 5 txfflsh: txfifo flush this bit selectively flushes a single or all transmit fifos, but cannot do so if the core is in the midst of a transaction. the application must write this bit only after chec king that the core is neither writing to the txfifo nor reading from the txfifo. verify using these registers: ? read: the nak effective interrupt ensure s the core is not reading from the fifo ? write: the ahbidl bit in otg_hs_grstctl ensures that the core is not writing anything to the fifo note: accessible in both peripheral and host modes. usb on-the-go high-speed (otg_hs) RM0033 1094/1317 doc id 15403 rev 3 bit 4 rxfflsh: rxfifo flush the application can flush the entire rxfifo using th is bit, but must first ensure that the core is not in the middle of a transaction. the application must only write to this bit after checking that th e core is neither reading from the rxfifo nor writing to the rxfifo. the application must wait until th e bit is cleared before performing any other operation. this bit requires 8 clocks (slowest of phy or ahb clock) to be cleared. note: accessible in both peripheral and host modes. bit 3 reserved bit 2 fcrst: host frame counter reset the application writes this bit to reset the fr ame number counter inside the core. when the frame counter is reset, the subsequent sof sent out by the core has a frame number of 0. note: only accessible in host mode. bit 1 hsrst: hclk soft reset the application uses this bit to flush the control logic in the ahb clock domain. only ahb clock domain pipelines are reset. fifos are not flushed with this bit. all state machines in the ahb clock domain are reset to the idle state after terminating the transactions on the ahb, following the protocol. csr control bits used by the ahb cloc k domain state machines are cleared. to clear this interrupt, status mask bits that control the interrupt status and are generated by the ahb clock domain state machine are cleared. because interrupt status bits are not cleared, the application can get the status of any core events that occurred after it set this bit. this is a self-clearing bit that the core clears af ter all necessary logic is reset in the core. this can take several clocks, depending on the core?s current state. note: accessible in both peripheral and host modes. RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1095/1317 bit 0 csrst: core soft reset resets the hclk and pclk domains as follows: clears the interrupts and all the csr register bits except for the following bits: ? rstpdmodl bit in otg_hs_pcgcctl ? gayehclk bit in otg_hs_pcgcctl ? pwrclmp bit in otg_hs_pcgcctl ? stppclk bit in otg_hs_pcgcctl ? fslspcs bit in otg_hs_hcfg ? dspd bit in otg_hs_dcfg all module state machines (except for the ahb slave unit) are reset to the idle state, and all the transmit fifos and the receive fifo are flushed. any transactions on the ahb master are terminated as soon as possible, after completing the last data phase of an ahb transfer. any tran sactions on the usb are terminated immediately. the application can write to this bit any time it wants to reset the core. this is a self-clearing bit and the core clears this bit after all the necessary logic is reset in the core, which can take several clocks, depending on the current state of the core. once this bit has been cleared, the software must wait at least 3 phy clocks befo re accessing the phy do main (synchronization delay). the software must also check that bit 31 in this register is set to 1 (ahb master is idle) before starting any operation. typically, the software reset is used during software development and also when you dynamically change the phy sele ction bits in the above listed usb configuration registers. when you change the phy, the corresponding clock for the phy is selected and used in the phy domain. once a new clock is selected, the phy domain has to be reset for proper operation. note: accessible in both peripheral and host modes. usb on-the-go high-speed (otg_hs) RM0033 1096/1317 doc id 15403 rev 3 otg_hs core interrupt register (otg_hs_gintsts) address offset: 0x014 reset value: 0x0400 0020 this register interrupts the application for system-level events in the current mode (peripheral mode or host mode). some of the bits in this register are valid only in host mode, while others are valid in peripheral mode only. this register also indicates the current mode. to clear the interrupt status bits of the rc_w1 type, the application must write 1 into the bit. the fifo status interrupts are read-only; once software reads from or writes to the fifo while servicing these interrupts, fifo interrupt conditions are cleared automatically. the application must clear the otg_hs_gin tsts register at initialization before unmasking the interrupt bit to avoid any interrupts generated prior to initialization. 313029282726252423222120191817161514131211109876543210 wkuint srqint discint cidschg reserved ptxfe hcint hprtint reserved datafsusp ipxfr/incompisoout iisoixfr oepint iepint reserved eopf isoodrp enumdne usbrst usbsusp esusp reserved boutnakeff ginakeff nptxfe rxflvl sof otgint mmis cmod rc_w1 rrr rc_w1rr rc_w1 rrrr rc_w1 r rc_w1 r bit 31 wkupint: resume/remote wakeup detected interrupt in peripheral mode, this interrupt is asserted when a resume is detected on the usb. in host mode, this interrupt is asserted when a remote wakeup is detected on the usb. note: accessible in both peripheral and host modes. bit 30 srqint: session request/new session detected interrupt in host mode, this interrupt is asserted when a session request is detected from the device. in peripheral mode, this interrupt is asserted when v bus is in the valid range for a b-device device. accessible in both peripheral and host modes. bit 29 discint: disconnect detected interrupt asserted when a device disconnect is detected. note: only accessible in host mode. bit 28 cidschg: connector id status change the core sets this bit when there is a change in connector id status. note: accessible in both peripheral and host modes. bit 27 reserved bit 26 ptxfe: periodic txfifo empty asserted when the periodic transmit fifo is ei ther half or completely empty and there is space for at least one entry to be written in the periodic request queue. the half or completely empty status is determined by the periodic txfifo empty level bit in the core ahb configuration register (ptxfelvl bit in otg_hs_gahbcfg). note: only accessible in host mode. RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1097/1317 bit 25 hcint: host channels interrupt the core sets this bit to indicate that an interrupt is pending on one of the channels of the core (in host mode). the application must read the host all channels interrupt (otg_hs_haint) register to determine the exact number of the channel on which the interrupt occurred, and then read the corresponding host channel-x interrupt (otg_hs_hcintx) register to determine the ex act cause of the interrupt. the application must clear the appropriate status bit in the otg_hs_hcintx register to clear this bit. note: only accessible in host mode. bit 24 hprtint: host port interrupt the core sets this bit to indicate a change in port status of one of the otg_hs controller ports in host mode. the application must read the host port control and status (otg_hs_hprt) register to determine the ex act event that caused this interrupt. the application must clear the appropriate status bit in the host port control and status register to clear this bit. note: only accessible in host mode. bits 23 reserved bit 22 datafsusp: data fetch suspended this interrupt is valid only in dma mode. this interrupt indicates that the core has stopped fetching data for in endpoints due to the un availability of txfifo space or request queue space. this interrupt is used by the application for an endpoint mismatch algorithm. for example, after detecting an endpoint mismatch, the application: ? sets a global nonperiodic in nak handshake ? disables in endpoints ? flushes the fifo ? determines the token sequence from the in token sequence learning queue ? re-enables the endpoints ? clears the global nonperiodic in nak handshake if the global nonperiodic in nak is cleared, the core has not yet fetched data for the in endpoint, and the in token is received: the core generates an ?in tok en received when fifo empty? interrupt. the otg then sends a nak response to the host. to avoid this scenario, the application can check the fetsusp interrupt in otg_fs_gintsts, which ensures that the fifo is full before clearing a global nak handshake. alternatively, the application can mask the ?in token rece ived when fifo empty? interrupt when clearing a global in nak handshake. bit 21 ipxfr: incomplete periodic transfer in host mode, the core sets this interrupt bit when there are incomplete periodic transactions still pending, which are scheduled for the current frame. note: only accessible in host mode. incompisoout: incomplete isochronous out transfer in peripheral mode, the core sets this interrupt to indicate that there is at least one isochronous out endpoint on which the transfer is not completed in the current frame. this interrupt is asserted along with the end of periodic frame interrupt (eopf) bit in this register. note: only accessible in peripheral mode. bit 20 iisoixfr: incomplete isochronous in transfer the core sets this interrupt to indicate that there is at least one isochronous in endpoint on which the transfer is not completed in the current frame. this interrupt is asserted along with the end of periodic frame interrup t (eopf) bit in this register. note: only accessible in peripheral mode. usb on-the-go high-speed (otg_hs) RM0033 1098/1317 doc id 15403 rev 3 bit 19 oepint: out endpoint interrupt the core sets this bit to indicate that an interrupt is pending on one of the out endpoints of the core (in peripheral mode). the application must read the device all endpoints interrupt (otg_hs_daint) register to determine the ex act number of the out endpoint on which the interrupt occurred, and then read the corresponding device out endpoint-x interrupt (otg_hs_doepintx) register to determine the exact cause of the interrupt. the application must clear the appropriate status bit in the corresponding otg_hs_doepintx register to clear this bit. note: only accessible in peripheral mode. bit 18 iepint: in endpoint interrupt the core sets this bit to indicate that an in terrupt is pending on one of the in endpoints of the core (in peripheral mode). the application must read the device all endpoints interrupt (otg_hs_daint) register to determine the ex act number of the in endpoint on which the interrupt occurred, and then read the corresp onding device in endpoint-x interrupt (otg_hs_diepintx) register to determine the exact cause of the interrupt. the application must clear the appropriate status bit in th e corresponding otg_hs_diepintx register to clear this bit. note: only accessible in peripheral mode. bits 17:16 reserved bit 15 eopf: end of periodic frame interrupt indicates that the period specified in the pe riodic frame interval field of the device configuration register (pfivl bit in otg_hs _dcfg) has been reached in the current frame. note: only accessible in peripheral mode. bit 14 isoodrp: isochronous out packet dropped interrupt the core sets this bit when it fails to writ e an isochronous out packet into the rxfifo because the rxfifo does not have enough space to accommodate a maximum size packet for the isochronous out endpoint. note: only accessible in peripheral mode. bit 13 enumdne: enumeration done the core sets this bit to indi cate that speed enumeration is complete. the application must read the device status (otg_hs_dsts) regi ster to obtain the enumerated speed. note: only accessible in peripheral mode. bit 12 usbrst: usb reset the core sets this bit to indicate that a reset is detected on the usb. note: only accessible in peripheral mode. bit 11 usbsusp: usb suspend the core sets this bit to indicate that a su spend was detected on the usb. the core enters the suspended state when there is no activity on the data lines for a period of 3 ms. note: only accessible in peripheral mode. bit 10 esusp: early suspend the core sets this bit to indicate that an idle state has been detected on the usb for 3 ms. note: only accessible in peripheral mode. bits 9:8 reserved RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1099/1317 bit 7 gonakeff: global out nak effective indicates that the set global out nak bit in the device control register (sgonak bit in otg_hs_dctl), set by the application, has taken effect in the core. this bit can be cleared by writing the clear global out nak bit in the device control register (cgonak bit in otg_hs_dctl). note: only accessible in peripheral mode. bit 6 ginakeff: global in nonperiodic nak effective indicates that the set global nonperiodic in nak bit in the device control register (sginak bit in otg_hs_dctl), set by the application, has taken effect in the core. that is, the core has sampled the global in nak bit set by the application. this bit can be cleared by clearing the clear global nonperiodic in nak bit in the device control register (cginak bit in otg_hs_dctl). this interrupt does not necessarily mean that a nak handshake is sent out on the usb. the stall bit takes precedence over the nak bit. note: only accessible in peripheral mode. bit 5 nptxfe: nonperiodic txfifo empty this interrupt is asserted when the nonperiodic txfifo is either half or completely empty, and there is space in at least one entry to be written to the nonperiodic transmit request queue. the half or completely empty status is determined by the nonperiodic txfifo empty level bit in the otg_hs_gahbcfg regist er (txfelvl bit in otg_hs_gahbcfg). note: only accessible in host mode. bit 4 rxflvl: rxfifo nonempty indicates that there is at least one packet pending to be read from the rxfifo. note: accessible in both host and peripheral modes. bit 3 sof: start of frame in host mode, the core sets this bit to indi cate that an sof (fs), or keep-alive (ls) is transmitted on the usb. the applic ation must write a 1 to this bit to clear the interrupt. in peripheral mode, in the core sets this bit to indicate that an sof token has been received on the usb. the application can read the device status register to get the current frame number. this interrupt is seen only when the core is operating in fs. note: accessible in both host and peripheral modes. bit 2 otgint: otg interrupt the core sets this bit to indicate an otg protocol event. the application must read the otg interrupt status (otg_hs_gotgint) register to determine the exact event that caused this interrupt. the application must clear the app ropriate status bit in the otg_hs_gotgint register to clear this bit. note: accessible in both host and peripheral modes. bit 1 mmis: mode mismatch interrupt the core sets this bit when the application is trying to access: a host mode register, when the core is operating in peripheral mode a peripheral mode register, when the core is operating in host mode the register access is completed on the ahb with an okay response, but is ignored by the core internally and does not affect the operation of the core. note: accessible in both host and peripheral modes. bit 0 cmod: current mode of operation indicates the current mode. 0: peripheral mode 1: host mode note: accessible in both host and peripheral modes. usb on-the-go high-speed (otg_hs) RM0033 1100/1317 doc id 15403 rev 3 otg_hs interrupt mask register (otg_hs_gintmsk) address offset: 0x018 reset value: 0x0000 0000 this register works with the core interrupt register to interrupt the application. when an interrupt bit is masked, the interrupt associated with that bit is not generated. however, the core interrupt (otg_hs_ gintsts) register bit corresponding to that interrupt is still set. 313029282726252423222120191817161514131211109876543210 wuim srqim discint cidschgm reserved ptxfem hcim prtim reserved fsuspm ipxfrm/iisooxfrm iisoixfrm oepint iepint epmism reserved eopfm isoodrpm enumdnem usbrst usbsuspm esuspm reserved gonakeffm ginakeffm nptxfem rxflvlm sofm otgint mmism reserved rwrwrwrw rwrw r rwrwrwrwrwrw rwrwrwrwrwrw rwrwrwrwrwrwrw bit 31 wuim: resume/remote wakeup detected interrupt mask 0: masked interrupt 1: unmasked interrupt note: accessible in both host and peripheral modes. bit 30 srqim: session request/new session detected interrupt mask 0: masked interrupt 1: unmasked interrupt note: accessible in both host and peripheral modes. bit 29 discint: disconnect detected interrupt mask 0: masked interrupt 1: unmasked interrupt note: accessible in both host and peripheral modes. bit 28 cidschgm: connector id status change mask 0: masked interrupt 1: unmasked interrupt note: accessible in both host and peripheral modes. bit 27 reserved bit 26 ptxfem: periodic txfifo empty mask 0: masked interrupt 1: unmasked interrupt note: only accessible in host mode. bit 25 hcim: host channels interrupt mask 0: masked interrupt 1: unmasked interrupt note: only accessible in host mode. bit 24 prtim: host port interrupt mask 0: masked interrupt 1: unmasked interrupt note: only accessible in host mode. bit 23 reserved RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1101/1317 bit 22 fsuspm: data fetch suspended mask 0: masked interrupt 1: unmasked interrupt note: only accessible in peripheral mode. bit 21 ipxfrm: incomplete periodic transfer mask 0: masked interrupt 1: unmasked interrupt note: only accessible in host mode. iisooxfrm: incomplete isochronous out transfer mask 0: masked interrupt 1: unmasked interrupt note: only accessible in peripheral mode. bit 20 iisoixfrm: incomplete isochronous in transfer mask 0: masked interrupt 1: unmasked interrupt note: only accessible in peripheral mode. bit 19 oepint: out endpoints interrupt mask 0: masked interrupt 1: unmasked interrupt note: only accessible in peripheral mode. bit 18 iepint: in endpoints interrupt mask 0: masked interrupt 1: unmasked interrupt note: only accessible in peripheral mode. bit 17 epmism: endpoint mismatch interrupt mask 0: masked interrupt 1: unmasked interrupt note: only accessible in peripheral mode. bit 16 reserved bit 15 eopfm: end of periodic frame interrupt mask 0: masked interrupt 1: unmasked interrupt note: only accessible in peripheral mode. bit 14 isoodrpm: isochronous out packet dropped interrupt mask 0: masked interrupt 1: unmasked interrupt note: only accessible in peripheral mode. bit 13 enumdnem: enumeration done mask 0: masked interrupt 1: unmasked interrupt note: only accessible in peripheral mode. bit 12 usbrst: usb reset mask 0: masked interrupt 1: unmasked interrupt note: only accessible in peripheral mode. usb on-the-go high-speed (otg_hs) RM0033 1102/1317 doc id 15403 rev 3 bit 11 usbsuspm: usb suspend mask 0: masked interrupt 1: unmasked interrupt note: only accessible in peripheral mode. bit 10 esuspm: early suspend mask 0: masked interrupt 1: unmasked interrupt note: only accessible in peripheral mode. bits 9:8 reserved. bit 7 gonakeffm: global out nak effective mask 0: masked interrupt 1: unmasked interrupt note: only accessible in peripheral mode. bit 6 ginakeffm: global nonperiodic in nak effective mask 0: masked interrupt 1: unmasked interrupt note: only accessible in peripheral mode. bit 5 nptxfem: nonperiodic txfifo empty mask 0: masked interrupt 1: unmasked interrupt note: accessible in both peripheral and host modes. bit 4 rxflvlm: receive fifo nonempty mask 0: masked interrupt 1: unmasked interrupt note: accessible in both peripheral and host modes. bit 3 sofm: start of frame mask 0: masked interrupt 1: unmasked interrupt note: accessible in both peripheral and host modes. bit 2 otgint: otg interrupt mask 0: masked interrupt 1: unmasked interrupt note: accessible in both peripheral and host modes. bit 1 mmism: mode mismatch interrupt mask 0: masked interrupt 1: unmasked interrupt note: accessible in both peripheral and host modes. bit 0 reserved RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1103/1317 otg_hs receive status debug read/otg status read and pop registers (otg_hs_grxstsr/otg_hs_grxstsp) address offset for read: 0x01c address offset for pop: 0x020 reset value: 0x0000 0000 a read to the receive status debug read register returns the contents of the top of the receive fifo. a read to the receive status read and pop register additionally pops the top data entry out of the rxfifo. the receive status contents must be interpreted differently in host and peripheral modes. the core ignores the receive status pop/read when the receive fifo is empty and returns a value of 0x0000 0000. the application must only pop the receive status fifo when the receive fifo nonempty bit of the core interrupt register (rxflvl bit in otg_hs_gintsts) is asserted. host mode: 313029282726252423222120191817161514131211109876543210 reserved pktsts dpid bcnt chnum rr r r bits 31:21 reserved bits 20:17 pktsts: packet status indicates the status of the received packet 0010: in data packet received 0011: in transfer completed (triggers an interrupt) 0101: data toggle error (triggers an interrupt) 0111: channel halted (triggers an interrupt) others: reserved bits 16:15 dpid: data pid indicates the data pid of the received packet 00: data0 10: data1 01: data2 11: mdata bits 14:4 bcnt: byte count indicates the byte count of the received in data packet. bits 3:0 chnum: channel number indicates the channel number to which the current received packet belongs. usb on-the-go high-speed (otg_hs) RM0033 1104/1317 doc id 15403 rev 3 peripheral mode: otg_hs receive fifo size register (otg_hs_grxfsiz) address offset: 0x024 reset value: 0x0000 0200 the application can program the ram size that must be allocated to the rxfifo. 313029282726252423222120191817161514131211109876543210 reserved frmnum pktsts dpid bcnt epnum rrr r r bits 31:25 reserved bits 24:21 frmnum: frame number this is the least significant 4 bits of the fram e number in which the packet is received on the usb. this field is supported only when isochronous out endpoints are supported. bits 20:17 pktsts: packet status indicates the status of the received packet 0001: global out nak (triggers an interrupt) 0010: out data packet received 0011: out transfer completed (triggers an interrupt) 0100: setup transaction completed (triggers an interrupt) 0110: setup data packet received others: reserved bits 16:15 dpid: data pid indicates the data pid of the received out data packet 00: data0 10: data1 01: data2 11: mdata bits 14:4 bcnt: byte count indicates the byte count of the received data packet. bits 3:0 epnum: endpoint number indicates the endpoint number to which the current received packet belongs. 313029282726252423222120191817161514131211109876543210 reserved rxfd r/rw bits 31:16 reserved bits 15:0 rxfd: rxfifo depth this value is in terms of 32-bit words. minimum value is 16 maximum value is 1024 the power-on reset value of this register is specified as the largest rx data fifo depth. RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1105/1317 otg_hs nonperiodic transmit fifo size/endpoint 0 transmit fifo size register (otg_hs_gnptxfsiz/otg_hs_tx0fsiz) address offset: 0x028 reset value: 0x0000 0200 host mode: peripheral mode: otg_hs nonperiodic transmit fifo/queue status register (otg_hs_gnptxsts) address offset: 0x02c reset value: 0x0008 0200 note: in peripheral mode, this register is not valid. this read-only register contains the free space information for the nonperiodic txfifo and the nonperiodic transmit request queue. 313029282726252423222120191817161514131211109876543210 nptxfd nptxfsa r/rw r/rw bits 31:16 nptxfd: nonperiodic txfifo depth this value is in terms of 32-bit words. minimum value is 16 maximum value is 1024 bits 15:0 nptxfsa: nonperiodic transmit ram start address this field contains the memory start address for nonperiodic transmit fifo ram. 313029282726252423222120191817161514131211109876543210 tx0fd tx0fsa r/rw r/rw bits 31:16 t0xfd: endpoint 0 txfifo depth this value is in terms of 32-bit words. minimum value is 16 maximum value is 256 bits 15:0 tx0fsa: endpoint 0 transmit ram start address this field contains the memory start add ress for endpoint 0 transmit fifo ram. 313029282726252423222120191817161514131211109876543210 reserved nptxqtop nptqxsav nptxfsav rr r usb on-the-go high-speed (otg_hs) RM0033 1106/1317 doc id 15403 rev 3 otg_hs i 2 c access register (otg_hs_gi2cctl) address offset: 0x030 reset value: 0x0000 0000 bit 31 reserved bits 30:24 nptxqtop: top of the nonperiodic transmit request queue entry in the nonperiodic tx request queue that is currently being processed by the mac. bits [30:27]: channel/endpoint number bits [26:25]: ? 00: in/out token ? 01: zero-length transmit packet (device in/host out) ? 10: ping/csplit token ? 11: channel halt command bit [24]: terminate (last entry for selected channel/endpoint) bits 23:16 nptqxsav: nonperiodic transmit request queue space available indicates the amount of free space available in the nonperiodic transmit request queue. this queue holds both in and out requests in host mode. peripheral mode has only in requests. 00: nonperiodic transmit request queue is full 01: dx1 location available 10: dx2 locations available bxn : dx n locations available (0 n dx8) others: reserved bits 15:0 nptxfsav: nonperiodic txfifo space available indicates the amount of free space available in the nonperiodic txfifo. values are in terms of 32-bit words. 00: nonperiodic txfifo is full 01: dx1 word available 10: dx2 words available 0xn: dx n words available (where 0 n dx1024) others: reserved 3130 29 282726 25 2423222120191817161514131211109876543210 bsydne rw reserved i2cdatse0 i2cdev adr reserved ack i2cen addr regaddr rwdata rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1107/1317 bit 31 bsydne : i2c busy/done the application sets this bit to 1 to start a request on the i 2 c interface. when the transfer is complete, the core deasserts this bit to 0. as long as the bit is set indicating that the i 2 c interface is busy, the application cannot start another request on the interface. bit 30 rw : read/write indicator this bit indicates whether a read or write register transfer must be performed on the interface. 0: write 1: read note: read/write bursting is not supported for registers. bit 29 reserved bit 28 i2cdatse0 : i 2 c datse0 usb mode this bit is used to select the full-speed interface usb mode. 0: vp_vm usb mode 1: dat_se0 usb mode bits 27:26 i2cdevadr : i 2 c device address this bit selects the address of the i 2 c slave on the usb 1.1 full-speed serial transceiver corresponding to the one used by the core for otg signalling. bit 25 reserved bit 24 ack : i 2 c ack this bit indicates whether an ack response was received from the i 2 c slave. it is valid when bsydne is cleared by the core, afte r the application has initiated an i 2 c access. 0: nak 1: ack bit 23 i2cen : i 2 c enable this bit enables the i 2 c master to initiate transactions on the i 2 c interface. bits 22:16 addr : i 2 c address this is the 7-bit i 2 c device address used by the application to access any external i 2 c slave, including the i 2 c slave on a usb 1.1 otg full-speed serial transceiver. bits 15:8 regaddr : i 2 c register address these bits allow to program the address of th e register to be read from or written to. bits 7:0 rwdata : i 2 c read/write data after a register read operation, these bi ts hold the read data for the application. during a write operation, the application can us e this register to program the data to be written to a register. usb on-the-go high-speed (otg_hs) RM0033 1108/1317 doc id 15403 rev 3 otg_hs general core configuration register (otg_hs_gccfg) address offset: 0x038 reset value: 0x0000 0000 313029282726252423222120191817161514131211109876543210 reserved novbussens sofouten vbusbsen vbusasen i2cpaden .pwrdwn reserved rw rw rw rw rw rw bits 31:22 reserved bit 21 novbussens : v bus sensing disable option when this bit is set, v bus is considered internally to be always at v bus valid level (5 v). this option removes the need for a dedicated v bus pad, and leave this pad free to be used for other purposes such as a shared functionality. v bus connection can be remapped on another general purpose input pad and monitored by software. this option is only suitable for host-only or device-only applications. 0: v bus sensing available by hardware 1: v bus sensing not available by hardware. bit 20 sofouten: sof output enable 0: sof pulse not available on pad 1: sof pulse available on pad bit 19 vbusbsen: enable the v bus sensing ?b? device 0: v bus sensing ?b? disabled 1: v bus sensing ?b? enabled bit 18 vbusasen: enable the v bus sensing ?a? device 0: v bus sensing ?a? disabled 1: v bus sensing ?a? enabled bit 17 i2cpaden : enable i 2 c bus connection for the external i 2 c phy interface. 0: i 2 c bus disabled 1: i 2 c bus enabled bit 16 pwrdwn: power down used to activate the transceiver in transmission/reception 0: power down active 1: power down deactivated (?transceiver active?) bits 15:0 reserved. RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1109/1317 otg_hs core id register (otg_hs_cid) address offset: 0x03c reset value:0x0000 1200 this is a read only register containing the product id. otg_hs host periodic transmit fifo size register (otg_hs_hptxfsiz) address offset: 0x100 reset value: 0x0200 0600 otg_hs device in endpoint transmit fifo size register (otg_hs_dieptxfx) (x = 1..7, where x is the fifo_number) address offset: 0x104 + (fifo_number ? 1) 0x04 reset value: 0x02000400 313029282726252423222120191817161514131211109876543210 product_id rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:0 product_id: product id field application-programmable id field. 313029282726252423222120191817161514131211109876543210 ptxfd ptxsa r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w r/r w bits 31:16 ptxfd: host periodic txfifo depth this value is in terms of 32-bit words. minimum value is 16 maximum value is 512 bits 15:0 ptxsa: host periodic txfifo start address the power-on reset value of this register is the sum of the largest rx data fifo depth and largest nonperiodic tx data fifo depth. 313029282726252423222120191817161514131211109876543210 ineptxfd ineptxsa r/rw r/rw r/rw r/rw r/rw r/rw r/rw r/rw r/rw r/rw r/rw r/rw r/rw r/rw r/rw r/rw r/rw r/rw r/rw r/rw r/rw r/rw r/rw r/rw r/rw r/rw r/rw r/rw r/rw r/rw r/rw r/r w bits 31:16 ineptxfd: in endpoint txfifo depth this value is in terms of 32-bit words. minimum value is 16 maximum value is 512 the power-on reset value of this register is s pecified as the largest in endpoint fifo number depth. usb on-the-go high-speed (otg_hs) RM0033 1110/1317 doc id 15403 rev 3 30.12.3 host-mode registers bit values in the register descriptions are expressed in binary unless otherwise specified. host-mode registers affect the operation of the core in the host mode. host mode registers must not be accessed in peripheral mode, as the results are undefined. host mode registers can be categorized as follows: otg_hs host configuration register (otg_hs_hcfg) address offset: 0x400 reset value: 0x0000 0000 this register configures the core after power-on. do not change to this register after initializing the host. bits 15:0 ineptxsa: in endpoint fifox transmit ram start address this field contains the memory start address for in endpoint transmit fifox. 313029282726252423222120191817161514131211109876543210 reserved fslss fslspcs rrwrw bits 31:3 reserved bit 2 fslss: fs- and ls-only support the application uses this bit to control the co re?s enumeration speed. using this bit, the application can make the core enumerate as an fs host, even if the connected device supports hs traffic. do not make changes to this field after initial programming. 0: hs/fs/ls, based on the maximum speed supported by the connected device 1: fs/ls-only, even if the connect ed device can support hs (read-only) bits 1:0 fslspcs: fs/ls phy clock select when the core is in fs host mode 01: phy clock is running at 48 mhz others: reserved when the core is in ls host mode 01: phy clock is running at 48 mhz. others: reserved RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1111/1317 otg_hs host frame interval register (otg_hs_hfir) address offset: 0x404 reset value: 0x0000 ea60 this register stores the frame interval information for the current speed to which the otg_hs controller has enumerated. otg_hs host frame number/frame time remaining register (otg_hs_hfnum) address offset: 0x408 reset value: 0x0000 3fff this register indicates the current frame number. it also indicates the time remaining (in terms of the number of phy clocks) in the current frame. 313029282726252423222120191817161514131211109876543210 reserved frivl rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:16 reserved bits 15:0 frivl: frame interval the value that the application programs to th is field specifies the interval between two consecutive sofs (fs), micro-sofs (hs) or ke ep-alive tokens (ls). this field contains the number of phy clocks that cons titute the required frame interv al. the application can write a value to this register only after the port enable bit of the host port cont rol and status register (pena bit in otg_hs_hprt) has been set. if no value is programmed, the core calculates the value based on the phy clock specified in the fs/ls phy clock select field of the host configuration register (fslspcs in otg_hs_hcfg): frame duration phy clock frequency note: the frivl bit can be modified whenever the application needs to change the frame interval time. 313029282726252423222120191817161514131211109876543210 ftrem frnum rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr bits 31:16 ftrem: frame time remaining indicates the amount of time remaining in the cu rrent frame, in terms of phy clocks. this field decrements on each phy clock. when it reaches zero, this field is reloaded with the value in the frame interval register and a new sof is transmitted on the usb. bits 15:0 frnum: frame number this field increments when a new sof is transmitt ed on the usb, and is cleared to 0 when it reaches 0x3fff. usb on-the-go high-speed (otg_hs) RM0033 1112/1317 doc id 15403 rev 3 otg_hs_host periodic transmit fifo/queue status register (otg_hs_hptxsts) address offset: 0x410 reset value: 0x0008 0100 this read-only register contains the free space information for the periodic txfifo and the periodic transmit request queue. 313029282726252423222120191817161514131211109876543210 ptxqtop ptxqsav ptxfsavl rrrrrrrrrrrrrrrrrwrwrwrwrwrwrwrwrwrwrwrwrwrwrwrw bits 31:24 ptxqtop: top of the periodic transmit request queue this indicates the entry in the periodic tx re quest queue that is currently being processed by the mac. this register is used for debugging. bit [31]: odd/even frame ? 0: send in even (micro) frame ? 1: send in odd (micro) frame bits [30:27]: channel/endpoint number bits [26:25]: type ? 00: in/out ? 01: zero-length packet ? 11: disable channel command bit [24]: terminate (last entry for the selected channel/endpoint) bits 23:16 ptxqsav: periodic transmit request queue space available indicates the number of free locations available to be written in the periodic transmit request queue. this queue holds both in and out requests. 00: periodic transmit request queue is full 01: dx1 location available 10: dx2 locations available bxn: dxn locations available (0 dxn ptxfd) others: reserved bits 15:0 ptxfsavl: periodic transmit data fifo space available indicates the number of free locations availabl e to be written to in the periodic txfifo. values are in terms of 32-bit words 0000: periodic txfifo is full 0001: dx1 word available 0010: dx2 words available bxn: dxn words available (where 0 dxn dx512) others: reserved RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1113/1317 otg_hs host all channels interrupt register (otg_hs_haint) address offset: 0x414 reset value: 0x0000 000 when a significant event occurs on a channel, the host all channels interrupt register interrupts the application using the host channels interrupt bit of the core interrupt register (hcint bit in otg_hs_gintsts). this is shown in figure 374 . there is one interrupt bit per channel, up to a maximum of 16 bits. bits in this register are set and cleared when the application sets and clears bits in the corresponding host channel-x interrupt register. otg_hs host all channels interrupt mask register (otg_hs_haintmsk) address offset: 0x418 reset value: 0x0000 0000 the host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. there is one interrupt mask bit per channel, up to a maximum of 16 bits. 313029282726252423222120191817161514131211109876543210 reserved haint rrrrrrrrrrrrrrrr bits 31:16 reserved bits 15:0 haint: channel interrupts one bit per channel: bit 0 for channel 0, bit 15 for channel 15 313029282726252423222120191817161514131211109876543210 reserved haintm rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:16 reserved bits 15:0 haintm: channel interrupt mask 0: masked interrupt 1: unmasked interrupt one bit per channel: bit 0 for channel 0, bit 15 for channel 15 usb on-the-go high-speed (otg_hs) RM0033 1114/1317 doc id 15403 rev 3 otg_hs host port control and status register (otg_hs_hprt) address offset: 0x440 reset value: 0x0000 0000 this register is available only in host mode. currently, the otg host supports only one port. a single register holds usb port-related information such as usb reset, enable, suspend, resume, connect status, and test mode for each port. it is shown in figure 374 . the rc_w1 bits in this register can trigger an interrupt to the application through the host port interrupt bit of the core interrupt register (hprtint bit in otg_hs_gintsts). on a port interrupt, the application must read this register and clear the bit that caused the interrupt. for the rc_w1 bits, the application must write a 1 to the bit to clear the interrupt. 313029282726252423222120191817161514131211109876 5 43210 reserved pspd ptctl ppwr plsts reserved prst psusp pres pocchng poca penchng pena pcdet pcsts r r rw rw rw rw rw r r rw rs rw rc_ w1 r rc_ w1 rc_ w0 rc_ w1 r bits 31:19 reserved bits 18:17 pspd: port speed indicates the speed of the device attached to this port. 00: high speed 01: full speed 10: low speed 11: reserved bits 16:13 ptctl: port test control the application writes a nonzero value to this field to put the port into a test mode, and the corresponding pattern is signaled on the port. 0000: test mode disabled 0001: test_j mode 0010: test_k mode 0011: test_se0_nak mode 0100: test_packet mode 0101: test_force_enable others: reserved bit 12 ppwr: port power the application uses this field to control power to this port, and the core clears this bit on an overcurrent condition. 0: power off 1: power on bits 11:10 plsts: port line status indicates the current logic level usb data lines bit [10]: logic level of otg_hs_fs_dp bit [11]: logic level of otg_hs_fs_dm bit 9 reserved RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1115/1317 bit 8 prst: port reset when the application sets this bit, a reset seque nce is started on this port. the application must time the reset period and clear this bit after the reset sequence is complete. 0: port not in reset 1: port in reset the application must leave this bit set for a minimum duration of at least 10 ms to start a reset on the port. the application can leave it set fo r another 10 ms in addition to the required minimum duration, before clearing the bit, even though there is no maximum limit set by the usb standard. high speed: 50 ms full speed/low speed: 10 ms bit 7 psusp: port suspend the application sets this bit to put this port in suspend mode. the core only stops sending sofs when this is set. to stop the phy clock, the application must set the port clock stop bit, which asserts the suspend input pin of the phy. the read value of this bit reflects the current su spend status of the port. this bit is cleared by the core after a remote wakeup signal is detected or the application sets the port reset bit or port resume bit in this register or the re sume/remote wakeup detected interrupt bit or disconnect detected interrupt bit in the core interrupt register (wkuint or discint in otg_hs_gintsts, respectively). 0: port not in suspend mode 1: port in suspend mode bit 6 pres: port resume the application sets this bit to drive resume signaling on the port. the core continues to drive the resume signal until the application clears this bit. if the core detects a usb remote wakeup sequence, as indicated by the port resume/remote wakeup detected interrupt bit of the core interrupt register (wkuint bit in otg_hs_gintsts), the core starts driving resu me signaling without application intervention and clears this bit when it detects a disconnect condition. the read value of this bit indicates whether the core is currently driving resume signaling. 0: no resume driven 1: resume driven bit 5 pocchng: port overcurrent change the core sets this bit when the status of the port overcurrent active bit (bit 4) in this register changes. bit 4 poca: port overcurrent active indicates the overcurrent condition of the port. 0: no overcurrent condition 1: overcurrent condition bit 3 penchng: port enable/disable change the core sets this bit when the status of t he port enable bit [2] in this register changes. usb on-the-go high-speed (otg_hs) RM0033 1116/1317 doc id 15403 rev 3 otg_hs host channel-x characteristics register (otg_hs_hccharx) (x = 0..11, where x = channel_number) address offset: 0x500 + (channel_number 0x20) reset value: 0x0000 0000 bit 2 pena: port enable a port is enabled only by the core after a reset sequence, and is disabled by an overcurrent condition, a disconnect condition, or by the application clearing this bit. the application cannot set this bit by a register write. it can only clear it to disable the port. this bit does not trigger any interrupt to the application. 0: port disabled 1: port enabled bit 1 pcdet: port connect detected the core sets this bit when a device connection is detected to trigge r an interrupt to the application using the host port interrupt bit in the core interrupt register (hprtint bit in otg_hs_gintsts). the application must writ e a 1 to this bit to clear the interrupt. bit 0 pcsts: port connect status 0: no device is attached to the port 1: a device is attached to the port 313029282726252423222120191817161514131211109876543210 chena chdis oddfrm dad mc eptyp lsdev reserved epdir epnum mpsiz rs rs rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bit 31 chena: channel enable this field is set by the application and cleared by the otg host. 0: channel disabled 1: channel enabled bit 30 chdis: channel disable the application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete. the application must wait for the channel disabled interrupt before treating the channel as disabled. bit 29 oddfrm: odd frame this field is set (reset) by the application to indicate that the otg host must perform a transfer in an odd frame. this field is applicable for only periodic (isochronous and interrupt) transactions. 0: even (micro) frame 1: odd (micro) frame bits 28:22 dad: device address this field selects the specific device serving as the data source or sink. RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1117/1317 bits 21:20 mc: multi count (mc) / error count (ec) ? when the split enable bit (spliten) in th e host channel-x split control register (otg_hs_hcspltx) is reset (0), th is field indicates to the host the number of transactions that must be executed per micro-frame for this periodic endpoint. for nonperiodic transfers, this field specifies the number of packets to be fetched for this channel before the internal dma engine changes arbitration. 00: reserved this field yields undefined results 01: 1 transaction b10: 2 transactions to be issued for this endpoint per micro-frame 11: 3 transactions to be issued for this endpoint per micro-frame. ? when the spliten bit is set (1) in otg_hs_ hcspltx, this field indicates the number of immediate retries to be performed for a periodic split transaction on transaction errors. this field must be set to at least 01. bits 19:18 eptyp: endpoint type indicates the transfer type selected. 00: control 01: isochronous 10: bulk 11: interrupt bit 17 lsdev: low-speed device this field is set by the application to indicate that this channel is communicating to a low- speed device. bit 16 reserved bit 15 epdir: endpoint direction indicates whether the transaction is in or out. 0: out 1: in bits 14:11 epnum: endpoint number indicates the endpoint number on the device serving as the data source or sink. bits 10:0 mpsiz: maximum packet size indicates the maximum packet size of the associated endpoint. usb on-the-go high-speed (otg_hs) RM0033 1118/1317 doc id 15403 rev 3 otg_hs host channel-x split control register ( otg_hs_hcspltx ) (x = 0..11, where x = channel_number) address offset: 0x504 + (channel_number 0x20) reset value: 0x0000 0000 313029282726252423222120191817161514131211109876543210 spliten reserved complsplt xactpos hubaddr prtaddr rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bit 31 spliten: split enable the application sets this bit to indicate that this channel is enabled to perform split transactions. bits 30:17 reserved bit 16 complsplt: do complete split the application sets this bit to request the otg host to perform a complete split transaction. bits 15:14 xactpos: transaction position this field is used to determine whether to send all, first, middle, or last payloads with each out transaction. 11: all. this is the entire data payload of this transaction (which is less than or equal to 188 bytes) 10: begin. this is the first data payload of this transaction (which is larger than 188 bytes) 00: mid. this is the middle payload of this transaction (which is larger than 188 bytes) 01: end. this is the last payload of this transaction (which is larger than 188 bytes) bits 13:7 hubaddr: hub address this field holds the device address of the transaction translator?s hub. bits 6:0 prtaddr: port address this field is the port number of the recipient transaction translator. RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1119/1317 otg_hs host channel-x interrupt register (otg_hs_hcintx) (x = 0..11, where x = channel_number) address offset: 0x508 + (channel_number 0x20) reset value: 0x0000 0000 this register indicates the status of a channel with respect to usb- and ahb-related events. it is shown in figure 374 . the application must read this register when the host channels interrupt bit in the core interrupt register ( hcint bit in otg_hs_gintsts) is set. before the application can read this register, it must first read the host all channels interrupt (otg_hs_haint) register to get the exact channel number for the host channel-x interrupt register. the application must clear the appropriate bit in this register to clear the corresponding bits in the otg_hs_haint and otg_hs_gintsts registers. 313029282726252423222120191817161514131211109876543210 reserved dterr frmor bberr txerr nyet ack nak stall ahberr chh xfrc rc_ w1 rc_ w1 rc_ w1 rc_ w1 rc_ w1 rc_ w1 rc_ w1 rc_ w1 rc_ w1 rc_ w1 rc_ w1 bits 31:11 reserved bit 10 dterr: data toggle error bit 9 frmor: frame overrun bit 8 bberr: babble error bit 7 txerr: transaction error indicates one of the following errors occurred on the usb. crc check failure timeout bit stuff error false eop bit 6 nyet: response received interrupt bit 5 ack: ack response received/transmitted interrupt bit 4 nak: nak response received interrupt bit 3 stall: stall response received interrupt bit 2 ahberr : ahb error this error is generated only in internal dma mode when an ahb error occurs during an ahb read/write operation. the application can read the corresponding dma channel address register to get the error address. bit 1 chh: channel halted indicates the transfer completed abnormally either because of any usb transaction error or in response to disable request by the application. bit 0 xfrc: transfer completed transfer completed normally without any errors. usb on-the-go high-speed (otg_hs) RM0033 1120/1317 doc id 15403 rev 3 otg_hs host channel-x interrupt mask register (otg_hs_hcintmskx) (x = 0..11, where x = channel_number) address offset: 0x50c + (channel_number 0x20) reset value: 0x0000 0000 this register reflects the mask for each channel status described in the previous section. 313029282726252423222120191817161514131211109876543210 reserved dterrm frmorm bberrm txerrm nyet ackm nakm stallm ahberr chhm xfrcm rw rw rw rw rw rw rw rw rw rw rw bits 31:11 reserved bit 10 dterrm: data toggle error mask 0: masked interrupt 1: unmasked interrupt bit 9 frmorm: frame overrun mask 0: masked interrupt 1: unmasked interrupt bit 8 bberrm: babble error mask 0: masked interrupt 1: unmasked interrupt bit 7 txerrm: transaction error mask 0: masked interrupt 1: unmasked interrupt bit 6 nyet: response received interrupt mask 0: masked interrupt 1: unmasked interrupt bit 5 ackm: ack response received/transmitted interrupt mask 0: masked interrupt 1: unmasked interrupt bit 4 nakm: nak response received interrupt mask 0: masked interrupt 1: unmasked interrupt bit 3 stallm: stall response received interrupt mask 0: masked interrupt 1: unmasked interrupt RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1121/1317 otg_hs host channel-x transfer size register (otg_hs_hctsizx) (x = 0..11, where x = channel_number) address offset: 0x510 + (channel_number 0x20) reset value: 0x0000 0000 bit 2 ahberr: ahb error this is generated only in internal dma mode when there is an ahb error during ahb read/write. the application can read the corresp onding channel?s dma address register to get the error address. bit 1 chhm: channel halted mask 0: masked interrupt 1: unmasked interrupt bit 0 xfrcm: transfer completed mask 0: masked interrupt 1: unmasked interrupt 313029282726252423222120191817161514131211109876543210 reserved dpid pktcnt xfrsiz rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bit 31 doping: do ping this bit is used only for out transfers. setting this field to 1 directs the host to do ping protocol. note: do not set this bit for in transfers. if this bit is set for in transfers it disables the channel. bits 30:29 dpid: data pid the application programs this field with the type of pid to use for the initial transaction. the host maintains this field for the rest of the transfer. 00: data0 01: data2 10: data1 11: mdata (noncontrol)/setup (control) bits 28:19 pktcnt: packet count this field is programmed by the application wit h the expected number of packets to be transmitted (out) or received (in). the host decrements this count on every success ful transmission or reception of an out/in packet. once this count reaches zero, the application is interrupted to indicate normal completion. bits 18:0 xfrsiz: transfer size for an out, this field is the number of data bytes the host sends during the transfer. for an in, this field is the buffer size that the application has reserved for the transfer. the application is expected to program this field as an integer multiple of the maximum packet size for in transactions (periodic and nonperiodic). usb on-the-go high-speed (otg_hs) RM0033 1122/1317 doc id 15403 rev 3 otg_hs host channel-x dma address register (otg_hs_hcdmax) (x = 0..11, where x = channel_number) address offset: 0x514 + (channel_number 0x20) reset value: 0x0000 0000 30.12.4 device-mode registers otg_hs device configuration register (otg_hs_dcfg) address offset: 0x800 reset value: 0x0220 0000 this register configures the core in peripheral mode after power-on or after certain control commands or enumeration. do not make changes to this register after initial programming. 313029282726252423222120191817161514131211109876543210 dmaaddr rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:0 dmaaddr: dma address this field holds the start address in the ex ternal memory from which the data for the endpoint must be fetched or to which it must be stored. this register is incremented on every ahb transaction. 313029282726252423222120191817161514131211109876543210 reserved perschivl reserved reserved pfivl dad reserved nzlsohsk dspd rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:26 reserved bits 25:24 perschivl: periodic scheduling interval this field specifies the amount of time the in ternal dma engine must allocate for fetching periodic in endpoint data. based on the number of periodic endpoints, this value must be specified as 25, 50 or 75% of the (micro)frame. ? when any periodic endpoints are active, the internal dma engine allocates the specified amount of time in fetching periodic in endpoint data ? when no periodic endpoint is active, then the internal dma engine services nonperiodic endpoints, ignoring this field ? after the specified time within a (mic ro)frame, the dma switches to fetching nonperiodic endpoints 00: 25% of (micro)frame 01: 50% of (micro)frame 10: 75% of (micro)frame 11: reserved bits 23:13 reserved RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1123/1317 bits 12:11 pfivl: periodic (micro)frame interval indicates the time within a (micro) frame at wh ich the application must be notified using the end of periodic (micro) frame interrupt. this c an be used to determine if all the isochronous traffic for that frame is complete. 00: 80% of the frame interval 01: 85% of the frame interval 10: 90% of the frame interval 11: 95% of the frame interval bits 10:4 dad: device address the application must program this field after every setaddress control command. bit 3 reserved bit 2 nzlsohsk: nonzero-length status out handshake the application can use this field to select the handshake the core sends on receiving a nonzero-length data packet during the out transaction of a cont rol transfer?s status stage. 1: send a stall handshake on a nonzero-length status out transaction and do not send the received out packet to the application. 0: send the received out packet to the applic ation (zero-length or nonzero-length) and send a handshake based on the nak and stall bits for the endpoint in the device endpoint control register. bits 1:0 dspd: device speed indicates the speed at which the application requires the core to enumerate, or the maximum speed the application can support. however, the actual bus speed is determined only after the chirp sequence is completed, and is based on the speed of the usb host to which the core is connected. 00: high speed 01: reserved 10: reserved 11: full speed (usb 1.1 transceiver clock is 48 mhz) usb on-the-go high-speed (otg_hs) RM0033 1124/1317 doc id 15403 rev 3 otg_hs device control register (otg_hs_dctl) address offset: 0x804 reset value: 0x0000 0000 313029282726252423222120191817161514131211109876543210 reserved poprgdne cgonak sgonak cginak sginak tctl gonsts ginsts sdis rwusig rwwwwwrwrwrwr rrwrw bits 31:12 reserved bit 11 poprgdne: power-on programming done the application uses this bit to indicate th at register programming is completed after a wakeup from power down mode. bit 10 cgonak: clear global out nak a write to this field clears the global out nak. bit 9 sgonak: set global out nak a write to this field sets the global out nak. the application uses this bit to send a nak handshake on all out endpoints. the application must set the this bit only after making sure that the global out nak effective bit in the core interrupt register (gonakeff bit in otg_hs_gintsts) is cleared. bit 8 cginak: clear global in nak a write to this field clears the global in nak. bit 7 sginak: set global in nak a write to this field sets the global nonperiodi c in nak.the application uses this bit to send a nak handshake on all nonperiodic in endpoints. the application must set this bit only after ma king sure that the global in nak effective bit in the core interrupt r egister (ginakeff bit in ot g_hs_gintsts) is cleared. bits 6:4 tctl: test control 000: test mode disabled 001: test_j mode 010: test_k mode 011: test_se0_nak mode 100: test_packet mode 101: test_force_enable others: reserved bit 3 gonsts: global out nak status 0: a handshake is sent based on the fifo status and the nak and stall bit settings. 1: no data is written to the rxfifo, irresp ective of space availability. sends a nak handshake on all packets, except on setup transactions. all isochronous out packets are dropped. RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1125/1317 table 160 contains the minimum duration (according to device state) for which the soft disconnect (sdis) bit must be set for the usb host to detect a device disconnect. to accommodate clock jitter, it is recommended that the application add some extra delay to the specified minimum duration. bit 2 ginsts: global in nak status 0: a handshake is sent out based on the data availability in the transmit fifo. 1: a nak handshake is sent out on all nonperiodic in endpoints, irrespective of the data availability in the transmit fifo. bit 1 sdis: soft disconnect the application uses this bit to signal the usb otg core to perform a soft disconnect. as long as this bit is set, the host does not see that the device is connected, and the device does not receive signals on the usb. the core stays in the disconnected state until the application clears this bit. 0: normal operation. when this bit is cleared after a soft disconnect, the core generates a device connect event to the usb host. when the device is reconnected, the usb host restarts device enumeration. 1: the core generates a device disconnect event to the usb host. bit 0 rwusig: remote wakeup signaling when the application sets this bit, the core initiates remote signaling to wake up the usb host. the application must set this bit to inst ruct the core to exit the suspend state. as specified in the usb 2.0 specification, the applic ation must clear this bit 1 ms to 15 ms after setting it. table 160. minimum duration for soft disconnect operating speed device state minimum duration high speed not idle or suspended (performing transactions) 125 s full speed suspended 1 ms + 2.5 s full speed idle 2.5 s full speed not idle or suspended (performing transactions) 2.5 s usb on-the-go high-speed (otg_hs) RM0033 1126/1317 doc id 15403 rev 3 otg_hs device status register (otg_hs_dsts) address offset: 0x808 reset value: 0x0000 0010 this register indicates the status of the core with respect to usb-related events. it must be read on interrupts from the device all interrupts (otg_hs_daint) register. 313029282726252423222120191817161514131211109876543210 reserved fnsof reserved eerr enumspd suspsts rrrrrrrrrrrrrr rrrr bits 31:22 reserved bits 21:8 fnsof: frame number of the received sof bits 7:4 reserved bit 3 eerr: erratic error the core sets this bit to report any erratic errors. due to erratic errors, the otg_hs controller go es into suspended state and an interrupt is generated to the application with early suspend bit of the core interrupt register (esusp bit in otg_hs_gintsts). if the early suspend is asserted due to an erratic error, the application can only perform a soft disconnect recover. bits 2:1 enumspd: enumerated speed indicates the speed at which the otg_hs cont roller has come up after speed detection through a chirp sequence. 00: high speed 01: reserved 10: reserved 11: full speed (phy clock is running at 48 mhz) others: reserved bit 0 suspsts: suspend status in peripheral mode, this bit is set as long as a suspend condition is detected on the usb. the core enters the suspended state when there is no activity on the usb data lines for a period of 3 ms. the core comes out of the suspend: ? when there is an activity on the usb data lines ? when the application writes to the remote wakeup signaling bit in the device control register (rwusig bit in otg_hs_dctl). RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1127/1317 otg_hs device in endpoint common interrupt mask register (otg_hs_diepmsk) address offset: 0x810 reset value: 0x0000 0000 this register works with each of the device in endpoint interrupt (otg_hs_diepintx) registers for all endpoints to generate an interrupt per in endpoint. the in endpoint interrupt for a specific status in the otg_hs_diepintx register can be masked by writing to the corresponding bit in this register. status bits are masked by default. 313029282726252423222120191817161514131211109876543210 reserved bim txfurm reserved inepnem inepnmm ittxfemsk tom reserved epdm xfrcm rw rw rw rw rw rw rw rw bits 31:10 reserved bit 9 bim: bna interrupt mask 0: masked interrupt 1: unmasked interrupt bit 8 txfurm: fifo underrun mask 0: masked interrupt 1: unmasked interrupt bit 7 reserved bit 6 inepnem: in endpoint nak effective mask 0: masked interrupt 1: unmasked interrupt bit 5 inepnmm: in token received with ep mismatch mask 0: masked interrupt 1: unmasked interrupt bit 4 ittxfemsk: in token received when txfifo empty mask 0: masked interrupt 1: unmasked interrupt bit 3 tom: timeout condition mask (nonisochronous endpoints) 0: masked interrupt 1: unmasked interrupt bit 2 reserved bit 1 epdm: endpoint disabled interrupt mask 0: masked interrupt 1: unmasked interrupt bit 0 xfrcm: transfer completed interrupt mask 0: masked interrupt 1: unmasked interrupt usb on-the-go high-speed (otg_hs) RM0033 1128/1317 doc id 15403 rev 3 otg_hs device out endpoint common interrupt mask register (otg_hs_doepmsk) address offset: 0x814 reset value: 0x0000 0000 this register works with each of the device out endpoint interrupt (otg_hs_doepintx) registers for all endpoints to generate an interrupt per out endpoint. the out endpoint interrupt for a specific status in the otg_hs _doepintx register can be masked by writing into the corresponding bit in this register. status bits are masked by default. 313029282726252423222120191817161514131211109876543210 reserved boim opem reserved b2bstup reserved otepdm stupm reserved epdm xfrcm rw rw rw rw rw rw rw bits 31:10 reserved bit 9 boim: bna interrupt mask 0: masked interrupt 1: unmasked interrupt bit 8 opem: out packet error mask 0: masked interrupt 1: unmasked interrupt bit 7 reserved bit 6 b2bstup: back-to-back setup packets received mask applies to control out endpoints only. 0: masked interrupt 1: unmasked interrupt bit 5 reserved bit 4 otepdm: out token received when endpoint disabled mask applies to control out endpoints only. 0: masked interrupt 1: unmasked interrupt bit 3 stupm: setup phase done mask applies to control endpoints only. 0: masked interrupt 1: unmasked interrupt bit 2 reserved bit 1 epdm: endpoint disabled interrupt mask 0: masked interrupt 1: unmasked interrupt bit 0 xfrcm: transfer completed interrupt mask 0: masked interrupt 1: unmasked interrupt RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1129/1317 otg_hs device all endpoints interrupt register (otg_hs_daint) address offset: 0x818 reset value: 0x0000 0000 when a significant event occurs on an endpoint, a device all endpoints interrupt register interrupts the application using the device out endpoints interrupt bit or device in endpoints interrupt bit of the core interrupt register (oepint or iepint in otg_hs_gintsts, respectively). there is one interrupt bit per endpoint, up to a maximum of 16 bits for out endpoints and 16 bits for in endpoints. for a bidirectional endpoint, the corresponding in and out interrupt bits are used. bits in this register are set and cleared when the application sets and clears bits in the corresponding device endpoint-x interrupt register (otg_hs_diepintx/otg_hs_doepintx). otg_hs all endpoints interrupt mask register (otg_hs_daintmsk) address offset: 0x81c reset value: 0x0000 0000 the device endpoint interrupt mask register works with the device endpoint interrupt register to interrupt the application when an event occurs on a device endpoint. however, the device all endpoints interrupt (otg_hs_ daint) register bit correspondi ng to that interrupt is still set. 313029282726252423222120191817161514131211109876543210 oepint iepint rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr bits 31:16 oepint: out endpoint interrupt bits one bit per out endpoint: bit 16 for out endpoint 0, bit 31 for out endpoint 15 bits 15:0 iepint: in endpoint interrupt bits one bit per in endpoint: bit 0 for in endpoint 0, bit 15 for endpoint 15 313029282726252423222120191817161514131211109876543210 oepm iepm rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:16 oepm: out ep interrupt mask bits one per out endpoint: bit 16 for out ep 0, bit 18 for out ep 3 0: masked interrupt 1: unmasked interrupt bits 15:0 iepm: in ep interrupt mask bits one bit per in endpoint: bit 0 for in ep 0, bit 3 for in ep 3 0: masked interrupt 1: unmasked interrupt usb on-the-go high-speed (otg_hs) RM0033 1130/1317 doc id 15403 rev 3 otg_hs device v bus discharge time register (otg_hs_dvbusdis) address offset: 0x0828 reset value: 0x0000 17d7 this register specifies the v bus discharge time after v bus pulsing during srp. otg_hs device v bus pulsing time register (otg_hs_dvbuspulse) address offset: 0x082c reset value: 0x0000 05b8 this register specifies the v bus pulsing time during srp. 313029282726252423222120191817161514131211109876543210 reserved vbusdt rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:16 reserved bits 15:0 vbusdt: device v bus discharge time specifies the v bus discharge time after v bus pulsing during srp. this value equals: v bus discharge time in phy clocks / 1 024 depending on your v bus load, this value may need adjusting. 313029282726252423222120191817161514131211109876543210 reserved dvbusp rw rw rw rw rw rw rw rw rw rw rw rw bits 31:12 reserved bits 11:0 dvbusp: device v bus pulsing time specifies the v bus pulsing time during srp. this value equals: v bus pulsing time in phy clocks / 1 024 RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1131/1317 otg_hs device threshold control register (otg_hs_dthrctl) address offset: 0x0830 reset value: 0x0000 0000 313029282726252423222120191817161514131211109876543210 reserved arpen reserved rxthrlen rxthren reserved txthrlen isothren nonisothren rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:28 reserved bit 27 arpen: arbiter parking enable this bit controls internal dma arbiter parking for in endpoints. when thresholding is enabled and this bit is set to one, then the arbiter par ks on the in endpoint for which there is a token received on the usb. this is done to avoid getting into underrun conditions. by default parking is enabled. bit 26 reserved bits 25: 17 rxthrlen: receive threshold length this field specifies the receive thresholding size in dwords. this field also specifies the amount of data received on the usb before the core can start transmitting on the ahb. the threshold length has to be at least eight dwords. the recommended value for rxthrlen is to be the same as the programmed ahb burst length (hbstlen bit in otg_hs_gahbcfg). bit 16 rxthren: receive threshold enable when this bit is set, the core enables thresholding in the receive direction. bits 15: 11 reserved bits 10:2 txthrlen: transmit threshold length this field specifies the transmit thresholding size in dwords. this field specifies the amount of data in bytes to be in the corresponding endpoint transmit fifo, before the core can start transmitting on the usb. the thresh old length has to be at least eight dwords. this field controls both isochronous and nonisochronous in endpoint thresholds. the recommended value for txthrlen is to be the same as the programmed ahb burst length (hbstlen bit in otg_hs_gahbcfg). bit 1 isothren: iso in endpoint threshold enable when this bit is set, the core enables thresholding for isochronous in endpoints. bit 0 nonisothren: nonisochronous in endpoints threshold enable when this bit is set, the core enables thresholding for nonisochronous in endpoints. usb on-the-go high-speed (otg_hs) RM0033 1132/1317 doc id 15403 rev 3 otg_hs device in endpoint fifo empty interrupt mask register: (otg_hs_diepempmsk) address offset: 0x834 reset value: 0x0000 0000 this register is used to control the in endpoint fifo empty interrupt generation (txfe_otg_hs_diepintx). otg_hs device each endpoint interrupt register (otg_hs_deachint) address offset: 0x0838 reset value: 0x0000 0000 there is one interrupt bit for endpoint 1 in and one interrupt bit for endpoint 1 out. 313029282726252423222120191817161514131211109876543210 reserved ineptxfem rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:16 reserved bits 15:0 ineptxfem: in ep tx fifo empty interrupt mask bits these bits act as mask bits for otg_hs_diepintx. txfe interrupt one bit per in endpoint: bit 0 for in endpoint 0, bit 15 for in endpoint 15 0: masked interrupt 1: unmasked interrupt 313029282726252423222120191817161514131211109876543210 reserved oep1int reserved iep1int reserved bits 31:18 reserved bit 17 oep1int: out endpoint 1 interrupt bit bits 16:2 reserved bit 1 iep1int: in endpoint 1interrupt bit bit 0 reserved RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1133/1317 otg_hs device each endpoint interrupt register mask (otg_hs_deachintmsk) address offset: 0x083c reset value: 0x0000 0000 there is one interrupt bit for endpoint 1 in and one interrupt bit for endpoint 1 out. otg_hs device each in endpoint-1 interrupt register (otg_hs_diepeachmsk1) address offset: 0x840 reset value: 0x0000 0000 313029282726252423222120191817161514131211109876543210 reserved oep1intm reserved iep1intm reserved bits 31:18 reserved bit 17 oep1intm: out endpoint 1 interrupt mask bit bits 16:2 reserved bit 1 iep1intm: in endpoint 1 interrupt mask bit bit 0 reserved 313029282726252423222120191817161514131211109876543210 reserved nakm reserved bim txfurm reserved inepnem inepnmm ittxfemsk tom reserved epdm xfrcm rw rw rw rw rw rw rw rw rw bits 31:14 reserved bit 13 nakm: nak interrupt mask 0: masked interrupt 1: unmasked interrupt bit 12:10 reserved bit 9 bim: bna interrupt mask 0: masked interrupt 1: unmasked interrupt bit 8 txfurm: fifo underrun mask 0: masked interrupt 1: unmasked interrupt bit 7 reserved usb on-the-go high-speed (otg_hs) RM0033 1134/1317 doc id 15403 rev 3 otg_hs device each out endpoint-1 interrupt register (otg_hs_doepeachmsk1) address offset: 0x880 reset value: 0x0000 0000 bit 6 inepnem: in endpoint nak effective mask 0: masked interrupt 1: unmasked interrupt bit 5 inepnmm: in token received with ep mismatch mask 0: masked interrupt 1: unmasked interrupt bit 4 ittxfemsk: in token received when txfifo empty mask 0: masked interrupt 1: unmasked interrupt bit 3 tom: timeout condition mask (nonisochronous endpoints) 0: masked interrupt 1: unmasked interrupt bit 2 reserved bit 1 epdm: endpoint disabled interrupt mask 0: masked interrupt 1: unmasked interrupt bit 0 xfrcm: transfer completed interrupt mask 0: masked interrupt 1: unmasked interrupt 313029282726252423222120191817161514131211109876543210 reserved nyetm nakm berrm reserved bim txfurm reserved inepnem inepnmm ittxfemsk tom reserved epdm xfrcm rw rw rw rw rw rw rw rw rw rw rw bits 31:15 reserved bit 14 nyetm : nyet interrupt mask 0: masked interrupt 1: unmasked interrupt bit 13 nakm: nak interrupt mask 0: masked interrupt 1: unmasked interrupt bit 12 berrm: bubble error interrupt mask 0: masked interrupt 1: unmasked interrupt bit 11:10 reserved RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1135/1317 otg device endpoint-x control register (otg_hs_diepctlx) (x = 0..7, where x = endpoint_number) address offset: 0x900 + (endpoint_number 0x20) reset value: 0x0000 0000 the application uses this register to control th e behavior of each logical endpoint other than endpoint 0. bit 9 bim: bna interrupt mask 0: masked interrupt 1: unmasked interrupt bit 8 opem: out packet error mask 0: masked interrupt 1: unmasked interrupt bits 7:3 reserved bit 2 ahberrm: ahb error mask 0: masked interrupt 1: unmasked interrupt bit 1 epdm: endpoint disabled interrupt mask 0: masked interrupt 1: unmasked interrupt bit 0 xfrcm: transfer completed interrupt mask 0: masked interrupt 1: unmasked interrupt 313029282726252423222120191817161514131211109876543210 epena epdis soddfrm sd0pid/sevnfrm snak cnak txfnum stall reserved eptyp naksts eonum/dpid usbaep reserved mpsiz rsrswwwwrwrwrwrw rw/ rs rw rw r r rw rw rw rw rw rw rw rw rw rw rw rw bit 31 epena: endpoint enable the application sets this bit to start transmitting data on an endpoint. the core clears this bit before setting any of the following interrupts on this endpoint: ? setup phase done ? endpoint disabled ? transfer completed bit 30 epdis: endpoint disable the application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. the app lication must wait for the endpoint disabled interrupt before treating the endpoint as disabled. the core clears this bit before setting the endpoint disabled interrupt. the application must set this bit only if endpoint enable is already set for this endpoint. usb on-the-go high-speed (otg_hs) RM0033 1136/1317 doc id 15403 rev 3 bit 29 soddfrm: set odd frame applies to isochronous in and out endpoints only. writing to this field sets the even /odd frame (eonum) field to odd frame. bit 28 sd0pid: set data0 pid applies to interrupt/bulk in endpoints only. writing to this field sets the endpoint data pid (dpid) field in this register to data0. sevnfrm: set even frame applies to isochronous in endpoints only. writing to this field sets the even/odd frame (eonum) field to even frame. bit 27 snak: set nak a write to this bit sets the nak bit for the endpoint. using this bit, the application can control the transmission of nak handshakes on an endpoint. the core can also set this bit for out endpoints on a transfer completed interrupt, or after a setup is received on the endpoint. bit 26 cnak: clear nak a write to this bit clears the nak bit for the endpoint. bits 25:22 txfnum: txfifo number these bits specify the fifo nu mber associated with this endpoint. each active in endpoint must be programmed to a separate fifo number. this field is valid only for in endpoints. bit 21 stall: stall handshake applies to noncontrol, nonisochronous in endpoints only (access type is rw). the application sets this bit to stall all tokens from the usb host to this endpoint. if a nak bit, global in nak, or global out nak is set along with this bit, the stall bit takes priority. only the application can clear this bit, never the core. applies to control endpoints only (access type is rs). the application can only set this bit, and the core clears it, when a setup token is received for this endpoint. if a nak bit, global in nak, or global out nak is set along with this bit, the stall bit takes priority. irrespective of this bit?s setting, the core always responds to setup data packets with an ack handshake. bit 20 reserved bits 19:18 eptyp: endpoint type this is the transfer type supported by this logical endpoint. 00: control 01: isochronous 10: bulk 11: interrupt RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1137/1317 bit 17 naksts: nak status it indicates the following: 0: the core is transmitting nonnak handshakes based on the fifo status. 1: the core is transmitting nak handshakes on this endpoint. when either the application or the core sets this bit: for nonisochronous in endpoints: the core stops transmitting any data on an in endpoint, even if there are data av ailable in the txfifo. for isochronous in endpoints: the core sends out a zero-length data packet, even if there are data available in the txfifo. irrespective of this bit?s sett ing, the core always responds to setup data packets with an ack handshake. bit 16 eonum: even/odd frame applies to isochronous in endpoints only. indicates the frame number in which the core transmits/receives isochronous data for this endpoint. the application must program the even /odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the sevnfrm and soddfrm fields in this register. 0: even frame 1: odd frame dpid: endpoint data pid applies to interrupt/bulk in endpoints only. contains the pid of the packet to be received or transmitted on this endpoint. the application must program the pid of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. the ap plication uses the sd0pid register field to program either data0 or data1 pid. 0: data0 1: data1 bit 15 usbaep: usb active endpoint indicates whether this endpoint is active in t he current configuration and interface. the core clears this bit for all endpoints (other than ep 0) after detecting a usb reset. after receiving the setconfiguration and setinterface comman ds, the application must program endpoint registers accordingly and set this bit. bits 14:11 reserved bits 10:0 mpsiz: maximum packet size the application must program this field with the maximum packet size for the current logical endpoint. this value is in bytes. usb on-the-go high-speed (otg_hs) RM0033 1138/1317 doc id 15403 rev 3 otg_hs device control out endpoint 0 control register (otg_hs_doepctl0) address offset: 0xb00 reset value: 0x0000 8000 this section describes the device control out endpoint 0 control register. nonzero control endpoints use registers for endpoints 1?15. 313029282726252423222120191817161514131211109876543210 epena epdis reserved snak cnak reserved stall snpm eptyp naksts reserved usbaep reserved mpsiz w r w w rs rw r r r r r r bit 31 epena: endpoint enable the application sets this bit to start transmitting data on endpoint 0. the core clears this bit before setting any of the following interrupts on this endpoint: ? setup phase done ? endpoint disabled ? transfer completed bit 30 epdis: endpoint disable the application cannot disable control out endpoint 0. bits 29:28 reserved bit 27 snak: set nak a write to this bit sets the nak bit for the endpoint. using this bit, the application can control the transmission of nak handshakes on an endpoint. the core can also set this bit on a transfer completed interrupt, or after a setup is received on the endpoint. bit 26 cnak: clear nak a write to this bit clears the nak bit for the endpoint. bits 25:22 reserved bit 21 stall: stall handshake the application can only set this bit, and the core clears it, when a setup token is received for this endpoint. if a nak bit or global out nak is set along with this bit, the stall bit takes priority. irrespective of this bit?s setting, the core always responds to setup data packets with an ack handshake. bit 20 snpm: snoop mode this bit configures the endpoint to snoop mode . in snoop mode, the core does not check the correctness of out packets before transferring them to application memory. bits 19:18 eptyp: endpoint type hardcoded to 2?b00 for control. RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1139/1317 otg_hs device endpoint-x control register (otg_hs_doepctlx) (x = 1..3, where x = endpoint_number) address offset for out endpoints: 0xb00 + (endpoint_number 0x20) reset value: 0x0000 0000 the application uses this register to control th e behavior of each logical endpoint other than endpoint 0. bit 17 naksts: nak status indicates the following: 0: the core is transmitting nonnak hand shakes based on the fifo status. 1: the core is transmitting nak handshakes on this endpoint. when either the application or the core sets this bit, the core stops receiv ing data, even if there is space in the rxfifo to accommodate the inco ming packet. irrespective of this bit?s setting, the core always responds to setup data packets with an ack handshake. bit 16 reserved bit 15 usbaep: usb active endpoint this bit is always set to 1, indicating that a control endpoint 0 is always active in all configurations and interfaces. bits 14:2 reserved bits 1:0 mpsiz: maximum packet size the maximum packet size for control out endpoint 0 is the same as what is programmed in control in endpoint 0. 00: 64 bytes 01: 32 bytes 10: 16 bytes 11: 8 bytes 313029282726252423222120191817161514131211109876543210 epena epdis soddfrm sd0pid/sevnfrm snak cnak reserved stall snpm eptyp naksts eonum/dpid usbaep reserved mpsiz rsrswwww rw/ rs rw rw rw r r rw rw rw rw rw rw rw rw rw rw rw rw bit 31 epena: endpoint enable applies to in and out endpoints. the application sets this bit to start transmitting data on an endpoint. the core clears this bit before setting any of the following interrupts on this endpoint: ? setup phase done ? endpoint disabled ? transfer completed usb on-the-go high-speed (otg_hs) RM0033 1140/1317 doc id 15403 rev 3 bit 30 epdis: endpoint disable the application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. the application must wait for the endpoint disabled interrupt before treating the endpoint as disabled. the core clears this bit before setting the endpoint disabled interrupt. the application must set this bit only if endpoint enable is already set for this endpoint. bit 29 soddfrm: set odd frame applies to isochronous out endpoints only. writing to this field sets the even /odd frame (eonum) field to odd frame. bit 28 sd0pid: set data0 pid applies to interrupt/bulk out endpoints only. writing to this field sets the endpoint data pid (dpid) field in this register to data0. sevnfrm: set even frame applies to isochronous out endpoints only. writing to this field sets the even/odd frame (eonum) field to even frame. bit 27 snak: set nak a write to this bit sets the nak bit for the endpoint. using this bit, the application can control the transmission of nak handshakes on an endpoint. the core can also set this bit for out endpoints on a transfer completed interrupt, or after a setup is received on the endpoint. bit 26 cnak: clear nak a write to this bit clears the nak bit for the endpoint. bits 25:22 reserved bit 21 stall: stall handshake applies to noncontrol, nonisochronous out endpoints only (access type is rw). the application sets this bit to stall all tokens from the usb host to this endpoint. if a nak bit, global in nak, or global out nak is set along with this bit, the stall bit takes priority. only the application can clear this bit, never the core. applies to control endpoints only (access type is rs). the application can only set this bit, and the core clears it, when a setup token is received for this endpoint. if a nak bit, global in nak, or global out nak is set along with this bit, the stall bit takes priority. irrespective of this bit?s setting, the core always responds to setup data packets with an ack handshake. bit 20 snpm: snoop mode this bit configures the endpoint to snoop mode . in snoop mode, the core does not check the correctness of out packets before transferring them to application memory. bits 19:18 eptyp: endpoint type this is the transfer type supported by this logical endpoint. 00: control 01: isochronous 10: bulk 11: interrupt RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1141/1317 bit 17 naksts: nak status indicates the following: 0: the core is transmitting nonnak handshakes based on the fifo status. 1: the core is transmitting nak handshakes on this endpoint. when either the application or the core sets this bit: the core stops receiving any data on an out endpoint, even if there is space in the rxfifo to accommodat e the incoming packet. irrespective of this bit?s setting, the core always responds to setup data packets with an ack handshake. bit 16 eonum: even/odd frame applies to isochronous in and out endpoints only. indicates the frame number in which the core transmits/receives isochronous data for this endpoint. the application must program the even/ odd frame number in which it intends to transmit/receive isochronous data for this endpoint using the sevnfrm and soddfrm fields in this register. 0: even frame 1: odd frame dpid: endpoint data pid applies to interrupt/bulk out endpoints only. contains the pid of the packet to be received or transmitted on this endpoint. the application must program the pid of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. the application uses the sd0pid register field to program either data0 or data1 pid. 0: data0 1: data1 bit 15 usbaep: usb active endpoint indicates whether this endpoint is active in t he current configuration and interface. the core clears this bit for all endpoints (other than ep 0) after detecting a usb reset. after receiving the setconfiguration and setinterface comman ds, the application must program endpoint registers accordingly and set this bit. bits 14:11 reserved bits 10:0 mpsiz: maximum packet size the application must program this field with the maximum packet size for the current logical endpoint. this value is in bytes. usb on-the-go high-speed (otg_hs) RM0033 1142/1317 doc id 15403 rev 3 otg_hs device endpoint-x interrupt register (otg_hs_diepintx) (x = 0..7, where x = endpoint_number) address offset: 0x908 + (endpoint_number 0x20) reset value: 0x0000 0080 this register indicates the status of an endpoint with respect to usb- and ahb-related events. it is shown in figure 374 . the application must read this register when the in endpoints interrupt bit of the core interrupt register (iepint in otg_hs_gintsts) is set. before the application can read this register, it must first read the device all endpoints interrupt (otg_hs_daint) register to get the exact endpoint number for the device endpoint-x interrupt register. the application must clear the appropriate bit in this register to clear the corresponding bits in the otg_hs_daint and otg_hs_gintsts registers. 313029282726252423222120191817161514131211109876543210 reserved nak berr pktdrpsts reserved bna txfifoudrn txfe inepne reserved ittxfe toc reserved epdisd xfrc r rc_ w1 /rw rc_ w1 rc_ w1 rc_ w1 rc_ w1 bits 31:14 reserved bit 13 nak: nak interrupt the core generates this interrupt when a nak is transmitted or received by the device. in case of isochronous in endpoints the interrupt gets generated when a zero length packet is transmitted due to unavailability of data in the tx fifo. bit 12 berr: babble error interrupt bit 11 pktdrpsts: packet dropped status this bit indicates to the application that an isoc out packet has been dropped. this bit does not have an associated mask bit and does not generate an interrupt. bit10 reserved bit 9 bna: buffer not available interrupt the core generates this interrupt when the descriptor accessed is not ready for the core to process, such as host busy or dma done. bit 8 txfifoudrn : transmit fifo underrun (txfifoundrn) the core generates this interrupt when it detects a transmit fifo underrun condition for this endpoint. dependency : this interrupt is valid only when thresholding is enabled bit 7 txfe: transmit fifo empty this interrupt is asserted when the txfifo for this endpoint is either half or completely empty. the half or completely empty status is determined by the txfifo empty level bit in the core ahb configuration register (txfelvl bit in otg_hs_gahbcfg). RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1143/1317 bit 6 inepne: in endpoint nak effective this bit can be cleared when the application clears the in endpoint nak by writing to the cnak bit in otg_hs_diepctlx. this interrupt indicates that the core has sa mpled the nak bit set (either by the application or by the core). the interrupt indicates that the in endpoint nak bit set by the application has taken effect in the core. this interrupt does not guarantee that a nak handshake is sent on the usb. a stall bit takes priority over a nak bit. bit 5 reserved bit 4 ittxfe: in token received when txfifo is empty applies to nonperiodic in endpoints only. indicates that an in token was received when the associated txfifo (periodic/nonperiodic) was empty. this interrupt is asserted on the endpoint for which the in token was received. bit 3 toc: timeout condition applies only to control in endpoints. indicates that the core has detected a timeout condition on the usb for the last in token on this endpoint. bit 2 reserved bit 1 epdisd: endpoint disabled interrupt this bit indicates that the endpoint is disabled per the application?s request. bit 0 xfrc: transfer completed interrupt this field indicates that the programmed transfer is complete on the ahb as well as on the usb, for this endpoint. usb on-the-go high-speed (otg_hs) RM0033 1144/1317 doc id 15403 rev 3 otg_hs device endpoint-x interrupt register (otg_hs_doepintx) (x = 0..7, where x = endpoint_number) address offset: 0xb08 + (endpoint_number 0x20) reset value: 0x0000 0080 this register indicates the status of an endpoint with respect to usb- and ahb-related events. it is shown in figure 374 . the application must read this register when the out endpoints interrupt bit of the core interrupt register (oepint bit in otg_hs_gintsts) is set. before the application can read this register, it must first read the device all endpoints interrupt (otg_hs_daint) register to get the exact endpoint number for the device endpoint-x interrupt register. the application must clear the appropriate bit in this register to clear the corresponding bits in the otg_hs_daint and otg_hs_gintsts registers. 313029282726252423222120191817161514131211109876543210 reserved nyet reserved b2bstup reserved otepdis stup reserved epdisd xfrc rc_ w1 /rw rc_ w1 rc_ w1 rc_ w1 rc_ w1 bits 31:15 reserved bit 14 nyet: nyet interrupt the core generates this interrupt w hen a nyet response is transmitted for a nonisochronous out endpoint. bits 13:7 reserved bit 6 b2bstup: back-to-back setup packets received applies to control out endpoint only. this bit indicates that the core has receiv ed more than three back-to-back setup packets for this particular endpoint. bit 5 reserved bit 4 otepdis: out token received when endpoint disabled applies only to control out endpoint. indicates that an out token was received when the endpoint was not yet enabled. this interrupt is asserted on the endpoint for which the out token was received. bit 3 stup: setup phase done applies to control out endpoints only. indicates that the setup phase for the contro l endpoint is complete and no more back-to- back setup packets were received for the current control transfer. on this interrupt, the application can decode the received setup data packet. bit 2 reserved bit 1 epdisd: endpoint disabled interrupt this bit indicates that the endpoint is disabled per the application?s request. bit 0 xfrc: transfer completed interrupt this field indicates that the programmed transfer is complete on the ahb as well as on the usb, for this endpoint. RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1145/1317 otg_hs device in endpoint 0 transfer size register (otg_hs_dieptsiz0) address offset: 0x910 reset value: 0x0000 0000 the application must modify this register before enabling endpoint 0. once endpoint 0 is enabled using the endpoint enable bit in the device control endpoint 0 control registers (epena in otg_hs_diepctl0), the core modifies this register. the application can only read this register once the core has cleared the endpoint enable bit. nonzero endpoints use the registers for endpoints 1?15. 313029282726252423222120191817161514131211109876543210 reserved pktcnt reserved xfrsiz rw rw rw rw rw rw rw rw rw bits 31:21 reserved bits 20:19 pktcnt: packet count indicates the total number of usb packets that constitute the transfer size amount of data for endpoint 0. this field is decremented every time a packet (m aximum size or short packet) is read from the txfifo. bits 18:7 reserved bits 6:0 xfrsiz: transfer size indicates the transfer size in bytes for endpoint 0. the core interrupts the application only after it has exhausted the transfer size amount of data. the transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. the core decrements this field every time a packet from the external memory is written to the txfifo. usb on-the-go high-speed (otg_hs) RM0033 1146/1317 doc id 15403 rev 3 otg_hs device out endpoint 0 transfer size register (otg_hs_doeptsiz0) address offset: 0xb10 reset value: 0x0000 0000 the application must modify this register before enabling endpoint 0. once endpoint 0 is enabled using the endpoint enable bit in the device control endpoint 0 control registers (epena bit in otg_hs_doepctl0), the core modifies this register. the application can only read this register once the core has cleared the endpoint enable bit. nonzero endpoints use the registers for endpoints 1?15. 313029282726252423222120191817161514131211109876543210 reserved stupc nt reserved pktcnt reserved xfrsiz rw rw rw rw rw rw rw rw rw rw bit 31 reserved bits 30:29 stupcnt: setup packet count this field specifies the number of back-to-back setup data packets the endpoint can receive. 01: 1 packet 10: 2 packets 11: 3 packets bits 28:20 reserved bit 19 pktcnt: packet count this field is decremented to zero afte r a packet is written into the rxfifo. bits 18:7 reserved bits 6:0 xfrsiz: transfer size indicates the transfer size in bytes for endpoint 0. the core interrupts the application only after it has exhausted the transfer size amount of data. the transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. the core decrements this field every time a packe t is read from the rxfi fo and written to the external memory. RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1147/1317 otg_hs device endpoint-x transfer size register (otg_hs_dieptsizx) (x = 1..3, where x = endpoint_number) address offset: 0x910 + (endpoint_number 0x20) reset value: 0x0000 0000 the application must modify this register before enabling the endpoint. once the endpoint is enabled using the endpoint enable bit in the device endpoint-x control registers (epena bit in otg_hs_diepctlx), the core modifies this register. the application can only read this register once the core has cleared the endpoint enable bit. 313029282726252423222120191817161514131211109876543210 reserved mcnt pktcnt xfrsiz rw/ r/r w rw/ r/r w rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bit 31 reserved bits 30:29 mcnt: multi count for periodic in endpoints, this field indicates the number of packets that must be transmitted per frame on the usb. the core uses this field to calculate the data pid for isochronous in endpoints. 01: 1 packet 10: 2 packets 11: 3 packets bit 28:19 pktcnt: packet count indicates the total number of usb packets that constitute the transfer size amount of data for this endpoint. this field is decremented every time a packet (maximum size or short packet) is read from the txfifo. bits 18:0 xfrsiz: transfer size this field contains the transfer size in bytes for the current endpoint. the core only interrupts the application after it has exhausted the transfer si ze amount of data. the transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. the core decrements this field every time a packet from the external memory is written to the txfifo. usb on-the-go high-speed (otg_hs) RM0033 1148/1317 doc id 15403 rev 3 otg_hs device in endpoint transmit fifo status register (otg_hs_dtxfstsx) (x = 0..5, where x = endpoint_number) address offset for in endpoints: 0x918 + (endpoint_number 0x20) this read-only register contains the free space information for the device in endpoint txfifo. otg_hs device endpoint-x transfer size register (otg_hs_doeptsizx) (x = 1..5, where x = endpoint_number) address offset: 0xb10 + (endpoint_number 0x20) reset value: 0x0000 0000 the application must modify this register before enabling the endpoint. once the endpoint is enabled using endpoint enable bit of the devi ce endpoint-x control re gisters (epena bit in otg_hs_doepctlx), the core modifies this register. the application can only read this register once the core has cleared the endpoint enable bit. 313029282726252423222120191817161514131211109876543210 reserved ineptfsav rrrrrrrrrrrrrrrr 31:16 reserved 15:0 ineptfsav: in endpoint txfifo space avail () indicates the amount of free space available in the endpoint txfifo. values are in terms of 32-bit words: 0x0: endpoint txfifo is full 0x1: 1 word available 0x2: 2 words available 0xn: n words available (0 < n < 512) others: reserved 3130 29282726252423222120191817161514131211109876543210 reserved rxdpid/s tupcnt pktcnt xfrsiz rw/r/ rw rw/r/ rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bit 31 reserved bits 30:29 rxdpid: received data pid applies to isochronous out endpoints only. this is the data pid received in the last packet for this endpoint. 00: data0 01: data2 10: data1 11: mdata RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1149/1317 otg_hs device endpoint- x dma address register (otg_hs_diepdmax / otg_hs_doepdmax) (x = 1..5, where x = endpoint_number) address offset for in endpoints: 0x914 + (endpoint_number 0x20) reset value: 0xxxxx xxxx address offset for out endpoints: 0xb14 + (endpoint_number 0x20) reset value: 0xxxxx xxxx 30.12.5 otg_hs power and cl ock gating control register (otg_hs_pcgcctl) address offset: 0xe00 reset value: 0x0000 0000 this register is available in host and peripheral modes. stupcnt: setup packet count applies to control out endpoints only. this field specifies the number of back-to-ba ck setup data packets the endpoint can receive. 01: 1 packet 10: 2 packets 11: 3 packets bit 28:19 pktcnt: packet count indicates the total number of usb packets that constitute the transfer size amount of data for this endpoint. this field is decremented every time a packet (maximum size or short packet) is written to the rxfifo. bits 18:0 xfrsiz: transfer size this field contains the transfer size in bytes for the current endpoint. the core only interrupts the application after it has exhausted the transfer si ze amount of data. the transfer size can be set to the maximum packet size of the endpoint, to be interrupted at the end of each packet. the core decrements this field every time a pack et is read from the rxfifo and written to the external memory. 3130 29282726252423222120191817161514131211109876543210 dmaaddr bits 31:0 dmaaddr: dma address this bit holds the start address of the external memory for storing or fetching endpoint data. note: for control endpoints, this field stores control out data packets as well as setup transaction data packets. when more than three setup packets are received back-to- back, the setup data packet in the memory is overwritten. this register is incremented on every ahb transaction. the application can give only a dword-aligned address. usb on-the-go high-speed (otg_hs) RM0033 1150/1317 doc id 15403 rev 3 30.12.6 otg_hs register map the table below gives the usb otg register map and reset values. 3130 29282726252423222120191817161514131211109876543210 reserved physusp reserved gatehclk stppclk rw rw rw bit 31:5 reserved bit 4 physusp: phy suspended indicates that the phy has been suspended. this bit is updated once the phy is suspended after the application has set the stppclk bit (bit 0). bits 3:2 reserved bit 1 gatehclk: gate hclk the application sets this bit to gate hclk to modules other than the ahb slave and master and wakeup logic when the usb is suspended or the session is not valid. the application clears this bit when the usb is resumed or a new session starts. bit 0 stppclk: stop phy clock the application sets this bit to stop the phy clock when the usb is suspended, the session is not valid, or the device is disconnected . the application clears this bit when the usb is resumed or a new session starts. table 161. otg_hs register map and reset values offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x000 otg_hs_got gctl reserved bsvld asvld dbct cidsts reserved dhnpen hshnpen hnprq hngscs reserved srq srqscs reset value 0 0 0 1 0 0 0 0 0 0 0x004 otg_hs_got gint reserved dbcdne adtochg hngdet reserved hnsschg srsschg reserved sedet res. reset value 0 0 0 0 0 0 0x008 otg_hs_gah bcfg reserved ptxfelvl txfelvl reserved gint reset value 00 0 0x00c otg_hs_gus bcfg ctxpkt fdmod fhmod reserved ulpiipd ptci pcci tsdps ulpievbusi ulpievbusd ulpicsm ulpiar ulpifsls reserved phylpcs reserved trdt hnpcap srpcap reserved tocal reset value 000 000000000 0 001010 000 0x010 otg_hs_grs tctl ahbidl dmareq reserved txfnum txfflsh rxfflsh reserved fcrst hsrst csrst reset value 1 0 00000000000 RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1151/1317 0x014 otg_hs_gint sts wkuint srqint discint cidschg reserved ptxfe hcint hprtint reserved datafsusp ipxfr/incompisoout iisoixfr oepint iepint reserved eopf isoodrp enumdne usbrst usbsusp esusp reserved boutnakeff ginakeff nptxfe rxflvl sof otgint mmis cmod reset value 0000 1 00 00000 000000 00100000 0x018 otg_hs_gint msk wuim srqim discint cidschgm reserved ptxfem hcim prtim reserved fsuspm ipxfrm/iisooxfrm iisoixfrm oepint iepint epmism reserved eopfm isoodrpm enumdnem usbrst usbsuspm esuspm reserved gonakeffm ginakeffm nptxfem rxflvlm sofm otgint mmism reserved reset value 0000 000 000000 000000 0000000 0x01c otg_hs_grx stsr (host mode) reserved pktsts dpid bcnt chnum reset value 0000 000000000000000 otg_hs_grx stsr (peripheral mode) reserved frmnum pktsts dpid bcnt epnum reset value 0000000000000000000000000 0x020 otg_hs_grx stsp (host mode) reserved pktsts dpid bcnt chnum reset value 0000 000000000000000 otg_hs_grx stsp (peripheral mode) reserved frmnum pktsts dpid bcnt epnum reset value 0000000000000000000000000 0x024 otg_hs_grx fsiz reserved rxfd reset value 0000001000000000 0x028 otg_hs_gnp txfsiz (host mode) nptxfd nptxfsa reset value 00000000000000000000001000000000 otg_hs_gnp txfsiz (peripheral mode) tx0fd tx0fsa reset value 00000000000000000000001000000000 0x02c otg_hs_gnp txsts res. nptxqtop nptqxsav nptxfsav reset value 0000000000001000000001000000000 0x030 otg_hs_gi2c ctl bsydne rw reserved i2cdatse0 i2cdevadr reserved ack i2cen addr regaddr rwdata reset value 0 0 000 000000000 0x038 otg_hs_gcc fg reserved novbussens sofouten vbusbsen vbusasen .i2cpaden .pwrdwn reserved reset value 0 0 0 0 0 0 0x03c otg_hs_cid product_id reset value 00000000000000000001001000000000 table 161. otg_hs register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 usb on-the-go high-speed (otg_hs) RM0033 1152/1317 doc id 15403 rev 3 0x100 otg_hs_hptx fsiz ptxfd ptxsa reset value 00000111011010000001000000100100 0x104 otg_hs_diep txf1 ineptxfd ineptxsa reset value 00000010000000000000010000000000 0x108 otg_hs_diep txf2 ineptxfd ineptxsa reset value 00000010000000000000010000000000 0x10c otg_hs_diep txf3 ineptxfd ineptxsa reset value 00000010000000000000010000000000 0x110 otg_hs_diep txf4 ineptxfd ineptxsa reset value 00000010000000000000010000000000 0x400 otg_hs_hcf g reserved fslss fslspcs reset value 000 0x404 otg_hs_hfir reserved frivl reset value 1110101001100000 0x408 otg_hs_hfn um ftrem frnum reset value 00000000000000000011111111111111 0x410 otg_hs_hptx sts ptxqtop ptxqsav ptxfsavl reset value 0 0 0 0 0 0 0 0yyyyyyyyyyyyyyyyyyyyyyyy 0x414 otg_hs_hain t reserved haint reset value 0000000000000000 0x418 otg_hs_hain tmsk reserved haintm reset value 0000000000000000 0x440 otg_hs_hprt reserved pspd ptctl ppwr plsts reserved prst psusp pres pocchng poca penchng pena pcdet pcsts reset value 0000000000000000000 0x500 otg_hs_hcc har0 chena chdis oddfrm dad mc eptyp lsdev reserved epdir epnum mpsiz reset value 000000000000000 0000000000000000 0x520 otg_hs_hcc har1 chena chdis oddfrm dad mc eptyp lsdev reserved epdir epnum mpsiz reset value 000000000000000 0000000000000000 0x540 otg_hs_hcc har2 chena chdis oddfrm dad mc eptyp lsdev reserved epdir epnum mpsiz reset value 000000000000000 0000000000000000 0x560 otg_hs_hcc har3 chena chdis oddfrm dad mc eptyp lsdev reserved epdir epnum mpsiz reset value 000000000000000 0000000000000000 0x580 otg_hs_hcc har4 chena chdis oddfrm dad mc eptyp lsdev reserved epdir epnum mpsiz reset value 000000000000000 0000000000000000 0x5a0 otg_hs_hcc har5 chena chdis oddfrm dad mc eptyp lsdev reserved epdir epnum mpsiz reset value 000000000000000 0000000000000000 table 161. otg_hs register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1153/1317 0x5c0 otg_hs_hcc har6 chena chdis oddfrm dad mc eptyp lsdev reserved epdir epnum mpsiz reset value 000000000000000 0000000000000000 0x5e0 otg_hs_hcc har7 chena chdis oddfrm dad mc eptyp lsdev reserved epdir epnum mpsiz reset value 000000000000000 0000000000000000 0x600 otg_hs_hcc har8 chena chdis oddfrm dad mc eptyp lsdev reserved epdir epnum mpsiz reset value 000000000000000 0000000000000000 0x620 otg_hs_hcc har9 chena chdis oddfrm dad mc eptyp lsdev reserved epdir epnum mpsiz reset value 000000000000000 0000000000000000 0x640 otg_hs_hcc har10 chena chdis oddfrm dad mc eptyp lsdev reserved epdir epnum mpsiz reset value 000000000000000 0000000000000000 0x660 otg_hs_hcc har11 chena chdis oddfrm dad mc eptyp lsdev reserved epdir epnum mpsiz reset value 000000000000000 0000000000000000 0x504 otg_hs_hcs plt0 spliten reserved complsplt xactpos hubaddr prtaddr reset value 0 00000000000000000 0x508 otg_hs_hcin t0 reserved dterr frmor bberr txerr nyet ack nak stall ahberr chh xfrc reset value 00000000000 0x524 otg_hs_hcs pl1 spliten reserved complsplt xactpos hubaddr prtaddr reset value 0 00000000000000000 0x528 otg_hs_hcin t1 reserved dterr frmor bberr txerr nyet ack nak stall ahberr chh xfrc reset value 00000000000 0x544 otg_hs_hcs plt2 spliten reserved complsplt xactpos hubaddr prtaddr reset value 0 00000000000000000 0x548 otg_hs_hcin t2 reserved dterr frmor bberr txerr nyet ack nak stall ahberr chh xfrc reset value 00000000000 0x564 otg_hs_hcs plt3 spliten reserved complsplt xactpos hubaddr prtaddr reset value 0 00000000000000000 table 161. otg_hs register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 usb on-the-go high-speed (otg_hs) RM0033 1154/1317 doc id 15403 rev 3 0x568 otg_hs_hcin t3 reserved dterr frmor bberr txerr nyet ack nak stall ahberr chh xfrc reset value 00000000000 0x584 otg_hs_hcs plt4 spliten reserved complsplt xactpos hubaddr prtaddr reset value 0 00000000000000000 0x588 otg_hs_hcin t4 reserved dterr frmor bberr txerr nyet ack nak stall ahberr chh xfrc reset value 00000000000 0x5a4 otg_hs_hcs plt5 spliten reserved complsplt xactpos hubaddr prtaddr reset value 0 00000000000000000 0x5a8 otg_hs_hcin t5 reserved dterr frmor bberr txerr nyet ack nak stall ahberr chh xfrc reset value 00000000000 0x5c4 otg_hs_hcs plt6 spliten reserved complsplt xactpos hubaddr prtaddr reset value 0 00000000000000000 0x5c8 otg_hs_hcin t6 reserved dterr frmor bberr txerr nyet ack nak stall ahberr chh xfrc reset value 00000000000 0x5e4 otg_hs_hcs plt7 spliten reserved complsplt xactpos hubaddr prtaddr reset value 0 00000000000000000 0x5e8 otg_hs_hcin t7 reserved dterr frmor bberr txerr nyet ack nak stall ahberr chh xfrc reset value 00000000000 0x604 otg_hs_hcs plt8 spliten reserved complsplt xactpos hubaddr prtaddr reset value 0 00000000000000000 0x608 otg_hs_hcin t8 reserved dterr frmor bberr txerr nyet ack nak stall ahberr chh xfrc reset value 00000000000 0x624 otg_hs_hcs plt9 spliten reserved complsplt xactpos hubaddr prtaddr reset value 0 00000000000000000 table 161. otg_hs register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1155/1317 0x628 otg_hs_hcin t9 reserved dterr frmor bberr txerr nyet ack nak stall ahberr chh xfrc reset value 00000000000 0x644 otg_hs_hcs plt10 spliten reserved complsplt xactpos hubaddr prtaddr reset value 0 00000000000000000 0x648 otg_hs_hcin t10 reserved dterr frmor bberr txerr nyet ack nak stall ahberr chh xfrc reset value 00000000000 0x664 otg_hs_hcs plt11 spliten reserved complsplt xactpos hubaddr prtaddr reset value 0 00000000000000000 0x668 otg_hs_hcin t11 reserved dterr frmor bberr txerr nyet ack nak stall ahberr chh xfrc reset value 00000000000 0x50c otg_hs_hcin tmsk0 reserved dterrm frmorm bberrm txerrm nyet ackm nakm stallm chhm xfrcm reset value 00000000000 0x52c otg_hs_hcin tmsk1 reserved dterrm frmorm bberrm txerrm nyet ackm nakm stallm ahberr chhm xfrcm reset value 00000000000 0x54c otg_hs_hcin tmsk2 reserved dterrm frmorm bberrm txerrm nyet ackm nakm stallm ahberr chhm xfrcm reset value 00000000000 0x56c otg_hs_hcin tmsk3 reserved dterrm frmorm bberrm txerrm nyet ackm nakm stallm ahberr chhm xfrcm reset value 00000000000 0x58c otg_hs_hcin tmsk4 reserved dterrm frmorm bberrm txerrm nyet ackm nakm stallm ahberr chhm xfrcm reset value 00000000000 0x5ac otg_hs_hcin tmsk5 reserved dterrm frmorm bberrm txerrm nyet ackm nakm stallm ahberr chhm xfrcm reset value 00000000000 0x5cc otg_hs_hcin tmsk6 reserved dterrm frmorm bberrm txerrm nyet ackm nakm stallm ahberr chhm xfrcm reset value 00000000000 0x5ec otg_hs_hcin tmsk7 reserved dterrm frmorm bberrm txerrm nyet ackm nakm stallm ahberr chhm xfrcm reset value 00000000000 table 161. otg_hs register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 usb on-the-go high-speed (otg_hs) RM0033 1156/1317 doc id 15403 rev 3 0x60c otg_hs_hcin tmsk8 reserved dterrm frmorm bberrm txerrm nyet ackm nakm stallm ahberr chhm xfrcm reset value 00000000000 0x62c otg_hs_hcin tmsk9 reserved dterrm frmorm bberrm txerrm nyet ackm nakm stallm ahberr chhm xfrcm reset value 00000000000 0x64c otg_hs_hcin tmsk10 reserved dterrm frmorm bberrm txerrm nyet ackm nakm stallm ahberr chhm xfrcm reset value 00000000000 0x66c otg_hs_hcin tmsk11 reserved dterrm frmorm bberrm txerrm nyet ackm nakm stallm ahberr chhm xfrcm reset value 00000000000 0x510 otg_hs_hcts iz0 reserved dpid pktcnt xfrsiz reset value 0000000000000000000000000000000 0x530 otg_hs_hcts iz1 reserved dpid pktcnt xfrsiz reset value 0000000000000000000000000000000 0x550 otg_hs_hcts iz2 reserved dpid pktcnt xfrsiz reset value 0000000000000000000000000000000 0x570 otg_hs_hcts iz3 reserved dpid pktcnt xfrsiz reset value 0000000000000000000000000000000 0x590 otg_hs_hcts iz4 reserved dpid pktcnt xfrsiz reset value 0000000000000000000000000000000 0x5b0 otg_hs_hcts iz5 reserved dpid pktcnt xfrsiz reset value 0000000000000000000000000000000 0x5d0 otg_hs_hcts iz6 reserved dpid pktcnt xfrsiz reset value 0000000000000000000000000000000 0x5f0 otg_hs_hcts iz7 reserved dpid pktcnt xfrsiz reset value 0000000000000000000000000000000 0x610 otg_hs_hcts iz8 reserved dpid pktcnt xfrsiz reset value 0000000000000000000000000000000 0x630 otg_hs_hcts iz9 reserved dpid pktcnt xfrsiz reset value 0000000000000000000000000000000 0x650 otg_hs_hcts iz10 reserved dpid pktcnt xfrsiz reset value 0000000000000000000000000000000 0x670 otg_hs_hcts iz11 reserved dpid pktcnt xfrsiz reset value 0000000000000000000000000000000 0x514 otg_hs_hcd ma0 dmaaddr reset value 00000000000000000000000000000000 table 161. otg_hs register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1157/1317 0x524 otg_hs_hcd ma1 dmaaddr reset value 00000000000000000000000000000000 0x544 otg_hs_hcd ma2 dmaaddr reset value 00000000000000000000000000000000 0x564 otg_hs_hcd ma3 dmaaddr reset value 00000000000000000000000000000000 0x584 otg_hs_hcd ma4 dmaaddr reset value 00000000000000000000000000000000 0x5a4 otg_hs_hcd ma5 dmaaddr reset value 00000000000000000000000000000000 0x5c4 otg_hs_hcd ma6 dmaaddr reset value 00000000000000000000000000000000 0x5e4 otg_hs_hcd ma7 dmaaddr reset value 00000000000000000000000000000000 0x604 otg_hs_hcd ma8 dmaaddr reset value 00000000000000000000000000000000 0x624 otg_hs_hcd ma9 dmaaddr reset value 00000000000000000000000000000000 0x644 otg_hs_hcd ma10 dmaaddr reset value 00000000000000000000000000000000 0x664 otg_hs_hcd ma11 dmaaddr reset value 00000000000000000000000000000000 0x800 otg_hs_ dcfg reserved perschivl reserved reserved pfivl dad reserved nzlsohsk dspd reset value 10 000000000 000 0x804 otg_hs_dctl reserved poprgdne cgonak sgonak cginak sginak tctl gonsts ginsts sdis rwusig reset value 000000000000 0x808 otg_hs_dsts reserved fnsof reserved eerr enumspd suspsts reset value 00000000000000 0000 0x810 otg_hs_diep msk reserved bim txfurm reserved inepnem inepnmm ittxfemsk tom reserved epdm xfrcm reset value 0000000 00 0x814 otg_hs_doe pmsk reserved boim opem reserved b2bstup reserved otepdm stupm reserved epdm xfrcm reset value 00 0000 00 0x818 otg_hs_dain t oepint iepint reset value 00000000000000000000000000000000 0x81c otg_hs_dain tmsk oepm iepm reset value 00000000000000000000000000000000 table 161. otg_hs register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 usb on-the-go high-speed (otg_hs) RM0033 1158/1317 doc id 15403 rev 3 0x828 otg_hs_dvb usdis reserved vbusdt reset value 0001011111010111 0x82c otg_hs_dvb uspulse reserved dvbusp reset value 010110111000 0x830 otg_hs_dth rctl reserved arpen reserved rxthrlen rxthren reserved txthrlen isothren nonisothren reset value 0 0000000000 00000000000 0x834 otg_hs_diep empmsk reserved ineptxfem reset value 0000000000000000 0x838 otg_hs_dea chint reserved reserved reserved reset value 0 0 0x83c otg_hs_dea chintmsk reserved reserved reserved reset value 0 0 0x840 otg_hs_diep eachmsk1 reserved nakm reserved bim txfurm reserved inepnem inepnmm ittxfemsk tom reserved epdm xfrcm reset value 0 00 0000 00 0x880 otg_hs_doe peachmsk1 reserved nyetm nakm berrm reserved bim txfurm reserved inepnem inepnmm ittxfemsk tom reserved epdm xfrcm reset value 000 00 0000 00 0x900 otg_hs_diep ctl0 epena epdis soddfrm sd0pid/sevnfrm snak cnak txfnum stall reserved eptyp naksts eonum/dpid usbaep reserved mpsiz reset value 00000000000 00000 00000000000 0x918 tg_fs_dtxfs ts0 reserved ineptfsav reset value 0000001000000000 0x920 otg_hs_diep ctl1 epena epdis soddfrm sd0pid/sevnfrm snak cnak txfnum stall reserved eptyp naksts eonum/dpid usbaep reserved mpsiz reset value 00000000000 00000 00000000000 0x938 tg_fs_dtxfs ts1 reserved ineptfsav reset value 0000001000000000 0x940 otg_hs_diep ctl2 epena epdis soddfrm sd0pid/sevnfrm snak cnak txfnum stall reserved eptyp naksts eonum/dpid usbaep reserved mpsiz reset value 00000000000 00000 00000000000 0x958 tg_fs_dtxfs ts2 reserved ineptfsav reset value 0000001000000000 table 161. otg_hs register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1159/1317 0x960 otg_hs_diep ctl3 epena epdis soddfrm sd0pid/sevnfrm snak cnak txfnum stall reserved eptyp naksts eonum/dpid usbaep reserved mpsiz reset value 00000000000 00000 00000000000 0x978 tg_fs_dtxfs ts3 reserved ineptfsav reset value 0000001000000000 0x980 otg_hs_diep ctl4 epena epdis soddfrm sd0pid/sevnfrm snak cnak txfnum stall reserved eptyp naksts eonum/dpid usbaep reserved mpsiz reset value 00000000000 00000 00000000000 0x9a0 otg_hs_diep ctl5 epena epdis soddfrm sd0pid/sevnfrm snak cnak txfnum stall reserved eptyp naksts eonum/dpid usbaep reserved mpsiz reset value 00000000000 00000 00000000000 0x9c0 otg_hs_diep ctl6 epena epdis soddfrm sd0pid/sevnfrm snak cnak txfnum stall reserved eptyp naksts eonum/dpid usbaep reserved mpsiz reset value 00000000000 00000 00000000000 0x9e0 otg_hs_diep ctl7 epena epdis soddfrm sd0pid/sevnfrm snak cnak txfnum stall reserved eptyp naksts eonum/dpid usbaep reserved mpsiz reset value 00000000000 00000 00000000000 0xb00 otg_hs_doe pctl0 epena epdis reserved snak cnak reserved stall snpm epty p naksts reserved usbaep reserved mpsi z reset value 0 0 0 0 0 0 0 0 0 1 0 0 0xb20 otg_hs_doe pctl1 epena epdis soddfrm sd0pid/sevnfrm snak cnak reserved stall snpm eptyp naksts eonum/dpid usbaep reserved mpsiz reset value 000000 0000000 00000000000 0xb40 otg_hs_doe pctl2 epena epdis soddfrm sd0pid/sevnfrm snak cnak reserved stall snpm eptyp naksts eonum/dpid usbaep reserved mpsiz reset value 000000 0000000 00000000000 table 161. otg_hs register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 usb on-the-go high-speed (otg_hs) RM0033 1160/1317 doc id 15403 rev 3 0xb60 otg_hs_doe pctl3 epena epdis soddfrm sd0pid/sevnfrm snak cnak reserved stall snpm eptyp naksts eonum/dpid usbaep reserved mpsiz reset value 000000 0000000 00000000000 0x908 otg_hs_diepi nt0 reserved nak berr pktdrpsts reserved bna txfifoudrn txfe inepne reserved ittxfe toc reserved epdisd xfrc reset value 000 0010 00 00 0x928 otg_hs_diepi nt1 reserved nak berr pktdrpsts reserved bna txfifoudrn txfe inepne reserved ittxfe toc reserved epdisd xfrc reset value 000 0010 00 00 0x948 otg_hs_diepi nt2 reserved nak berr pktdrpsts reserved bna txfifoudrn txfe inepne reserved ittxfe toc reserved epdisd xfrc reset value 000 0010 00 00 0x968 otg_hs_diepi nt3 reserved nak berr pktdrpsts reserved bna txfifoudrn txfe inepne reserved ittxfe toc reserved epdisd xfrc reset value 000 0010 00 00 0x988 otg_hs_diepi nt4 reserved nak berr pktdrpsts reserved bna txfifoudrn txfe inepne reserved ittxfe toc reserved epdisd xfrc reset value 000 0010 00 00 0x9a8 otg_hs_diepi nt5 reserved nak berr pktdrpsts reserved bna txfifoudrn txfe inepne reserved ittxfe toc reserved epdisd xfrc reset value 000 0010 00 00 0x9c8 otg_hs_diepi nt6 reserved nak berr pktdrpsts reserved bna txfifoudrn txfe inepne reserved ittxfe toc reserved epdisd xfrc reset value 000 0010 00 00 0x9e8 otg_hs_diepi nt7 reserved nak berr pktdrpsts reserved bna txfifoudrn txfe inepne reserved ittxfe toc reserved epdisd xfrc reset value 000 0010 00 00 0xb08 otg_hs_doe pint0 reserved nyet reserved b2bstup reserved otepdis stup reserved epdisd xfrc reset value 0 0 0 1 0 0 table 161. otg_hs register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1161/1317 0xb28 otg_hs_doe pint1 reserved nyet reserved b2bstup reserved otepdis stup reserved epdisd xfrc reset value 0 0 0 0 0 0 0xb48 otg_hs_doe pint2 reserved nyet reserved b2bstup reserved otepdis stup reserved epdisd xfrc reset value 0 0 0 0 0 0 0xb68 otg_hs_doe pint3 reserved nyet reserved b2bstup reserved otepdis stup reserved epdisd xfrc reset value 0 0 0 0 0 0 0xb88 otg_hs_doe pint4 reserved nyet reserved b2bstup reserved otepdis stup reserved epdisd xfrc reset value 0 0 0 0 0 0 0xba8 otg_hs_doe pint5 reserved nyet reserved b2bstup reserved otepdis stup reserved epdisd xfrc reset value 0 0 0 0 0 0 0xbc8 otg_hs_doe pint6 reserved nyet reserved b2bstup reserved otepdis stup reserved epdisd xfrc reset value 0 0 0 0 0 0 0xbe8 otg_hs_doe pint7 reserved nyet reserved b2bstup reserved otepdis stup reserved epdisd xfrc reset value 0 0 0 0 0 0 0x910 otg_hs_diep tsiz0 reserved pktc nt reserved xfrsiz reset value 00 0000000 0x930 otg_hs_diep tsiz1 reserved mcnt pktcnt xfrsiz reset value 0000000000000000000000000000000 0x934 otg_hs_diep dma1 dmaaddr reset value 00000000000000000000000000000000 0x93c otg_hs_diep dmab1 dmabaddr reset value 00000000000000000000000000000000 0x950 otg_hs_diep tsiz2 reserved mcnt pktcnt xfrsiz reset value 0000000000000000000000000000000 0x954 otg_hs_diep dma2 dmaaddr reset value 00000000000000000000000000000000 0x95c otg_hs_diep dmab2 dmabaddr reset value 00000000000000000000000000000000 0x970 otg_hs_diep tsiz3 reserved mcnt pktcnt xfrsiz reset value 0000000000000000000000000000000 0x974 otg_hs_diep dma3 dmaaddr reset value 00000000000000000000000000000000 0x97c otg_hs_diep dmab3 dmabaddr reset value 00000000000000000000000000000000 table 161. otg_hs register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 usb on-the-go high-speed (otg_hs) RM0033 1162/1317 doc id 15403 rev 3 refer to table 1 on page 50 for the register boundary addresses. 30.13 otg_hs programming model 30.13.1 core initialization the application must perform the core initialization sequence. if the cable is connected during power-up, the current mode of operation bit in the core interrupt register (cmod bit in otg_hs_gintsts) reflects the mode. the otg_hs controller enters host mode when an ?a? plug is connected or peripheral mode when a ?b? plug is connected. this section explains the in itialization of the otg_hs co ntroller after power-on. the application must follow the initia lization sequence irrespective of host or peripheral mode operation. all core global registers are initialized according to the core?s configuration: 0xb10 otg_hs_doe ptsiz0 reserved stup cnt reserved pktcnt reserved xfrsiz reset value 00 0 0000000 0xb30 otg_hs_doe ptsiz1 reserved rxdpid/ stupcnt pktcnt xfrsiz reset value 0000000000000000000000000000000 0xb34 otg_hs_doe pdma1 dmaaddr reset value 00000000000000000000000000000000 0xb3c otg_hs_doe pdmab1 dmabaddr reset value 00000000000000000000000000000000 0xb50 otg_hs_doe ptsiz2 reserved rxdpid/ stupcnt pktcnt xfrsiz reset value 0000000000000000000000000000000 0xb54 otg_hs_doe pdma2 dmaaddr reset value 00000000000000000000000000000000 0xb5c otg_hs_doe pdmab2 dmabaddr reset value 00000000000000000000000000000000 0xb70 otg_hs_doe ptsiz3 reserved rxdpid/ stupcnt pktcnt xfrsiz reset value 0000000000000000000000000000000 0xb74 otg_hs_doe pdma3 dmaaddr reset value 00000000000000000000000000000000 0xb7c otg_hs_doe pdmab3 dmabaddr reset value 00000000000000000000000000000000 0xe00 otg_hs_pcg cctl reserved physusp reserved gatehclk stppclk reset value table 161. otg_hs register map and reset values (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1163/1317 1. program the following fields in the global ahb configuration (otg_hs_gahbcfg) register: ? dma mode bit ? ahb burst length field ? global interrupt mask bit gint = 1 ? rxfifo nonempty (rxflvl bit in otg_hs_gintsts) ? periodic txfifo empty level 2. program the following fields in otg_hs_gusbcfg register: ? hnp capable bit ? srp capable bit ? fs timeout calibration field ? usb turnaround time field 3. the software must unmask the following bits in the gintmsk register: otg interrupt mask mode mismatch interrupt mask 4. the software can read the cmod bit in otg_hs_gintsts to determine whether the otg_hs controller is operating in host or peripheral mode. 30.13.2 host initialization to initialize the core as host, the app lication must perform the following steps: 1. program the hprtint in gintmsk to unmask 2. program the otg_hs_hcfg regi ster to select full-speed host 3. program the ppwr bit in otg_hs_hprt to 1. this drives v bus on the usb. 4. wait for the pcdet interr upt in otg_hs_hprt0. this indicates that a device is connecting to the port. 5. program the prst bit in otg_hs_hprt to 1. this starts the reset process. 6. wait at least 10 ms for the reset process to complete. 7. program the prst bit in otg_hs_hprt to 0. 8. wait for the penchng interrupt in otg_hs_hprt. 9. read the pspd bit in otg_hs_hprt to get the enumerated speed. 10. program the hfir register with a value corresponding to the selected phy clock 1. 11. program the fslspcs field in otg_fs_hcfg register according to the speed of the detected device read in step 9. if fslspcs has been changed, reset the port. 12. program the otg_hs_grxfsiz register to select the size of the receive fifo. 13. program the otg_hs_gnptxfsiz register to select the size and the start address of the nonperiodic transmit fifo for nonperiodic transactions. 14. program the otg_hs_hptxfsiz register to select the size and start address of the periodic transmit fifo for periodic transactions. to communicate with devices, the system software must initialize and enable at least one channel. usb on-the-go high-speed (otg_hs) RM0033 1164/1317 doc id 15403 rev 3 30.13.3 device initialization the application must perform the following steps to initialize the core as a device on power- up or after a mode change from host to device. 1. program the following fields in the otg_hs_dcfg register: ? device speed ? nonzero-length status out handshake 2. program the otg_hs_gintmsk register to unmask the following interrupts: ? usb reset ? enumeration done ? early suspend ? usb suspend ?sof 3. program the vbusbsen bit in the otg_hs_gccfg register to enable v bus sensing in ?b? peripheral mode and supply the 5 volts across the pull-up resistor on the dp line. 4. wait for the usbrst interrupt in otg_hs_gintsts. it indicates that a reset has been detected on the usb that lasts for about 10 ms on receiving this interrupt. wait for the enumdne interrupt in otg_hs_gin tsts. this interrupt indicates the end of reset on the usb. on receivin g this interrupt, the application must read the otg_hs_dsts register to determine the enumeration speed and perform the steps listed in endpoint initialization on enumeration completion on page 1193 . at this point, the device is ready to accept sof packets and perform control transfers on control endpoint 0. 30.13.4 dma mode the otg host uses the ahb master interface to fetch the transmit packet data (ahb to usb) and receive the data update (usb to ahb). the ahb master uses the programmed dma address (hcdmax register in host m ode and diepdmax/doepdmax register in peripheral mode) to access the data buffers. 30.13.5 host programming model channel initialization the application must initialize one or more channels before it can communicate with connected devices. to initialize and enable a channel, the application must perform the following steps: RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1165/1317 1. program the gintmsk register to unmask the following: 2. channel interrupt ? nonperiodic transmit fifo empty for out transactions (applicable for slave mode that operates in pipelined transaction-level with the packet count field programmed with more than one). ? nonperiodic transmit fifo half-empty for out transactions (applicable for slave mode that operates in pipelined transac tion-level with the packet count field programmed with more than one). 3. program the otg_hs_haintmsk register to unmask the selected channels? interrupts. 4. program the otg_hs_hcintmsk register to unmask the transaction-related interrupts of interest given in the host channel interrupt register. 5. program the selected channel?s otg_hs_hctsizx register with the total transfer size, in bytes, and the expected number of packets, including short packets. the application must program the pid field with the initial data pid (to be used on the first out transaction or to be expected from the first in transaction). 6. program the selected channels in the otg_hs_hcspltx register(s) with the hub and port addresses (split transactions only). 7. program the selected channels in the hcdmax register(s) with the buffer start address. 8. program the otg_hs_hccharx re gister of the selected chan nel with the device?s endpoint characteristics, such as type, speed, direction, and so forth. (the channel can be enabled by setting the channel enable bit to 1 only when the application is ready to transmit or receive any packet). halting a channel the application can disable any channel by programming the otg_hs_hccharx register with the chdis and chena bits set to 1. this enables the otg_hs host to flush the posted requests (if any) and generates a channel halted interrupt. the application must wait for the chh interrupt in otg_hs_hcint x before reallocating the channel for other transactions. the otg_hs host does not interrupt the transaction that has already been started on the usb. to disable a channel in dma mode operation, the application does not need to check for space in the request queue. the otg_hs host checks for space to write the disable request on the disabled channel?s turn during arbitration. meanwhile, all posted requests are dropped from the request queue when the chdis bit in hccharx is set to 1. before disabling a channel, the application must ensure that there is at least one free space available in the nonperiodic request queue (when disabling a nonperiodic channel) or the periodic request queue (when disabling a pe riodic channel). the application can simply flush the posted requests when the request queue is full (before disabling the channel), by programming the otg_hs_hccharx register wit h the chdis bit set to 1, and the chena bit cleared to 0. the application is expected to disable a channel on any of the following conditions: 1. when an xfrc interrupt in otg_hs_hcintx is received during a nonperiodic in transfer or high-bandwidth interrupt in transfer (slave mode only) 2. when an stall, txerr, bberr or dte rr interrupt in otg_hs_hcintx is received for an in or out channel (slave mode only). for high-bandwidth interrupt ins in slave mode, once the application has received a dterr interrupt it must disable the channel usb on-the-go high-speed (otg_hs) RM0033 1166/1317 doc id 15403 rev 3 and wait for a channel halted interrupt. the application must be able to receive other interrupts (dterr, nak, data, txerr) for the same channel before receiving the halt. 3. when a discint (disconnect device) in terrupt in otg_hs_gintsts is received. (the application is expected to disable all enabled channels 4. when the application aborts a transfer before normal completion. ping protocol when the otg_hs host operates in high speed, the application must initiate the ping protocol when communicating with high-speed bulk or control (data and status stage) out endpoints. the application must initiate the ping protocol when it receives a nak/nyet/txerr interrupt. when the hs_otg host receives one of the above responses, it does not continue any transaction for a specific endpoint, drops all posted or fetched out requests (from the request queue), and flushes the corresponding data (from the transmit fifo). this is valid in slave mode only. in slave mode, the application can send a ping token either by setting the doping bit in hctsizx before enabling the channel or by just writing the hctsizx register with the doping bit set w hen the channel is already enabled. this enables the hs_otg host to write a ping request entry to the request queue. the application must wait for the response to the ping token (a nak, ack, or txerr interrupt) before continuing the transaction or sending another ping token. the application can continue the data transaction only after receiving an ack from the out endpoint for the requested ping. in dma mode operation, the application does not need to set the doping bit in hctsizx for a nak/nyet response in case of bulk/control out. the otg_hs host automatically sets the doping bit in hctsizx, and issues the ping tokens for bulk/control out. the hs_otg host continues sending ping tokens until it receives an ack, and then switches automatically to the data transaction. operational model the application must initialize a channel before communicating to the connected device. this section explains the sequence of operati on to be performed for different types of usb transactions. writing the transmit fifo the otg_hs host automatically writes an entry (out request) to the periodic/nonperiodic request queue, along with the last dword write of a packet. the application must ensure that at least one free space is available in the periodic/nonperiodic request queue before starting to write to the transmit fifo. the app lication must always write to the transmit fifo in dwords. if the packet size is nondword aligned, the application must use padding. the otg_hs host determines the actual packet size based on the programmed maximum packet size and transfer size. RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1167/1317 figure 376. transmit fifo write task 1 mps or lps fifo space available? wait for write 1 packet data to transmit fifo more packets to send? yes no no read gnptxsts/ hptxfsiz registers for available fifo and queue spaces yes mps: maximum packet size lps: last packet size tacet start done ai15673 txfelvl or ptxfelvl interrupt in otg_fs_gahbcfg usb on-the-go high-speed (otg_hs) RM0033 1168/1317 doc id 15403 rev 3 reading the receive fifo the application must ignore all packet statuses other than in data packet (bx0010). figure 377. receive fifo read task bulk and control out/setup transactions a typical bulk or control out/setup pipelined transaction-level operation is shown in figure 378 . see channel 1 (ch_1). two bulk out packets are transmitted. a control rxflvl interrupt ? read the received packet from the receive fifo read otg_fs_grxstsp pktsts 0b0010? yes yes unmask rxflvl interrupt bcnt > 0? no mask rxflvl interrupt yes unmask rxflvl interrupt no no start ai15674 RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1169/1317 setup transaction operates in the same way but has only one packet. the assumptions are: ? the application is attempting to send two maximum-packet-size packets (transfer size = 1, 024 bytes). ? the nonperiodic transmit fifo can hold two packets (128 bytes for fs). ? the nonperiodic request queue depth = 4. normal bulk and control out/setup operations the sequence of operations for channel 1 is as follows: a) initialize channel 1 b) write the first packet for channel 1 c) along with the last dword write, the co re writes an entry to the nonperiodic request queue d) as soon as the nonperiodic queue becomes nonempty, the core attempts to send an out token in the current frame e) write the second (last) packet for channel 1 f) the core generates the xfrc interrup t as soon as the last transaction is completed successfully g) in response to the xfrc interrupt, de-allocate the channel for other transfers h) handling nonack responses usb on-the-go high-speed (otg_hs) RM0033 1170/1317 doc id 15403 rev 3 figure 378. normal bulk/control out/setup and bulk/control in transactions - dma mode RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1171/1317 figure 379. normal bulk/control out/setup and bulk/control in transactions - slave mode the channel-specific interrupt service routine for bulk and control out/setup transactions in slave mode is shown in the following code samples. interrupt service routine for bulk/control out/setup and bulk/control in transactions a) bulk/control out/setup unmask (nak/txerr/stall/xfrc) if ( xfrc ) { reset error count usb on-the-go high-speed (otg_hs) RM0033 1172/1317 doc id 15403 rev 3 mask ack de-allocate channel } else if ( stall ) { transfer done = 1 unmask chh disable channel } else if ( nak or txerr ) { rewind buffer pointers unmask chh disable channel if ( txerr ) { increment error count unmask ack } else { reset error count } } else if ( chh ) { mask chh if (transfer done or (error_count == 3)) { de-allocate channel } else { re-initialize channel } } else if ( ack ) { reset error count mask ack } the application is expected to write the data packets into the transmit fifo as and when the space is available in the tr ansmit fifo and the request queue. the application can make use of the nptxfe interrupt in otg_hs_gintsts to find the transmit fifo space. b) bulk/control in unmask (txerr/xfrc/bberr/stall/dterr) if ( xfrc ) { reset error count unmask chh disable channel RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1173/1317 reset error count mask ack } else if ( txerr or bberr or stall ) { unmask chh disable channel if ( txerr ) { increment error count unmask ack } } else if ( chh ) { mask chh if (transfer done or (error_count == 3)) { de-allocate channel } else { re-initialize channel } } else if ( ack ) { reset error count mask ack } else if ( dterr ) { reset error count } the application is expected to write the requests as and when the request queue space is available and until the xfrc interrupt is received. bulk and control in transactions a typical bulk or control in pipelined tr ansaction-level operation is shown in figure 380 . see channel 2 (ch_2). the assumptions are: ? the application is attempting to receive two maximum-packet-size packets (transfer size = 1 024 bytes). ? the receive fifo can contain at least one maximum-packet-size packet and two status dwords per packet (72 bytes for fs). ? the nonperiodic request queue depth = 4. usb on-the-go high-speed (otg_hs) RM0033 1174/1317 doc id 15403 rev 3 figure 380. bulk/control in transactions - dma mode RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1175/1317 figure 381. bulk/control in transactions - slave mode the sequence of operations is as follows: a) initialize channel 2. b) set the chena bit in hcchar2 to write an in request to the nonperiodic request queue. c) the core attempts to send an in token after completing the current out transaction. d) the core generates an rxflvl interrupt as soon as the received packet is written to the receive fifo. e) in response to the rxflvl interrupt, mask the rxflvl interrupt and read the received packet status to determine the number of bytes received, then read the usb on-the-go high-speed (otg_hs) RM0033 1176/1317 doc id 15403 rev 3 receive fifo accordingly. following this, unmask the rxflvl interrupt. f) the core generates the rxflvl interrupt for the transfer completion status entry in the receive fifo. g) the application must read and ignore the receive packet status when the receive packet status is not an in data packet (pktsts in grxstsr 0b0010). h) the core generates the xfrc interrupt as soon as the receive packet status is read. i) in response to the xfrc interrupt, disable the channel and stop writing the otg_hs_hcchar2 register for further re quests. the core writes a channel disable request to the nonperiodic request queue as soon as the otg_hs_hcchar2 register is written. j) the core generates the rxflvl interrupt as soon as the halt status is written to the receive fifo. k) read and ignore the receive packet status. l) the core generates a chh interrupt as soon as the halt status is popped from the receive fifo. m) in response to the chh interrupt, de-allocate the channel for other transfers. n) handling nonack responses control transactions in slave mode setup, data, and status stages of a control transfer must be performed as three separate transfers. setup-, data- or status-stage out transactions are performed similarly to the bulk out transactions explained previously. data- or status-stage in transactions are performed similarly to the bulk in transactions explained previously. for all three stages, the application is expected to set the eptyp field in otg_hs_hcchar1 to control. during the setu p stage, the application is expected to set the pid field in otg_hs_hctsiz1 to setup. interrupt out transactions a typical interrupt out operation in slave mode is shown in figure 382 . the assumptions are: ? the application is attempting to send one packet in every frame (up to 1 maximum packet size), starting with the odd frame (transfer size = 1 024 bytes) ? the periodic transmit fifo can hold one packet (1 kb) ? periodic request queue depth = 4 the sequence of operations is as follows: a) initialize and enable channel 1. the application must set the oddfrm bit in otg_hs_hcchar1. b) write the first packet for channel 1. for a high-bandwidth interrupt transfer, the application must write the subsequent packets up to mcnt (maximum number of packets to be transmitted in the next frame times) before switching to another channel. c) along with the last dword write of eac h packet, the otg_hs host writes an entry to the periodic request queue. d) the otg_hs host attempts to send an out token in the next (odd) frame. e) the otg_hs host generates an xfrc interrupt as soon as the last packet is transmitted successfully. f) in response to the xfrc interrupt, reinitialize the channel for the next transfer. RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1177/1317 figure 382. normal interrupt out/in transactions - dma mode usb on-the-go high-speed (otg_hs) RM0033 1178/1317 doc id 15403 rev 3 figure 383. normal interrupt out/in transactions - slave mode interrupt service routine for interrupt out/in transactions a) interrupt out unmask (nak/txerr/stall/xfrc/frmor) if ( xfrc ) { reset error count mask ack de-allocate channel } else if ( stall or frmor ) { RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1179/1317 mask ack unmask chh disable channel if ( stall ) { transfer done = 1 } } else if ( nak or txerr ) { rewind buffer pointers reset error count mask ack unmask chh disable channel } else if ( chh ) { mask chh if (transfer done or (error_count == 3)) { de-allocate channel } else { re-initialize channel (in next b_interval - 1 frame) } } else if ( ack ) { reset error count mask ack } the application is expected to write the data packets into the transmit fifo when the space is available in the transmit fifo and the request queue up to the count specified in the mcnt field before switching to another channel. the application uses the nptxfe interrupt in otg_hs_gints ts to find the transmit fifo space. b) interrupt in unmask (nak/txerr/xfrc/bberr/stall/frmor/dterr) if ( xfrc ) { reset error count mask ack if (otg_hs_hctsizx.pktcnt == 0) { de-allocate channel } else { usb on-the-go high-speed (otg_hs) RM0033 1180/1317 doc id 15403 rev 3 transfer done = 1 unmask chh disable channel } } else if ( stall or frmor or nak or dterr or bberr ) { mask ack unmask chh disable channel if ( stall or bberr ) { reset error count transfer done = 1 } else if (! frmor ) { reset error count } } else if ( txerr ) { increment error count unmask ack unmask chh disable channel } else if ( chh ) { mask chh if (transfer done or (error_count == 3)) { de-allocate channel } else re-initialize channel (in next b_interval - 1 /frame) } } else if ( ack ) { reset error count mask ack RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1181/1317 } the application is expected to write the requests for the same channel when the request queue space is available up to the count specified in the mcnt field before switching to another channel (if any). interrupt in transactions the assumptions are: ? the application is attempting to receive one packet (up to 1 maximum packet size) in every frame, starting with odd (transfer size = 1 024 bytes). ? the receive fifo can hold at least one maximum-packet-size packet and two status dwords per packet (1 031 bytes). ? periodic request queue depth = 4. normal interrupt in operation the sequence of operations is as follows: a) initialize channel 2. the applic ation must set the oddfrm bit in otg_hs_hcchar2. b) set the chena bit in otg_hs_hcchar2 to write an in request to the periodic request queue. for a high-bandwidth interrupt transfer, the application must write the otg_hs_hcchar2 register mcnt (max imum number of expected packets in the next frame times) before switching to another channel. c) the otg_hs host writes an in request to the periodic request queue for each otg_hs_hcchar2 register write with the chena bit set. d) the otg_hs host attempts to send an in token in the next (odd) frame. e) as soon as the in packet is received and written to the receive fifo, the otg_hs host generates an rxflvl interrupt. f) in response to the rxflvl interrupt, read the received packet status to determine the number of bytes received, then read the receive fifo accordingly. the application must mask the rxflvl interrupt before reading the receive fifo, and unmask after reading the entire packet. g) the core generates the rxflvl interrupt for the transfer completion status entry in the receive fifo. the application must read and ignore the receive packet status when the receive packet status is not an in data packet (pktsts in grxstsr 0b0010). h) the core generates an xfrc interrupt as soon as the receive packet status is read. i) in response to the xfrc interrupt, read the pktcnt field in otg_hs_hctsiz2. if the pktcnt bit in otg_hs_hctsiz2 is not equal to 0, disable the channel before re-initializing the channel for the next transfer, if any). if pktcnt bit in usb on-the-go high-speed (otg_hs) RM0033 1182/1317 doc id 15403 rev 3 otg_hs_hctsiz2 = 0, reinitialize the channel for the next transfer. this time, the application must reset the oddfrm bit in otg_hs_hcchar2. isochronous out transactions a typical isochronous out operation in slave mode is shown in figure 384 . the assumptions are: ? the application is attempting to send one packet every frame (up to 1 maximum packet size), starting with an odd frame. (transfer size = 1 024 bytes). ? the periodic transmit fifo can hold one packet (1 kb). ? periodic request queue depth = 4. the sequence of operations is as follows: a) initialize and enable channel 1. the application must set the oddfrm bit in otg_hs_hcchar1. b) write the first packet for channel 1. for a high-bandwidth isochronous transfer, the application must write the subsequent packets up to mcnt (maximum number of packets to be transmitted in the next frame times before switching to another channel. c) along with the last dword write of eac h packet, the otg_hs host writes an entry to the periodic request queue. d) the otg_hs host attempts to send the out token in the next frame (odd). e) the otg_hs host generates the xfrc interrupt as soon as the last packet is transmitted successfully. f) in response to the xfrc interrupt, reinitialize the channel for the next transfer. g) handling nonack responses RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1183/1317 figure 384. normal isochronous out/in transactions - dma mode usb on-the-go high-speed (otg_hs) RM0033 1184/1317 doc id 15403 rev 3 figure 385. normal isochronous out/in transactions - slave mode interrupt service routine for isochronous out/in transactions code sample: isochronous out unmask (frmor/xfrc) if ( xfrc ) { de-allocate channel } else if ( frmor ) { unmask chh disable channel } RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1185/1317 else if ( chh ) { mask chh de-allocate channel } code sample: isochronous in unmask (txerr/xfrc/frmor/bberr) if ( xfrc or frmor ) { if ( xfrc and (otg_hs_hctsizx.pktcnt == 0)) { reset error count de-allocate channel } else { unmask chh disable channel } } else if ( txerr or bberr ) { increment error count unmask chh disable channel } else if ( chh ) { mask chh if (transfer done or (error_count == 3)) { de-allocate channel } else { re-initialize channel } } usb on-the-go high-speed (otg_hs) RM0033 1186/1317 doc id 15403 rev 3 isochronous in transactions the assumptions are: ? the application is attempting to receive one packet (up to 1 maximum packet size) in every frame starting with the next odd frame (transfer size = 1 024 bytes). ? the receive fifo can hold at least one maximum-packet-size packet and two status dwords per packet (1 031 bytes). ? periodic request queue depth = 4. the sequence of operations is as follows: a) initialize channel 2. the applic ation must set the oddfrm bit in otg_hs_hcchar2. b) set the chena bit in otg_hs_hcchar2 to write an in request to the periodic request queue. for a high-bandwidth isochronous transfer, the application must write the otg_hs_hcchar2 register mcnt (maximum number of expected packets in the next frame times) before switching to another channel. c) the otg_hs host writes an in request to the periodic request queue for each otg_hs_hcchar2 register write with the chena bit set. d) the otg_hs host attempts to send an in token in the next odd frame. e) as soon as the in packet is received and written to the receive fifo, the otg_hs host generates an rxflvl interrupt. f) in response to the rxflvl interrupt, read the received packet status to determine the number of bytes received, then read the receive fifo accordingly. the application must mask the rxflvl interrupt before reading the receive fifo, and unmask it after reading the entire packet. g) the core generates an rxflvl interrupt for the transfer completion status entry in the receive fifo. this time, the application must read and ignore the receive packet status when the receive packet status is not an in data packet (pktsts bit in otg_hs_grxstsr 0b0010). h) the core generates an xfrc interrupt as soon as the receive packet status is read. i) in response to the xfrc interrupt, read the pktcnt field in otg_hs_hctsiz2. if pktcnt 0 in otg_hs_hctsiz2, disable the channel before re-initializing the channel for the next transfer, if any. if pktcnt = 0 in otg_hs_hctsiz2, reinitialize the channel for the next transfer. this time, the application must reset the oddfrm bit in otg_hs_hcchar2. selecting the queue depth choose the periodic and nonperiodic request queue depths carefully to match the number of periodic/nonperiodic endpoints accessed. the nonperiodic request queue depth affects the performance of nonperiodic transfers. the deeper the queue (along with sufficient fifo size), the more often the core is able to pipeline nonperiodic transfers. if the queue size is small, the core is able to put in new requests only when the queue space is freed up. the core?s periodic request queue depth is critical to perform periodic transfers as scheduled. select the periodic queue depth, based on the number of periodic transfers scheduled in a micro-frame. in slave mode, however, the application must also take into account the disable entry that must be put into the queue. so, if there are two nonhigh-bandwidth periodic endpoints, the periodic request queue depth must be at least 4. if at least one high-bandwidth endpoint is supported, the queue depth must be RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1187/1317 8. if the periodic request queue depth is smaller than the periodic transfers scheduled in a micro-frame, a frame overrun condition occurs. handling babble conditions otg_hs controller handles two cases of babble: packet babble and port babble. packet babble occurs if the device sends more data than the maximum packet size for the channel. port babble occurs if the core continues to receive data from the device at eof2 (the end of frame 2, which is very close to sof). when otg_hs controller detects a packet babble, it stops writing data into the rx buffer and waits for the end of packet (eop). when it detects an eop, it flushes already written data in the rx buffer and generates a babble interrupt to the application. when otg_hs controller detects a port babble, it flushes the rxfifo and disables the port. the core then generates a port disabled interrupt (hprtint in otg_hs_gintsts, penchng in otg_hs_hprt) . on receiving this interrupt, the application must determine that this is not due to an overcurrent condition (another cause of the port disabled interrupt) by checking poca in otg_hs_hprt, then perform a soft reset. the core does not send any more tokens after it has detected a port babble condition. bulk and control out/setup transactions in dma mode the sequence of operations is as follows: a) initialize and enable channel 1 as explained in section : channe l initialization . b) the hs_otg host starts fetching the first packet as soon as the channel is enabled. for internal dma mode, the otg_hs host uses the programmed dma address to fetch the packet. c) after fetching the last dword of the second (last) packet, the otg_hs host masks channel 1 internally for further arbitration. d) the hs_otg host generates a chh interrupt as soon as the last packet is sent. e) in response to the chh interrupt, de-allocate the channel for other transfers. nak and nyet handling with internal dma a) the otg_hs host sends a bulk out transaction. b) the device responds with nak or nyet. c) if the application has unmasked nak or nyet, the core generates the corresponding interrupt(s) to the application. the application is not required to usb on-the-go high-speed (otg_hs) RM0033 1188/1317 doc id 15403 rev 3 service these interrupts, since the core takes care of rewinding the buffer pointers and re-initializing the channel without application intervention. d) the core automatically issues a ping token. e) when the device returns an ack, the core continues with the transfer. optionally, the application can utilize these interrup ts, in which case the nak or nyet interrupt is masked by the application. the core does not generate a separate interrupt when nak or nyet is received by the host functionality. bulk and control in transactions in dma mode the sequence of operations is as follows: a) initialize and enable the used channel (channel x) as explained in section : channel initialization . b) the otg_hs host writes an in request to the request queue as soon as the channel receives the grant from the arbiter (arbitration is performed in a round- robin fashion). c) the otg_hs host starts writing the rece ived data to the system memory as soon as the last byte is re ceived with no errors. d) when the last packet is received, the otg_hs host sets an internal flag to remove any extra in requests from the request queue. e) the otg_hs host flushes the extra requests. f) the final request to disable channel x is written to the request queue. at this point, channel 2 is internally masked for further arbitration. g) the otg_hs host generates the chh interrupt as soon as the disable request comes to the top of the queue. h) in response to the chh interrupt, de-allocate the channel for other transfers. interrupt out transactions in dma mode a) initialize and enable channel x as explained in section : channel initialization . b) the otg_hs host starts fetching the fi rst packet as soon the channel is enabled and writes the out request along with the last dword fetch. in high-bandwidth RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1189/1317 transfers, the hs_otg host continues fetching the next packet (up to the value specified in the mc field) before switching to the next channel. c) the otg_hs host attempts to send the out token at the beginning of the next odd frame/micro-frame. d) after successfully transmitting the packet, the otg_hs host generates a chh interrupt. e) in response to the chh interrupt, reinitialize the channel for the next transfer. interrupt in transactions in dma mode the sequence of operations (channelx) is as follows: a) initialize and enable channel x as explained in section : channel initialization . b) the otg_hs host writes an in request to the request queue as soon as the channel x gets the grant from the arbiter (round-robin with fairness). in high- bandwidth transfers, the otg_hs host writes consecutive writes up to mc times. c) the otg_hs host attempts to send an in token at the beginning of the next (odd) frame/micro-frame. d) as soon the packet is received and written to the receive fifo, the otg_hs host generates a chh interrupt. e) in response to the chh interrupt, reinitialize the channel for the next transfer. isochronous out transactions in dma mode a) initialize and enable channel x as explained in section : channel initialization . b) the otg_hs host starts fetching the first packet as soon as the channel is enabled, and writes the out request along with the last dword fetch. in high- bandwidth transfers, the otg_hs host continues fetching the next packet (up to the value specified in the mc field) before switching to the next channel. c) the otg_hs host attempts to send an out token at the beginning of the next (odd) frame/micro-frame. d) after successfully transmitting the packet, the hs_otg host generates a chh interrupt. e) in response to the chh interrupt, reinitialize the channel for the next transfer. isochronous in transactions in dma mode the sequence of operations ((channel x) is as follows: a) initialize and enable channel x as explained in section : channel initialization . b) the otg_hs host writes an in request to the request queue as soon as the channel x gets the grant from the arbiter (round-robin with fairness). in high- usb on-the-go high-speed (otg_hs) RM0033 1190/1317 doc id 15403 rev 3 bandwidth transfers, the otg_hs host performs consecutive write operations up to mc times. c) the otg_hs host attempts to send an in token at the beginning of the next (odd) frame/micro-frame. d) as soon the packet is received and written to the receive fifo, the otg_hs host generates a chh interrupt. e) in response to the chh interrupt, reinitialize the channel for the next transfer. bulk and control out/setup split transactions in dma mode the sequence of operations in (channel x) is as follows: a) initialize and enable channel x for start split as explained in section : channel initialization . b) the otg_hs host starts fetching the fi rst packet as soon the channel is enabled and writes the out request along with the last dword fetch. c) after successfully transmitting start split, the otg_hs host generates the chh interrupt. d) in response to the chh interrupt, set the complsplt bit in hcsplt1 to send the complete split. e) after successfully transmitting complete split, the otg_hs host generates the chh interrupt. f) in response to the chh interrupt, de-allocate the channel. bulk/control in split transactions in dma mode the sequence of operations (channel x) is as follows: a) initialize and enable channel x as explained in section : channel initialization . b) the otg_hs host writes the start split request to the nonperiodic request after getting the grant from the arbiter. the otg_hs host masks the channel x internally for the arbitration after writing the request. c) as soon as the in token is transmitted, the otg_hs host generates the chh interrupt. d) in response to the chh interrupt, set the complsplt bit in hcsplt2 and re- enable the channel to send the complete split token. this unmasks channel x for arbitration. e) the otg_hs host writes the complete split request to the nonperiodic request after receiving the grant from the arbiter. f) the otg_hs host starts writing the packet to the system memory after receiving the packet successfully. g) as soon as the received packet is written to the system memory, the otg_hs host generates a chh interrupt. h) in response to the chh interrupt, de-allocate the channel. interrupt out split transactions in dma mode the sequence of operations in (channel x) is as follows: a) initialize and enable channel 1 for start split as explained in section : channel initialization . the application must set the oddfrm bit in hcchar1. b) the hs_otg host starts reading the packet. c) the hs_otg host attempts to send the start split transaction. d) after successfully transmitting the start split, the otg_hs host generates the RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1191/1317 chh interrupt. e) in response to the chh interrupt, set the complsplt bit in hcsplt1 to send the complete split. f) after successfully completing the complete split transaction, the otg_hs host generates the chh interrupt. g) in response to chh interrupt, de-allocate the channel. interrupt in split transactions in dma mode the sequence of operations in (channel x) is as follows: a) initialize and enable channel x for start split as explained in section : channel initialization . b) the otg_hs host writes an in request to the request queue as soon as channel x receives the grant from the arbiter. c) the otg_hs host attempts to send the start split in token at the beginning of the next odd micro-frame. d) the otg_hs host generates the chh interrupt after successfully transmitting the start split in token. e) in response to the chh interrupt, set the complsplt bit in hcsplt2 to send the complete split. f) as soon as the packet is received success fully, the otg_hs host starts writing the data to the system memory. g) the otg_hs host generates the chh interrupt after transferring the received data to the system memory. h) in response to the chh inte rrupt, de-allocate or reinitia lize the channel for the next start split. isochronous out split transactions in dma mode the sequence of operations (channel x) is as follows: a) initialize and enable channel x for start split (begin) as explained in section : channel initialization . the application must set the oddfrm bit in hcchar1. program the mps field. b) the hs_otg host starts reading the packet. c) after successfully transmitting the start split (begin), the hs_otg host generates the chh interrupt. d) in response to the chh interrupt, reinitialize the registers to send the start split (end). e) after successfully transmitting the star t split (end), the otg_hs host generates a chh interrupt. f) in response to the chh interrupt, de-allocate the channel. isochronous in split transactions in dma mode the sequence of operations (channel x) is as follows: a) initialize and enable channel x for start split as explained in section : channel initialization . b) the otg_hs host writes an in request to the request queue as soon as channel x receives the grant from the arbiter. c) the otg_hs host attempts to send the start split in token at the beginning of the next odd micro-frame. usb on-the-go high-speed (otg_hs) RM0033 1192/1317 doc id 15403 rev 3 d) the otg_hs host generates the chh interrupt after successfully transmitting the start split in token. e) in response to the chh interrupt, set the complsplt bit in hcsplt2 to send the complete split. f) as soon as the packet is received success fully, the otg_hs host starts writing the data to the system memory. g) the otg_hs host generates the chh interrupt after transferring the received data to the system memory. in response to the chh interrupt, de-allocate the channel or reinitialize the channel for the next start split. 30.13.6 device programming model endpoint initialization on usb reset 1. set the nak bit for all out endpoints ? snak = 1 in otg_hs_doepctlx (for all out endpoints) 2. unmask the following interrupt bits ? inep0 = 1 in otg_hs_daintmsk (control 0 in endpoint) ? outep0 = 1 in otg_hs_daintmsk (control 0 out endpoint) ?stup=1 in doepmsk ? xfrc = 1 in doepmsk ? xfrc = 1 in diepmsk ? toc = 1 in diepmsk 3. set up the data fifo ram for each of the fifos ? program the otg_hs_grxfsiz register, to be able to receive control out data and setup data. if thresholding is not enabled, at a minimum, this must be equal to 1 max packet size of control endpoint 0 + 2 dwords (for the status of the control out data packet) + 10 dwords (for setup packets). ? program the otg_hs_tx0fsiz register (depending on the fifo number chosen) to be able to transmit control in data. at a minimum, this must be equal to 1 max packet size of control endpoint 0. 4. program the following fields in the endpoint-specific registers for control out endpoint 0 to receive a setup packet ? stupcnt = 3 in otg_hs_doeptsiz0 (to receive up to 3 back-to-back setup packets) 5. in dma mode, the doepdma0 register should have a valid memory address to store any setup packets received. at this point, all initia lization required to receive setup packets is done. RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1193/1317 endpoint initialization on enumeration completion 1. on the enumeration done interrupt (enumdne in otg_hs_gintsts), read the otg_hs_dsts register to determine the enumeration speed. 2. program the mpsiz field in otg_hs_diepctl0 to set the maximum packet size. this step configures control endpoint 0. the maximum packet size for a control endpoint depends on the enumeration speed. 3. in dma mode, program the doepctl0 register to enable control out endpoint 0, to receive a setup packet. ? epena bit in doepctl0 = 1 at this point, the device is ready to receive sof packets and is configured to perform control transfers on control endpoint 0. endpoint initialization on setaddress command this section describes what the application must do when it receives a setaddress command in a setup packet. 1. program the otg_hs_dcfg register with the device address received in the setaddress command 1. program the core to send out a status in packet endpoint initialization on setconfiguration/setinterface command this section describes what the application must do when it receives a setconfiguration or setinterface command in a setup packet. 1. when a setconfiguration command is received, the application must program the endpoint registers to configure them with the characteristics of the valid endpoints in the new configuration. 2. when a setinterface command is received, the application must program the endpoint registers of the endpoints affected by this command. 3. some endpoints that were active in the prior configuration or alternate setting are not valid in the new configuration or alternate setting. these invalid endpoints must be deactivated. 4. unmask the interrupt for each active endpoint and mask the interrupts for all inactive endpoints in the otg_hs_daintmsk register. 5. set up the data fifo ram for each fifo. 6. after all required endpoints are configured; the application must program the core to send a status in packet. at this point, the device core is configured to receive and transmit any type of data packet. endpoint activation this section describes the steps required to activate a device endpoint or to configure an existing device endpoint to a new type. usb on-the-go high-speed (otg_hs) RM0033 1194/1317 doc id 15403 rev 3 1. program the characteristics of the required endpoint into the following fields of the otg_hs_diepctlx register (for in or bidirectional endpoints) or the otg_hs_doepctlx register (for out or bidirectional endpoints). ? maximum packet size ? usb active endpoint = 1 ? endpoint start data toggle (for interrupt and bulk endpoints) ? endpoint type ? txfifo number 2. once the endpoint is activated, the core st arts decoding the tokens addressed to that endpoint and sends out a valid handshake for each valid token received for the endpoint. endpoint deactivation this section describes the steps required to deactivate an existing endpoint. 1. in the endpoint to be deactivated, clear the usb active endpoint bit in the otg_hs_diepctlx register (for in or bidirectional endpoints) or the otg_hs_doepctlx register (for out or bidirectional endpoints). 2. once the endpoint is deactivated, the core ignores tokens addressed to that endpoint, which results in a timeout on the usb. note: 1 the application must meet the following conditions to set up the device core to handle traffic: nptxfem and rxflvlm in gintmsk must be cleared. 30.13.7 operational model setup and out data transfers this section describes the internal data flow and application-level operations during data out transfers and setup transactions. packet read this section describes how to read packets (out data and setup packets) from the receive fifo in slave mode. 1. on catching an rxflvl interrupt (otg_hs_gintsts register), the application must read the receive status pop register (otg_hs_grxstsp). 2. the application can mask the rxflvl inte rrupt (in otg_hs_gintsts) by writing to rxflvl = 0 (in gintmsk), until it has read the packet from the receive fifo. 3. if the received packet?s byte count is not 0, the byte count amount of data is popped from the receive data fifo and stored in memory. if the received packet byte count is 0, no data is popped from the receive data fifo. 4. the receive fifo?s packet status readout indicates one of the following: a) global out nak pattern: pktsts = global out nak, bcnt = 0x000, epnum = don?t care (0x0), dpid = don?t care (0b00). these data indicate that the global out nak bit has taken effect. b) setup packet pattern: pktsts = setup, bcnt = 0x008, epnum = control ep num, dpid = d0. RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1195/1317 these data indicate that a setup packet for the specified endpoint is now available for reading from the receive fifo. c) setup stage done pattern: pktsts = setup stage done, bcnt = 0x0, epnum = control ep num, dpid = don?t care (0b00). these data indicate that the setup stage for the specified endpoint has completed and the data stage has started. after this entry is popped from the receive fifo, the core asserts a setup interrupt on the specified control out endpoint. d) data out packet pattern: pktsts = dataout, bcnt = size of the received data out packet (0 bcnt 1 024), epnum = epnum on which the packet was received, dpid = actual data pid. e) data transfer completed pattern: pktsts = data out transfer done, bcnt = 0x0, epnum = out ep num on which the data transfer is complete, dpid = don?t care (0b00). these data indicate that an out data transfer for the specified out endpoint has completed. after this entry is popped from the receive fifo, the core asserts a transfer completed interrupt on the specified out endpoint. 5. after the data payload is popped from the receive fifo, the rxflvl interrupt (otg_hs_gintsts) must be unmasked. 6. steps 1?5 are repeated every time the application detects assertion of the interrupt line due to rxflvl in otg_hs_gintsts. reading an empty receive fifo can result in undefined core behavior. figure 386 provides a flowchart of the above procedure. figure 386. receive fifo packet read in slave mode setup transactions this section describes how the core handles setup packets and the application?s sequence for handling setup transactions. application requirements dword_cnt = bcnt[11:2] + c ( bcnt[1] | bcnt[1]) rcv_out_pkt() rd_data = rd_reg (otg_fs_grxstsp); mem[0:dword_cnt-1] = rd_rxfifo(rd_data.epnum, dword_cnt) n rd_data.bcnt = 0 wait until rxflvl in otg_fs_gintstsg packet store in memory y ai15677 usb on-the-go high-speed (otg_hs) RM0033 1196/1317 doc id 15403 rev 3 1. to receive a setup packet, the stupcnt field (otg_hs_doeptsizx) in a control out endpoint must be programmed to a nonzero value. when the application programs the stupcnt field to a nonzero value, the core receives setup packets and writes them to the rece ive fifo, irrespective of the nak status and epena bit setting in otg_hs_doepctlx. the stupcnt field is decremented every time the control endpoint receives a setup packet. if the stupcnt field is not programmed to a proper value before receiving a setup packet, the core still receives the setup packet and decrements the stupcnt field, but the application may not be able to determine the correct number of setup packets received in the setup stage of a control transfer. ? stupcnt = 3 in otg_hs_doeptsizx 2. the application must always allocate some extra space in the receive data fifo, to be able to receive up to three setup packets on a control endpoint. ? the space to be reserved is 10 dwords. three dwords are required for the first setup packet, 1 dword is required for the setup stage done dword and 6 dwords are required to store two extra setup packets among all control endpoints. ? 3 dwords per setup packet are required to store 8 bytes of setup data and 4 bytes of setup status (setup packet pattern). the core reserves this space in the receive data. ? fifo to write setup data only, and never uses this space for data packets. 3. the application must read the 2 dwords of the setup packet from the receive fifo. 4. the application must read and discard the setup stage done dword from the receive fifo. internal data flow 5. when a setup packet is received, the core writes the received data to the receive fifo, without checking for available space in the receive fifo and irrespective of the endpoint?s nak and stall bit settings. ? the core internally sets the in nak and out nak bits for the control in/out endpoints on which the setup packet was received. 6. for every setup packet received on the usb, 3 dwords of data are written to the receive fifo, and the stupcnt field is decremented by 1. ? the first dword contains control information used internally by the core ? the second dword contains the first 4 bytes of the setup command ? the third dword contains the last 4 bytes of the setup command 7. when the setup stage changes to a data in/out stage, the core writes an entry (setup stage done dword) to the receive fifo, indicating the completion of the setup stage. 8. on the ahb side, setup packets are emptied by the application. 9. when the application pops the setup stage done dword from the receive fifo, the core interrupts the application with an stup interrupt (otg_hs_doepintx), indicating it can process the received setup packet. ? the core clears the endpoint enable bit for control out endpoints. application programming sequence RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1197/1317 1. program the otg_hs_doeptsizx register. ? stupcnt = 3 2. wait for the rxflvl interrupt (otg_hs_gintsts) and empty the data packets from the receive fifo. 3. assertion of the stup interrupt (otg_h s_doepintx) marks a su ccessful completion of the setup data transfer. ? on this interrupt, the application must read the otg_hs_doeptsizx register to determine the number of setup packets received and process the last received setup packet. figure 387. processing a setup packet handling more than three back-to-back setup packets per the usb 2.0 specification, normally, during a setup packet error, a host does not send more than three back-to-back setup packets to the same endpoint. however, the usb 2.0 specification does not limit the number of back-to-back setup packets a host can send to the same endpoint. when this condition occurs, the otg_hs controller generates an interrupt (b2bstup in otg_hs_doepintx). setting the global out nak internal data flow: 1. when the application sets the global out nak (sgonak bit in otg_hs_dctl), the core stops writing data, except setup packets, to the receive fifo. irrespective of the space availability in the receive fifo, no nisochronous out tokens receive a nak handshake response, and the core ignores isochronous out data packets 2. the core writes the global out nak pattern to the receive fifo. the application must reserve enough receive fifo space to write this data pattern. wait for stup in otg_fs_doepintx rem_supcnt = rd_reg(doeptsizx) setup_cmd[31:0] = mem[4 ? 2 * rem_supcnt] setup_cmd[63:32] = mem[5 ? 2 * rem_supcnt] ctrl-rd/wr/2 stage find setup cmd type write 2-stage read setup_np_in_pkt status in phase rcv_out_pkt data out phase setup_np_in_pkt data in phase ai15678 usb on-the-go high-speed (otg_hs) RM0033 1198/1317 doc id 15403 rev 3 3. when the application pops the global out nak pattern dword from the receive fifo, the core sets the gonakeff interrupt (otg_hs_gintsts). 4. once the application detects this interrupt, it can assume that the core is in global out nak mode. the application can clear this interrupt by clearing the sgonak bit in otg_hs_dctl. application programming sequence 1. to stop receiving any kind of data in the receive fifo, the application must set the global out nak bit by programming the following field: ? sgonak = 1 in otg_hs_dctl 2. wait for the assertion of the gonakeff interrupt in otg_hs_gintsts. when asserted, this interrupt indicates that the core has stopped receiving any type of data except setup packets. 3. the application can receive valid out packets after it has set sgonak in otg_hs_dctl and before the core asserts the gonakeff interrupt (otg_hs_gintsts). 4. the application can temporarily mask this interrupt by writing to the ginakeffm bit in gintmsk. ? ginakeffm = 0 in gintmsk 5. whenever the application is ready to exit the global out nak mode, it must clear the sgonak bit in otg_hs_dctl. this al so clears the go nakeff interrupt (otg_hs_gintsts). ? otg_hs_dctl = 1 in cgonak 6. if the application has masked this interrupt earlier, it must be unmasked as follows: ? ginakeffm = 1 in gintmsk disabling an out endpoint the application must use this sequence to disable an out endpoint that it has enabled. application programming sequence: 1. before disabling any out endpoint, the application must enable global out nak mode in the core. ? sgonak = 1 in otg_hs_dctl 2. wait for the gonakeff in terrupt (otg_hs_gintsts) 3. disable the required out endpoint by programming the following fields: ? epdis = 1 in otg_hs_doepctlx ? snak = 1 in otg_hs_doepctlx 4. wait for the epdisd in terrupt (otg_hs_doepintx), wh ich indicates that the out endpoint is completely disabled. when the epdisd interrupt is asserted, the core also clears the following bits: ? epdis = 0 in otg_hs_doepctlx ? epena = 0 in otg_hs_doepctlx 5. the application must clear the global out nak bit to start receiving data from other nondisabled out endpoints. ? sgonak = 0 in otg_hs_dctl generic nonisochronous out data transfers RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1199/1317 this section describes a regular nonisochronous out data transfer (control, bulk, or interrupt). application requirements: 1. before setting up an out transfer, the application must allocate a buffer in the memory to accommodate all data to be received as part of the out transfer. 2. for out transfers, the transfer size field in the endpoint?s transfer size register must be a multiple of the maximum packet size of the endpoint, adjusted to the dword boundary. ? transfer size[epnum] = n (mpsiz[epnum] + 4 ? (mpsiz[epnum] mod 4)) ? packet count[epnum] = n ? n > 0 3. on any out endpoint interrupt, the applic ation must read the endpoint?s transfer size register to calculate the size of the payload in the memory. the received payload size can be less than the programmed transfer size. ? payload size in memory = application programmed initial transfer size ? core updated final transfer size ? number of usb packets in which this payload was received = application programmed initial packet count ? core updated final packet count internal data flow: 1. the application must set the transfer size and packet count fields in the endpoint- specific registers, clear the nak bit, and enable the endpoint to receive the data. 2. once the nak bit is cleared, the core starts receiving data and writes it to the receive fifo, as long as there is space in the receive fifo. for every data packet received on the usb, the data packet and its status are written to the receive fifo. every packet (maximum packet size or short packet) written to the receive fifo decrements the packet count field for that endpoint by 1. ? out data packets received with bad data crc are flushed from the receive fifo automatically. ? after sending an ack for the packet on the usb, the core discards nonisochronous out data packets that the host, which cannot detect the ack, re- sends. the application does not detect multiple back-to-back data out packets on the same endpoint with the same data pid. in this case the packet count is not decremented. ? if there is no space in the receive fifo, isochronous or nonisochronous data packets are ignored and not written to the receive fifo. additionally, nonisochronous out tokens receive a nak handshake reply. ? in all the above three cases, the packet count is not decremented because no data are written to the receive fifo. 3. when the packet count becomes 0 or when a short packet is received on the endpoint, the nak bit for that endpoint is set. once the nak bit is set, the isochronous or nonisochronous data packets are ignored and not written to the receive fifo, and nonisochronous out tokens receive a nak handshake reply. 4. after the data are written to the receive fifo, the application reads the data from the receive fifo and writes it to external memory, one packet at a time per endpoint. 5. at the end of every packet write on the ahb to external memory, the transfer size for the endpoint is decremented by the size of the written packet. usb on-the-go high-speed (otg_hs) RM0033 1200/1317 doc id 15403 rev 3 6. the out data transfer completed pattern for an out endpoint is written to the receive fifo on one of the following conditions: ? the transfer size is 0 and the packet count is 0 ? the last out data packet written to the receive fifo is a short packet (0 packet size < maximum packet size) 7. when either the application pops this entry (out data transfer completed), a transfer completed interrupt is generated for the endpoint and the endpoint enable is cleared. application programming sequence: 1. program the otg_hs_doeptsizx register for the transfer size and the corresponding packet count. 2. program the otg_hs_doepctlx register with the endpoint characteristics, and set the epena and cnak bits. ? epena = 1 in otg_hs_doepctlx ? cnak = 1 in otg_hs_doepctlx 3. wait for the rxflvl interrupt (in otg_hs_gintsts) and empty the data packets from the receive fifo. ? this step can be repeated many times, depending on the transfer size. 4. asserting the xfrc interrupt (otg_hs_do epintx) marks a successful completion of the nonisochronous out data transfer. 5. read the otg_hs_doeptsizx register to determine the size of the received data payload. generic isochronous out data transfer this section describes a regular isochronous out data transfer. application requirements: 1. all the application requirements for nonisochronous out data transfers also apply to isochronous out data transfers. 2. for isochronous out data transfers, the transfer size and packet count fields must always be set to the number of maximum-packet-size packets that can be received in a single frame and no more. isochronous out data transfers cannot span more than 1 frame. 3. the application must read all isochronous out data packets from the receive fifo (data and status) before the end of the periodic frame (eopf interrupt in otg_hs_gintsts). 4. to receive data in the following frame, an isochronous out endpoint must be enabled after the eopf (otg_hs_gintsts) a nd before the sof (otg_hs_gintsts). internal data flow: 1. the internal data flow for isochronous out endpoints is the same as that for nonisochronous out endpoints, but for a few differences. 2. when an isochronous out endpoint is enabled by setting the endpoint enable and clearing the nak bits, the even/odd frame bit must also be set appropriately. the core receives data on an isochronous out endpoint in a particular frame only if the following condition is met: ? eonum (in otg_hs_doepctlx) = soffn[0] (in otg_hs_dsts) 3. when the application completely reads an isochronous out data packet (data and status) from the receive fifo, the core updates the rxdpid field in RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1201/1317 otg_hs_doeptsizx with the data pid of the last isochronous out data packet read from the receive fifo. application programming sequence: 1. program the otg_hs_doeptsizx register for the transfer size and the corresponding packet count 2. program the otg_hs_doepctlx register with the endpoint characteristics and set the endpoint enable, clearnak, and even/odd frame bits. ? epena = 1 ?cnak=1 ? eonum = (0: even/1: odd) 3. in slave mode, wait for the rxflvl interrupt (in otg_hs_gintsts) and empty the data packets from the receive fifo ? this step can be repeated many times, depending on the transfer size. 4. the assertion of the xfrc interrupt (in otg_hs_doepintx) marks the completion of the isochronous out data transfer. this inte rrupt does not necessarily mean that the data in memory are good. 5. this interrupt cannot always be detected for isochronous out transfers. instead, the application can detect the iisooxfrm interrupt in otg_hs_gintsts. 6. read the otg_hs_doeptsizx register to determine the size of the received transfer and to determine the validity of the data received in the frame. the application must treat the data received in memory as valid only if one of the following conditions is met: ? rxdpid = d0 (in otg_hs_doeptsizx) and the number of usb packets in which this payload was received = 1 ? rxdpid = d1 (in otg_hs_doeptsizx) and the number of usb packets in which this payload was received = 2 ? rxdpid = d2 (in otg_hs_doeptsizx) and the number of usb packets in which this payload was received = 3 the number of usb packets in which this payload was received = application programmed initial packet count ? core updated final packet count the application can discard invalid data packets. incomplete isochronous out data transfers this section describes the application prog ramming sequence when isochronous out data packets are dropped inside the core. internal data flow: 1. for isochronous out endpoints, the xfrc interrupt (in otg_hs_doepintx) may not always be asserted. if the core drops isochronous out data packets, the application could fail to detect the xfrc interrupt (otg_hs_doepintx) under the following circumstances: ? when the receive fifo cannot accommodate the complete iso out data packet, the core drops the received iso out data ? when the isochronous out data packet is received with crc errors ? when the isochronous out token received by the core is corrupted ? when the application is very slow in reading the data from the receive fifo 2. when the core detects an end of periodic frame before transfer completion to all isochronous out endpoints, it asserts the incomplete isochronous out data interrupt usb on-the-go high-speed (otg_hs) RM0033 1202/1317 doc id 15403 rev 3 (iisooxfrm in otg_hs_gintsts), indicating that an xfrc interrupt (in otg_hs_doepintx) is not asserted on at least one of the isochronous out endpoints. at this point, the endpoint with the incomplete transfer remains enabled, but no active transfers remain in progress on this endpoint on the usb. application programming sequence: 1. asserting the iisooxfrm interrupt (otg_hs_gintsts) indicates that in the current frame, at least one isochronous out endpoint has an incomplete transfer. 2. if this occurs because isochronous out data is not completely emptied from the endpoint, the application must ensure that the application empties all isochronous out data (data and status) from the receive fifo before proceeding. ? when all data are emptied from the receive fifo, the application can detect the xfrc interrupt (otg_hs_doepintx). in this case, the application must re- enable the endpoint to receive isochronous out data in the next frame. 3. when it receives an iisooxfrm interrupt (in otg_hs_gintsts), the application must read the control registers of all isochronous out endpoints (otg_hs_doepctlx) to determ ine which endpoints had an incomplete transfer in the current micro-frame. an endpoint transfer is incomplete if both the following conditions are met: ? eonum bit (in otg_hs_doepctlx) = soffn[0] (in otg_hs_dsts) ? epena = 1 (in otg_hs_doepctlx) 4. the previous step must be performed before the sof interrupt (in otg_hs_gintsts) is detected, to ensure that the current frame number is not changed. 5. for isochronous out endpoints with incomplete transfers, the application must discard the data in the memory and disable the endpoint by setting the epdis bit in otg_hs_doepctlx. 6. wait for the epdis interrupt (in otg_hs_doepintx) and enable the endpoint to receive new data in the next frame. ? because the core can take some time to disable the endpoint, the application may not be able to receive the data in the next frame after receiving bad isochronous data. stalling a nonisochronous out endpoint this section describes how the application can stall a nonisochronous endpoint. 1. put the core in the global out nak mode. 2. disable the required endpoint ? when disabling the endpoint, instead of setting the snak bit in otg_hs_doepctl, set stall = 1 (in otg_hs_doepctl). the stall bit always takes precedence over the nak bit. 3. when the application is ready to end the stall handshake for the endpoint, the stall bit (in otg_hs_doepctlx) must be cleared. 4. if the application is setting or clearing a stall for an endpoint due to a setfeature.endpoint halt or clearfeature.endpoint halt command, the stall bit must be set or cleared before the application sets up the status stage transfer on the control endpoint. RM0033 usb on-the-go high-speed (otg_hs) d o c id 154 03 re v 3 1 203 /13 1 7 exam ples th is sect ion d e scr i b e s and d e p i ct s som e fu nd ame n t a l tr ansf e r t ype s an d sce nar io s . sla v e m ode b u lk out t r an sa ctio n fig u r e 38 8 d epict s th e r e cep t io n o f a sing le bu lk out dat a p a c k e t fr om th e usb t o t h e ahb a nd de scr i b e s t h e e v en ts in v o lv ed in t h e p r o c e s s . fi gu re 38 8. sl a v e mod e b u l k o u t t r an sac ti on af t e r a set c o n f i gu r a t i on /se t i n t e r f ace comm and , t h e ap plicat ion init ializ e s a ll out en dp oint s b y setting cnak = 1 and epen a = 1 (in o t g_ hs_doe pctlx), and setting a suitab le xfrsiz and pktcnt in the o t g_hs_doeptsizx register . 1. ho st a tte m p ts to s e n d da ta ( o u t to k e n ) to an e n d p o in t. 2 . when th e core re ce iv es t h e out t o k e n on t h e usb , it st or es t h e pac k e t in th e rxf i fo be ca use space is a v a ilab l e th er e . 3. af ter w r it ing t h e co m p le te p a c k e t in th e r xfifo , t h e c o r e th en a sse r t s th e rxfl vl in te rr u p t (in o t g _ h s _g int s t s ) . 4 . on r e ce iv ing t he pktcnt n u mb er o f usb pac k e ts , th e co re int e r n a lly se ts t h e nak b i t f o r th is e n d p o in t to p r e v en t it fr o m re ce ivin g a n y m o r e pa c k e t s . 5 . the app lica t ion pr ocesses th e int e r r upt an d re ads th e da ta f r om t he rxfif o . 6 . when t h e app licat ion ha s r ead all th e da ta ( e q u iv ale n t t o xfrsi z ), th e core gen er a t e s an xfrc interr upt (in o t g_hs_doe pintx). 7 . the app lica t ion pr ocesses th e int e r r upt an d uses th e se tt in g of t h e xfrc int e r r up t bit ( i n o t g _ h s _d oep i ntx) to d e t e r m ine t h a t t h e in te nd e d tr an sf er is com p let e . init_ou t _ e p ho s t de v i c e us b o u t a c k rxflvl intr i wr_ r e g ( d o ept si z x ) w r _r e g(doepctlx) 512 bytes o u t n a k xa ct _1 a p p lic a t ion xfrc i n t r d o e p c t l x . n a k = 1 pktcnt 0 xfrsiz = 0 r i d le u n t i l in t r rc v _ o ut _pkt() i d le u ntil intr on new x f e r o r r x fi fo not em pt y 1 2 3 4 5 6 7 8 xfrsiz = 51 2 b y t e s pktcnt = 1 epena = 1 c n ak = 1 ai15679 usb on-the-go high-speed (otg_hs) RM0033 1204/1317 doc id 15403 rev 3 in data transfers packet write this section describes how the application writes data packets to the endpoint fifo in slave mode when dedicated transmit fifos are enabled. 1. the application can either choose the polling or the interrupt mode. ? in polling mode, the application monitors th e status of the endpoint transmit data fifo by reading the otg_hs_dtxfstsx register, to determine if there is enough space in the data fifo. ? in interrupt mode, the application waits for the txfe interrupt (in otg_hs_diepintx) and then reads the otg_hs_dtxfstsx register, to determine if there is enough space in the data fifo. ? to write a single nonzero length data packet, there must be space to write the entire packet in the data fifo. ? to write zero length packet, the application must not look at the fifo space. 2. using one of the above mentioned methods, when the application determines that there is enough space to write a transmit packet, the application must first write into the endpoint control register, before writing the data into the data fifo. typically, the application, must do a read modify write on the otg_hs_diepctlx register to avoid modifying the contents of the register, except for setting the endpoint enable bit. the application can write multiple packets for the same endpoint into the transmit fifo, if space is available. for periodic in endpoints, the application must write packets only for one micro-frame. it can write packets for the next periodic transaction only after getting transfer complete for the previous transaction. setting in endpoint nak internal data flow: 1. when the application sets the in nak for a particular endpoint, the core stops transmitting data on the end point, irrespective of data availability in the endpoint?s transmit fifo. 2. nonisochronous in tokens receive a nak handshake reply ? isochronous in tokens receive a zero-data-length packet reply 3. the core asserts the inepne (in endpoint nak effective) interrupt in otg_hs_diepintx in re sponse to the snak bit in otg_hs_diepctlx. 4. once this interrupt is seen by the application, the application can assume that the endpoint is in in nak mode. this interrupt can be cleared by the application by setting the cnak bit in otg_hs_diepctlx. application programming sequence: RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1205/1317 1. to stop transmitting any data on a particular in endpoint, the application must set the in nak bit. to set this bit, the following field must be programmed. ? snak = 1 in otg_hs_diepctlx 2. wait for assertion of the inepne interr upt in otg_hs_diepint x. this interrupt indicates that the core has stopped transmitting data on the endpoint. 3. the core can transmit valid in data on the endpoint after the application has set the nak bit, but before the assertion of the nak effective interrupt. 4. the application can mask this interrupt te mporarily by writing to the inepnem bit in diepmsk. ? inepnem = 0 in diepmsk 5. to exit endpoint nak mode , the application must clear t he nak status bit (naksts) in otg_hs_diepctlx. this also clears the inepne interrupt (in otg_hs_diepintx). ? cnak = 1 in otg_hs_diepctlx 6. if the application masked this interrupt earlier, it must be unmasked as follows: ? inepnem = 1 in diepmsk in endpoint disable use the following sequence to disable a specif ic in endpoint that has been previously enabled. application programming sequence: 1. the application must stop writing data on the ahb for the in endpoint to be disabled. 2. the application must set the endpoint in nak mode. ? snak = 1 in otg_hs_diepctlx 3. wait for the inepne inte rrupt in otg_hs_diepintx. 4. set the following bits in the otg_hs_diepctlx register for the endpoint that must be disabled. ? epdis = 1 in otg_hs_diepctlx ? snak = 1 in otg_hs_diepctlx 5. assertion of the epdisd interrupt in otg_hs_diepintx indicates that the core has completely disabled the specified endpoint. along with the assertion of the interrupt, the core also clears the following bits: ? epena = 0 in otg_hs_diepctlx ? epdis = 0 in otg_hs_diepctlx 6. the application must read the otg_hs_dieptsizx register for the periodic in ep, to calculate how much data on the endpoint were transmitted on the usb. 7. the application must flush the data in the endpoint transmit fifo, by setting the following fields in the otg_hs_grstctl register: ? txfnum (in otg_hs_grstctl) = en dpoint transmit fifo number ? txfflsh in (otg_hs_grstctl) = 1 the application must poll the otg_hs_grstctl register, until the txfflsh bit is cleared by the core, which indicates the end of flush operation. to transmit new data on this endpoint, the application can re-enable the endpoint at a later point. generic nonperiodic in data transfers application requirements: usb on-the-go high-speed (otg_hs) RM0033 1206/1317 doc id 15403 rev 3 1. before setting up an in transfer, the application must ensure that all data to be transmitted as part of the in transfer are part of a single buffer. 2. for in transfers, the transfer size field in the endpoint transfer size register denotes a payload that constitutes multiple maximum-packet-size packets and a single short packet. this short packet is transmitted at the end of the transfer. ? to transmit a few maximum-packet-size packets and a short packet at the end of the transfer: transfer size[epnum] = x mpsiz[epnum] + sp if (sp > 0), then packet count[epnum] = x + 1. otherwise, packet count[epnum] = x ? to transmit a single zero-length data packet: transfer size[epnum] = 0 packet count[epnum] = 1 ? to transmit a few maximum-packet-size packets and a zero-length data packet at the end of the transfer, the application must split the transfer into two parts. the first sends maximum-packet-size data pa ckets and the second sends the zero- length data packet alone. first transfer: transfer size[epnum] = x mpsiz[epnum]; packet count = n ; second transfer: transfer size[epnum] = 0; packet count = 1; 3. once an endpoint is enabled for data transfers, the core updates the transfer size register. at the end of the in transfer, the application must read the transfer size register to determine how much data posted in the transmit fifo have already been sent on the usb. 4. data fetched into transmit fifo = application-programmed initial transfer size ? core- updated final transfer size ? data transmitted on usb = (application-pr ogrammed initial packet count ? core updated final packet count) mpsiz[epnum] ? data yet to be transmitted on usb = (app lication-programmed initial transfer size ? data transmitted on usb) internal data flow: 1. the application must set the transfer size and packet count fields in the endpoint- specific registers and enable the endpoint to transmit the data. 2. the application must also write the required data to the transmit fifo for the endpoint. 3. every time a packet is written into the transmit fifo by the application, the transfer size for that endpoint is decremented by the packet size. the data is fetched from the memory by the application, until the transfer size for the endpoint becomes 0. after writing the data into the fifo, the ?number of packets in fifo? count is incremented (this is a 3-bit count, internally maintained by the core for each in endpoint transmit fifo. the maximum number of packets maintained by the core at any time in an in endpoint fifo is eight). for zero-length packets, a separate flag is set for each fifo, without any data in the fifo. 4. once the data are written to the transmit fifo, the core reads them out upon receiving an in token. for every nonisochronous in data packet transmitted with an ack RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1207/1317 handshake, the packet count for the endpoint is decremented by one, until the packet count is zero. the packet count is not decremented on a timeout. 5. for zero length packets (indicated by an internal zero length flag), the core sends out a zero-length packet for the in token and decrements the packet count field. 6. if there are no data in the fifo for a received in token and the packet count field for that endpoint is zero, the core generates an ?in token received when txfifo is empty? (ittxfe) interrupt for the endpoint, provided that the endpoint nak bit is not set. the core responds with a nak handshake for nonisochronous endpoints on the usb. 7. the core internally rewinds the fifo pointers and no timeout interrupt is generated. 8. when the transfer size is 0 and the packet count is 0, the transfer complete (xfrc) interrupt for the endpoint is generated and the endpoint enable is cleared. application programming sequence: 1. program the otg_hs_dieptsizx register with the transfer size and corresponding packet count. 2. program the otg_hs_diepctlx register with the endpoint characteristics and set the cnak and epena (endpoint enable) bits. 3. when transmitting nonzero length data packet, the application must poll the otg_hs _dtxfstsx register (where x is the fifo number associated with that endpoint) to determine whether there is enough space in the data fifo. the application can optionally use txfe (in otg_hs_diepintx) before writing the data. generic periodic in data transfers this section describes a typica l periodic in data transfer. application requirements: 1. application requirements 1, 2, 3, and 4 of generic nonperiodic in data transfers on page 1205 also apply to periodic in data transfers, except for a slight modification of requirement 2. ? the application can only transmit multiples of maximum-packet-size data packets or multiples of maximum-packet-size packets, plus a short packet at the end. to usb on-the-go high-speed (otg_hs) RM0033 1208/1317 doc id 15403 rev 3 transmit a few maximum-packet-size packets and a short packet at the end of the transfer, the following conditions must be met: transfer size[epnum] = x mpsiz[epnum] + sp (where x is an integer 0, and 0 sp < mpsiz[epnum]) if (sp > 0), packet count[epnum] = x + 1 otherwise, packet count[epnum] = x ; mcnt[epnum] = packet count[epnum] ? the application cannot transmit a zero-length data packet at the end of a transfer. it can transmit a single zero-length data pa cket by itself. to transmit a single zero- length data packet: ? transfer size[epnum] = 0 packet count[epnum] = 1 mcnt[epnum] = packet count[epnum] 2. the application can only schedule data transfers one frame at a time. ? (mcnt ? 1) mpsiz xfersiz mcnt mpsiz ? pktcnt = mcnt (in otg_hs_dieptsizx) ? if xfersiz < mcnt mpsiz, the last data packet of the transfer is a short packet. ? note that: mcnt is in otg_hs_diept sizx, mpsiz is in otg_hs_diepctlx, pktcnt is in otg_hs_dieptsizx an d xfersiz is in otg_hs_dieptsizx 3. the complete data to be transmitted in the frame must be written into the transmit fifo by the application, before the in token is received. even when 1 dword of the data to be transmitted per frame is missing in the transmit fifo when the in token is received, the core behaves as when the fifo is empty. when the transmit fifo is empty: ? a zero data length packet would be transmitted on the usb for isochronous in endpoints ? a nak handshake would be transmitted on the usb for interrupt in endpoints 4. for a high-bandwidth in endpoint with three packets in a frame, the application can program the endpoint fifo size to be 2 max_pkt_size and have the third packet loaded in after the first packet has been transmitted on the usb. internal data flow: 1. the application must set the transfer size and packet count fields in the endpoint- specific registers and enable the endpoint to transmit the data. 2. the application must also write the required data to the associated transmit fifo for the endpoint. 3. every time the application writes a packet to the transmit fifo, the transfer size for that endpoint is decremented by the packet size. the data are fetched from application memory until the transfer size for the endpoint becomes 0. 4. when an in token is received for a periodic endpoint, the core transmits the data in the fifo, if available. if the complete data payload (complete packet, in dedicated fifo mode) for the frame is not present in the fifo, then the core generates an in token received when txfifo empty interrupt for the endpoint. ? a zero-length data packet is transmitted on the usb for isochronous in endpoints ? a nak handshake is transmitted on the usb for interrupt in endpoints 5. the packet count for the endpoint is decremented by 1 under the following conditions: RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1209/1317 ? for isochronous endpoints, when a zero- or nonzero-length data packet is transmitted ? for interrupt endpoints, when an ack handshake is transmitted ? when the transfer size and packet count are both 0, the transfer completed interrupt for the endpoint is generated and the endpoint enable is cleared. 6. at the ?periodic frame interval? (controlled by pfivl in otg_hs_dcfg), when the core finds nonempty any of the isochron ous in endpoint fifos scheduled for the current frame nonempty, the core generates an iisoixfr interrupt in otg_hs_gintsts. application programming sequence: 1. program the otg_hs_diepctlx register with the endpoint characteristics and set the cnak and epena bits. 2. write the data to be transmitted in the next frame to the transmit fifo. 3. asserting the ittxfe interrupt (in otg_hs_diepintx) indicates that the application has not yet written all data to be transmitted to the transmit fifo. 4. if the interrupt endpoint is already enabled when this interrupt is detected, ignore the interrupt. if it is not enabled, enable the endpoint so that the data can be transmitted on the next in token attempt. 5. asserting the xfrc interrupt (in otg_hs_diepintx) with no ittxfe interrupt in otg_hs_diepintx indicates the successful co mpletion of an isochronous in transfer. a read to the otg_hs_dieptsizx register must give transfer size = 0 and packet count = 0, indicating all data were transmitted on the usb. 6. asserting the xfrc interrupt (in otg_hs_diepintx), with or without the ittxfe interrupt (in otg_hs_diepintx), indicates the successful completion of an interrupt in transfer. a read to the otg_hs_dieptsizx register must give transfer size = 0 and packet count = 0, indicating all data were transmitted on the usb. 7. asserting the incomplete isochronous in transfer (iisoixfr) interrupt in otg_hs_gintsts with none of the aforementioned interrupts indicates the core did not receive at least 1 periodic in token in the current frame. incomplete isochronous in data transfers this section describes what the application must do on an incomplete isochronous in data transfer. internal data flow: 1. an isochronous in transfer is treated as in complete in one of the following conditions: a) the core receives a corrupted isochronous in token on at least one isochronous in endpoint. in this case, the application detects an incomplete isochronous in transfer interrupt (iisoixfr in otg_hs_gintsts). b) the application is slow to write the complete data payload to the transmit fifo and an in token is received before the complete data payload is written to the fifo. in this case, the application detects an in token received when txfifo empty interrupt in otg_hs_diepintx. the application can ignore this interrupt, as it eventually results in an incomplete isochro nous in transfer interrupt (iisoixfr in otg_hs_gintsts) at the end of periodic frame. the core transmits a zero-length data packet on the usb in response to the received in token. usb on-the-go high-speed (otg_hs) RM0033 1210/1317 doc id 15403 rev 3 2. the application must stop writing the data payload to the transmit fifo as soon as possible. 3. the application must set the nak bit and the disable bit for the endpoint. 4. the core disables the endpoint, clears the disable bit, and asserts the endpoint disable interrupt for the endpoint. application programming sequence 1. the application can ignore the in token received when txfifo empty interrupt in otg_hs_diepintx on any isochronous in endpoint, as it eventually results in an incomplete isochronous in transfer interrupt (in otg_hs_gintsts). 2. assertion of the incomplete isochronous in transfer interrupt (in otg_hs_gintsts) indicates an incomplete isochronous in trans fer on at least one of the isochronous in endpoints. 3. the application must read the endpoint control register for all isochronous in endpoints to detect endpoints with incomplete in data transfers. 4. the application must stop writing data to the periodic transmit fifos associated with these endpoints on the ahb. 5. program the following fields in the otg_hs_diepctlx register to disable the endpoint: ? snak = 1 in otg_hs_diepctlx ? epdis = 1 in otg_hs_diepctlx 6. the assertion of the endpoint disabled interrupt in otg_hs_diepintx indicates that the core has disabled the endpoint. ? at this point, the application must flush the data in the associated transmit fifo or overwrite the existing data in the fifo by enabling the endpoint for a new transfer in the next micro-frame. to flush the data, the application must use the otg_hs_grstctl register. stalling nonisochronous in endpoints this section describes how the application can stall a nonisochronous endpoint. application programming sequence: 1. disable the in endpoint to be stalled. set the stall bit as well. 2. epdis = 1 in otg_hs_diepctlx, when the endpoint is already enabled ? stall = 1 in otg_hs_diepctlx ? the stall bit always takes precedence over the nak bit 3. assertion of the endpoint disabled interrupt (in otg_hs_diepintx) indicates to the application that the core has disabled the specified endpoint. 4. the application must flush the nonperiodic or periodic transmit fifo, depending on the endpoint type. in case of a nonperiodic endpoint, the application must re-enable the other nonperiodic endpoints that do not need to be stalled, to transmit data. 5. whenever the application is ready to end the stall handshake for the endpoint, the stall bit must be cleared in otg_hs_diepctlx. 6. if the application sets or clears a stall bit for an endpoint due to a setfeature.endpoint halt command or clearfeature.endpoint halt command, the stall bit must be set or cleared before the application sets up the status stage transfer on the control endpoint. special case: stalling the control out endpoint RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1211/1317 the core must stall in/out tokens if, during the data stage of a control transfer, the host sends more in/out tokens than are specified in the setup packet. in this case, the application must enable the ittxfe interrupt in otg_hs_diepintx and the otepdis interrupt in otg_hs_doepintx during the data stage of the control transfer, after the core has transferred the amount of data specified in the setup packet. then, when the application receives this interrupt, it must set the stall bit in the corresponding endpoint control register, and clear this interrupt. 30.13.8 worst case response time when the otg_hs controller acts as a device, there is a worst case response time for any tokens that follow an isochronous out. this worst case response time depends on the ahb clock frequency. the core registers are in the ahb domain, and the core does not accept another token before updating these register values. the worst case is for any token following an isochronous out, because for an isochronous transaction, there is no handshake and the next token could come sooner. this worst case value is 7 phy clocks when the ahb clock is the same as the phy clock. when the ahb clock is faster, this value is smaller. if this worst case condition occurs, the core responds to bulk/interrupt tokens with a nak and drops isochronous and setup tokens. the ho st interprets this as a timeout condition for setup and retries the setup packet. for isochronous transfers, the incomplete isochronous in transfer interrupt (iisoixfr) and incomplete isochronous out transfer interrupt (iisooxfr) inform the application that isochronous in/out packets were dropped. choosing the value of trdt in otg_hs_gusbcfg the value in trdt (otg_hs_gusbcfg) is the ti me it takes for the mac, in terms of phy clocks after it has received an in token, to get the fifo status, and thus the first data from the pfc block. this time involves the synchronization delay between the phy and ahb clocks. the worst case delay for this is when the ahb clock is the same as the phy clock. in this case, the delay is 5 clocks. once the mac receives an in token, this information (token received) is synchronized to the ahb clock by the pfc (the pfc runs on the ahb clock). the pfc then reads the data from the spram and writes them into the dual clock source buffer. the mac then reads the data out of the source buffer (4 deep). if the ahb is running at a higher frequency than the phy, the application can use a smaller value for trdt (in otg_hs_gusbcfg). figure 389 has the following signals: tkn_rcvd: token received information from mac to pfc dynced_tkn_rcvd: doubled sync tkn_rcvd, from pclk to hclk domain spr_read: read to spram spr_addr: address to spram spr_rdata: read data from spram srcbuf_push: push to the source buffer srcbuf_rdata: read data from the source buffer. data seen by mac usb on-the-go high-speed (otg_hs) RM0033 1212/1317 doc id 15403 rev 3 the application can use the following formula to calculate the value of trdt: 4 ahb clock + 1 phy clock = (2 clock sy nc + 1 clock memory address + 1 clock memory data from sync ram) + (1 phy clock (next phy clock mac can sample the 2 clock fifo outputs) figure 389. trdt max timing case 30.13.9 otg programming model the otg_hs controller is an otg device supporting hnp and srp. when the core is connected to an ?a? plug, it is referred to as an a-device. when the core is connected to a ?b? plug it is referred to as a b-device. in host mode, the otg_hs controller turns off v bus to conserve power. srp is a method by which the b-device signals the a-device to turn on v bus power. a device must perform both data-line pulsing and v bus pulsing, but a host can detect either data-line pulsing or v bus pulsing for srp. hnp is a method by which the b- device negotiates and switches to host role. in negotiated mode after hnp, the b-device suspends the bus and reverts to the device role. 12345678 0ns 50ns 100ns 150ns 200ns hclk pclk tkn_rcvd dsynced_tkn_rcvd spr_read spr_addr spr_rdata srcbuf_push srcbuf_rdata 5 clocks d1 a1 d1 ai15680 RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1213/1317 a-device session request protocol the application must set the srp-capable bit in the core usb configuration register. this enables the otg_hs controller to detect srp as an a-device. figure 390. a-device srp 1. drv_vbus = v bus drive signal to the phy vbus_valid = v bus valid signal from phy a_valid = a-device v bus level signal to phy dp = data plus line dm = data minus line 1. to save power, the application suspends and turns off port power when the bus is idle by writing the port suspend and port power bits in the host port control and status register. 2. phy indicates port power off by deasserting the vbus_valid signal. 3. the device must detect se0 for at least 2 ms to start srp when v bus power is off. 4. to initiate srp, the device turns on its data line pull-up resistor for 5 to 10 ms. the otg_hs controller dete cts data-line pulsing. 5. the device drives v bus above the a-device session valid (2.0 v minimum) for v bus pulsing. the otg_hs controller interrupts the application on detecting srp. the session request detected bit is set in global interrupt status register (srqint set in otg_hs_gintsts). 6. the application must service the session request detected interrupt and turn on the port power bit by writing the port power bit in the host port control and status register. the phy indicates port power-on by asserting the vbus_valid signal. 7. when the usb is powered, the device connects, completing the srp process. a i156 8 1 b drv_vbu s vbu s _valid a_valid otg_h s _f s _dp otg_h s _f s _dm sus pend v bu s p u l s ing d a t a line p u l s ing connect 1 6 2 5 3 47 low usb on-the-go high-speed (otg_hs) RM0033 1214/1317 doc id 15403 rev 3 b-device session request protocol the application must set the srp-capable bit in the core usb configuration register. this enables the otg_hs controller to initiate srp as a b-device. srp is a means by which the otg_hs controller can request a new session from the host. figure 391. b-device srp 1. vbus_valid = v bus valid signal from phy b_valid = b-device valid session to phy dischrg_vbus = discharge signal to phy sess_end = session end signal to phy chrg_vbus = charge v bus signal to phy dp = data plus line dm = data minus line 1. to save power, the host suspends and turns off port power when the bus is idle. the otg_hs controller sets the early suspend bit in the core interrupt register after 3 ms of bus idleness. following this, the otg_hs controller sets the usb suspend bit in the core interrupt register. the otg_hs controller informs the phy to discharge v bus . 2. the phy indicates the session?s end to the de vice. this is the initial condition for srp. the otg_hs controller requires 2 ms of se0 before initiating srp. for a usb 1.1 full-speed serial transceiver, the application must wait until v bus discharges to 0.2 v afte r bsvld (in otg_hs_gotgctl) is deasserted. this a i156 8b 2 vbu s _valid b_valid di s chrg_vbu s s e ss _end otg_h s _f s _dp otg_h s _f s _dm chrg_vbu s sus pend d a t a line p u l s ing connect v bu s p u l s ing 1 6 2 3 4 5 8 7 low RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1215/1317 discharge time can be obtained from the transceiver vendor and varies from one transceiver to another. 3. the usb otg core informs the phy to speed up v bus discharge. 4. the application init iates srp by writing the session re quest bit in the otg control and status register. the otg_hs controller perform data-line pulsing followed by v bus pulsing. 5. the host detects srp from either the data-line or v bus pulsing, and turns on v bus . the phy indicates v bus power-on to the device. 6. the otg_hs controller performs v bus pulsing. the host starts a new session by turning on v bus , indicating srp success. the otg_hs controller interrupts the applicatio n by setting the session request success status change bit in the otg interrupt status register. the application reads the session request success bit in the otg control and status register. 7. when the usb is powered, the otg_hs controller connects, completing the srp process. a-device host negotiation protocol hnp switches the usb host role from the a-device to the b-device. the application must set the hnp-capable bit in the core usb configuration register to enable the otg_hs controller to perform hnp as an a-device. figure 392. a-device hnp 1. dppulldown = signal from core to phy to enable/ disable the pull-down on the dp line inside the phy. dmpulldown = signal from core to phy to enable/di sable the pull-down on the dm line inside the phy. 1. the otg_hs controller sends the b-device a setfeature b_hnp_enable descriptor to enable hnp support. the b-device?s ack response indicates that the b-device supports hnp. the application must set hos t set hnp enable bit in the otg control a i156 83b otg core dp dm dppulldown dmpulldown ho s t device ho s t 1 sus pend 2 3 45 re s et 6 tr a ffic 7 8 connect tr a ffic usb on-the-go high-speed (otg_hs) RM0033 1216/1317 doc id 15403 rev 3 and status register to indicate to the otg_hs controller that the b-device supports hnp. 2. when it has finished using the bus, the application suspends by writing the port suspend bit in the host port control and status register. 3. when the b-device observes a usb suspend, it disconnects, indicating the initial condition for hnp. the b-device initiates hnp only when it must swit ch to the host role; otherwise, the bus continues to be suspended. the otg_hs controller sets the host negotiation detected interrupt in the otg interrupt status register, indicating the start of hnp. the otg_hs controller deasserts the dm pull down and dm pull down in the phy to indicate a device role. the phy enables the otg_hs_dp pull-up resistor to indicate a connect for b-device. the application must read the current mode bit in the otg control and status register to determine peripheral mode operation. 4. the b-device detects the connection, issues a usb reset, and enumerates the otg_hs controller for data traffic. 5. the b-device continues the host role, initiating traffic, and suspends the bus when done. the otg_hs controller sets the early suspend bit in the core interrupt register after 3 ms of bus idleness. following this, the otg_ hs controller sets the usb suspend bit in the core interrupt register. 6. in negotiated mode, the otg_hs controller detects the suspend, disconnects, and switches back to the host role. the otg_hs controller asserts the dm pull down and dm pull down in the phy to indicate its assumption of the host role. 7. the otg_hs controller sets the connector id status change interrupt in the otg interrupt status register. the application must read the connector id status in the otg control and status register to determine the otg_hs controller operation as an a- device. this indicates the completion of hnp to the application. the application must read the current mode bit in the otg control and status register to determine host mode operation. 8. the b-device connects, completing the hnp process. b-device host negotiation protocol hnp switches the usb host role from b-device to a-device. the application must set the hnp-capable bit in the core usb configuration register to enable the otg_hs controller to perform hnp as a b-device. RM0033 usb on-the-go high-speed (otg_hs) doc id 15403 rev 3 1217/1317 figure 393. b-device hnp 1. dppulldown = signal from core to phy to enable/ disable the pull-down on the dp line inside the phy. dmpulldown = signal from core to phy to enable/di sable the pull-down on the dm line inside the phy. 1. the a-device sends the setfeature b_hnp_enable descriptor to enable hnp support. the otg_hs controller?s ack response indicates that it supports hnp. the application must set the device hnp enable bit in the otg control and status register to indicate hnp support. the application sets the hnp request bit in the otg control and status register to indicate to the otg_hs controller to initiate hnp. 2. when it has finished using the bus, the a-device suspends by writing the port suspend bit in the host port control and status register. the otg_hs controller sets the early suspend bit in the core interrupt register after 3 ms of bus idleness. following this, the otg_hs controller sets the usb suspend bit in the core interrupt register. the otg_hs controller disconnects and the a-device detects se0 on the bus, indicating hnp. the otg_hs controller assert s the dp pull down and dm pull down in the phy to indicate its assumption of the host role. the a-device responds by activating its otg_hs_dp pull-up resistor within 3 ms of detecting se0. the otg_hs controller detects this as a connect. the otg_hs controller sets the host negotiation success status change interrupt in the otg interrupt status register, indicating the hnp status. the application must read the host negotiation success bit in the otg control and status register to determine a i156 8 4 b otg core dp dm dppulldown dmpulldown ho s t device device 1 sus pend 2 3 45 re s et 6 tr a ffic 7 8 connect tr a ffic usb on-the-go high-speed (otg_hs) RM0033 1218/1317 doc id 15403 rev 3 host negotiation success. the application must read the current mode bit in the core interrupt register (otg_hs_gintsts) to determine host mode operation. 3. the application sets the reset bit (prst in otg_hs_hprt) and the otg_hs controller issues a usb reset and enumerates the a-device for data traffic. 4. the otg_hs controller continues the host role of initiating traffic, and when done, suspends the bus by writing the port suspend bit in the host port control and status register. 5. in negotiated mode, when the a-device detects a suspend, it disconnects and switches back to the host role. the otg_hs controller deasserts the dp pull down and dm pull down in the phy to indicate the assumption of the device role. 6. the application must read the current mode bit in the core interrupt (otg_hs_gintsts) register to determine the host mode operation. 7. the otg_hs controller connects, completing the hnp process. RM0033 flexible static memory controller (fsmc) doc id 15403 rev 3 1219/1317 31 flexible static memory controller (fsmc) 31.1 fsmc main features the fsmc block is able to interface with synchronous and asynchronous memories and 16- bit pc memory cards. its main purpose is to: translate the ahb transactions into the appropriate external device protocol meet the access timing requirements of the external devices all external memories share the addresses, data and control signals with the controller. each external device is accessed by means of a unique chip select. the fsmc performs only one access at a time to an external device. the fsmc has the following main features: interfaces with static memory-mapped devices including: ? static random access memory (sram) ? read-only memory (rom) ? nor flash memory/onenand flash memory ? psram (4 memory banks) two banks of nand flash with ecc hardware that checks up to 8 kbytes of data 16-bit pc card compatible devices supports burst mode access to synchronous devices (nor flash and psram) 8- or 16-bit wide databus independent chip select control for each memory bank independent configuration for each memory bank programmable timings to support a wide range of devices, in particular: ? programmable wait states (up to 15) ? programmable bus turnaround cycles (up to 15) ? programmable output enable and write enable delays (up to 15) ? independent read and write timings and protocol, so as to support the widest variety of memories and timings write enable and byte lane select outputs for use with psram and sram devices translation of 32-bit wide ahb transactions into consecutive 16-bit or 8-bit accesses to external 16-bit or 8-bit devices a write fifo, 2 words long, each word is 32 bits wide, only stores data and not the address. therefore, this fifo only buffers ahb write burst transactions. this makes it possible to write to slow memories and free the ahb quickly for other operations. only one burst at a time is buffered: if a new ahb burst or single transaction occurs while an operation is in progress, the fifo is drain ed. the fsmc will insert wait states until the current memory access is complete). external asynchronous wait control the fsmc registers that define the external de vice type and associated characteristics are usually set at boot time and do not change until the next reset or power-up. however, it is possible to change the settings at any time. flexible static memory controller (fsmc) RM0033 1220/1317 doc id 15403 rev 3 31.2 block diagram the fsmc consists of four main blocks: the ahb interface (including the fsmc configuration registers) the nor flash/psram controller the nand flash/pc card controller the external device interface the block diagram is shown in figure 394 . figure 394. fsmc block diagram 31.3 ahb interface the ahb slave interface enables internal cpus and other bus master peripherals to access the external static memories. ahb transactions are translated into the external device protocol. in particular, if the selected external memory is 16 or 8 bits wide, 32-bit wide transactions on the ahb are split into consecutive 16- or 8-bit accesses. ahb bus f s mc interr u pt to nvic nor hclk from clock controller controller memory nand/pc c a rd controller memory config u r a tion regi s ter s s ign a l s nand s ign a l s s h a red s ign a l s nor/p s ram f s mc_ne[4:1] f s mc_nl (or nadv) f s mc_nwait f s mc_a[25:0] f s mc_d[15:0] f s mc_noe f s mc_nwe f s mc_niord f s mc_nreg f s mc_cd s ign a l s pc c a rd a i15591 f s mc_nbl[1:0] f s mc_nce[ 3 :2] f s mc_int[ 3 :2] f s mc_intr f s mc_nce4_1 f s mc_nce4_2 f s mc_niowr f s mc_clk RM0033 flexible static memory controller (fsmc) doc id 15403 rev 3 1221/1317 the fsmc generates an ahb error in the following conditions: when reading or writing to an fsmc bank which is not enabled when reading or writing to the nor flash bank while the faccen bit is reset in the fsmc_bcrx register. when reading or writing to the pc card banks while the input pin fsmc_cd (card presence detection) is low. the effect of this ahb error depends on the ahb master which has attempted the r/w access: if it is the cortex?-m3 cpu, a hard fault interrupt is generated if is a dma, a dma transfer error is generated and the corresponding dma channel is automatically disabled. the ahb clock (hclk) is the reference clock for the fsmc. 31.3.1 supported me mories and transactions general transaction rules the requested ahb transaction data size can be 8-, 16- or 32-bit wide whereas the accessed external device has a fixed data width. this may lead to inconsistent transfers. therefore, some simple transaction rules must be followed: ahb transaction size and memory data size are equal there is no issue in this case. ahb transaction size is greater than the memory size in this case, the fsmc splits the ahb transaction into smaller consecutive memory accesses in order to meet the external data width. ahb transaction size is smaller than the memory size asynchronous transfers may or not be consistent depending on the type of external device. ? asynchronous accesses to devices that have the byte select feature (sram, rom, psram). in this case, the fsmc allows read/write transactions and accesses the right data through its byte lanes bl[1:0] ? asynchronous accesses to devices that do not have the byte select feature (nor and nand flash 16-bit). this situation occurs when a byte access is requested to a 16-bit wide flash memory. clearly, the device cannot be accessed in byte mode (only 16-bit words can be read from/written to the flash memory) therefore: a) write transactions are not allowed b) read transactions are allowed (the controller reads the entire 16-bit memory word and uses the needed byte only). configuration registers the fsmc can be configured using a register set. see section 31.5.6 , for a detailed description of the nor flash/psram controller registers. see section 31.6.8 , for a detailed description of the nand flash/pc card registers. flexible static memory controller (fsmc) RM0033 1222/1317 doc id 15403 rev 3 31.4 external device address mapping from the fsmc point of view, the external memory is divided into 4 fixed-size banks of 256 mbytes each (refer to figure 395 ): bank 1 used to address up to 4 nor flash or psram memory devices. this bank is split into 4 nor/psram regions with 4 dedicated chip select. banks 2 and 3 used to address nand flash devices (1 device per bank) bank 4 used to address a pc card device for each bank the type of memory to be used is user-defined in the configuration register. figure 395. fsmc memory banks 31.4.1 nor/psram address mapping haddr[27:26] bits are used to select one of the four memory banks as shown in ta b l e 1 6 2 . bank 1 nand flash nor / psram suppo rted memory type banks 4 64 mb 6000 0000h 6ff f fff fh address 7000 0000h 7ff f fff fh 8000 0000h 8ff f fff fh 9000 0000h 9ff f fff fh bank 2 4 64 mb bank 3 4 64 mb bank 4 4 64 mb pc ca rd ai14719 table 162. nor/psram bank selection haddr[27:26] (1) 1. haddr are internal ahb address lines t hat are translated to external memory. selected bank 00 bank 1 nor/psram 1 01 bank 1 nor/psram 2 10 bank 1 nor/psram 3 11 bank 1 nor/psram 4 RM0033 flexible static memory controller (fsmc) doc id 15403 rev 3 1223/1317 haddr[25:0] contain the external memory address. since haddr is a byte address whereas the memory is addressed in words, the address actually issued to the memory varies according to the memory data width, as shown in the following table. wrap support for nor flash/psram wrap burst mode for synchronous memories is not supported. the memories must be configured in linear burst mode of undefined length. 31.4.2 nand/pc card address mapping in this case, three banks are available, each of them divided into memory spaces as indicated in ta b l e 1 6 4 . for nand flash memory, the common and attr ibute memory spaces are subdivided into three sections (see in ta bl e 1 6 5 below) located in the lower 256 kbytes: data section (first 64 kbytes in the common/attribute memory space) command section (second 64 kbytes in the common / attribute memory space) address section (next 128 kbytes in the common / attribute memory space) table 163. external memory address memory width (1) 1. in case of a 16-bit external memory width, the fs mc will internally use haddr[25:1] to generate the address for external memory fsmc_a[24:0]. whatever the external memory widt h (16-bit or 8-bit), fs mc_a[0] should be connected to external memory address a[0]. data address issued to the memory maximum memo ry capacity (bits) 8-bit haddr[25:0] 64 mbytes x 8 = 512 mbit 16-bit haddr[25:1] >> 1 64 mbytes/2 x 16 = 512 mbit table 164. memory mapping and timing registers start address end address fsmc ba nk memory space timing register 0x9c00 0000 0x9fff ffff bank 4 - pc card i/o fsmc_pio4 (0xb0) 0x9800 0000 0x9bff ffff attribute fsmc_patt4 (0xac) 0x9000 0000 0x93ff ffff common fsmc_pmem4 (0xa8) 0x8800 0000 0x8bff ffff bank 3 - nand flash attribute fsmc_patt3 (0x8c) 0x8000 0000 0x83ff ffff common fsmc_pmem3 (0x88) 0x7800 0000 0x7bff ffff bank 2- nand flash attribute fsmc_patt2 (0x6c) 0x7000 0000 0x73ff ffff common fsmc_pmem2 (0x68) table 165. nand bank selections section name haddr[17:16] address range address section 1x 0x020000-0x03ffff command section 01 0x010000-0x01ffff data section 00 0x000000-0x0ffff flexible static memory controller (fsmc) RM0033 1224/1317 doc id 15403 rev 3 the application software uses the 3 secti ons to access the nand flash memory: to send a command to nand flash memory : the software must write the command value to any memory location in the command section. to specify the nand flash address that must be read or written : the software must write the address value to any memory location in the address section. since an address can be 4 or 5 bytes long (depending on the actual memory size), several consecutive writes to the address section are needed to specify the full address. to read or write data : the software reads or writes the data value from or to any memory location in the data section. since the nand flash memory automatically increments addresses, there is no need to increment the address of the data section to access consecutive memory locations. 31.5 nor flash/psram controller the fsmc generates the appropriate signal timings to drive the following types of memories: asynchronous sr am and rom ?8-bit ? 16-bit ? 32-bit psram (cellular ram) ? asynchronous mode ? burst mode ? multiplexed or nonmultiplexed nor flash ? asynchronous mode or burst mode ? multiplexed or nonmultiplexed the fsmc outputs a unique chip select signal ne[4:1] per bank. all the other signals (addresses, data and control) are shared. for synchronous accesses, the fsmc issues the clock (clk) to the selected external device. this clock is a submultiple of the hclk clock. the size of each bank is fixed and equal to 64 mbytes. each bank is configured by means of dedicated registers (see section 31.5.6 ). the programmable memory parameters include access timings (see ta b l e 1 6 6 ) and support for wait management (for psram and nor flash accessed in burst mode). table 166. programmable nor/psram access parameters parameter function access mode unit min. max. address setup duration of the address setup phase asynchronous ahb clock cycle (hclk) 015 address hold duration of the address hold phase asynchronous, muxed i/os ahb clock cycle (hclk) 115 RM0033 flexible static memory controller (fsmc) doc id 15403 rev 3 1225/1317 31.5.1 external memory interface signals table 167 , table 168 and table 169 list the signals that are typically used to interface nor flash, sram and psram. note: prefix ?n?. specifies the associated signal as active low. nor flash, nonmultiplexed i/os nor flash memories are addressed in 16-bit words. the maximum capacity is 512 mbit (26 address lines). nor flash, multiplexed i/os data setup duration of the data setup phase asynchronous ahb clock cycle (hclk) 1 256 bust turn duration of the bus turnaround phase asynchronous and synchronous read ahb clock cycle (hclk) 015 clock divide ratio number of ahb clock cycles (hclk) to build one memory clock cycle (clk) synchronous ahb clock cycle (hclk) 116 data latency number of clock cycles to issue to the memory before the first data of the burst synchronous memory clock cycle (clk) 217 table 166. programmable nor/psram access parameters (continued) parameter function access mode unit min. max. table 167. nonmultipled i/o nor flash fsmc signal name i/o function clk o clock (for synchronous burst) a[25:0] o address bus d[15:0] i/o bidirectional data bus ne[x] o chip select, x = 1..4 noe o output enable nwe o write enable nl(=nadv) o latch enable (this signal is called address valid, nadv, by some nor flash devices) nwait i nor flash wait input signal to the fsmc table 168. multiplexed i/o nor flash fsmc signal name i/o function clk o clock (for synchronous burst) a[25:16] o address bus ad[15:0] i/o 16-bit multiplexed, bidirectional address/data bus flexible static memory controller (fsmc) RM0033 1226/1317 doc id 15403 rev 3 nor-flash memories are addressed in 16-bit words. the maximum capacity is 512 mbit (26 address lines). psram/sram, nonmultiplexed i/os psram memories are addressed in 16-bit word s. the maximum capacity is 512 mbit (26 address lines). ne[x] o chip select, x = 1..4 noe o output enable nwe o write enable nl(=nadv) o latch enable (this signal is called address valid, nadv, by some nor flash devices) nwait i nor flash wait input signal to the fsmc table 169. nonmultiplexed i/os psram/sram fsmc signal name i/o function clk o clock (only for psram synchronous burst) a[25:0] o address bus d[15:0] i/o data bidirectional bus ne[x] o chip select, x = 1..4 (called nce by psram (cellular ram i.e. cram)) noe o output enable nwe o write enable nl(= nadv) o address valid only for psram input (memory signal name: nadv) nwait i psram wait input signal to the fsmc nbl[1] o upper byte enable (memory signal name: nub) nbl[0] o lowed byte enable (memory signal name: nlb) table 168. multiplexed i/o nor flash (continued) fsmc signal name i/o function RM0033 flexible static memory controller (fsmc) doc id 15403 rev 3 1227/1317 psram, multiplexed i/os psram memories are addressed in 16-bit word s. the maximum capacity is 512 mbit (26 address lines). 31.5.2 supported me mories and transactions table 171 below displays an example of the supported devices, access modes and transactions when the memory data bus is 16-bit for nor, psram and sram. transactions not allowed (or not supported) by the fsmc in this example appear in gray. table 170. multiplexed i/o psram fsmc signal name i/o function clk o clock (for synchronous burst) a[25:16] o address bus ad[15:0] i/o 16-bit multiplexed, bidirectional address/data bus ne[x] o chip select, x = 1..4 (called nce by psram (cellular ram i.e. cram)) noe o output enable nwe o write enable nl(= nadv) o address valid psram input (memory signal name: nadv) nwait i psram wait input signal to the fsmc nbl[1] o upper byte enable (memory signal name: nub) nbl[0] o lowed byte enable (memory signal name: nlb) table 171. nor flash/psram supported memories and transactions device mode r/w ahb data size memory data size allowed/ not allowed comments nor flash (muxed i/os and nonmuxed i/os) asynchronous r 8 16 y asynchronous w 8 16 n asynchronous r 16 16 y asynchronous w 16 16 y asynchronous r 32 16 y split into 2 fsmc accesses asynchronous w 32 16 y split into 2 fsmc accesses asynchronous page r - 16 n mode is not supported synchronous r 8 16 n synchronous r 16 16 y synchronous r 32 16 y flexible static memory controller (fsmc) RM0033 1228/1317 doc id 15403 rev 3 31.5.3 general timing rules signals synchronization all controller output signals change on the rising edge of the internal clock (hclk) in synchronous read and write mode, the output data change s on the falling edge of the memory clock (fsmc_clk). 31.5.4 nor flash/psram contro ller asynchronous transactions asynchronous static memories (nor flash, sram) signals are synchronized by the internal clock hclk. this clock is not issued to the memory the fsmc always samples the data before de-ass erting the chip select signal ne. this guarantees that the memory data-hold timing constraint is met (chip enable high to data transition, usually 0 ns min.) when extended mode is set, it is possible to mix modes a, b, c and d in read and write (it is for instance possible to read in mode a and write in mode b). psram (multiplexed i/os and nonmultiplexed i/os) asynchronous r 8 16 y asynchronous w 8 16 y use of byte lanes nbl[1:0] asynchronous r 16 16 y asynchronous w 16 16 y asynchronous r 32 16 y split into 2 fsmc accesses asynchronous w 32 16 y split into 2 fsmc accesses asynchronous page r - 16 n mode is not supported synchronous r 8 16 n synchronous r 16 16 y synchronous r 32 16 y synchronous w 8 16 y use of byte lanes nbl[1:0] synchronous w 16/32 16 y sram and rom asynchronous r 8 / 16 16 y use of byte lanes nbl[1:0] asynchronous w 8 / 16 16 y use of byte lanes nbl[1:0] asynchronous r 32 16 y split into 2 fsmc accesses asynchronous w 32 16 y split into 2 fsmc accesses table 171. nor flash/psram supported memories and transactions (continued) device mode r/w ahb data size memory data size allowed/ not allowed comments RM0033 flexible static memory controller (fsmc) doc id 15403 rev 3 1229/1317 mode 1 - sram/cram figure 396. mode1 read accesses figure 397. mode1 write accesses a[25:0] noe add s et data s t memory tr a n sa ction nex d[15:0] hclk cycle s hclk cycle s nwe nbl[1:0] d a t a driven b y memory a i15557 high a[25:0] noe addset (datast + 1) memory transaction nex d[15:0] hclk cycles hclk cycles nwe nbl[1:0] data driven by fsmc ai15558 1hclk flexible static memory controller (fsmc) RM0033 1230/1317 doc id 15403 rev 3 the one hclk cycle at the end of the write transaction helps guarantee the address and data hold time after the nwe rising edge. due to the presence of this one hclk cycle, the datast value must be greater than zero (datast > 0). table 172. fsmc_bcrx bit fields bit number bit name value to set 31-16 0x0000 15 asyncwait set to 1 if the memory suppor ts this feature. otherwise keep at 0. 14-10 0x0 9 waitpol meaningful only if bit 15 is 1 8 bursten 0x0 7 - 6 faccen - 5-4 mwid as needed 3-2 mtyp as needed, exclude 10 (nor flash) 1 muxen 0x0 0 mbken 0x1 table 173. fsmc_btrx bit fields bit number bit name value to set 31-20 0x0000 19-16 busturn time between nex high to nex low (busturn hclk) 15-8 datast duration of the second access phase (datast+1 hclk cycles for write accesses, datast hclk cycles for read accesses). 7-4 0x0 3-0 addset duration of the first access phase (addset hclk cycles). minimum value for addset is 0. RM0033 flexible static memory controller (fsmc) doc id 15403 rev 3 1231/1317 mode a - sram/psram (cram) oe toggling figure 398. modea read accesses figure 399. modea write accesses the differences compared with mode1 are the toggling of noe and the independent read and write timings. a[25:0] noe add s et data s t memory tr a n sa ction nex d[15:0] hclk cycle s hclk cycle s nwe nbl[1:0] d a t a driven b y memory a i15559 high a[25:0] noe add s et (data s t + 1) memory tr a n sa ction nex d[15:0] hclk cycle s hclk cycle s nwe nbl[1:0] d a t a driven b y f s mc a i15560 1hclk flexible static memory controller (fsmc) RM0033 1232/1317 doc id 15403 rev 3 table 174. fsmc_bcrx bit fields bit number bit name value to set 31-16 0x0000 15 asyncwait set to 1 if the memory supports this feature. otherwise keep at 0. 14 extmod 0x1 13-10 0x0 9 waitpol meaningful only if bit 15 is 1 8 bursten 0x0 7 - 6 faccen - 5-4 mwid as needed 3-2 mtyp as needed, exclude 10 (nor flash) 1 muxen 0x0 0 mbken 0x1 table 175. fsmc_btrx bit fields bit number bit name value to set 31-30 0x0 29-28 accmod 0x0 27-20 0x000 19-16 busturn time between nex high to nex low (busturn hclk) 15-8 datast duration of the second access phase (datast hclk cycles) in read. 7-4 0x0 3-0 addset duration of the first access phas e (addset hclk cycles) in read. minimum value for addset is 1. table 176. fsmc_bwtrx bit fields bit number bit name value to set 31-30 0x0 29-28 accmod 0x0 27-20 0x000 19-16 busturn time between nex high to nex low (busturn hclk). 15-8 datast duration of the second access phase (datast+1 hclk cycles) in write. RM0033 flexible static memory controller (fsmc) doc id 15403 rev 3 1233/1317 mode 2/b - nor flash figure 400. mode2/b read accesses 7-4 0x0 3-0 addset duration of the first access phase (addset hclk cycles) in write minimum value for addset is 1. table 176. fsmc_bwtrx bit fields (continued) bit number bit name value to set a[25:0] noe add s et data s t memory tr a n sa ction nex d[15:0] hclk cycle s hclk cycle s nwe nadv d a t a driven b y memory a i15561 high flexible static memory controller (fsmc) RM0033 1234/1317 doc id 15403 rev 3 figure 401. mode2 write accesses figure 402. modeb write accesses the differences with mode1 are the toggling of nadv and the independent read and write timings when extended mode is set (mode b). a[25:0] noe add s et (data s t + 1) memory tr a n sa ction nex d[15:0] hclk cycle s hclk cycle s nwe nadv d a t a driven b y f s mc a i15562 1hclk a[25:0] noe add s et (data s t + 1) memory tr a n sa ction nex d[15:0] hclk cycle s hclk cycle s nwe nadv d a t a driven b y f s mc a i1556 3 1hclk RM0033 flexible static memory controller (fsmc) doc id 15403 rev 3 1235/1317 table 177. fsmc_bcrx bit fields bit number bit name value to set 31-16 0x0000 15 asyncwait set to 1 if the memory supp orts this feature. otherwise keep at 0. 14 extmod 0x1 for mode b, 0x0 for mode 2 13-10 0x0 9 waitpol meaningful only if bit 15 is 1 8 bursten 0x0 7 - 6 faccen 0x1 5-4 mwid as needed 3-2 mtyp 10 (nor flash) 1 muxen 0x0 0 mbken 0x1 table 178. fsmc_btrx bit fields bit number bit name value to set 31-30 0x0 29-28 accmod 0x1 if extended mode is set 27-20 0x000 19-16 busturn time between nex high to nex low (busturn hclk) 15-8 datast duration of the access second phase (datast hclk cycles) in read. 7-4 0x0 3-0 addset duration of the access first phase (addset hclk cycles) in read. minimum value for addset is 1. table 179. fsmc_bwtrx bit fields bit number bit name value to set 31-30 0x0 29-28 accmod 0x1 if extended mode is set 27-20 0x000 19-16 busturn time between nex high to nex low (busturn hclk) 15-8 datast duration of the access second phase (datast+1 hclk cycles) in write. flexible static memory controller (fsmc) RM0033 1236/1317 doc id 15403 rev 3 note: the fsmc_bwtrx register is valid only if extended mode is set (mode b), otherwise all its content is don?t care. mode c - nor flash - oe toggling figure 403. modec read accesses 7-4 0x0 3-0 addset duration of the access first phase (addset hclk cycles) in write. minimum value for addset is 1. table 179. fsmc_bwtrx bit fields (continued) bit number bit name value to set a[25:0] noe add s et data s t memory tr a n sa ction nex d[15:0] hclk cycle s hclk cycle s nwe nadv d a t a driven b y memory a i15564 high RM0033 flexible static memory controller (fsmc) doc id 15403 rev 3 1237/1317 figure 404. modec write accesses the differences compared with mode1 are the toggling of noe and nadv and the independent read and write timings. table 180. fsmc_bcrx bit fields bit no. bit name value to set 31-16 0x0000 15 asyncwait set to 1 if the memory suppo rts this feature. otherwise keep at 0. 14 extmod 0x1 13-10 0x0 9 waitpol meaningful only if bit 15 is 1 8 bursten 0x0 7 - 6 faccen 1 5-4 mwid as needed 3-2 mtyp 0x02 (nor flash) 1 muxen 0x0 0 mbken 0x1 a[25:0] noe add s et (data s t + 1) memory tr a n sa ction nex d[15:0] hclk cycle s hclk cycle s nwe nadv d a t a driven b y f s mc a i15565 1hclk flexible static memory controller (fsmc) RM0033 1238/1317 doc id 15403 rev 3 table 181. fsmc_btrx bit fields bit no. bit name value to set 31-30 0x0 29-28 accmod 0x2 27-20 0x000 19-16 busturn time between nex high to nex low (busturn hclk) 15-8 datast duration of the second access phase (datast hclk cycles) in read. 7-4 0x0 3-0 addset duration of the first access pha se (addsethclk cycles) in read. minimum value for addset is 1. table 182. fsmc_bwtrx bit fields bit no. bit name value to set 31-30 0x0 29-28 accmod 0x2 27-20 0x000 19-16 busturn time between nex high to nex low (busturn hclk) 15-8 datast duration of the second access phase (datast+1 hclk cycles) in write. 7-4 0x0 3-0 addset duration of the first access phase (addset hclk cycles) in write. minimum value for addset is 1. RM0033 flexible static memory controller (fsmc) doc id 15403 rev 3 1239/1317 mode d - asynchronous access with extended address figure 405. moded read accesses figure 406. moded write accesses a[25:0] noe add s et data s t memory tr a n sa ction nex d[15:0] hclk cycle s hclk cycle s nwe nadv d a t a driven b y memory a i15566 high addhld hclk cycle s a[25:0] noe add s et (data s t+ 1) memory tr a n sa ction nex d[15:0] hclk cycle s hclk cycle s nwe nadv d a t a driven b y f s mc a i15567 1hclk addhld hclk cycle s flexible static memory controller (fsmc) RM0033 1240/1317 doc id 15403 rev 3 the differences with mode1 are the toggling of nadv, noe that goes on toggling after nadv changes and the independent read and write timings. table 183. fsmc_bcrx bit fields bit no. bit name value to set 31-16 0x0000 15 asyncwait set to 1 if the memory supports this feature. otherwise keep at 0. 14 extmod 0x1 13-10 0x0 9 waitpol meaningful only if bit 15 is 1 8 bursten 0x0 7 - 6 faccen set according to memory support 5-4 mwid as needed 3-2 mtyp as needed 1 muxen 0x0 0 mbken 0x1 table 184. fsmc_btrx bit fields bit no. bit name value to set 31-30 0x0 29-28 accmod 0x2 27-20 0x000 19-16 busturn time between nex high to nex low (busturn hclk) 15-8 datast duration of the second access phase (datast hclk cycles) in read. 7-4 addhld duration of the middle phase of the read access (addhld hclk cycles) 3-0 addset duration of the first access ph ase (addsethclk cycles) in read. minimum value for addset is 1. table 185. fsmc_bwtrx bit fields bit no. bit name value to set 31-30 0x0 29-28 accmod 0x2 27-20 0x000 19-16 busturn time between nex high to nex low (busturn hclk) 15-8 datast duration of the second access phase (datast+1 hclk cycles) in write. RM0033 flexible static memory controller (fsmc) doc id 15403 rev 3 1241/1317 mode muxed - asynchronous access muxed nor flash figure 407. multiplexed read accesses 7-4 addhld duration of the middle phase of the write access (addhld hclk cycles) 3-0 addset duration of the first access phas e (addset hclk cycles) in write. minimum value for addset is 1. table 185. fsmc_bwtrx bit fields (continued) bit no. bit name value to set a[25:16] noe add s et data s t memory tr a n sa ction nex ad[15:0] hclk cycle s hclk cycle s nwe nadv d a t a driven b y memory a i1556 8 high addhld hclk cycle s lower a ddre ss flexible static memory controller (fsmc) RM0033 1242/1317 doc id 15403 rev 3 figure 408. multiplexed write accesses the difference with mode d is the drive of the lower address byte(s) on the databus. table 186. fsmc_bcrx bit fields bit no. bit name value to set 31-16 0x0000 15 asyncwait set to 1 if the memory supports this feature. otherwise keep at 0. 14 extmod 0x0 13-10 0x0 9 waitpol meaningful only if bit 15 is 1 8 bursten 0x0 7 - 6 faccen 0x1 5-4 mwid as needed 3-2 mtyp 0x2 (nor) 1 muxen 0x1 0 mbken 0x1 table 187. fsmc_btrx bit fields bit no. bit name value to set 31-20 0x0000 19-16 busturn time between nex high to nex low (busturn hclk) a[25:16] noe add s et (data s t + 1) memory tr a n sa ction nex ad[15:0] hclk cycle s hclk cycle s nwe nadv d a t a driven b y f s mc a i15569 1hclk addhld hclk cycle s lower a ddre ss RM0033 flexible static memory controller (fsmc) doc id 15403 rev 3 1243/1317 wait management in asynchronous accesses if the asynchronous memory asserts a wait signal to advise that it's not yet ready to accept or to provide data, the asyncwait bit ha s to be set in fsmc_bcrx register. if the wait signal is active (high or low depending on the waitpol bit), the second access phase (data setup phase) programmed by the datast bits, is extended until wait becomes inactive. unlike the data setup phase, the first access phases (address setup and address hold phases), programmed by the addset and addhld bits, are not wait sensitive and so they are not prolonged. the data phase must be programmed so that wait can be detected 4 hclk cycles before the data sampling. the following cases must be considered: 1. memory asserts the wait signal aligned to noe/nwe which toggles: data_setup phase >= 4 * hclk + max_wait_assertion_time 2. memory asserts the wait signal aligned to nex (or noe/nwe not toggling): if max_wait_assertion_time > (address_phase + hold_phase) data_setup phase >= 4 * hclk + (max_wait_assertion_time - address_phase - hold_phase) otherwise data_setup phase >= 4 * hclk where max_wait_assertion_time is the maximum time taken by the memory to assert the wait signal once nex/noe/nwe is low. the figure 409 and figure 410 show the number of hclk clock cycles that memory access is extended after wait is removed by the asynchronous memory (independently of the above cases). 15-8 datast duration of the second access phase (datast hclk cycles for read accesses and datast+1 hclk cycles for write accesses). 7-4 addhld duration of the middle p hase of the access (addhld hclk cycles). 3-0 addset duration of the first access phase (addset hclk cycles). minimum value for addset is 1. table 187. fsmc_btrx bit fields (continued) bit no. bit name value to set flexible static memory controller (fsmc) RM0033 1244/1317 doc id 15403 rev 3 figure 409. asynchronous wait during a read access figure 410. asynchronous wait during a write access a[25:0] noe ( # , + memory transaction . 7 ! ) 4 d[15:0] . % x d a t a d r i v e n b y m e m o r y a i a d d r e s s p h a s e d o n t c a r e d a t a ? s e t u p p h a s e a[25:0] nwe memory transaction nwait d[15:0] nex data driven by fsmc ai15797 3hclk address phase don?t care data phase 1hclk RM0033 flexible static memory controller (fsmc) doc id 15403 rev 3 1245/1317 31.5.5 synchronous burst transactions the memory clock, clk, is a submultiple of hclk according to the value of parameter clkdiv. nor flash memories specify a minimum time from nadv assertion to clk high. to meet this constraint, the fsmc does not issue the cl ock to the memory during the first internal clock cycle of the synchronous access (before nadv assertion). this guarantees that the rising edge of the memory clock occurs in the middle of the nadv low pulse. data latency versus nor flash latency the data latency is the number of cycles to wait before sampling the data. the datlat value must be consistent with the latency va lue specified in the nor flash configuration register. the fsmc does not include the clock cycle when nadv is low in the data latency count. caution: some nor flash memories include the nadv low cycle in the data latency count, so the exact relation between the nor flash latency and the fmsc datlat parameter can be either of: nor flash latency = datlat + 2 nor flash latency = datlat + 3 some recent memories assert nwait during the latency phase. in such cases datlat can be set to its minimum value. as a result, the fsmc samples the data and waits long enough to evaluate if the data are valid. thus the fsmc detects when the memory exits latency and real data are taken. other memories do not assert nwait during latency. in this case the latency must be set correctly for both the fsmc and the memory, otherwise invalid data are mistaken for good data, or valid data are lost in the initial phase of the memory access. single-burst transfer when the selected bank is configured in synchronous burst mode, if an ahb single-burst transaction is requested, the fsmc performs a burst transaction of length 1 (if the ahb transfer is 16-bit), or length 2 (if the ahb transfer is 32-bit) and de-assert the chip select signal when the last data is strobed. clearly, such a transfer is not the most efficient in terms of cycles (compared to an asynchronous read). nevertheless, a random a synchronous access would first require to re- program the memory access mode, which would altogether last longer. wait management for synchronous burst nor flash, nwait is evaluated after the programmed latency p e r i o d , ( data l at + 2 ) c l k c l o c k c y c l e s . if nwait is sensed active (low level when waitpol = 0, high level when waitpol = 1), wait states are inserted until nwait is sensed inactive (high level when waitpol = 0, low level when waitpol = 1). when nwait is inactive, the data is considered valid either immediately (bit waitcfg = 1) or on the next clock edge (bit waitcfg = 0). flexible static memory controller (fsmc) RM0033 1246/1317 doc id 15403 rev 3 during wait-state insertion via the nwait si gnal, the controller continues to send clock pulses to the memory, keeping the chip select and output enable signals valid, and does not consider the data valid. there are two timing configurations for t he nor flash nwait signal in burst mode: flash memory asserts the nwait signal one data cycle before the wait state (default after reset) flash memory asserts the nwait signal during the wait state these two nor flash wait state configurations are supported by the fsmc, individually for each chip select, thanks to the waitcfg bit in the fsmc_bcrx registers (x = 0..3). figure 411. wait configurations addr[15:0] d a t a d a t a a ddr[25:16] memory tr a n sa ction = bu r s t of 4 h a lf word s hclk clk a[25:16] nadv nwait (waitcfg = 1) a/d[15:0] in s erted w a it s t a te d a t a nwait (waitcfg = 0) a i1579 8 RM0033 flexible static memory controller (fsmc) doc id 15403 rev 3 1247/1317 figure 412. synchronous multiplexed read mode - nor, psram (cram) 1. byte lane outputs bl are not shown; for nor access, they are held high, and, for psram (cram) access, they are held low. ! d d r ; = d a t a d a t a a d d r ; = - e m o r y t r a n s a c t i o n b u r s t o f h a l f w o r d s ( # , + # , + ! ; = . % x . / % . 7 % ( i g h . ! $ 6 . 7 ! ) 4 7 ! ) 4 # & ' ! $ ; = c l o c k c y c l e c l o c k c y c l e $ ! 4 ! , ! 4 i n s e r t e d w a i t s t a t e $ a t a s t r o b e s a i b # , + c y c l e s d a t a d a t a $ a t a s t r o b e s table 188. fsmc_bcrx bit fields bit no. bit name value to set 31-20 0x0000 19 cburstrw no effect on synchronous read 18-15 0x0 14 extmod 0x0 13 waiten when high, the first data after latency period is taken as always valid, regardless of the wait from memory value 12 wren no effect on synchronous read 11 waitcfg to be set according to memory 10 wrapmod no effect 9 waitpol to be set according to memory flexible static memory controller (fsmc) RM0033 1248/1317 doc id 15403 rev 3 8 bursten 0x1 7 fwprlvl set to protect memory from accidental write access 6 faccen set according to memory support 5-4 mwid as needed 3-2 mtyp 0x1 or 0x2 1 muxen as needed 0 mbken 0x1 table 189. fsmc_btrx bit fields bit no. bit name value to set 27-24 datlat data latency 23-20 clkdiv 0x0 to get clk = hclk 0x1 to get clk = 2 hclk .. 19-16 busturn time between nex high to nex low (busturn hclk) 15-8 datast no effect 7-4 addhld no effect 3-0 addset no effect table 188. fsmc_bcrx bit fields (continued) bit no. bit name value to set RM0033 flexible static memory controller (fsmc) doc id 15403 rev 3 1249/1317 figure 413. synchronous multiplexed write mode - psram (cram) 1. memory must issue nwait signal one cycle in advance, accordingly waitcfg must be programmed to 0. 2. byte lane (nbl) outputs are not shown, they are held low while nex is active. addr[15:0] d a t a a ddr[25:16] memory tr a n sa ction = bu r s t of 2 h a lf word s hclk clk a[25:16] nex noe nwe hi-z nadv nwait (waitcfg = 0) a/d[15:0] 1 clock cycle 1 clock cycle (datalat + 2) in s erted w a it s t a te a i147 3 1d clk cycle s d a t a flexible static memory controller (fsmc) RM0033 1250/1317 doc id 15403 rev 3 table 190. fsmc_bcrx bit fields bit no. bit name value to set 31-20 0x0000 19 cburstrw 0x1 18-15 0x0 14 extmod 0x0 13 waiten when high, the first data after latency period is taken as always valid, regardless of the wait from memory value 12 wren no effect on synchronous read 11 waitcfg 0x0 10 wrapmod no effect 9 waitpol to be set according to memory 8 bursten no effect on synchronous write 7 fwprlvl set to protect memory from accidental writes 6 faccen set according to memory support 5-4 mwid as needed 3-2 mtyp 0x1 1 muxen as needed 0 mbken 0x1 table 191. fsmc_btrx bit fields bit no. bit name value to set 31-30 - 0x0 27-24 datlat data latency 23-20 clkdiv 0 to get clk = hclk (not supported) 1 to get clk = 2 hclk 19-16 busturn no effect 15-8 datast no effect 7-4 addhld no effect 3-0 addset no effect RM0033 flexible static memory controller (fsmc) doc id 15403 rev 3 1251/1317 31.5.6 nor/psram contro ller registers sram/nor-flash chip-select control registers 1..4 (fsmc_bcr1..4) address offset: 0xa000 0000 + 8 * (x ? 1), x = 1...4 reset value: 0x0000 30dx this register contains the control information of each memory bank, used for srams, roms and asynchronous or burst nor flash memories. 3130292827262524232221201918171615141312111098 7 6543210 reserved cburstrw reserved ascycwait extmod waiten wren waitcfg wrapmod waitpol bursten reserved faccen mwid mtyp muxen mbken rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bit 19 cburstrw: write burst enable. for cellular ram, the bit enables synchronous burs t protocol during write operations. for flash memory access in burst mode, this bit enables/disables the wait state insertion via the nwait signal. the enable bit for the synchronous burst pr otocol during read access is the bursten bit in the fsmc_bcrx register. 0: write operations are always performed in asynchronous mode 1: write operations are per formed in synchronous mode. bit 15 asyncwait : wait signal during asynchronous transfers this bit enables the fsmc to use the wait signal even during an asynchronous protocol. 0: nwait signal is not taken in to account when running an asynchronous protocol (default after reset) 1: nwait signal is taken in to account when running an asynchronous protocol bit 14 extmod: extended mode enable. this bit enables the fsmc to program inside the fsmc_bwtr register, so it allows different timings for read and write. 0: values inside fsmc_bwtr register are not taken into account (default after reset) 1: values inside fsmc_bwtr register are taken into account bit 13 waiten: wait enable bit. for flash memory access in burst mode, this bit enables/disables wait-state insertion via the nwait signal: 0: nwait signal is disabled (its level not taken into account, no wait state inserted after the programmed flash latency period) 1: nwait signal is enabled (its level is taken into account after the programmed flash latency period to insert wait states if asserted) (default after reset) bit 12 wren: write enable bit. this bit indicates whether write operations are enabled/disabled in the bank by the fsmc: 0: write operations are disabled in the bank by the fsmc, an ahb error is reported, 1: write operations are enabled for the ba nk by the fsmc (default after reset). flexible static memory controller (fsmc) RM0033 1252/1317 doc id 15403 rev 3 bit 11 waitcfg: wait timing configuration. for memory access in burst mode, the nwait signal indicates whether the data from the memory are valid or if a wait state must be inserted. this configuration bit determines if nwait is asserted by the memory one clock cycle before th e wait state or dur ing the wa it state: 0: nwait signal is active one data cycle bef ore wait state (default after reset), 1: nwait signal is active during wait state (not for cellular ram). bit 10 wrapmod: wrapped burst mode support. defines whether the controller will or not split an ahb burst wrap access into two linear accesses. valid only when accessing memories in burst mode 0: direct wrapped burst is not enabled (default after reset), 1: direct wrapped burst is enabled. note: this bit has no effect as the cpu and dma cannot generate wrapping burst transfers. bit 9 waitpol: wait signal polarity bit. defines the polarity of the wait signal from memory. valid only when accessing the memory in burst mode: 0: nwait active low (default after reset), 1: nwait active high. bit 8 bursten: burst enable bit. enables the burst access mode for the memory. valid only with synchronous burst memories: 0: burst access mode disabled (default after reset) 1: burst access mode enable bit 7 reserved. bit 6 faccen: flash access enable enables nor flash memory access operations. 0: corresponding nor flash memory access is disabled 1: corresponding nor flash memory access is enabled (default after reset) bits 5:4 mwid: memory databus width. defines the external memory device width, valid for all type of memories. 00: 8 bits, 01: 16 bits (default after reset), 10: reserved, do not use, 11: reserved, do not use. bits 3:2 mtyp: memory type. defines the type of external memory attached to the corresponding memory bank: 00: sram, rom (default after reset for bank 2...4) 01: psram (cellular ram: cram) 10: nor flash/onenand flash (default after reset for bank 1) 11: reserved bit 1 muxen: address/data multiplexing enable bit. when this bit is set, the address and data values are multiplexed on the databus, valid only with nor and psram memories: 0: address/data nonmultiplexed 1: address/data multiplexed on databus (default after reset) bit 0 mbken: memory bank enable bit. enables the memory bank. after reset bank1 is enabled, all others are disabled. accessing a disabled bank causes an error on ahb bus. 0: corresponding memory bank is disabled 1: corresponding memory bank is enabled RM0033 flexible static memory controller (fsmc) doc id 15403 rev 3 1253/1317 sram/nor-flash chip-select timing registers 1..4 (fsmc_btr1..4) address offset: 0xa000 0000 + 0x04 + 8 * (x ? 1), x = 1..4 reset value: 0x0fff ffff this register contains the control information of each memory bank, used for srams, roms and nor flash memories. if the extmod bit is set in the fsmc_bcrx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (fsmc_bwtrx registers). 313029282726252423222120191817161514131211109876543210 reserved accmod datlat clkdiv busturn datast addhld addset rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 29:28 accmod: access mode specifies the asynchronous access modes as shown in the timing diagrams. these bits are taken into account only when the extmod bit in the fsmc_bcrx register is 1. 00: access mode a 01: access mode b 10: access mode c 11: access mode d bits 27:24 datlat : data latency for synchronous burst nor flash memory for nor flash with synchronous burst mode enab led, defines the number of memory clock cycles (+2) to issue to the memory before getting the first data: 0000: data latency of 2 clk clock cycles for first burst access 1111: data latency of 17 clk clock cycles for first burst access (default value after reset) note: this timing parameter is not expressed in hclk periods, but in flash clock (clk) periods. in asynchronous nor flash, sram or rom accesses, this value is don't care. in the case of cram, this field must be set to ?0?. bits 23:20 clkdiv: clock divide ratio (for clk signal) defines the period of clk clock output signal, expressed in number of hclk cycles: 0000: reserved 0001: clk period = 2 hclk periods 0010: clk period = 3 hclk periods 1111: clk period = 16 hclk periods (default value after reset) in asynchronous nor flash, sram or rom accesses, this value is don?t care. flexible static memory controller (fsmc) RM0033 1254/1317 doc id 15403 rev 3 bits 19:16 busturn: bus turnaround phase duration these bits are written by software to insert the bus turnaround delay after a read access only from multiplexed nor flash memory to avoid bu s contention if the controller needs to drive addresses on the databus for the next side-by -side transaction. busturn can be set to the minimum if the slowest memory does not take more than 6 hclk clock cycles to put the databus in hi-z state. these bits are written by software to add a dela y at the end of a write/ read transaction. this delay allows to match the minimum time between consecutive transactions (t ehel from nex high to nex low) and the maximum time needed by the memory to free the data bus after a read access (tehqz): (bustrun + 1)hclk period t ehelmin and (bustrun + 2)hclk period t ehqzmax if extmod = ?0? (bustrun + 2)hclk period max (t ehelmin , t ehqzmax ) if extmod = ?1?. 0000: busturn phase duration = 0 hclk clock cycle added ... 1111: busturn phase duration = 15 hclk clock cycles (default value after reset) bits 15:8 datast: data-phase duration these bits are written by software to defin e the duration of the data phase (refer to figure 396 to figure 408 ), used in srams, roms and asynchronous nor flash accesses: 0000 0000: reserved 0000 0001: datast phase dur ation = 1 hclk clock cycles 0000 0010: datast phase dur ation = 2 hclk clock cycles ... 1111 1111: datast phase duration = 255 hclk clock cycles (default value after reset) for each memory type and access mode data-phase duration, please refer to the respective figure ( figure 396 to figure 408 ). example: mode1, write access, datast=1: data-phase duration= datast+1 = 2 hclk clock cycles. note: in synchronous accesses, this value is don't care. bits 7:4 addhld: address-hold phase duration these bits are written by software to define the duration of the address hold phase (refer to figure 405 to figure 408 ), used in mode d and multiplexed accesses: 0000: reserved 0001: addhld phase duration =1 hclk clock cycle 0010: addhld phase durati on = 2 hclk clock cycle ... 1111: addhld phase dur ation = 15 hclk clock cycles (default val ue after reset) for each access mode address-hold phase duration, please refer to the respective figure ( figure 405 to figure 408 ). note: in synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration. bits 3:0 addset: address setup phase duration these bits are written by software to define the duration of the address setup phase (refer to figure 396 to figure 408 ), used in srams, roms and asynchronous nor flash accesses: 0000: addset phase dura tion = 0 hclk clock cycle ... 1111: addset phase duration = 1615 hclk clock cycles (default value after reset) for each access mode address setup phase duration, please refer to the respective figure (refer to figure 396 to figure 408 ). note: in synchronous accesses, this value is don?t care. RM0033 flexible static memory controller (fsmc) doc id 15403 rev 3 1255/1317 note: psrams (crams) have a variable latency due to internal refresh. therefore these memories issue the nwait signal during the whole latency phase to prolong the latency as needed. with psrams (crams) the filed datlat must be set to 0, so that the fsmc exits its latency phase soon and starts sampling nwait from memory, then starts to read or write when the memory is ready. this method can be used also with the late st generation of synchronous flash memories that issue the nwait signal, unlike older fl ash memories (check the datasheet of the specific flash memory being used). sram/nor-flash write timing registers 1..4 (fsmc_bwtr1..4) address offset: 0xa000 0000 + 0x104 + 8 * (x ? 1), x = 1...4 reset value: 0x0fff ffff this register contains the control information of each memory bank, used for srams, roms and nor flash memories. when the extmod bit is set in the fsmc_bcrx register, then this register is active for write access. 313029282726252423222120191817161514131211109876543210 res. accm od datlat clkdiv reserved datast addhld addset rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 29:28 accmod: access mode. specifies the asynchronous access modes as shown in the next timing diagrams.these bits are taken into account only when the extmod bit in the fsmc_bcrx register is 1. 00: access mode a 01: access mode b 10: access mode c 11: access mode d bits 27:24 datlat: data latency (for synchronous burst nor flash). for nor flash with synchronous burst mode en abled, defines the number of memory clock cycles (+2) to issue to the memory before getting the first data: 0000: (0x0) data latency of 2 clk clock cycles for first burst access ... 1111: (0xf) data latency of 17 clk clock cycles for first burst access (default value after reset) note: this timing parameter is not expressed in hclk periods, but in flash clock ( clk ) periods. in asynchronous nor flash, sram or rom accesses, this value is don?t care. in case of cram, this field must be set to 0 bits 23:20 clkdiv: clock divide ratio (for clk signal). defines the period of clk clock output si gnal, expressed in number of hclk cycles: 0000: reserved 0001 clk period = 2 hclk periods 0010 clk period = 3 hclk periods 1111: clk period = 16 hclk periods (default value after reset) in asynchronous nor flash, sram or rom accesses, this value is don?t care. flexible static memory controller (fsmc) RM0033 1256/1317 doc id 15403 rev 3 31.6 nand flash/pc card controller the fsmc generates the appropriate signal timings to drive the following types of device: nand flash ?8-bit ? 16-bit 16-bit pc card compatible devices the nand/pc card controller can control three external banks. bank 2 and bank 3 support nand flash devices. bank 4 supports pc card devices. each bank is configured by means of dedicated registers ( section 31.6.8 ). the programmable memory parameters include access timings (shown in ta bl e 1 9 2 ) and ecc configuration. bits 19:16 busturn : bus turnaround phase duration these bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (t ehel from enx high to enx low): (bustrun + 1) hclk period t ehelmin . 0000: busturn phase duration = 0 hclk clock cycle added ... 1111: busturn phase duration = 15 hclk clock cycles added (default value after reset) bits 15:8 datast: data-phase duration. these bits are written by software to defi ne the duration of the data phase (refer to figure 396 to figure 408 ), used in srams, roms and asynchronous nor flash accesses: 0000 0000: reserved 0000 0001: datast phase duration = 1 hclk clock cycles 0000 0010: datast phase duration = 2 hclk clock cycles ... 1111 1111: datast phase duration = 255 hclk clock cycles (default value after reset) note: in synchronous accesses, this value is don't care. bits 7:4 addhld: address-hold phase duration. these bits are written by software to define the duration of the address hold phase (refer to figure 405 to figure 408 ), used in srams, roms and asynchronous multiplexed nor flash accesses: 0000: reserved 0001: addhld phase duration = 1 hclk clock cycle 0010: addhld phase duration = 2 hclk clock cycle ... 1111: addhld phase duration = 15 hclk clock cycles (default value after reset) note: in synchronous nor flash accesses, this value is not used, the address hold phase is always 1 flash clock period duration. bits 3:0 addset: address setup phase duration. these bits are written by software to define the duration of the address setup phase in hclk cycles (refer to figure 405 to figure 408 ), used in srams, roms and asynchronous nor flash accessed: 0000: addset phase duration = 0 hclk clock cycle ... 1111: addset phase duration = 15 hclk clock cycles (default value after reset) note: in synchronous nor flash accesses, this value is don?t care. RM0033 flexible static memory controller (fsmc) doc id 15403 rev 3 1257/1317 31.6.1 external memory interface signals the following tables list the signals that are typically used to interface nand flash and pc card. caution: when using a pc card or a compactflash in i/o mode, the nios16 input pin must remain at ground level during the whole operation, otherwise the fsmc may not operate properly. this means that the nios16 input pin must not be connected to the card, but directly to ground (only 16-bit accesses are allowed). note: prefix ?n?. specifies the associated signal as active low. 8-bit nand flash t there is no theoretical capacity limitati on as the fsmc can manage as many address cycles as needed. table 192. programmable nand/ pc card access parameters parameter function access mode unit min. max. memory setup time number of clock cycles (hclk) to set up the address before the command assertion read/write ahb clock cycle (hclk) 1 256 memory wait minimum duration (hclk clock cycles) of the command assertion read/write ahb clock cycle (hclk) 2 256 memory hold number of clock cycles (hclk) to hold the address (and the data in case of a wr ite access) after the command de-assertion read/write ahb clock cycle (hclk) 1 255 memory databus high-z number of clock cycles (hclk) during which the databus is kept in high-z state after the start of a write access write ahb clock cycle (hclk) 0 255 table 193. 8-bit nand flash fsmc signal name i/o function a[17] o nand flash address latch enable (ale) signal a[16] o nand flash command latch enable (cle) signal d[7:0] i/o 8-bit multiplexed, bidirectional address/data bus nce[x] o chip select, x = 2, 3 noe(= nre) o output enable (memory signal name: read enable, nre) nwe o write enable nwait/int[3:2] i nand flash ready/busy input signal to the fsmc flexible static memory controller (fsmc) RM0033 1258/1317 doc id 15403 rev 3 16-bit nand flash there is no theoretical capacity limitation as the fsmc can manage as many address cycles as needed. table 194. 16-bit nand flash fsmc signal name i/o function a[17] o nand flash address latch enable (ale) signal a[16] o nand flash command latch enable (cle) signal d[15:0] i/o 16-bit multiplexed, bidirectional address/data bus nce[x] o chip select, x = 2, 3 noe(= nre) o output enable (memory signal name: read enable, nre) nwe o write enable nwait/int[3:2] i nand flash ready/busy input signal to the fsmc table 195. 16-bit pc card fsmc signal name i/o function a[10:0] o address bus nios16 i data transfer in i/o space. it must be shorted to gnd (16-bit transfer only) niord o output enable for i/o space niowr o write enable for i/o space nreg o register signal indicating if access is in common or attribute space d[15:0] i/o bidirectional databus nce4_1 o chip select 1 nce4_2 o chip select 2 (indicates if access is 16-bit or 8-bit) noe o output enable in common and in attribute space nwe o write enable in common and in attribute space nwait i pc card wait input signal to the fsmc (memory signal name iordy) intr i pc card interrupt to t he fsmc (only for pc cards that can generate an interrupt) cd i pc card presence detection. active high. if an access is performed to the pc card banks while cd is low, an ahb error is generated. refer to section 31.3: ahb interface RM0033 flexible static memory controller (fsmc) doc id 15403 rev 3 1259/1317 31.6.2 nand flash / pc card supported memories and transactions table 196 below shows the supported devices, access modes and transactions. transactions not allowed (or not supported) by the nand flash / pc card controller appear in gray. 31.6.3 timing diagrams for nand and pc card each pc card/compactflash and nand flash memory bank is managed through a set of registers: control register: fsmc_pcrx interrupt status register: fsmc_srx ecc register: fsmc_eccrx timing register for common memory space: fsmc_pmemx timing register for attribute memory space: fsmc_pattx timing register for i/o space: fsmc_piox each timing configuration register contains three parameters used to define number of hclk cycles for the three phases of any pc card/compactflash or nand flash access, plus one parameter that defines the timing for starting driving the databus in the case of a write. figure 414 shows the timing parameter definitions for common memory accesses, knowing that attribute and i/o (only for pc card) memory space access timings are similar. table 196. supported memories and transactions device mode r/w ahb data size memory data size allowed/ not allowed comments nand 8-bit asynchronous r 8 8 y asynchronous w 8 8 y asynchronous r 16 8 y split into 2 fsmc accesses asynchronous w 16 8 y split into 2 fsmc accesses asynchronous r 32 8 y split into 4 fsmc accesses asynchronous w 32 8 y split into 4 fsmc accesses nand 16-bit asynchronous r 8 16 y asynchronous w 8 16 n asynchronous r 16 16 y asynchronous w 16 16 y asynchronous r 32 16 y split into 2 fsmc accesses asynchronous w 32 16 y split into 2 fsmc accesses flexible static memory controller (fsmc) RM0033 1260/1317 doc id 15403 rev 3 figure 414. nand/pc card controller timing for common memory access 1. noe remains high (inactive) during write access. nwe remains high (inactive) during read access. 31.6.4 nand flash operations the command latch enable (cle) and address latch enable (ale) signals of the nand flash device are driven by some address signals of the fsmc controller. this means that to send a command or an address to the nand flash memory, the cpu has to perform a write to a certain address in its memory space. a typical page read operation from the nand flash device is as follows: 1. program and enable the corresponding memory bank by configuring the fsmc_pcrx and fsmc_pmemx (and for some devices, fsmc_pattx, see section 31.6.5: nand flash pre-wait functionality on page 1261 ) registers according to the characteristics of the nand flash (pwid bits for the databus width of the nand flash, ptyp = 1, pwaiten = 1, pbken = 1, see section common memory space timing register 2..4 (fsmc_pmem2..4) on page 1267 for timing configuration). 2. the cpu performs a byte write in the common memory space, with data byte equal to one flash command byte (for example 0x 00 for samsung nand flash devices). the cle input of the nand flash is active during the write strobe (low pulse on nwe), thus the written byte is interpreted as a command by the nand flash. once the command is latched by the nand flash device, it d oes not need to be written for the following page read operations. 3. the cpu can send the start address (startad) for a read operation by writing four bytes (or three for smaller capacity devi ces), startad[7:0], then startad[16:9], startad[24:17] and finally startad[25] for 64 mb x 8 bit nand flash) in the common memory or attribute space. the ale input of the nand flash device is active during the write strobe (low pulse on nwe), thus the written bytes are interpreted as the start address for read operations. using the attribute memory space makes it i b ( # , + ! ; = . # % x . 2 % ' . ) / 7 . ) / 2 . 7 % . / % w r i t e ? d a t a r e a d ? d a t a ( i g h 6 a l i d - % - x 3 % 4 - % - x 7 ! ) 4 - % - x ( / , $ - % - x ( ) : RM0033 flexible static memory controller (fsmc) doc id 15403 rev 3 1261/1317 possible to use a different timing configuration of the fsmc, which can be used to implement the prewait functionality needed by some nand flash memories (see details in section 31.6.5: nand flash pre-wait functionality on page 1261 ). 4. the controller waits for the nand flash to be ready (r/nb signal high) to become active, before starting a new access (to same or another memory bank). while waiting, the controller maintains the nce signal active (low). 5. the cpu can then perform byte read operations in the common memory space to read the nand flash page (data field + spare field) byte by byte. 6. the next nand flash page can be read without any cpu command or address write operation, in three different ways: ? by simply performing the operation described in step 5 ? a new random address can be accessed by restarting the operation at step 3 ? a new command can be sent to the nand flash device by restarting at step 2 31.6.5 nand flash pr e-wait functionality some nand flash devices require that, after writing the last part of the address, the controller wait for the r/nb si gnal to go low as shown in figure 415 . figure 415. access to non ?ce don?t care? nand-flash 1. cpu wrote byte 0x00 at address 0x7001 0000. 2. cpu wrote byte a7~a0 at address 0x7002 0000. 3. cpu wrote byte a16~a9 at address 0x7002 0000. 4. cpu wrote byte a24~a17 at address 0x7002 0000. 5. cpu wrote byte a25 at address 0x7802 0000: fsmc performs a write access using fsmc_patt2 timing definition, where atthold 7 (providing that (7+1) hclk = 112 ns > t wb max). this guarantees that nce remains low until r/nb goes low and high again (only requested for nand flash memories where nce is not don?t care). nce noe i/o[7:0] r/nb ai14733 high twb cle ale 0x00 a7-a0 a16-a9 a24-a17 a25 tr nwe (1) (2) (3) (4) (5) nce must stay low flexible static memory controller (fsmc) RM0033 1262/1317 doc id 15403 rev 3 when this functionality is needed, it can be guaranteed by programming the memhold value to meet the t wb timing, however any cpu read or write access to the nand flash then has the hold delay of (m emhold + 1) hclk cycles insert ed from the rising edge of the nwe signal to the next access. to overcome this timing constraint, the attribute memory space can be used by programming its timing register with an atthold value that meets the t wb timing, and leaving the memhold value at its minimum. then, the cpu must use the common memory space for all nand flash read and write access es, except when writ ing the last address byte to the nand flash device, where the cpu must write to the attribute memory space. 31.6.6 error correction code computation e cc (nand flash) the fsmc pc-card controller includes two error correction code computation hardware blocks, one per memory bank. they are used to reduce the host cpu workload when processing the error correction code by software in the system. these two registers are identical and associated with bank 2 and bank 3, respectively. as a consequence, no hardware ecc computation is available for memories connected to bank 4. the error correction code (ecc) algorithm implemented in the fsmc can perform 1-bit error correction and 2-bit error detection per 256, 512, 1 024, 2 048, 4 096 or 8 192 bytes read from or written to nand flash. the ecc modules monitor the nand flash databus and read/write signals (nce and nwe) each time the nand flash memory bank is active. the functional operations are: when access to nand flash is made to bank 2 or bank 3, the data present on the d[15:0] bus is latched and used for ecc computation. when access to nand flash occurs at any other address, the ecc logic is idle, and does not perform any operation. thus, write operations for defining commands or addresses to nand flash are not taken into account for ecc computation. once the desired number of bytes has been read from/written to the nand flash by the host cpu, the fsmc_eccr2/3 registers must be read in order to retrieve the computed value. once read, they should be cleared by resetting the eccen bit to zero. to compute a new data block, the eccen bit must be set to one in the fsmc_pcr2/3 registers. 31.6.7 pc card/compactflash operations address spaces & memory accesses the fsmc supports compact flash storage or pc cards in memory mode and i/o mode (true ide mode is not supported). the compact flash storage and pc cards are made of 3 memory spaces: common memory space attribute space i/o memory space the nce2 and nce1 pins (fsmc_nce4_2 and fsmc_nce4_1 respectively) select the card and indicate whether a byte or a word operation is being performed: nce2 accesses RM0033 flexible static memory controller (fsmc) doc id 15403 rev 3 1263/1317 the odd byte on d15-8 and nce1 accesses the even byte on d7-0 if a0=0 or the odd byte on d7-0 if a0=1. the full word is accessed on d15-0 if both nce2 and nce1 are low. the memory space is selected by asserting low noe for read accesses or nwe for write accesses, combined with the low assertion of nce2/nce1 and nreg. if pin nreg=1 during the memory access, the common memory space is selected if pin nreg=0 during the memory access, the attribute memory space is selected the i/o space is selected by asserting low niord for read accesses or niowr for write accesses [instead of noe/nwe for memory space], combined with nce2/nce1. note that nreg must also be asserted low during accesses to i/o space. three type of accesses are allowed for a 16-bit pc card: accesses to common memory space for data storage can be either 8-bit accesses at even addresses or 16 bit ahb accesses. note that 8-bit accesses at odd addresses are not support ed and will not lead to the low assertion of nce2. a 32-bit ahb request is translated into two 16-bit memory accesses. accesses to attribute memory space where the pc card stores configuration information are limited to 8-bit ahb accesses at even addresses. note that a 16-bit ahb access will be conv erted into a single 8-bit memory transfer: nce1 will be asserted low, nce2 will be assert ed high and only the even byte on d7- d0 will be valid. instead a 32-bit ahb acce ss will be converted into two 8-bit memory transfers at even addresses: nce1 will be asserted low, nce2 will be asserted high and only the even bytes will be valid. accesses to i/o space must be limited to ahb 16 bit accesses. table 197. 16-bit pc-card signals and access type nce2 nce1 nreg noe/nwe niord /niowr a10 a9 a7-1 a0 space access type allowed/not allowed 1 0 101xxx-xx common memory space read/write byte on d7-d0 yes yes yes 0 1 1 0 1 x x x-x x read/write byte on d15-d8 not supported 0 0 1 0 1 x x x-x 0 read/write word on d15-d0 yes x 0 00101x-x0 attribute space read or write configuration registers yes x 0 00100x-x0 read or write cis (card information structure) yes 1 0 001xxx-x1 invalid attribute space read or write (odd address) yes 0 1 0 0 1 x x x-x x read or write (odd address) yes flexible static memory controller (fsmc) RM0033 1264/1317 doc id 15403 rev 3 the fsmc bank 4 gives access to thos e 3 memory spaces as described in section 31.4.2: nand/pc card address mapping - table 164: memory mapping and timing registers wait feature the compactflash storage or pc card may request the fsmc to extend the length of the access phase programmed by memwaitx/attwaitx/iowaitx bits, asserting the nwait signal after noe/nwe or niord/niowr activation if the wait feature is enabled through the pwaiten bit in the fsmc_pcrx register. in order to detect the nwait assertion correctly, the memwaitx/attwaitx/iowaitx bits must be programmed as follows: xxwaitx >= 4 + max_wait_assertion_time/hclk where max_wait_assertion_time is the maximum time taken by nwait to go low once noe/nwe or niord/niowr is low. after the de-assertion of nwait, the fsmc extends the wait phase for 4 hclk clock cycles. 1 0 010xxx-x0 i/o space read even byte on d7-0 not supported 1 0 0 1 0 x x x-x 1 read odd byte on d7-0 not supported 1 0 0 1 0 x x x-x 0 write even byte on d7-0 not supported 1 0 0 1 0 x x x-x 1 write odd byte on d7-0 not supported 0 0 0 1 0 x x x-x 0 read word on d15-0 yes 0 0 0 1 0 x x x-x 0 write word on d15-0 yes 0 1 0 1 0 x x x-x x read odd byte on d15-8 not supported 0 1 0 1 0 x x x-x x write odd byte on d15-8 not supported table 197. 16-bit pc-card signals and access type (continued) nce2 nce1 nreg noe/nwe niord /niowr a10 a9 a7-1 a0 space access type allowed/not allowed RM0033 flexible static memory controller (fsmc) doc id 15403 rev 3 1265/1317 31.6.8 nand flash/pc card controller registers pc card/nand flash control registers 2..4 (fsmc_pcr2..4) address offset: 0xa0000000 + 0x40 + 0x20 * (x ? 1), x = 2..4 reset value: 0x0000 0018 31302928272625242322212019181716151413121110987654321 0 reserved eccps tar tclr res. eccen pwid ptyp pbken pwaiten reserved rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 19:17 eccps: ecc page size. defines the page size for the extended ecc: 000: 256 bytes 001: 512 bytes 010: 1024 bytes 011: 2048 bytes 100: 4096 bytes 101: 8192 bytes bits 16:13 tar: ale to re delay. sets time from ale low to re low in number of ahb clock cycles (hclk). time is: t_ar = (tar + set + 2) thclk where thclk is the hclk clock period 0000: 1 hclk cycle (default) 1111: 16 hclk cycles note: set is memset or attset according to the addressed space. bits 12:9 tclr: cle to re delay. sets time from cle low to re low in number of ahb clock cycles (hclk). time is t_clr = (tclr + set + 2) thclk where thclk is the hclk clock period 0000: 1 hclk cycle (default) 1111: 16 hclk cycles note: set is memset or attset according to the addressed space. bits 8:7 reserved. bits 6 eccen: ecc computation logic enable bit 0: ecc logic is disabled and reset (default after reset), 1: ecc logic is enabled. bits 5:4 pwid: databus width. defines the external memory device width. 00: 8 bits (default after reset) 01: 16 bits (mandatory for pc card) 10: reserved, do not use 11: reserved, do not use bit 3 ptyp: memory type. defines the type of device attached to the corresponding memory bank: 0: pc card, compactflash, cf+ or pcmcia 1: nand flash (default after reset) flexible static memory controller (fsmc) RM0033 1266/1317 doc id 15403 rev 3 fifo status and interrupt register 2..4 (fsmc_sr2..4) address offset: 0xa000 0000 + 0x44 + 0x20 * (x-1), x = 2..4 reset value: 0x0000 0040 this register contains information about fifo status and interrupt. the fsmc has a fifo that is used when writing to memories to store up to16 words of data from the ahb. this is used to quickly write to the ahb and free it for transactions to peripherals other than the fsmc, while the fsmc is draining its fifo into the memory. this register has one of its bits that indicates the status of the fifo, for ecc purposes. the ecc is calculated while the data are written to the memory, so in order to read the correct ecc the software must wait until the fifo is empty. bit 2 pbken: pc card/nand flash memory bank enable bit. enables the memory bank. accessing a disabled memory bank causes an error on ahb bus 0: corresponding memory bank is disabled (default after reset) 1: corresponding memory bank is enabled bit 1 pwaiten: wait feature enable bit. enables the wait feature for the pc card/nand flash memory bank: 0: disabled 1: enabled note: for a pc card, when th e wait feature is enabled, the memwaitx/attwaitx/iowaitx bits must be programmed to a value as follows: xxwaitx 4 + max_wait_assertion_time/hclk where max_wait_assertion_time is the maximum time take n by nwait to go low once noe/nwe or niord/niowr is low. bit 0 reserved. 313029282726252423222120191817161514131211109876543210 reserved fempt ifen ilen iren ifs ils irs r rwrwrwrwrwrw bit 6 fempt: fifo empty. read-only bit that provides the status of the fifo 0: fifo not empty 1: fifo empty bit 5 ifen: interrupt falling edge detection enable bit 0: interrupt falling edge detection request disabled 1: interrupt falling edge detection request enabled bit 4 ilen: interrupt high-level detection enable bit 0: interrupt high-level detection request disabled 1: interrupt high-level detection request enabled bit 3 iren: interrupt rising edge detection enable bit 0: interrupt rising edge detection request disabled 1: interrupt rising edge detection request enabled RM0033 flexible static memory controller (fsmc) doc id 15403 rev 3 1267/1317 common memory space timing register 2..4 (fsmc_pmem2..4) address offset: address: 0xa000 0000 + 0x48 + 0x20 * (x ? 1), x = 2..4 reset value: 0xfcfc fcfc each fsmc_pmemx (x = 2..4) read/write register contains the timing information for pc card or nand flash memory bank x, used for access to the common memory space of the 16-bit pc card/compactflash, or to access the nand flash for command, address write access and data read/write access. bit 2 ifs: interrupt falling edge status the flag is set by hardware and reset by software. 0: no interrupt falling edge occurred 1: interrupt falling edge occurred bit 1 ils: interrupt high-level status the flag is set by hardware and reset by software. 0: no interrupt high-level occurred 1: interrupt high-level occurred bit 0 irs: interrupt rising edge status the flag is set by hardware and reset by software. 0: no interrupt rising edge occurred 1: interrupt rising edge occurred 313029282726252423222120191817161514131211109876543210 memhizx memholdx memwaitx memsetx rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:24 memhizx: common memory x databus hiz time defines the number of hclk clock cycles during which the databus is kept in hiz after the start of a pc card/nand flash write access to common memory space on socket x. only valid for write transaction: 0000 0000: (0x00) 0 hcl k cycle (for pc card) 1111 1111: (0xff) 255 hclk cycles (for pc card) - (default value after reset) bits 23:16 memholdx: common memory x hold time defines the number of hclk clock cycles to hold address ( and data for write access) after the command deassertion (nwe, noe), for pc card/nand flash read or write access to common memory space on socket x: 0000 0000: reserved 0000 0001: 1 hclk cycle 1111 1111: 255 hclk cycles (default value after reset) bits 15:8 memwaitx: common memory x wait time defines the minimum number of hclk (+1) clock cycles to assert the command (nwe, noe), for pc card/nand flash read or write access to common memory space on socket x. the duration for command assertion is extended if the wait signal (nwait) is active (low) at the end of the programmed value of hclk: 0000 0000: reserved 0000 0001: 2hclk cycles (+ wait cycle introduced by deasserting nwait) 1111 1111: 256 hclk cycles (+ wait cycle introduced by the card deasserting nwait) (default value after reset) flexible static memory controller (fsmc) RM0033 1268/1317 doc id 15403 rev 3 attribute memory space timing registers 2..4 (fsmc_patt2..4) address offset: 0xa000 0000 + 0x4c + 0x20 * (x ? 1), x = 2..4 reset value: 0xfcfc fcfc each fsmc_pattx (x = 2..4) read/write register contains the timing information for pc card/compactflash or nand flash memory bank x. it is used for 8-bit accesses to the attribute memory space of the pc card/compactflash or to access the nand flash for the last address write access if the timing must differ from that of previous accesses (for ready/busy management, refer to section 31.6.5: nand flash pre-wait functionality ). bits 7:0 memsetx: common memory x setup time defines the number of hclk (+1) clock cycles to set up the address bef ore the command assertion (nwe, noe), for pc card/nand flash read or write access to common memory space on socket x: 0000 0000: 1 hclk cycle (for pc card) / hclk cycles (for nand flash) 1111 1111: 256 hclk cycles (for pc card) / 257 hclk cycles (for nand flash) - (default value after reset) 313029282726252423222120191817161514131211109876543210 atthizx attholdx attwaitx attsetx rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:24 atthizx: attribute memory x databus hiz time defines the number of hclk cloc k cycles during which the databus is kept in hiz after the start of a pc card/nand flash write access to attribute memory space on socket x. only valid for write transaction: 0000 0000: 0 hclk cycle 1111 1111: 255 hclk cycles ( default value after reset) bits 23:16 attholdx: attribute memory x hold time defines the number of hclk clock cycles to ho ld address (and data fo r write access) after the command deassertion (nwe, noe), for pc card/nand flash read or write access to attribute memory space on socket x 0000 0000: reserved 0000 0001: 1 hclk cycle 1111 1111: 255 hclk cycles ( default value after reset) bits 15:8 attwaitx: attribute memory x wait time defines the minimum number of hclk (+1) clock cycles to assert the command (nwe, noe), for pc card/nand flash read or write access to attribute memory space on socket x. the duration for command assertion is extended if the wait signal (nwait) is active (low) at the end of the programmed value of hclk: 0000 0000: reserved 0000 0001: 2 hclk cycles (+ wait cycle introduced by deassertion of nwait) 1111 1111: 256 hclk cycles (+ wait cycle intr oduced by the card deasserting nwait) (default value after reset) RM0033 flexible static memory controller (fsmc) doc id 15403 rev 3 1269/1317 i/o space timing register 4 (fsmc_pio4) address offset: 0xa000 0000 + 0xb0 reset value: 0xfcfcfcfc the fsmc_pio4 read/write registers contain the timing information used to gain access to the i/o space of the 16-bit pc card/compactflash. bits 7:0 attsetx: attribute memory x setup time defines the number of hclk (+1) clock cycl es to set up addre ss before the command assertion (nwe, noe), for pc card/nand flash read or write access to attribute memory space on socket x: 0000 0000: 1 hclk cycle 1111 1111: 256 hclk cycles ( default value after reset) 313029282726252423222120191817161514131211109876543210 iohizx ioholdx iowaitx iosetx rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw bits 31:24 iohizx: i/o x databus hiz time defines the number of hclk clock cycles during which the databus is kept in hiz after the start of a pc card write access to i/o space on socket x. only valid for write transaction: 0000 0000: 0 hclk cycle 1111 1111: 255 hclk cycles (default value after reset) bits 23:16 ioholdx: i/o x hold time defines the number of hclk clock cycles to hold address (and data for write access) after the command deassertion (nwe, noe), for pc ca rd read or write access to i/o space on socket x: 0000 0000: reserved 0000 0001: 1 hclk cycle 1111 1111: 255 hclk cycles (default value after reset) bits 15:8 iowaitx: i/o x wait time defines the minimum number of hclk (+1) clock cycles to assert the command (smnwe, smnoe), for pc card read or write access to i/o space on socket x. the duration for command assertion is extended if the wait signal (nwait) is active (low) at the end of the programmed value of hclk: 0000 0000: reserved, do not use this value 0000 0001: 2 hclk cycles (+ wait cycle introduced by deassertion of nwait) 1111 1111: 256 hclk cycles (+ wait cycle intr oduced by the card deasserting nwait) (default value after reset) bits 7:0 iosetx: i/o x setup time defines the number of hclk (+1) clock cycles to set up the address before the command assertion (nwe, noe), for pc card read or write access to i/o space on socket x: 0000 0000: 1 hclk cycle 1111 1111: 256 hclk cycles (default value after reset) flexible static memory controller (fsmc) RM0033 1270/1317 doc id 15403 rev 3 ecc result registers 2/3 (fsmc_eccr2/3) address offset: 0xa000 0000 + 0x54 + 0x20 * (x ? 1), x = 2 or 3 reset value: 0x0000 0000 these registers contain the current error correction code value computed by the ecc computation modules of the fsmc controller (one module per nand flash memory bank). when the cpu reads the data from a nand flash memory page at the correct address (refer to section 31.6.6: error correction code computation ecc (nand flash) ), the data read from or written to the nand flash are processed automatically by ecc computation module. at the end of x bytes read (according to the eccps field in the fsmc_pcrx registers), the cpu must read the computed ecc value from the fsmc_eccx registers, and then verify whether these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it if applicable. the fsmc_eccrx registers should be cleared after being read by setting the eccen bit to zero. for computing a new data block, the eccen bit must be set to one. 313029282726252423222120191817161514131211109876543210 eccx r bits 31:0 eccx: ecc result this field provides the value com puted by the ecc computation logic. table 198 hereafter describes the contents of these bit fields. table 198. ecc result relevant bits eccps[2:0] page size in bytes ecc bits 000 256 ecc[21:0] 001 512 ecc[23:0] 010 1024 ecc[25:0] 011 2048 ecc[27:0] 100 4096 ecc[29:0] 101 8192 ecc[31:0] RM0033 flexible static memory controller (fsmc) doc id 15403 rev 3 1271/1317 31.6.9 fsmc register map the following table summarizes the fsmc registers. table 199. fsmc register map offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0xa000 0000 fsmc_bcr1 reserved cburstrw reserved asyncwait extmod waiten wren waitcfg waitpol bursten reserved faccen mwid mtyp muxen mbken reset value 0xa000 0008 fsmc_bcr2 reserved cburstrw reserved asyncwait extmod waiten wren waitcfg wrapmod waitpol bursten reserved faccen mwid mtyp muxen mbken 0xa000 0010 fsmc_bcr3 reserved cburstrw reserved asyncwait extmod waiten wren waitcfg wrapmod waitpol bursten reserved faccen mwid mtyp muxen mbken 0xa000 0018 fsmc_bcr4 reserved cburstrw reserved asyncwait extmod waiten wren waitcfg wrapmod waitpol bursten reserved faccen mwid mtyp muxen mbken 0xa000 0004 fsmc_btr1 res. accm od datlat clkdiv busturn datast addhld addset 0xa000 000c fsmc_btr2 res. accm od datlat clkdiv busturn datast addhld addset 0xa000 0014 fsmc_btr3 res. accm od datlat clkdiv busturn datast addhld addset 0xa000 001c fsmc_btr4 res. accm od datlat clkdiv busturn datast addhld addset 0xa000 0104 fsmc_bwtr1 res. accm od datlat clkdiv reserved datast addhld addset 0xa000 010c fsmc_bwtr2 res. accm od datlat clkdiv reserved datast addhld addset 0xa000 0114 fsmc_bwtr3 res. accm od datlat clkdiv reserved datast addhld addset 0xa000 011c fsmc_bwtr4 res. accm od datlat clkdiv reserved datast addhld addset 0xa000 0060 fsmc_pcr2 reserved eccps tar tclr res. eccen pwid ptyp pbken pwaiten reserved 0xa000 0080 fsmc_pcr3 reserved eccps tar tclr res. eccen pwid ptyp pbken pwaiten reserved 0xa000 00a0 fsmc_pcr4 reserved eccps tar tclr res. eccen pwid ptyp pbken pwaiten reserved 0xa000 0064 fsmc_sr2 reserved fempt ifen ilen iren ifs ils irs 0xa000 0084 fsmc_sr3 reserved fempt ifen ilen iren ifs ils irs 0xa000 00a4 fsmc_sr4 reserved fempt ifen ilen iren ifs ils irs 0xa000 0068 fsmc_pmem2 memhizx memholdx memwaitx memsetx 0xa000 0088 fsmc_pmem3 memhizx memholdx memwaitx memsetx flexible static memory controller (fsmc) RM0033 1272/1317 doc id 15403 rev 3 refer to table 1 on page 50 for the register boundary addresses. 0xa000 00a8 fsmc_pmem4 memhizx memholdx memwaitx memsetx 0xa000 006c fsmc_patt2 atthizx attholdx attwaitx attsetx 0xa000 008c fsmc_patt3 atthizx attholdx attwaitx attsetx 0xa000 00ac fsmc_patt4 atthizx attholdx attwaitx attsetx 0xa000 00b0 fsmc_pio4 iohizx ioholdx iowaitx iosetx 0xa000 0074 fsmc_eccr2 eccx 0xa000 0094 fsmc_eccr3 eccx table 199. fsmc register map (continued) offset register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RM0033 debug support (dbg) doc id 15403 rev 3 1273/1317 32 deb ug suppor t (dbg) 32.1 over vie w th e stm3 2f2 0 x a n d stm 32f 21x ar e b u ilt a r ou nd a cor t e x- m 3 cor e wh ich co nt ain s h a r d w a re e xt e n s io ns f o r ad v a nced d e b u g g ing f e at ur es . t he d e b ug e xt e n s io ns allo w t h e cor e t o be st opp ed e i th er o n a giv e n in str u ct ion f e tch ( b re akpo int ) or dat a a c cess ( w at chp o int ) . when st op ped , t h e cor e ? s int e r n a l st at e an d th e syst em? s e xt e r nal sta t e ma y b e e xam ined . o n ce e x a m ina t io n is co mple te , t he cor e a nd t h e syste m ma y be re st or ed and pr og r a m e x ec ut ion r e s u m e d. th e de b u g f eat ur es ar e used b y t h e d e b u g ger host wh en con nect i ng t o an d de b u ggin g t he stm 32f 20x and st m32 f 21 x mcus . t w o int e r f aces f o r de b u g ar e a v a ilab l e: ser i al wire jt a g de b u g por t figu re 41 6. bloc k diag ram of st m32 m c u and cor t e x -m 3-le ve l de b u g s upp or t not e : th e de b u g f eat ur es emb edd ed in t h e co r t e x - m 3 cor e ar e a subset of th e arm cor e sigh t de sig n k i t. e s t r i c t e d d i cortex- m 3 co r e s wj- d p ahb- ap br id g e nvic dw t fp b itm tpi u dco d e inte r f a ce s y s te m inte r f a ce int e r n a l pr iv a te p e ri ph e r a l bu s (p p b ) ext e r n a l pr iv a te pe r i p h e r a l bu s (p p b ) b us m a tri x d a t a tr a ce p o r t dbg m cu s tm 3 2f2 0x/ s tm 3 2f21x deb u g s upp or t c o r t ex- m 3 de b u g s u ppor t jt m s / jt di jt do/ njt r s t jt ck/ s wdi o s wcl k trace s wo trace s wo tr a c ec k tr a c ed [ 3 :0] a i1710 3 debug support (dbg) RM0033 1274/1317 doc id 15403 rev 3 th e arm co r t e x - m 3 cor e pr o v id es in te g r at e d on- chip de b ug supp or t . i t is co mpr i se d of : swj- dp: ser i al wire / jt a g de b u g por t ahp - ap: ahb access p or t i tm: i n st r u m ent at ion tr a c e macro c ell fpb: fl ash pat ch br ea kp oint d w t : dat a w a t chp oint tr ig ge r tpui: t r ace po r t un it int e rf ace (a v a ila b l e o n lar ger p a c kag es , wh er e th e co rr espo ndin g pin s ar e ma ppe d) etm: embe dde d t r a c e m a cro c e ll ( a v a ilab l e on l a rg er p a c kag es , wh er e th e cor r esp ond ing pi ns a r e m app ed) i t a l so i n clude s d e b ug f e a t u r e s de dicat e d t o t h e stm 32f 20x and st m32 f 21 x: fle x ib le de b ug pin o u t assignm ent mcu d e b u g b o x ( supp or t f o r lo w- po w e r mo des , cont r o l o v er p e r i ph er a l cloc ks , et c.) not e : f o r f u r t her inf o r m at ion o n deb u g fu ncti ona lity su pp or t ed b y t h e arm cor t e x-m3 cor e , r e f e r t o the cor t e x-m 3- r r 2p0 t e chn i ca l ref e ren ce man u al and to t h e co resig h t de sig n kit- r2 p0 trm ( s e e se ct ion 3 2. 2: re f e re nc e arm d o c u m e nt atio n ). 32.2 ref e rence arm documentation cor t e x? - m3 r2 p0 t e ch n i ca l re f e re nc e ma n u al ( t rm ) (se e re lat e d d o cume nt s o n pag e 1) arm de b u g in te rf ac e v5 arm coresight d e sign kit re vision r2 p0 t e ch n i ca l re f e re nc e ma n u al 32.3 swj deb u g por t (serial wire and jt a g ) th e stm 32f 20x an d stm3 2f2 1 x cor e int e g r at es t he se r i al wire / jt a g de b u g p o r t ( s wj- dp). i t is an arm sta nda rd co re sig h t deb u g por t t hat comb ines a jt a g - d p ( 5 - p in) int e r f a ce an d a sw -dp (2 -p in ) in te rf ac e . t h e jt a g de b u g p o r t ( jt a g - dp) p r o vid e s a 5- pin st an da rd jt a g in ter f a ce to th e ah p- ap por t . the se r i al wire deb u g p o r t ( s w - dp) pr o vid es a 2 - p i n (cloc k + d a t a ) in te rf ace t o t he ahp - ap por t . i n t h e swj- dp , t he t w o jt a g p i ns of th e sw -dp ar e m u lt iple x ed wit h some of t he f i v e jt a g pin s of th e jt a g - d p . RM0033 debug support (dbg) doc id 15403 rev 3 1275/1317 fi gu re 41 7. swj de b ug p or t fig u r e 41 7 sh o w s th at th e asynchr ono us t r a c e out pu t ( t ra cesw o ) is m u lt ip le x ed wit h tdo . this mea n s t h a t t h e a s yn ch ro nou s t r ace can o n ly be used wit h sw - d p , no t jt a g - d p . 32.3.1 mechanism to select the jt a g -dp or the sw -dp by def au lt, t he jt a g - d e b ug p o r t is a c t i v e . i f t h e d e b u g ger host w a n t s to s witch t o t he sw - d p , it m u st pr o v id e a de dicat ed jt a g seq uen ce on tm s/ tck (r espe ct iv ely map ped t o swdio a n d swclk) which disab l e s t he jt a g - d p a nd en ab les th e sw - d p . this w a y it is possib l e to a c t i v a t e t h e swdp u s in g on ly t h e swclk and swdi o pins . this sequence is : 1. se nd m o re th a n 50 t c k cyc les with t m s ( s wdi o ) =1 2 . sen d th e 16 -bit sequ ence o n tms (swdio ) = 0 111 10 011 110 01 11 ( m sb t r a n smit te d fir st) 3. se nd m o re th a n 50 t c k cyc les with t m s ( s wdi o ) =1 32 .4 pinout and deb u g por t pins th e stm3 2f2 0 x a n d stm 32f 21x mcus ar e a v a ilab l e in v a r i o u s pac kag e s wit h dif f er en t n u mbers of a v ailab l e pins . as a result, some functionality (etm) relate d to pin a v ailability ma y d i ff er bet w e en p a c kag es . trac e s wo jtdo jtdi njt r s t nt r s t td i tdo s wj-dp tdo td i ntr s t tck tm s np o t r s t jt a g -dp npo t r s t fr o m po we r - on re s et dbgr e s etn dbgdi dbgdo dbgdoen db gc lk s w- d p s wclk t ck s wdoe n s wdo s wditm s s wd / j t a g s elect jtm s / s wdio jtck/ s wclk ( as ynchro no us tr a ce) a i171 3 9 debug support (dbg) RM0033 1276/1317 doc id 15403 rev 3 32.4.1 swj deb ug por t pins fiv e p i ns ar e used as ou tp ut s f r o m th e stm3 2f2 0 x a nd stm 32f 21x f o r t he swj- dp a s a l te r n a t e fu nc tio n s of g e n e r a l- pu r p ose i / o s . th ese pin s a r e a v aila b l e o n all pa c k a g e s . 32.4.2 fle x ib le swj-dp pin assignment after res e t (s ysresetn or poresetn), all fiv e pins used f o r the swj-dp are assigned a s d e d i ca te d p i ns imme diat e l y u s a b le b y th e de b ugg er host (n ot e t h a t th e t r ace out pu t s a r e n o t a s sig ned e x ce pt if e xplicit ly pr og r a mme d b y t he d e b ugg er h o st ). ho w e v e r , the stm32f20x and s t m32f21x mcu s off e r the possibility of dis a b ling some or a ll o f t h e swj-dp p o r t s a nd so , of re lea s in g th e associat ed p i ns f o r ge ner a l -p ur pose i o ( g pi o) u s a g e . f o r m o re det ails on h o w t o disab l e swj- dp p o r t p i ns , plea se r e f e r to sec t ion 6 .3.2: i/o pin m u ltiple x e r and mapping . note: w hen the apb br idge w r ite b u ff er is full, it tak e s one e x tr a apb cycle when wr iting the gpi o_ a f r r e gist er . t h is is be ca us e th e de ac tiv a tio n of th e jt a gs w p i ns is do ne in t w o cycle s t o gu ar a n t ee a clea n le v e l o n th e n t rst an d tck in put sig n a l s of t he cor e . cycle 1 : t he jt a g sw inpu t sign als t o t h e cor e ar e t i ed t o 1 or 0 (t o 1 f o r ntrst , tdi an d tms , to 0 f o r tck) cycle 2 : t he gpi o con t r o lle r ta k e s th e cont r o l sig nal s of th e swjt a g i o pi ns ( lik e cont r o ls o f d i rect ion , pu ll-u p / d o w n, sch m itt t r igge r act i v a t i on, et c.) . t a b l e 20 0. swj de b u g p o r t pi ns sw j-dp pi n name jt a g deb u g po r t sw d e b u g p o r t pin assign ment t y pe desc ription t ype deb ug assignme nt jt ms/s wdio i jt a g t e st mode selectio n io s e r i al wire data i n put/ output pa 1 3 jtck/swcl k i jt a g t e st clo c k i s e r ial wire cloc k p a 14 jtdi i jt a g t e st data in put - - p a 15 jt do/t ra cesw o o jt a g t e st data o u t p ut - tra c esw o if async tr ace is e nab l e d pb3 njtrst i jt a g t e st nres et - - pb4 t a b l e 201. fle x i b l e swj - dp pi n a s s i g n ment a v ail a b l e deb u g po r t s swj io pin as signed pa 1 3 / jtms/ swdio pa 1 4 / jt c k / swclk pa 1 5 / jtdi pb3 / jtd o pb4/ nj t rs t full swj (j t a g-dp + sw -dp) - reset state x x x x x full s w j (jt a g- dp + sw -dp) b u t without nj trst x x x x jt a g -dp disab led an d sw -dp en ab l e d x x jtag-dp disabled and sw-dp disabled rele ased RM0033 debug support (dbg) doc id 15403 rev 3 1277/1317 32.4.3 internal pull-up and pull-do wn on jt a g pins i t is nece s sar y t o en sure th at t h e jt a g in pu t pin s ar e no t f l oa tin g since th e y ar e dir e ct ly co nn e cte d to flip -f lop s t o co ntr o l th e de b u g m o d e f e at ur es . spe cia l c a r e m u s t b e ta k e n wit h t h e swclk/ tck p i n wh ich is dir e ct ly con nect e d t o t he cloc k of so me of th ese f lip-f lo ps . t o a v oi d an y u n cont r o lled io le v e ls , th e de vice em bed s in te r n a l p u ll- up s an d pu ll-do wns on t h e jt a g in put pin s : nj tr st : in te r n a l p u ll- up jtdi: in te r n al pull- up jtm s /sw d io : int e r n al pu ll-u p tck/swclk: inter n al pull-do wn on ce a jt a g i o is r e le as ed b y th e u ser s o ft w a r e , t h e g p io co n tro lle r t a k e s con tr o l ag a i n. th e re set st at es of t h e g p io co nt ro l r e g i st er s p u t t h e i/ os in t he eq uiv a le nt st at e: nj tr st : input pull-up jtdi: in put pu ll-u p jtm s /sw d io : inp u t p u ll-u p jtck /swc lk: input pull-do wn jtdo : in pu t f l oa tin g th e sof t w ar e ca n th en u s e t he se i/ os as st an da rd g p i o s . note: t he jt a g ieee standard recommends to ad d pull-ups on td i, tms and ntrst b u t there is n o sp ecial r e comme n d a t i on f o r t c k. ho w e v e r , f o r jt ck, th e de vice n eed s an i n t e g r a t e d pull-do wn. ha vin g emb e d ded p u ll- up s an d pu ll-do wns re mo v e s th e nee d t o add e xte r n a l r e sist ors . debug support (dbg) RM0033 1278/1317 doc id 15403 rev 3 32.4.4 using serial wire and releasing the un use d deb ug pins as gpios t o use t h e se r i al wire dp t o rele ase som e gpi o s , t h e user so ft w a re m u st cha n g e t he g p io ( p a15, pb3 and pb4 ) co nf igu r at ion m ode in th e gpi o _m oder r egist er . t h is r e le ases p a 15 , pb3 an d pb4 wh ich no w b e come a v aila b l e as g p io s . whe n de b u ggin g , th e host per f o r m s t he f o llo wing a c t i on s: un d e r sy ste m re se t, all swj pin s ar e ass i gn e d ( j t a g - d p + sw - d p) . unde r syst em r e set , t h e d e b u g ger host sen d s th e jt a g se qu ence t o s w it ch fr om t h e jt a g -d p to the sw -d p . stil l u nde r syst em r e set , t h e d e b u g ger se ts a br eakp o int on v e ct or r e set . the syste m re se t is r e le ased a nd t h e cor e ha lts . all th e deb u g co mm un ica t io ns fr om t h is poin t ar e do ne u s in g t he sw - d p . the o t her jt a g pin s can t h e n be r eassign ed as gpi o s b y th e user so ft w a re . no te : f or u s er s o ft w a r e de sig n s , no te t h a t: to release the deb ug pins , rememb er that the y will be first confi gured either in input-pull-up ( n trst , tms , tdi) o r pu ll-d o wn ( t ck) or out pu t t r ista te (tdo) f o r a cer t ain du r a t i o n af te r r e set unt il th e inst ant when t h e user sof t w ar e re lea s e s t h e p i ns . whe n de b ug p i ns (jt a g o r sw or t r a c e) a r e map ped , cha ngi ng t h e co rr espo ndin g i o pin con f ig ur a t io n in t he i o po r t con t r o lle r ha s no e f f e ct . 32.5 stm32f20x and stm32f21x jt a g t a p connection th e stm3 2f2 0 x a n d stm 32f 21x mcus int e g r at e tw o ser i ally co nn ecte d jt a g t aps , t h e b oun da r y scan t a p (i r is 5- bit wid e ) a n d t h e co r t e x- m 3 t ap (i r is 4- bit wid e). t o acce ss th e t ap of t h e co r t e x - m 3 f o r d e b u g p u r poses: 1 . fir s t , it is n e cessar y t o sh ift th e byp ass inst r u ct ion of th e bo und ar y scan t a p . 2 . the n , f o r ea ch i r sh ift , t h e scan ch ain cont a i ns 9 b i t s (=5 + 4 ) an d th e un u s e d t ap instr u cti on m u st be shifted in using the b y p ass instr u ction. 3 . f o r e a ch d a t a sh ift , t he un used t a p , which is in byp ass mod e , a d d s 1 e xt r a dat a bit in t he da ta scan ch ain. note: impor t a nt : o n ce ser i al- w ire is se lect ed usin g th e de dicat e d arm jt a g se que nce , t h e bo u n d a r y sca n t a p is au to m a tic a lly d i sab l ed ( jt m s f o rc ed h i gh ) . RM0033 debug support (dbg) doc id 15403 rev 3 1279/1317 figu re 41 8. j t a g t a p conn ect ions 32.6 id codes and loc k ing mec h anism th er e ar e se v e r a l i d co des inside t h e st m32 f 20 x an d stm3 2f2 1 x m c us . st st ro ngly r e comm end s t o o l s d e signe rs to lo c k t h e i r de b u gg ers using t h e mcu devi ce i d co de located in the e xter nal ppb memo r y map at address 0xe0042000. 32.6.1 mcu de vice id code th e stm3 2f2 0 x a n d stm 32f 21x mcus int e g r at e an mcu i d co de . t h is i d id en tif i es th e st mcu p a r t -n u m be r an d th e die r e vision. i t is p a r t o f t h e dbg_ mcu comp one nt and is ma pp ed on th e e xte r n al ppb b u s (see sect ion 3 2. 16 o n pag e 12 91 ). this code is a c cessib l e using t h e jt a g d e b u g p o r t ( 4 t o 5 pins) o r t he sw d e b u g p o r t ( t w o pi ns) or b y th e us er soft w a re . i t is e v en accessib l e while the mcu is under sys tem reset. dbgmcu _ id code ad dre ss: 0xe004 200 0 o n ly 3 2 - b it s a c cess su ppo r t e d . re ad- on ly . boundary s can tap njtr s t cortex-m 3 tap jtm s tm s ntr s t tm s ntr s t jtdi jtdo tdi tdo tdi tdo s w-dp s tm 3 2f20 xxx s e lec ted ir i s 5- b it wide ir i s 4- b it wide a i17104 31 30 29 28 2 7 26 2 5 24 23 2 2 21 20 19 1 8 17 16 rev_ id r rrrr r r r r r rrrr r r 1 5 1 4 1 3 1 2 1 1 1 0 9 8 76 5432 1 0 reser v e d dev _ id r r r r rr rrrr r r debug support (dbg) RM0033 1280/1317 doc id 15403 rev 3 32.6.2 boundar y scan t a p jt a g id code th e t ap of t h e st m32 f 20 x an d stm3 2f2 1 x bsc ( b o u n dar y scan) int e g r a t e s a jt a g i d cod e eq ual t o 0 x 4 ba0047 7. 32.6.3 cor t e x -m3 t a p th e t a p of t h e arm cor t e x-m3 int e g r at es a jt a g i d code . t h is i d co de is th e arm def au lt o ne an d ha s no t b een m odif i e d . th is cod e is o n ly a cce ssib le b y t he jt a g deb u g p o r t . this code is 0 x4b a00 477 ( cor resp ond s t o cor t e x-m3 r 2 p 0 , se e se ct ion 3 2. 2: re f e re n ce arm do cu men t a t io n ). o n ly t h e dev_i d (1 1: 0) sh ould b e used f o r iden t i ficat i on b y th e de b u gge r/ pr og r a mme r t ools . 32.6.4 cor t e x -m3 jedec-106 id code th e arm co r t e x- m 3 int e g r at es a jedec-1 06 i d cod e . i t is lo ca te d in t he 4 k b r o m t a b l e mapped on the inter n al ppb b u s at address 0xe00f f000_0xe 00fffff . th is co de is accessib l e b y t h e jt a g de b ug p o r t ( 4 t o 5 pin s ) or b y t he sw deb u g p o r t (t w o p i ns) or b y th e user so ft w a re . 32.7 jt a g deb u g por t a st an da rd jt a g st at e ma ch ine is imp l eme n t e d wit h a 4 - b i t inst r u ctio n reg i ste r (i r) and f i v e da ta r e g i st er s ( f o r f u ll de ta ils , r e f e r to the cor t e x-m3 r 2 p0 t e chn i cal re f e re nce ma n ual ( t rm), f o r r e f e r ences , ple a se see sect ion 3 2. 2: re f e re nce arm d o cume nt at ion ) . bits 31:16 rev_id(15:0) re visio n iden ti fi er thi s fiel d indi cates the re vision of the de vice: ? 0 x1 00 0 = re vision a ? 0 x1 00 1 = re vision z ? 0 x2 00 0 = re vision b ? 0 x2 00 1 = re vision y bits 15:12 reser v ed bits 11 :0 dev_id(11:0) : de vice ide n ti fi er the d e vi ce id is 0x411 t a b l e 20 2. j t a g de b u g p o r t dat a re gi ste r s i r ( 3 :0 ) d ata r e gi st er d e ta il s 1 111 byp ass [1 bit] 1 110 idcod e [3 2 bits] id code 0 x4ba004 77 (arm co r t e x-m3 r2 p0 id co de) RM0033 debug support (dbg) d o c id 154 03 re v 3 1 281 /13 1 7 1 010 dp a cc [3 5 bits] deb u g por t access register thi s in iti a tes a d e b u g por t a nd all o ws a c ce ss to a deb u g por t re gister . ? w hen tr an sf err i n g data in: bits 34:3 = d a t a [31 : 0 ] = 32 -b it d a ta to tr an sf er f o r a wr ite re quest bits 2:1 = a[3:2] = 2-bit add re ss of a deb ug por t re gister . bit 0 = rnw = re ad requ est (1) or wr ite requ est (0). ? w hen tr an sf err i n g data out : bits 34:3 = d a t a [31 : 0 ] = 32 -b it d a ta w h ich is read f o llo win g a re ad req uest bits 2:0 = a c k[2:0] = 3 - b i t ac kno w l edg e: 01 0 = ok/f a ul t 00 1 = w a it o t her = rese r v ed re f e r t o t ab l e 203 f o r a de scr iption o f the a(3:2 ) b its 1 011 ap a c c [3 5 bits] access por t access register initiates an access p o r t an d allo w s access to an access por t register . ? w hen tr an sf err i n g data in: bits 34:3 = d a t a [31 : 0 ] = 32 -b it d a t a to shift in f o r a wr ite reques t bits 2:1 = a[3:2] = 2-bit add r e ss (sub- a ddress ap registers). bit 0 = rnw = read req uest (1 ) o r wr i t e req uest (0 ). ? w hen tr an sf err i n g data out : bits 34:3 = d a t a [31 : 0 ] = 32 -b it d a ta w h ich is read f o llo win g a re ad req uest bits 2:0 = a c k[2:0] = 3 - b i t ac kno w l edg e: 01 0 = ok/f a ul t 00 1 = w a it o t her = rese r v ed the r e a r e ma n y ap regi sters (see ahb-ap) ad dressed as the co mb ina t io n of: ? t he shifted v a l ue a[3 : 2 ] ? t he current v a lu e of the dp select reg i ste r 1 000 abor t [3 5 bits] abo r t re gist er ? b its 31:1 = reser v ed ? b it 0 = d a p abor t : wr ite 1 to ge nerate a d a p ab or t. t a b l e 20 3. 3 2 - b it deb ug por t regist er s ad d r es sed t h r o ugh t h e shif te d v a lue a[ 3: 2] ad dr ess a ( 3 : 2) v a lue desc ription 0x0 0 0 re ser v e d 0x4 0 1 dp ctrl/st a t reg i ster . u sed to : ? r equest a system or deb u g po w e r - up ? c on fi gure the transf e r o perati on f o r ap a cce sses ? c on trol the p u shed compa r e and pu shed v e r i fy op er a t i ons . ? r ea d some status fl ags (o v e rr un , po w e r-up a c kn o wled ges) t a b l e 20 2. j t a g de b u g p o r t dat a re giste r s (c ontin ue d) i r ( 3 :0 ) d ata r e gi st er d e ta il s debug support (dbg) RM0033 1282/1317 doc id 15403 rev 3 32 .8 sw de b u g por t 32.8.1 sw pr otocol intr oduction th is synchr ono us se r i al pr ot ocol uses t w o pin s : swc l k: clo c k fro m h o s t to t a r g e t swd i o : b i dir e ctio na l th e pr ot ocol allo ws t w o ban ks of re giste r s (dp a cc re gist ers an d ap a cc r e g i ste r s) t o be r e a d and wr it t en t o . bits ar e tr a n sf er re d ls b-fir s t on t h e w i re . f o r swdi o b i dir e ctio nal ma na gem ent , t h e line m u st b e pu lled- up o n t he bo ar d (1 00 k r e comm end ed b y arm) . ea ch t i me t h e d i re ct io n of swdio ch ang es in th e pr ot ocol, a tu r n aro u n d tim e is inse r t ed whe r e t h e line is n o t dr iv en b y th e host nor th e ta rg et . by def au lt, t h is t u r n a r ou nd t i me is on e bit tim e , ho w e v e r t h is ca n be a d ju st ed b y co n f igu r in g th e s w cl k fr e q u e n c y . 32.8.2 sw pr otocol sequence ea ch seq u e n ce co nsist of th re e ph ases: 1 . p a c k e t re que st (8 b i ts) t r a n smit te d b y t he ho st 2 . ac kno wledg e re sp on se ( 3 bit s ) t r an smi t t e d b y t h e ta rg et 3 . dat a tr ansf e r p h a s e ( 3 3 b i ts) t r a n smit te d b y t he ho st or t h e ta rg et 0x8 1 0 dp select reg i ster : u sed to se lect the curren t access por t a nd the ac tiv e 4-w o rds re gist er w i n d o w . ? b its 31:24: apsel: select the cur r ent ap ? b its 23:8: reser v ed ? b its 7:4: apb ank sel: sele ct th e acti v e 4-w o rds re gister w i ndo w o n the current ap ? b i t s 3: 0: re se r v e d 0xc 1 1 dp rdbuff re gister : used to allo w the de b ugg er to ge t the final resu lt a f ter a se que nce of o perati ons (withou t requ esti ng ne w jt a g -dp o per a t i on) t a b l e 20 3. 3 2 - b it deb ug por t regist er s ad d r es sed t h r o ugh t h e shif te d v a lue a[ 3: 2] ad dr ess a ( 3 : 2) v a lue desc ription tabl e 20 4. p a c k et re que st ( 8 - b i t s ) b i t n ame d e scription 0 s ta r t must b e ?1 ? 1 apndp 0: dp access 1: a p access 2r n w 0: wr ite req uest 1: read re quest RM0033 debug support (dbg) doc id 15403 rev 3 1283/1317 ref e r to the cor t e x -m3 r2 p0 trm f o r a d e t a ile d descr ipt i on o f dp a c c and ap a cc r egist er s . th e pa c k e t req u e s t is alw a ys f o llo w ed b y t h e t u r nar ou nd t i me ( d e f a u lt 1 b i t ) wh er e ne ith e r th e ho st no r ta rg et d r iv e th e lin e . th e a c k re sp onse m u st be f o llo w ed b y a t u r nar ou nd t i me only if it is a read t r an sa ctio n o r if a w a i t or f a u l t a c kn o wle dg e ha s be en r e c e iv e d . th e d a t a t r an sf er m u st be f o l l o w ed b y a t u r n a r o und t i me o n ly if it is a read tr ansa c t i on . 32.8.3 sw -dp state mac h ine (r eset, idle states, id code) th e sta t e machin e of th e sw - d p ha s an in t e r n al id code wh ich id ent if ies th e sw - d p . it f o llo ws t h e jep- 106 st and ar d. this id co de is th e de f a ult arm on e an d is set t o 0 x2b a01 477 ( cor resp ond ing t o cor t e x-m3 r2p 0 ) . not e : n ot e t h a t t he sw - d p st at e machin e is in act i v e u n t il th e t a rg et rea d s th is i d cod e . the s w -dp state machine is in r eset st a t e ei ther after po w e r-on reset, or after the dp h a s s wit ch ed f r o m jt a g t o swd o r af t e r t h e lin e is h i gh f o r m o r e th an 5 0 cycles the sw -d p state machine is in id le st a t e if the line is lo w f o r at least tw o c ycles after res e t state . after r eset state , it is manda tor y to fir st en te r int o an id le sta t e an d t o p e r f o r m a rea d access of the dp-sw id c o d e regi ster . otherw ise , the target will iss u e a f a ul t ac kn o wle dge r e spo n se on a not h e r t r an sactio ns . 4:3 a (3:2) a ddre ss field o f the dp or ap regi sters (ref e r to t ab l e 203 ) 5 p ar ity s ing l e bit par i t y of p r ecedi ng bits 6s t o p 0 7p a r k not dr iv en b y t h e host . mu st be r e a d as ? 1 ? b y th e ta rg et be cause of t he pu ll-u p t a b l e 20 5. a c k res pons e (3 bit s ) b i t n ame d e scription 0. .2 ac k 00 1: f a ul t 01 0: w a it 10 0: ok t a b l e 20 6. d a t a t r ans f er ( 3 3 bi t s ) b i t n ame d e scription 0..3 1 wd a t a or rd a t a wr i t e o r re ad data 32 pa r i t y sing le par ity of th e 3 2 data bits t a b l e 20 4. p a c k et re que st ( 8 - b i t s ) (c ont in ue d) b i t n ame d e scription debug support (dbg) RM0033 1284/1317 doc id 15403 rev 3 fu r t h e r d e t a ils of t h e sw -dp st at e ma chine can be f oun d in t he cor t e x -m 3 r2 p0 trm an d th e cor e sig h t de sig n kit r 2p0 t r m . 32.8.4 dp and ap read/write accesses read a c ce sses t o th e dp ar e no t p o ste d : t h e ta rg et r e spo n se can be i mmed i at e (if a c k = ok ) o r ca n be d e la y e d (if a c k=w a i t ) . read a c ce sses t o th e ap a r e p o ste d . t h is me a n s th at th e re su lt o f th e a c c e s s is re tu r n ed on t h e ne xt t r a n sf e r . if t h e ne xt access t o be do ne is no t an ap access , th en t he dp-rdb uff r egist er m u st be r ead to o b t a in t h e r e sult . the readok fla g of th e dp- c trl/ st a t re giste r is u pda t ed on e v er y ap r e a d access o r rdb u f f re ad r e q u e s t to k n o w if th e a p re a d ac ces s w a s s u c ces sfu l . the sw -dp imple m en ts a wr ite b u ff er ( f or b o t h dp o r ap wr it es), th at ena b l e s it to accept a wr ite oper ation e v en when other tr ansactions are still outs tanding. if the wr ite b u f f e r is f u ll, t he t a r get ac kno wled ge r e spon se is ? w ait? . wit h t he e xcep t io n of i d code r ead or ctrl/ s t a t re ad or abo r t wr ite wh ich ar e a c cep t ed e v en if t h e wr ite b u ff er is fu ll. be ca us e of th e as yn chr o no us clo c k d o m a i n s sw clk a n d hc lk, two e x tr a swcl k cycles ar e ne ede d af t e r a wr it e tr ansact i on ( a f t e r t h e p a r i t y b i t) to m a k e t h e wr it e e f f e ct iv e int e r n a lly . t h es e c ycle s sho u l d be applied while dr ivin g the line lo w (idle st at e) thi s is p a r t icular ly impo r t a n t wh en wr it ing t h e ctrl /st a t f o r a po w e r- up r e q uest . i f t h e ne x t tr ansaction (requir i ng a po w e r-up) oc curs immediately , it will f a il. 32.8.5 sw -dp register s access t o th ese r egist er s ar e init ia te d wh en apndp=0 t a b l e 20 7. sw -dp r e gi st er s a(3:2) r/w ctrlsel bit of select re g i s t er regis t er notes 00 r ead idcode th e ma n u f a cturer code is no t set to st code . 0x2 b a 0 147 7 (i dentifie s the sw -dp) 00 wr ite abor t 01 r ead/w r ite 0 dp-ctrl/st a t pur pose is to : ? r eque st a system or deb ug po w e r-up ? configu r e the tr a n sf er ope r a tion f o r ap accesses ? control the pushe d compare an d pushe d v e r i fy ope r a tion s . ? r ead some status flag s (o v e rr un , p o w e r-up ac kno w l edge s) 01 r ead/w r ite 1 wi re contr o l pur pose is to con f i gure the ph ysical ser i al po r t protocol (li k e the d u r a tio n of the tur narou nd ti me ) 10 r ead read resend enab les reco v e r y o f th e read da ta from a corr up te d deb u gge r tr an sf er , withou t repe ating the or i g ina l ap tr an sf er . RM0033 debug support (dbg) doc id 15403 rev 3 1285/1317 32.8.6 sw -ap register s access t o th ese r egist er s ar e init ia te d wh en apndp=1 th er e ar e man y ap reg i st er s ( see ahb-ap) ad dr essed as th e comb inat io n of : t h e s h if te d v a lu e a[3 : 2 ] t h e c u r r e n t v a lue o f th e dp sel ect re gis t er 32.9 ahb-ap (ahb access por t) - v a l i d f o r both jt a g -dp an d sw -d p fe atures: syst em a c cess i s ind epe nd ent of t h e pr ocesso r sta t u s . either sw -dp or jt a g -dp accesses ah b-ap . the ahb- ap is an ahb m a ste r int o t h e bu s ma t r ix. co nseq uen t l y , it ca n access a ll t h e data b u ses (d code bus , system bus , inte r nal and e xter n al ppb b u s) b u t the ic ode bu s . bitb an d tr ansact i on s ar e supp or t e d . ahb - ap tr ansactions b ypass the fpb . th e ad dr ess of t he 32 -b its ahp- ap r e siste r s ar e 6-b i t s wide ( up t o 64 w o r d s o r 25 6 b y t e s) a nd con s ist s of : c) b i ts [7:4] = the bits [7:4] ap banksel of the d p select register d) bit s [3 :2 ] = t h e 2 add re ss bit s o f a( 3: 2) o f t he 35 -b it p a c k e t re que st f o r sw - d p . 10 wr ite select the pur pose is to select the current access po r t and the activ e 4-w o rds regi ste r wi ndo w 11 r ead/w r ite read buff e r th is re ad b u ff e r is useful b e cause ap accesses are p o sted (the resul t of a read ap requ est is a v a ilab l e on the ne xt ap tr an sa cti on). t h i s r e a d b u f f er ca pt ur es da t a fro m t h e ap , prese n ted as the re su lt o f a pre viou s rea d , witho ut in itiating a ne w transaction t a b l e 20 7. sw -dp r e gi st er s ( c ont i n u e d) a(3:2) r/w ctrlsel bit of select re g i s t er regis t er notes debug support (dbg) RM0033 1286/1317 doc id 15403 rev 3 th e ahb- ap o f t h e cor t e x - m 3 includ es 9 x 32 -b its re gist ers: ref e r to t h e co r t e x - m 3 r 2p0 t r m f o r f u r t he r de ta ils . 32.10 core deb u g cor e de b u g is a c cessed t h r o u gh t h e cor e de b u g re gist er s . deb u g a c ce ss to t h ese re giste r s is b y m e an s o f th e ad v anced hig h - per f o r m ance bus (ahb-ap) p o r t . th e pr ocesso r can a c cess th ese re giste r s dir e ctly o v er t h e in te r n al pr iv at e p e r i p her al bus (ppb). i t con s i s t s o f 4 r egist er s: note: impor t a nt : th es e re gis t e r s ar e no t r e set b y a sys te m re se t. th e y a r e o n ly re se t b y a p o wer - on r e s e t . ref e r to t h e co r t e x - m 3 r 2p0 t r m f o r f u r t he r de ta ils . t a b l e 20 8. cor t e x -m 3 ahb-ap reg i s t e r s ad dres s offset register na me note s 0x00 a h b- ap control and status wo r d configu r es a nd control s tr an sf ers thro ugh the ahb interf ace (siz e , hprot, status on curren t transf e r , ad dress incremen t typ e 0x04 ah b-ap t r ansf e r addr ess 0x0c a h b- ap data read/wr i te 0x10 ah b-ap bank e d da ta 0 directly map s the 4 alig ned da ta w o rds w i thout re wr iting th e t r a n sf er address reg i ste r . 0x14 ah b-ap bank e d da ta 1 0x18 ah b-ap bank e d da ta 2 0x1c a h b- ap bank ed data 3 0xf8 ah b-ap deb ug r o m addre s s b a se address of the de b u g in te rf ace 0xfc ah b-ap id re gister t a b l e 20 9. core debug registe r s r e giste r de scription dhcsr the 3 2 -bit deb u g halting co ntrol and status regi ster thi s pro vi des status inf o r m a t i on abo ut the state o f the processo r en ab l e co re d e b u g halt and step the processo r dcrsr the 1 7 -bit deb u g core regi ste r sel e cto r re gister : thi s sel e cts the processo r reg i ste r to transf e r da ta to or fro m . dcrdr the 3 2 -bit deb u g core regi ste r da ta re gister : thi s ho lds data f o r read ing an d wr iting reg i sters to and from the p r ocessor selected b y the dcrsr (selector) register . demc r the 3 2 -bit deb u g exce pti on and mon i tor c ontrol reg i ste r : thi s pro vi des v e cto r ca tchi ng an d d e b u g mon i tor c ontrol. thi s reg i ste r con t a i ns a bit n a med tr cena w h i ch e n a b le th e use of a tr a c e. RM0033 debug support (dbg) doc id 15403 rev 3 1287/1317 t o h a lt o n re se t, it is ne ce ssa r y to : enab le the bit0 (vc _ c o rr eset) of the deb u g and exception monitor control regist er en ab le t he bit 0 ( c _ d eb ugen) of th e deb ug halt ing con t rol a nd st at us re giste r . 32.11 capability of the deb u g g er host to connect under system reset th e stm3 2f2 0 x a n d stm 32f 21x mcus? re se t sys tem compr ises t h e f o llo w ing reset sources: por (po w er-on re set) w h ich asser t s a r eset at each po w e r-up . in te r n a l w a tch d o g re se t sof t w ar e re se t ex ter n al reset th e cor t e x-m3 d i f f e r e n t i at es t h e re se t of th e de b u g pa r t (g en er all y porreset n ) a nd t he other one (sy sresetn) th is w a y , it is p o ssib l e f o r th e de b u gge r t o conn ect u nde r syst em reset , p r o g r a m m ing t h e co re de b u g re gis t er s to ha lt th e cor e wh en f e t chin g th e re se t v e ct or . t h en th e h o st ca n release the sy stem reset and the core will i mmediately halt without ha ving e x ecuted an y in st r u ct ion s . i n ad dit i on , it is po ssib le to pro g r a m a n y de b ug f eat u r es un der syst em reset . not e : i t is hig h ly r e com m en ded f o r th e de b u gge r ho st t o co nne ct (se t a br ea kp oin t in t he r e set v e ct or ) un de r syst em re set . 32.12 fpb (flash patc h breakpoint) th e fpb unit : imp l eme n t s ha rd w a r e br ea kp oint s pa tche s cod e an d dat a f r o m co de spa c e t o syst e m spa c e . this f e at ur e giv e s t he pos sibil it y t o correct soft w a re b u gs located in the code memor y spac e . th e use of a sof t w ar e p a tch o r a hard w a r e bre a kpo i nt is e xclusiv e . th e fpb co nsists of : 2 lit er al comp ar a t o r s f o r mat ching a gain st lit er al loa d s f r om code spa ce a n d r e ma ppin g t o a co rr espo ndin g ar ea in t h e syst em space . 6 inst r u ct ion comp ar a t o r s f o r ma tchin g ag ainst i n str u ct ion f e tche s f r o m co de sp ace . the y ca n be u s e d eit h e r t o rem ap t o a cor r e s p ond ing a r e a in th e syst em spa c e or t o ge ner at e a bre a kpoin t i n st r u ct ion t o th e cor e . debug support (dbg) RM0033 1288/1317 doc id 15403 rev 3 32.13 d w t (data watc hpoint trig g e r) th e d w t un it con s ist s of f our co mpa r at or s . t h e y ar e con f ig ur a b le a s : a ha rd w a r e w a t c hp oint or a t r igge r t o an etm o r a pc sa mp le r o r a d a t a ad dr es s s a m p ler th e d w t also p r o v ides some me an s t o giv e some p r o f il ing inf o r m at io ns . f o r t h is , some cou n t e r s ar e accessib l e t o g i v e th e n u mb er o f : cloc k cycle f o l ded i n st r u ct i o n s l o a d sto r e un it ( l s u ) op er a t io ns slee p cycles cpi (cloc k per instr u ctions) in te rr u p t o v er he ad 32.14 itm (instrumenta tion trace macr ocel l) 32.14.1 general description th e i t m is a n app licat ion- dr iv e n tr ace so ur ce t h at sup p o r t s pr in tf sty l e d e b u g g i ng t o tr ac e o per at ing syst e m ( o s) a n d a pplica t io n e v en ts , an d emit s diag no st ic syst e m in f o r m at ion. th e i t m emit s t r a c e inf o r m at ion a s pa c k e t s which can b e gen er a t ed as: so ft w a re tra c e . sof t w ar e can wr it e dir e ctly to t h e it m st im ulu s re gist er s t o emit p a cke t s . har d ware trace . th e d w t ge ner at es t h ese pac k e t s , a nd t h e i t m em its th em. time st amping. time sta m ps ar e emit t e d r e la tiv e to p a c k e ts . th e i t m cont ain s a 2 1 - b it coun te r t o ge ner at e th e ti mest amp . the co r t e x - m 3 cloc k or t h e b i t cloc k r a t e of th e ser i al wire vie w er ( s wv) out pu t cloc ks t h e co unt er . th e pa c k e t s e m it te d b y th e i t m ar e ou tp ut t o t h e tpi u ( t r a ce p o r t i n t e rf ace unit ). the f o r m at t e r o f t he tpi u ad ds so me e x t r a pa c k e t s ( r e f e r to t p iu) an d t hen o u t p u t t he comp let e p a c k e t s se que nce t o th e de b u gge r ho st. th e bit trcen of t h e de b u g exce pt ion an d mo nit o r con t r o l regi st er m u st be e nab le d b e f o r e y ou p r og r a m or use th e i t m. 32.14.2 time stamp pac kets, sync hr onization and o v erflo w pac kets t i me s ta m p pa c k e t s en co de tim e sta m p in f o r m at ion , ge n e r i c co n tro l an d sy nc hr on iza tio n. it u s e s a 2 1 -b it t i me st am p co un te r (wit h po ssib le pr escaler s ) which is r e set a t e a ch tim e sta m p pa c k e t e m is sio n . t h is co un te r ca n be e i th er clo c k e d b y t h e cp u clo c k or th e swv cloc k. a synchron iza t io n pa c k e t co n s ist s o f 6 b y t e s equ al t o 0x80_ 00 _00 _00 _0 0_0 0 which is e m it te d to t h e tpiu as 00 00 00 00 0 0 80 ( l sb emit t ed f i rst ) . a sy nc hr on iza t io n pa c k e t is a tim e s t a m p p a c k e t co ntr o l. it is em itt e d a t e a c h d w t tr ig ge r . RM0033 debug support (dbg) doc id 15403 rev 3 1289/1317 f o r th is , t h e d w t m u st be c o n f ig ur ed t o tr igg e r t h e i t m : th e bit cyc cntena (b it0 ) o f th e d w t co nt ro l re gis t e r must b e se t. i n ad d i tion , th e bit2 ( sync e na) of th e itm t r ac e control regis t er must be set. no te : if th e syn ena bit is n o t se t, th e d w t ge ne r a t e s sy nc hr on iza t io n tr ig ge rs t o th e t p iu wh ich will s e nd only tpiu s ynchronization pac k e ts and not itm synchronization pac k e ts . an o v er f l o w pa c k e t co nsist s is a specia l t i me st am p pac k e t s which ind i ca te s t h a t da t a has b een wr it t en b u t th e fi fo w a s f u ll. t a b l e 21 0. m a i n itm r e gi st er s a d dre s s r egister d etails @e0000fb0 i tm loc k access w r ite 0xc5a cce55 to unl oc k w r ite acce ss to th e other itm re gisters @e0 000 e80 i tm trace control bi ts 31-24 = al w a ys 0 bits 23 = busy bi ts 22-16 = 7-bits a t b id whi c h iden tifie s the source of th e tr a ce data. bi ts 15-10 = al w a ys 0 bi ts 9:8 = tsprescal e = time stamp pre scaler bi ts 7-5 = rese r v ed bi t 4 = sw oena = en ab l e sw v b eha vi or (to cloc k th e timestamp coun te r b y the swv cloc k). bi t 3 = d w tena: ena b le the d w t sti m ulu s bi t 2 = syncena: this bi t m u st be to 1 to ena b l e the d w t to g ene r a te synchron i zation tr igg e rs so that th e tpiu ca n the n e m i t the synchron i zation pa c k e ts . bit 1 = tsena (tim estam p enab le) bi t 0 = itmena: globa l enab l e bit of th e itm @e0 000 e40 i tm trace pr ivil ege bi t 3: mask to e nab le tracin g por ts31:24 bi t 2: mask to e nab le tracin g por ts23:16 bi t 1: mask to e nab le tracin g por ts15:8 bi t 0: mask to e nab le tracin g por ts7:0 @e0 000 e00 i tm trace enab le ea ch b i t e nab l e s the co rre s p ond ing stim ul us por t to gen er a t e tr ace . @e000 000 0- e0 0000 7c sti m ul us p o r t regi sters 0-31 w r ite th e 32-bi ts data on the sele cte d stimulus p o r t (32 a v ail a b l e ) to be tr ace d o u t. debug support (dbg) RM0033 1290/1317 doc id 15403 rev 3 example of c onfiguration t o o u t p u t a sim p le v a lu e to th e tpiu: conf igu r e t h e tpi u and assign tra c e i/ o s b y con f ig ur in g t h e dbgmcu_cr (r ef er t o se ctio n 3 2. 17 .2 : t r a c e p i n as sign m e n t a nd sect ion 3 2. 16. 3 : deb ug mcu co n f ig ur a t io n r e gist er ) wr it e 0xc 5 a c ce5 5 to th e itm l o c k acce ss re gis t e r t o un lo c k th e wr ite a c c e s s to t h e itm regist ers wr ite 0 x 000 100 05 t o t he i t m t r a c e co nt ro l reg i ste r t o ena b l e th e it m wit h sync en ab led a nd an a t b i d d i ff er en t f r o m 0x00 wr ite 0 x 1 to t h e itm t r ace ena b le reg i ste r t o ena b l e th e stim u l us p o r t 0 wr ite 0 x1 to t h e itm t r ace pr ivilege re giste r t o unm ask st im ulus por t s 7 : 0 wr ite t h e v a lue t o ou t put in th e stim u l us p o r t re giste r 0: th is can b e do ne b y sof t w ar e (u sing a pr in t f f unct i on ) 32.15 etm (embed ded trace macr ocell) 32.15.1 general description th e etm en ab les th e re co nst r uctio n of pro g r a m e x e cut ion. dat a ar e tr aced usin g th e da t a w a t c h p o i nt a nd t r ace (d wt ) comp one nt o r t h e i n st r u ctio n t r a c e macro c e ll (i tm) wh ere a s in st r u ct ion s ar e t r aced u sing t he emb edd ed t r ace macr ocell (etm ). th e etm tr a n smit s inf o r m at ion as pac k e t s a nd is t r igg e r ed b y emb e d ded re so ur ce s . the s e r e sou r ces m u st be p r o g r a m m ed in dep en den tly an d th e t r igge r sour ce is sele ct ed u sing t he t r ig ge r ev ent re gist er ( 0 xe00 410 08) . an e v ent co uld b e a simple e v e n t (a ddr ess m a t c h f r o m an a ddr ess com par at or ) or a logic equ at ion b e t w e en 2 e v e n t s . t he t r igg e r sou r ce is o ne of t he f our t h comp ar a t o r s of t h e d w t mod u le , t he f o llo wing e v e n t s can b e mon i t o re d: cloc k cycle matching dat a ad dre ss ma tchin g f o r mo re in f o r m a t io ns on t he t r igg e r r e sou r ces re f e r t o se ct ion 3 2. 13 : d w t (d at a w a tc hp o i nt tr ig ge r) . th e pa c k e t s t r an smit te d b y th e etm ar e ou tp ut to t h e t p iu (t r a ce p o r t in te rf ace unit ). the f o r m a tte r of th e tpiu ad ds so m e e x tr a pa c k e t s ( r e f e r to sect ion 3 2. 17 : tpi u ( t r a ce por t in te rf ace un it ) ) a nd t h e n out pu t s t he comp let e pa c k e t se que nce t o th e de b u gge r ho st. 32.15.2 signal pr ot ocol, pac ket types th is p a r t is descr ibe d in t he chap t e r 7 et m v 3 sig nal pro t ocol of t h e arm i h i 00 14n document. RM0033 debug support (dbg) doc id 15403 rev 3 1291/1317 32.15.3 main etm register s f o r mo re in f o r m a t io n on r e g i st er s r e f e r to t h e ch apt er 3 of t h e arm i h i 00 14n specif ica t ion. 32.15.4 configuration e xample t o o u t p u t a sim p le v a lu e to th e tpiu: conf igu r e th e t p i u an d en ab le t h e i / i o _ t ra cen t o assign tra c e i / o s in t h e xl- and hig h - den sit y de vice? s de b u g co nf igu r at ion r e g i st e r . wr ite 0 x c5 a cce55 t o t he etm lo c k acce ss re gist er t o un loc k t h e wr it e access t o th e itm regist ers wr it e 0x0 0 0 0 1 d 1e to th e co nt ro l r e g i ste r (c on fig u r e th e tr ac e) wr it e 00 00 4 0 6 f to t h e t r igg e r e v en t re gis ter ( d e fin e th e tr ig ge r e v e n t) wr ite 0 0 0 000 6f t o th e t r a c e en ab le ev ent re gist er ( def in e an e v e n t t o st ar t / st op) wr ite 0 0 0 000 01 t o t he t r a ce sta r t / sto p re giste r ( ena b l e t h e tr ace) wr ite 0 0 0 019 1e to t h e et m co nt ro l re giste r (e nd o f con f ig ur a t io n) 32.16 mcu deb u g component (dbgmcu) th e mcu d e b u g com pon ent he lps t h e deb ug ge r pr o v id e su pp or t f o r : l o w- po we r m o de s cloc k co nt ro l f o r time rs , w a tchd og, i 2 c a n d b x can d u r i n g a br eakpo int cont r o l of t h e tr a ce pins assignm ent 32.16.1 deb u g suppor t f o r lo w-po wer modes t o ent er lo w- po w e r mo de , t h e in st r u ct ion wfi or wfe m u st b e e x ecut ed . th e mcu im plem ent s se v e r a l lo w-p o w e r m ode s which can e i th er d eact i v a t e t he cpu cloc k or r e d u c e th e po we r o f the c p u . t a b l e 21 1. m a i n et m regi st er s ad dr ess regis t er de tails 0xe004 1fb0 etm l o c k access w r ite 0xc5a cce55 to unl oc k the wr ite a cce ss to th e other etm registers . 0xe00 410 00 etm co ntrol this regi ste r con t rol s the general ope r a tion o f the etm, f o r i n sta n ce ho w tr acin g is e nab led. 0xe00 410 10 etm status this regi ster pro vide s in f o r m a t i on abou t the cu rrent status o f the trace an d tr i gger log i c. 0xe00 410 08 etm t r igg e r ev ent this regi ste r de fi nes th e e v e n t tha t will co ntro l tr i gger . 0xe004 101c etm t r ace ena b le control t his regi st e r de fi nes which compa r ator is selected. 0xe00 410 20 etm t r ace en ab le ev e n t t his regi ste r de fi nes th e trace ena b lin g e v e n t. 0xe00 410 24 etm t r ace star t/stop this regi ste r de fi nes th e traces used b y th e tr i gge r sou r ce to star t an d stop the tr ace , respectiv e ly . debug support (dbg) RM0033 1292/1317 doc id 15403 rev 3 th e cor e doe s n o t a llo w fclk or hclk t o be t u r ned o f f du r i ng a d e b ug session. as t h e s e ar e re qu ir ed f o r th e de b u gg e r c o n n e c t ion , du r i ng a d e b ug , th e y m u s t r e m a in act i v e . th e mcu integ r ates spec ial means t o allo w th e user to d e b u g sof t w ar e in lo w-p o w e r m ode s . f o r t h is , th e de b u gge r ho st m u st f i r s t se t some deb ug co nf igur at ion r egist er s t o chan ge t h e lo w-po w e r mode beha v ior : in sleep mode , d bg_sleep bit of dbgmcu_cr register m u st be pre v iously set b y the deb ugger . this will f e ed hclk w i th the same c l oc k th at is pro v ided to fclk (syst em c l oc k pre v iously configured b y the softw are). in stop mode , the bit db g_st op m u st be pre v ious ly s e t b y the deb u gger . this w ill enab le the inter n al rc osc illator cloc k to f e ed fclk and h c lk in st op mode . 32.16.2 deb u g suppor t f o r time r s , watc hdog, bxcan and i 2 c dur i n g a br ea kp oint , it is n e cessar y t o ch oo se h o w t he cou n t e r o f t i mer s a nd w a tch dog sh ou ld be h a v e : the y can con t in u e t o coun t inside a br ea kp oi nt. this is usually required when a pwm is controlling a motor , f o r e xample . t h e y c a n s t op t o co un t in sid e a br ea kp o i nt . t h is is re qu ire d f o r w a tc hd o g pu r p os es . f o r t h e b x can, t he u s e r can choo se to b l o c k t he up da te o f t h e r e ceiv e r e g i st er dur in g a br ea kp o i nt . fo r t h e i 2 c , t he use r ca n choo se to b l oc k t he smb u s t i meo u t d u r i n g a br eakp o int . 32.16.3 deb u g mcu con figuration register th is r e g i st er allo ws t he con f ig ur a t io n of th e mcu un de r deb u g. this co ncer n s: lo w-p o w e r mod e su pp or t time r an d w a t chd og coun t e r sup por t b xcan co m m un ica t io n su pp or t t r ac e pin a ssig n m e nt this dbgmc u _cr i s mapped on the exte r n al ppb b u s at address 0xe0042004 it is asynchronously reset b y the poreset (and not the system reset). it can be w r itten b y t h e d e b u g ger und er syst e m r e set . if the deb u gger host does not s u ppor t thes e f e at ures , it is still possib l e f o r the user s o ftw a re to wr it e t o th es e r e gist er s . d b g m c u_ cr ad dre ss: 0xe004 2 0 0 4 o n ly 3 2 - b it acce ss supp or t e d po r reset : 0 x 0 000 000 0 (n ot r e set b y syst em r e set ) 31 30 29 28 27 26 25 24 23 22 2 1 2 0 19 18 1 7 16 reser v e d RM0033 debug support (dbg) d o c id 154 03 re v 3 1 293 /13 1 7 32.16.4 deb u g mcu apb1 freez e register (dbgmcu_apb1_fz) th e dbgmcu_apb1_f z reg i ste r is u s e d t o co nf igu r e t h e mcu und er deb u g. i t co ncer n s apb1 per i pher als . it is mapped on t he e x ter nal ppb b u s at address 0xe004 2008. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reser v e d tra c e_ mode [1: 0 ] tr a c e_ io e n re s e r v ed dbg_ st a n d by dbg_ st op dbg_ sl eep rw rw rw r w rw rw bi ts 31:8 r e ser v ed, must be k e pt cle a red. bits 7:5 tra c e_mode[1: 0 ] and tra c e_ioe n : t r ace pi n a ssignmen t control ? w ith tra c e_ioen=0: tra ce_mode= xx: tr a ce pin s no t assig ned (de f aul t sta t e ) ? w ith tra c e_ioen=1: ? t ra ce_mode= 00: tra c e p i n assig n ment f o r asynch ro nou s mod e ? t ra ce_mode= 01: tra c e p i n assig n ment f o r syn c h r onous mod e with a tra c ed a t a siz e of 1 ? t ra ce_mode= 10: tra c e p i n assig n ment f o r syn c h r onous mod e with a tra c ed a t a siz e of 2 ? t ra ce_mode= 11: tra c e p i n assig n ment f o r syn c h r onous mod e with a tra c ed a t a siz e of 4 bits 4:3 re ser v ed, must be k e pt cle a red. bi t 2 dbg_st andby : de b u g stand b y mo de 0 : (fc l k=off , hcl k= off) the who l e dig i tal par t is u npo w e red . f rom soft w a r e point of vie w , e xiting from s t an db y is iden ti ca l th an f e tchin g re set v e ctor (e xcep t a f e w statu s b i t in dicated that th e mc u i s resu mi ng fro m standb y) 1 : (fc l k=on, h c lk=on) in thi s case , the d i gital p a r t is not unp o w ere d and fclk and h c lk are pro vide d b y the i n te r n al rc oscill at or w h ich remain s a c tiv e . in a ddi tio n , the mcu g ene r a te a syste m reset du r i ng sta ndb y mode so that e xiting fro m sta ndb y is id entical than f e tc hing from reset bi t 1 dbg_st o p: de b u g stop mode 0 : (fc l k=off , hcl k= off) in st op mod e , the cloc k controll er d i sab l es all cloc ks (inclu ding h clk a nd fclk). wh en e xi t in g from st op mod e , the cloc k co nfiguration is i dentical to the o ne after r e set (cpu clo c k e d b y the 8 mhz inter nal rc o s ci llator (hsi)). conseq uen tly , the so ftw a re m u st re prog r a m the cloc k cont roll er to en ab le the pll , the xta l , e t c. 1 : (fc l k=on, h c lk=on) in thi s case , w hen en te r i ng st op mode , fclk an d hclk are p r o vided b y the in te r n a l rc oscilla to r wh ich remains activ e in st op mode . whe n e xitin g st op mode , th e so ftw a re m u st reprog ram the cl o c k con t rol l er to e nab l e th e pl l, the xtal, e t c. (i n th e sa me w a y it w ould do in case of dbg_ st op= 0 ) bi t 0 dbg_sleep: deb u g sleep mod e 0: (fclk = on, hclk=off) in sleep mode , fclk is cloc k e d b y the system cloc k as pre viously co nfigure d b y the softw are whil e hclk is disab l ed. in sle ep mode , the clo c k con t rol l er configu r ation is n o t reset and remains in th e pre viousl y p r og r a mmed state . con seque ntly , wh en e xiti ng fro m sle ep mode , the so ftw a re doe s no t n eed to recon f ig ure th e cloc k co ntrolle r . 1 : (fclk= on , h c lk=on) in thi s case , when enter i ng sle ep mo de , hclk i s f ed b y the same cl oc k tha t is pro vide d to fclk (system cl oc k a s p r e vio usly configu r ed b y the so ftw a re). debug support (dbg) RM0033 1294/1317 doc id 15403 rev 3 th e re gist er is asynchro no usly r e set b y th e por ( a n d no t t he syst em r e set ) . it can be wr it te n b y t he de b ugg er u nde r syst em r e set . ad dre s s : 0 x e0 04 20 08 only 32-bits ac ce ss are suppor t ed. p o w e r o n re se t ( p or): 0x000 0 0 0 00 ( not re se t b y syst e m r e set ) 31 30 2 9 2 8 27 26 25 24 23 2 2 21 20 19 18 17 1 6 reser v ed dbg_can2_s t o p dbg_can1_s t o p reser v ed db g_i2c3_s mb us_ t imeout db g_i2c2_s mb us_ t imeout db g_i2c1_s mb us_ t imeout reser v e d r w rw rw rw rw 1 5 1 4 1 3 1 2 1 1 1 0 987 654321 0 reser v e d dbg_iwdg_st o p dbg_ wwdg_st op db g_r t c_ st op reser v ed db g_ti m14_s t o p db g_ti m13_s t o p db g_ti m12_s t o p dbg_tim7 _st o p dbg_tim6 _st o p dbg_tim5 _st o p dbg_tim4 _st o p dbg_tim3 _st o p dbg_tim2 _st o p r w r w rw rw rw rw r w rw rw rw rw bits 31 :2 6 r ese r v e d bit 25 db g_c an2_st o p: deb ug can2 stoppe d when co re is h a lted 0: same beha vior as i n nor mal mode 1 : t h e c a n2 rece i v e re gi st ers a r e fro z e n bit 24 db g_c an1_st o p: deb ug can1 stoppe d when co re is h a lted 0: same beha vior as i n nor mal mode 1 : t h e c a n1 rece i v e re gi st ers a r e fro z e n bit 23 dbg _ i2c3_smb us _t imeo ut : smbus timeou t mode stopp ed whe n core is halted 0: same beha vior as i n nor mal mode 1 : t h e smb u s ti me o u t i s f r oz en bit 22 dbg _ i2c2_smb us _t imeo ut : smbus timeou t mode stopp ed whe n core is halted 0: same beha vior as i n nor mal mode 1 : t h e smb u s time o u t is f r oz en bit 21 dbg _ i2c1_smb us _t imeo ut : smbus timeou t mode stopp ed whe n core is halted 0: same beha vior as i n nor mal mode 1 : t h e smb u s time o u t is f r oz en bi t 20 :13 r ese r v e d bit 12 db g_iwd g _st o p: deb ug ind epe nden t w a tchdo g stop ped wh en core is halted 0: the i ndep end ent w a tchd og coun te r clo c k con t in u e s e v e n if the core is hal ted 1: the indep end ent w a tchd og coun te r clo c k is sto ppe d when the core is hal te d RM0033 debug support (dbg) doc id 15403 rev 3 1295/1317 32.16.5 deb u g mcu apb2 freez e register (dbgmcu_apb2_fz) th e dbgmcu_apb2_f z reg i ste r is u s e d t o co nf igu r e t h e mcu und er deb u g. i t co ncer n s apb2 per i pher als . this register is mappe d on the e x ter n al ppb b u s at address 0xe004 200c it is a sy n ch ro n o u sly re se t b y t h e po r ( a nd n o t th e sys te m re se t) . it ca n b e w r itte n b y th e de b u g g e r un de r sys te m re se t. ad dre s s: 0xe004 2 0 0 c only 32-bit acc e s s is suppor ted. po r: 0x000 0 0 0 00 ( not re se t b y syst e m r e set ) bit 11 db g_wwdg_st o p: deb u g win d o w w a tchdo g sto pped wh en core is ha lted 0: the wi ndo w w a tchdo g counter cloc k c ontin ue s e v en if th e core is h a lted 1: the wi ndo w w a tchdo g counter cloc k is stop ped wh en th e core is halted bit 10 db g_r t c_ st op: r t c sto ppe d when co re i s h a lted 0: the r t c co unter cl oc k co ntin ues e v en if the core is ha lted 1: the r t c co unter cl oc k i s stopp ed when the co re is ha lted bit 9 r eser v e d bits 8:0 db g_timx _st o p: timx coun te r stoppe d when co re is ha lted (x=2..7, 1 2 ..14 ) 0: the clo c k o f th e in v o lv ed timer coun te r is f e d e v e n i f the core is halted 1: the clo c k o f th e in v o lv ed timer counter is stop ped wh en the core is halted 31 3 0 29 28 2 7 26 25 2 4 23 22 21 20 19 18 17 16 reser v ed dbg_tim11 _st o p dbg_tim1 0 _s t o p db g_ t i m 9 _ st o p rw r w rw 15 1 4 13 12 1 1 10 9 8 7 6 5 4 3 2 1 0 re s e r v ed dbg_tim8 _ st op db g_ t i m 1 _ st o p rw r w bits 31 :1 9 r ese r v e d bits 18 :1 6 db g_timx _st o p: timx coun te r stoppe d when co re i s ha lted (x=9..11) 0: the clo c k o f th e in v o lv ed timer coun te r is f e d e v e n i f the core is halted 1: the clo c k o f th e in v o lv ed timer counter is stop ped wh en the core is halted bits 15:2 reser v ed bit 1 db g_tim8 _st o p : tim8 coun te r stopp ed whe n co re is h a lted 0: the clo c k o f th e in v o lv ed timer coun te r is f e d e v e n i f the core is halted 1: the clo c k o f th e in v o lv ed timer counter is stop ped wh en the core is halted bit 0 db g_tim1 _st o p: tim1 cou n ter stop ped wh en core is halted 0: the clo c k o f th e in v o lv ed timer coun te r is f e d e v e n i f the core is halted 1: the clo c k o f th e in v o lv ed timer counter is stopped when the core is halted debug support (dbg) RM0033 1296/1317 doc id 15403 rev 3 32.17 tpiu (trace por t interface unit) 32.17.1 intr oduction th e tpi u a c t s a s a b r idge b e t w e en t h e o n - c h i p tr ace da ta f r o m th e i t m an d th e etm . th e ou tp ut d a t a str e a m encap sulat e s t he t r ace sour ce id , t h a t is t h en capt u r ed b y a tr ace po r t an a l yz er (t p a ) . th e cor e emb eds a simple tpi u , espe cia lly d e signe d f o r lo w-cost deb ug ( c onsist i ng of a sp ec ial v e r s io n of th e co re sigh t tpi u ). figu re 41 9. t p iu b l oc k dia g ra m 32.17.2 tra ce pin assignment asyn ch ro nou s mo de the asynchr ono us mod e r equ ire s 1 e x tr a pin and is a v aila b l e on a ll pa c k a ges . i t is o n ly a v aila b l e if usin g se r i al wire m o de ( n o t in j t a g m o de ) . sy nch r on ou s mo d e the synchr on ous mo de re qu ire s f r o m 2 to 6 e x t r a p i ns dep en ding o n t he da ta t r a c e siz e and is on ly a v a ilab l e in t h e la rge r pac ka ges . in ad dit i on it is a v ailab l e in jt a g mo de and in ser i al wire mode and pro v ides be tter bandwidth output capabilities than asynchr ono us tr a c e . fo r m a tt er tr a ce o u t ( s er i a liz e r ) tra c eclkin tra ceck tra c ed a t a [ 3 :0 ] trace s wo clk dom a in tra c e clkin dom a in ext e r n a l ppb bu s tpiu tpiu a s y nchrono us fifo a s ynchrono us fifo etm itm a i17114 t a b l e 21 2. asy n c h r onou s tra c e p i n a ssignme n t tpui pi n n a me t r ac e sync h r o nous mode stm32 f 20 x and stm32f21x pin assignme nt t y pe desc ription tra c esw o o tra c e async data output pb 3 RM0033 debug support (dbg) d o c id 154 03 re v 3 1 297 /13 1 7 tpui tra c e pin a ssignment by def au lt, t hese pin s a r e no t assigne d. the y can be assign ed b y set t i ng t he tra c e_ioen and tr a c e_mod e b i ts in t h e mcu deb ug co m p one nt co nfigur at ion re gi st er . th is conf ig ur at io n has to be do ne b y t h e d e b u g ger host . i n ad dit i on , t he n u m ber o f pin s t o assign de pe nds on t he t r ace conf ig ur at io n (asynchr o n ous or sy nc hr on o u s ) . asyn c hr o nous mod e : 1 e xt r a p i n is ne ed e d sync h r on ous mode : f r o m 2 t o 5 e xtr a pins ar e ne ede d de pen din g on t he siz e o f t he d a t a tr ac e po r t re gis t er ( 1 , 2 or 4 ) : ? t r a ceck ? t r a ced( 0) if po r t siz e is c o n f ig ur ed t o 1, 2 or 4 ? t r a ced( 1) if po r t siz e is c o n f ig ur ed t o 2 or 4 ? t r a ced(2) if por t siz e is c o nfigured to 4 ? t r a ced(3) if por t siz e is c o nfigured to 4 t o assig n th e tra c e pin , t h e d e b u g ger hos t m u st pr og r a m th e bit s tra c e_i o en and tra c e_mo de[ 1 : 0 ] of th e de b ug mcu con f igur at ion reg i st er (dbgmcu_cr). by de f a ult t h e t r a c e pins ar e not assigne d. this register is mappe d on the e x ter n al ppb and is reset b y the pores e t (and not b y the system reset). it can be wr itten b y the deb ugger u nder system reset. t a b l e 21 3. sy nc hr onous tra c e pin as signme n t tpui p i n na me t r a ce sync h r o nous m o de stm32 f 20 x and stm32f21x pin assignme nt t y pe desc ription tra c eck o tra c e c l oc k p e2 t r a c ed[3:0] o t r a c e sync data out p uts can be 1, 2 or 4 . pe [6:3] table 214. fle xi b l e tra c e p i n a ssi gnme n t dbgmcu_cr re gister pins as signed f o r : t r a c e i o pi n assi gn ed tra c e_ io en tra c e_ mode[1:0] pb3 / jtdo/ tra c e s w o pe2 / tr a c eck pe3 / tra c ed[ 0 ] pe 4 / tra c ed[ 1 ] pe5 / tra c ed[ 2 ] pe6 / tra c ed[ 3 ] 0x x no t r ace (d ef a u l t st at e) released (1) 10 0 asynchro nous tr a c e trac e s w o re lease d (us a b l e as gp io) 101 synchronous trace 1 bit released (1) tr a c eck t ra ced[0 ] 11 0 synchronous trace 2 bit trac eck t ra ced[0 ] tra c ed[1 ] 111 synchronous trace 4 bit trac eck t ra ced[0 ] tra c ed[1 ] t ra ced[2 ] tra ced[3] debug support (dbg) RM0033 1298/1317 doc id 15403 rev 3 no te : b y d e f a u lt, th e tra c ec lki n in pu t clo c k o f t h e tpiu is t i ed to g n d . i t is as sign e d to hcl k two clo c k cy cle s a fte r th e bit tra c e_ io en ha s b e e n s e t. th e d e b u g ger m u st t h e n pr og r a m t h e t r ace mo de b y wr it ing t he pr o t o c ol[ 1 : 0 ] b i ts in t he spp_r (selected pin protocol ) register of the tpiu . pr o t ocol =0 0: t r ace p o r t mo de ( s ynchr o n ous) pr o t ocol =0 1 or 1 0 : se r i al wire ( m a n chest e r o r nrz ) mod e (a syn c h r o nou s mo de ). def ault sta t e is 01 it th en a l so co n f igu r es th e tr a c e p o r t s i z e b y w r iting t h e b i ts [3 :0 ] in th e cps ps_r (c ur re nt syn c p o r t siz e reg i st er ) o f th e tpi u : 0x1 f o r 1 p i n (d ef au lt sta t e ) 0x2 f o r 2 p i ns 0x8 f o r 4 p i ns 32.17.3 tpui f o rmatter th e f o r m at te r pr ot ocol ou t put s d a t a in 16 -b yte f r a m es: se v e n b yt e s of dat a e i gh t b yte s of m i x e d- us e b yte s co nsis tin g of: ? 1 b i t (l sb) to in dica te it is a d a t a b yte ( ? 0) o r a n id b yt e (?1 ) . ? 7 bit s ( m sb) which ca n be d a t a or ch ang e of so ur ce i d t r a c e . one b yte of auxiliar y bits where each bit corresponds to one of the eight mix ed-use by t e s: ? i f t he cor r e s p ond ing b yte w a s a dat a, th is b i t giv e s bi t0 o f t he d a t a . ? i f th e cor r e spon din g b yte w a s an i d ch ang e , th is bit in dicat e s whe n th at i d ch an ge t a k e s eff e c t . not e : r ef er to t h e arm cor e sigh t ar ch ite c t u re spe c i f icat ion v1 .0 ( a rm i h i 0 029 b) f o r f u r t her inf o r m ation 32.17.4 tpui frame sync hr onization pac kets th e tpui can g ene r a t e t w o t ypes of synch r on izat ion pa c k e t s: t h e f r am e syn ch r o n iz at ion p a c k e t (o r f u ll w o r d s ync hr on iza tio n pa c k e t) i t consist s of th e w o rd : 0x7f _ff_ ff_ ff (l sb e m itt e d fir st) . th is seq uen ce ca n not occur a t an y ot he r tim e pr o v id ed t h a t t he i d sou r ce code 0x7f ha s no t b een u sed. it is output per i odic ally be tw een fr am e s . i n co nt in uo us m ode , th e tp a m u st discar d all th ese f r am es o n ce a syn c h r o n izat ion f r ame h a s bee n f oun d. t h e h a lf -w o r d sy nc hr on iza t io n pa c k e t i t consist s of th e ha lf w o rd : 0x7 f _ff ( l sb emit t ed f i rst ) . it is output per i odic ally bet w e e n or wi thin fr a m es . the se pac k e t s ar e on ly g ene r a t e d in co nt in uou s mo de a nd en ab le t h e tp a t o det ect t hat th e tra c e po r t is in idle mo de (n o tra c e t o be cap t u r e d ) . whe n det ect e d b y t he tp a, it m u st b e disca r d ed. 1. when serial wire mode is used, it is rele ased. b u t when jtag is used, it is assigned to jt do. RM0033 debug support (dbg) doc id 15403 rev 3 1299/1317 32.17.5 t r ansmission of the sync hr onization frame pac ket t h e r e is no sy nc hr on iza t io n co un te r re gis t er im p l em e n te d in th e t p iu of th e co re . con s e q u ent ly , th e syn c h r o n izat ion t r ig ger ca n only be g ene r a t e d b y th e dw t . ref e r to t h e r e g i st er s d w t con t r o l reg i st er (b its synct ap[ 11: 10 ]) and t h e d w t cu rr en t pc sa mple r cycle co unt re gist er . th e tpui f r am e syn c h r o n izat ion p a c k e t (0 x7 f_f f _ff _ ff) is em itt e d : a fte r ea ch tpiu re se t re lea se . this re se t is sy nc hr on o u sly r e le as ed wit h th e r i sing e d g e o f th e tra c e c lk in c l oc k . th is m e an s t h a t this p a c k e t is tr a n s m it te d wh en th e tra c e_i o en bit in th e dbg m cu_ cfg re gis t e r is se t. in th is ca se , the wo rd 0x7f _ff_ ff_ ff is n o t f o llo w ed b y a n y f o r m at te d pa c k e t . at each d w t t r igg e r ( a ssumin g d w t ha s be en p r e vio usly con f ig ur ed) . t w o cases occur : ? i f t h e b i t s y nena of th e itm is re se t, on ly t h e wor d 0x 7f_ f f_ ff_ff is em itt e d w i th ou t a n y f o r m a tte d st re am w h ic h f o llo w s . ? i f the bit s ynena of the itm is set, then the itm sy nchronization pac k e ts will f o llo w (0 x80_ 00_ 00 _00 _0 0_0 0) , f o r m at te d b y t he tpui ( t r a ce sour ce id ad ded ). 32.17.6 synchr onous mode t h e tr a ce d a t a ou tp ut siz e ca n be c o n f ig ur ed t o 4, 2 or 1 p i n: t r a c e d (3 :0 ) th e ou tp ut clo c k is o u t p u t t o t he de b u gg er ( t ra ceck) here , tra c ec lkin is dr iv en inter nally and is connected to hc lk only w h en tra c e is us ed . not e : i n t h is synchr o n ous mod e , it i s no t r equ ire d to p r o vide a st ab le cloc k fr eq uen cy . th e tra c e i / o s ( i nclud i ng tra c eck) ar e dr iv en b y t he r i sing edg e of tra c lki n (e qua l t o hclk). conseq ue nt ly , t h e out pu t f r e q u ency o f tra c eck is e qua l to hclk/ 2. 32.17.7 async h r onous mode this is a lo w cost alter n ativ e to output the tr ace usin g only 1 pin : t h is i s t he asynchr o n ous o u t put pin t r a c esw o . o b viou sly t her e is a lim ite d ba ndwid th . tra c esw o is m u ltiple x ed with j t d o when using t h e sw -dp pin . th is w a y , t h is f u n c t i on alit y is a v a ilab l e in all stm 32f 20x and st m32 f 21 x pa c k a g e s . th is asynchr o n ous mod e r e q u ir es a const a n t fr eq ue ncy f o r tra c eclki n . f o r t h e st an dar d u a r t ( n rz) ca pt ur e mecha n ism, 5% accu r a cy is ne ede d. t he ma nche st er encod ed v e rsion is toler a nt up to 10%. 32.17.8 tra ceclkin connection i nside the stm32f2 0x and stm32f21x i n t he stm3 2f2 0 x and st m32 f21 x, th is tra c ecl k in inpu t is int e r n ally co nn ecte d to hclk. t h is m ean s t h a t when in asyn chro no us t r a c e m ode , th e ap plicat ion is re st r i cte d t o u s e t o t i me f r am es wh ere th e cpu fr eq uen cy is st ab le . note: impor t a nt : whe n using a s ynchr o n ous t r ace: it is im por t a n t t o be a w a r e t h a t : the def a ult cloc k of the stm32f 20x and stm32f21x mc us is the inter n al rc osc illator . its fr eq ue n cy un de r re se t is d i ff e r e n t fr o m th e on e af te r r e s e t re le as e . t h is is be ca u se th e rc debug support (dbg) RM0033 1300/1317 doc id 15403 rev 3 calib r a t i on is t he de f a ult one u n d e r syst e m r e set and is up dat e d at e a ch syst em r e set re lea s e . consequently, the trace port analyzer (tpa) should not enable the trace (with the trace_ioen bit) under system reset, bec ause a synchronizatio n frame packet will be issued with a different bit ti me than trace packets which will be transmitted after reset release. RM0033 debug support (dbg) doc id 15403 rev 3 1301/1317 32.17.9 tpiu register s the tpiu apb registers can be read and wr itte n only if the bit tr cena of the deb u g except ion a n d m onit o r co nt ro l re giste r (demcr) is set . ot her wise , th e re giste r s ar e re ad as z e r o (t he o u t p u t of th is b i t en ab les th e pcl k o f t h e tpiu ). t a b l e 21 5. impor t a nt tpiu reg i s t e r s ad dr ess register de scription 0xe004 000 4 c u r re nt p o r t siz e allo ws the tr ace po r t siz e to b e se lected: bit 0: p o r t siz e = 1 bit 1: p o r t siz e = 2 bit 2 : p o r t siz e = 3, no t suppor ted bit 3: p o r t siz e = 4 only 1 bit must be se t. by de f aul t, the p o r t siz e is one bi t. (0x00 000 001) 0xe004 00f0 sel e cted pin pr ot oco l allo ws the t r ace p o r t protocol to be sele cted : bit1:0= 0 0 : sy nc t r ac e p o r t mo de 01: ser i a l w i re ou tp ut - manche ster (def ault v a lu e) 10: ser i a l w i re ou tp ut - nrz 11: reser v ed 0xe004 030 4 f o r m atter a nd fl u sh co nt rol bit 31-9 = alw a ys ?0 bit 8 = t r igi n = alw a ys ?1 to indi ca te th at tr i g ge rs ar e in d i cat e d bi t 7- 4 = al w a ys 0 bi t 3- 2 = al w a ys 0 bit 1 = enfcon t. in sync t r ace mode (sel ect_ pin_pro toco l register bit1:0= 00), thi s bi t is f o rced to ?1: t h e f o r m at ter is automatical ly e nab led in con t i n u ous mode . in asynch ronou s mode (sele ct_ pi n_protocol re gister b i t1:0 < > 00 ), th is bit ca n be wr i t ten to acti v a te or not the f o r m atter . bi t 0 = al w a y s 0 the resultin g def a u lt v a lue i s 0x1 0 2 note: in synchron ous mode , becau se the tra c ec tl pi n i s n o t mapp ed outsid e the ch ip , the f o r m atte r is al w a ys ena b l ed i n con t in uo us mo de -th i s w a y th e f o r m atter inser t s some c o ntrol pa c k e t s to i den tify th e so urce of the tr ace p a c k e ts). 0xe004 030 0 f o r m atter a nd flush status not used in co r t e x-m3, a l w a ys read a s 0x0 0000 008 debug support (dbg) RM0033 1302/1317 doc id 15403 rev 3 32.17.10 example of configuration set th e bit t r cena in t h e de b u g exce pt ion an d mo nit o r con t r o l regi st er (demcr) wr ite t h e tpiu curr en t p o r t siz e reg i st er to t h e desir ed v a lu e (d ef au lt is 0 x 1 f o r a 1- bit por t siz e ) wr it e tpi u f o r m a tte r an d f l us h con t r o l re gis t er t o 0 x 1 0 2 (d ef au lt v a lu e) wr it e th e t p i u se le ct pin pr ot oc ol to se lec t th e sy nc o r a s y n c m o de . exa m p l e : 0x 2 f o r async nrz mode (u ar t lik e) wr it e the d b gm cu co nt ro l r e g i ste r to 0 x 20 ( b it io _ t r a cen) to a s s i gn tra c e i/o s f o r a syn c mo d e . a tp iu s y nc p a c k e t is e m it te d at th is t i me ( f f_ ff_ff_7 f ) conf igu r e t h e itm a n d wr it e th e i t m stim u l us r e g i st e r to out pu t a v a lu e 32.18 db g reg i ster map th e f o llo wing t a b l e summ ar iz e s t he deb u g r e g i st er s . t a b l e 216 . dbg reg i s t e r ma p and re set v a lu es ad dr . re g ister 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 x e 004 2000 dbgmcu_id c ode re v _ i d reserved dev_i d reset v a lu e (1) xx xx xx x x x x xx xx xx xx xx x x xx xx xx 0 x e 004 2004 d bgmcu_cr reser v ed db g_ti m7_st o p db g_ti m6_st o p db g_ti m5_st o p db g_ti m8_st o p dbg_i2c2_s mbus_ t imeout reserved tra c e_ mo de [1 : 0 ] tr ac e_ io e n reser v ed dbg_standby dbg_stop dbg_sleep rese t v a l u e 0 000 0 0 00 00 0 0 x e 004 2008 dbgmc u_ apb 1_fz reser v e d dbg_can2_sto p dbg_can1_ s t o p reser v ed d b g_i2c3_ s mb us _timeout d b g_i2c2_ s mb us _timeout d b g_i2c1_ s mb us _timeout reser v ed db g_iwdg_s t o p dbg _wwdg_ st o p reserved dbg_tim14_stop dbg_tim13_stop dbg_tim12_stop dbg_tim7_stop dbg_tim6_stop dbg_tim5_stop dbg_tim4_stop dbg_tim3_stop dbg_tim2_stop rese t v a l u e 00 000 0 0 0 00 000 000 0 0 x e 004 20 0c dbgmc u_ apb 2_fz reserv ed dbg_ t i m11 _ st op dbg_ t i m10 _ st op d b g_ti m9_s t o p reser v e d d b g_ti m8_s t o p d b g_ti m1_s t o p r e se t v a l u e 0 00 00 1. th e reset value is prod uct de pendent. f o r more in formation, re fer to section 32.6.1: mc u device id code . RM0033 device electronic signature doc id 15403 rev 3 1303/1317 33 device electronic signature the electronic signature is stored in the system memory area in the flash memory module, and can be read using the jtag/swd or the cpu. it contains factory-programmed identification data that allow the user firmware or other external devices to automatically match its interface to the characteristics of the stm32f20x and stm32f21x microcontroller. 33.1 unique device id register (96 bits) the unique device identifier is ideally suited: for use as serial numbers (for example usb string serial numbers or other end applications) for use as security keys in order to increase the security of code in flash memory while using and combining this un ique id with software cryp tographic primitives and protocols before programming the internal flash memory to activate secure boot processes, etc. the 96-bit unique device identifier provides a reference number which is unique for any device and in any context. these bits can never be altered by the user. the 96-bit unique device identifier can also be read in single bytes/half-words/words in different ways and then be concatenated using a custom algorithm. base address: 0x1fff 7a10 address offset: 0x00 read only = 0xxxxx xxxx where x is factory-programmed address offset: 0x04 read only = 0xxxxx xxxx where x is factory-programmed 313029282726252423222120191817161514131211109876543210 u_id(32:0) rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr bits 31:0 u_id (31:0): 31:0 unique id bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 u_id(63:48) rrrrrrrrrrrrrrrr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 u_id(47:32) rrrrrrrrrrrrrrrr bits 31:0 u_id(63:32): 63:32 unique id bits device electronic signature RM0033 1304/1317 doc id 15403 rev 3 address offset: 0x08 read only = 0xxxxx xxxx where x is factory-programmed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 u_id(95:80) rrrrrrrrrrrrrrrr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 u_id(79:64) rrrrrrrrrrrrrrrr bits 31:0 u_id(95:64): 95:64 unique id bits. index RM0033 1305/1317 doc id 15403 rev 3 index a adc_ccr . . . . . . . . . . . . . . . . . . . . . . . . . . .243 adc_cdr . . . . . . . . . . . . . . . . . . . . . . . . . . .245 adc_cr1 . . . . . . . . . . . . . . . . . . . . . . . . . . .231 adc_cr2 . . . . . . . . . . . . . . . . . . . . . . . . . . .233 adc_csr . . . . . . . . . . . . . . . . . . . . . . . . . . .242 adc_dr . . . . . . . . . . . . . . . . . . . . . . . . . . . .240 adc_htr . . . . . . . . . . . . . . . . . . . . . . . . . . .237 adc_jdrx . . . . . . . . . . . . . . . . . . . . . . . . . . .240 adc_jofrx . . . . . . . . . . . . . . . . . . . . . . . . .237 adc_jsqr . . . . . . . . . . . . . . . . . . . . . . . . . .239 adc_ltr . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 adc_smpr1 . . . . . . . . . . . . . . . . . . . . . . . . .236 adc_smpr2 . . . . . . . . . . . . . . . . . . . . . . . . .236 adc_sqr1 . . . . . . . . . . . . . . . . . . . . . . . . . .238 adc_sqr2 . . . . . . . . . . . . . . . . . . . . . . . . . .238 adc_sqr3 . . . . . . . . . . . . . . . . . . . . . . . . . .239 adc_sr . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 c can_btr . . . . . . . . . . . . . . . . . . . . . . . . . . .788 can_esr . . . . . . . . . . . . . . . . . . . . . . . . . . .787 can_fa1r . . . . . . . . . . . . . . . . . . . . . . . . . .798 can_ffa1r . . . . . . . . . . . . . . . . . . . . . . . . .798 can_firx . . . . . . . . . . . . . . . . . . . . . . . . . . .799 can_fm1r . . . . . . . . . . . . . . . . . . . . . . . . . .797 can_fmr . . . . . . . . . . . . . . . . . . . . . . . . . . .796 can_fs1r . . . . . . . . . . . . . . . . . . . . . . . . . .797 can_ier . . . . . . . . . . . . . . . . . . . . . . . . . . . .786 can_mcr . . . . . . . . . . . . . . . . . . . . . . . . . . .779 can_msr . . . . . . . . . . . . . . . . . . . . . . . . . . .781 can_rdhxr . . . . . . . . . . . . . . . . . . . . . . . . .795 can_rdlxr . . . . . . . . . . . . . . . . . . . . . . . . .795 can_rdtxr . . . . . . . . . . . . . . . . . . . . . . . . .794 can_rf0r . . . . . . . . . . . . . . . . . . . . . . . . . .784 can_rf1r . . . . . . . . . . . . . . . . . . . . . . . . . .785 can_rixr . . . . . . . . . . . . . . . . . . . . . . . . . . .793 can_tdhxr . . . . . . . . . . . . . . . . . . . . . . . . .792 can_tdlxr . . . . . . . . . . . . . . . . . . . . . . . . .792 can_tdtxr . . . . . . . . . . . . . . . . . . . . . . . . .791 can_tixr . . . . . . . . . . . . . . . . . . . . . . . . . . .790 can_tsr . . . . . . . . . . . . . . . . . . . . . . . . . . .782 crc_dr . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 crc_idr . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 cryp_cr . . . . . . . . . . . . . . . . . . . . . . . . . . .506 cryp_din . . . . . . . . . . . . . . . . . . . . . . . . . . .509 cryp_dmacr . . . . . . . . . . . . . . . . . . . . . . .511 cryp_dout . . . . . . . . . . . . . . . . . . . . . . . . 510 cryp_imscr . . . . . . . . . . . . . . . . . . . . . . . . 511 cryp_iv0lr . . . . . . . . . . . . . . . . . . . . . . . . 515 cryp_iv0rr . . . . . . . . . . . . . . . . . . . . . . . . 515 cryp_iv1lr . . . . . . . . . . . . . . . . . . . . . . . . 516 cryp_iv1rr . . . . . . . . . . . . . . . . . . . . . . . . 516 cryp_k0lr . . . . . . . . . . . . . . . . . . . . . . . . . 513 cryp_k0rr . . . . . . . . . . . . . . . . . . . . . . . . . 513 cryp_k1lr . . . . . . . . . . . . . . . . . . . . . . . . . 513 cryp_k1rr . . . . . . . . . . . . . . . . . . . . . . . . . 514 cryp_k2lr . . . . . . . . . . . . . . . . . . . . . . . . . 514 cryp_k2rr . . . . . . . . . . . . . . . . . . . . . . . . . 514 cryp_k3lr . . . . . . . . . . . . . . . . . . . . . . . . . 514 cryp_k3rr . . . . . . . . . . . . . . . . . . . . . . . . . 515 cryp_misr . . . . . . . . . . . . . . . . . . . . . . . . . 512 cryp_risr . . . . . . . . . . . . . . . . . . . . . . . . . 512 cryp_sr . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 d dac_cr . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 dac_dhr12l1 . . . . . . . . . . . . . . . . . . . . . . . 263 dac_dhr12l2 . . . . . . . . . . . . . . . . . . . . . . . 264 dac_dhr12ld . . . . . . . . . . . . . . . . . . . . . . 265 dac_dhr12r1 . . . . . . . . . . . . . . . . . . . . . . 263 dac_dhr12r2 . . . . . . . . . . . . . . . . . . . . . . 264 dac_dhr12rd . . . . . . . . . . . . . . . . . . . . . . 265 dac_dhr8r1 . . . . . . . . . . . . . . . . . . . . . . . 263 dac_dhr8r2 . . . . . . . . . . . . . . . . . . . . . . . 264 dac_dhr8rd . . . . . . . . . . . . . . . . . . . . . . . 266 dac_dor1 . . . . . . . . . . . . . . . . . . . . . . . . . . 266 dac_dor2 . . . . . . . . . . . . . . . . . . . . . . . . . . 266 dac_sr . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 dac_swtrigr . . . . . . . . . . . . . . . . . . . . . . 262 dbgmcu_apb1 . . . . . . . . . . . . . . . . . . . . . 1293 dbgmcu_apb2_fz . . . . . . . . . . . . . . . . . . 1295 dbgmcu_cr . . . . . . . . . . . . . . . . . . . . . . . 1292 dbgmcu_idcode . . . . . . . . . . . . . . . . . . 1279 dcmi_cr . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 dcmi_cwsize . . . . . . . . . . . . . . . . . . . . . . . 288 dcmi_cwstrt . . . . . . . . . . . . . . . . . . . . . . 288 dcmi_dr . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 dcmi_escr . . . . . . . . . . . . . . . . . . . . . . . . . 286 dcmi_esur . . . . . . . . . . . . . . . . . . . . . . . . . 287 dcmi_icr . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 dcmi_ier . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 dcmi_mis . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 dcmi_ris . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 dcmi_sr . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 RM0033 index doc id 15403 rev 3 1306/1317 dma_hifcr . . . . . . . . . . . . . . . . . . . . . . . . .194 dma_hisr . . . . . . . . . . . . . . . . . . . . . . . . . . .192 dma_lifcr . . . . . . . . . . . . . . . . . . . . . . . . . .193 dma_lisr . . . . . . . . . . . . . . . . . . . . . . . . . . .191 dma_sxcr . . . . . . . . . . . . . . . . . . . . . . . . . .195 dma_sxfcr . . . . . . . . . . . . . . . . . . . . . . . . .200 dma_sxm0ar . . . . . . . . . . . . . . . . . . . . . . . .199 dma_sxm1ar . . . . . . . . . . . . . . . . . . . . . . . .199 dma_sxndtr . . . . . . . . . . . . . . . . . . . . . . . .198 dma_sxpar . . . . . . . . . . . . . . . . . . . . . . . . .198 e eth_dmabmr . . . . . . . . . . . . . . . . . . . . . . .906 eth_dmachrbar . . . . . . . . . . . . . . . . . . . .919 eth_dmachrdr . . . . . . . . . . . . . . . . . . . . .919 eth_dmachtbar . . . . . . . . . . . . . . . . . . . .919 eth_dmachtdr . . . . . . . . . . . . . . . . . . . . .918 eth_dmaier . . . . . . . . . . . . . . . . . . . . . . . .915 eth_dmamfbocr . . . . . . . . . . . . . . . . . . .917 eth_dmaomr . . . . . . . . . . . . . . . . . . . . . . .912 eth_dmardlar . . . . . . . . . . . . . . . . . . . . .908 eth_dmarpdr . . . . . . . . . . . . . . . . . . . . . .908 eth_dmarswtr . . . . . . . . . . . . . . . . . . . . .917 eth_dmasr . . . . . . . . . . . . . . . . . . . . . . . . .909 eth_dmatdlar . . . . . . . . . . . . . . . . . . . . .909 eth_dmatpdr . . . . . . . . . . . . . . . . . . . . . .907 eth_maca0hr . . . . . . . . . . . . . . . . . . . . . .887 eth_maca0lr . . . . . . . . . . . . . . . . . . . . . . .888 eth_maca1hr . . . . . . . . . . . . . . . . . . . . . .888 eth_maca1lr . . . . . . . . . . . . . . . . . . . . . . .889 eth_maca2hr . . . . . . . . . . . . . . . . . . . . . .889 eth_maca2lr . . . . . . . . . . . . . . . . . . . . . . .890 eth_maca3hr . . . . . . . . . . . . . . . . . . . . . .890 eth_maca3lr . . . . . . . . . . . . . . . . . . . . . . .891 eth_maccr . . . . . . . . . . . . . . . . . . . . . . . . .872 eth_macdbgr . . . . . . . . . . . . . . . . . . . . . .884 eth_macfcr . . . . . . . . . . . . . . . . . . . . . . . .878 eth_macffr . . . . . . . . . . . . . . . . . . . . . . . .875 eth_machthr . . . . . . . . . . . . . . . . . . . . . .876 eth_machtlr . . . . . . . . . . . . . . . . . . . . . . .877 eth_macimr . . . . . . . . . . . . . . . . . . . . . . . .887 eth_macmiiar . . . . . . . . . . . . . . . . . . . . . .877 eth_macmiidr . . . . . . . . . . . . . . . . . . . . . .878 eth_macpmtcsr . . . . . . . . . . . . . . . . . . . .883 eth_macrwuffr . . . . . . . . . . . . . . . . . . .882 eth_macsr . . . . . . . . . . . . . . . . . . . . . . . . .886 eth_macvlantr . . . . . . . . . . . . . . . . . . . .880 eth_mmccr . . . . . . . . . . . . . . . . . . . . . . . .892 eth_mmcrfaecr . . . . . . . . . . . . . . . . . . . .897 eth_mmcrfcecr . . . . . . . . . . . . . . . . . . .897 eth_mmcrgufcr . . . . . . . . . . . . . . . . . . .898 eth_mmcrimr . . . . . . . . . . . . . . . . . . . . . . 895 eth_mmcrir . . . . . . . . . . . . . . . . . . . . . . . 892 eth_mmctgfcr . . . . . . . . . . . . . . . . . . . . 897 eth_mmctgfmsccr . . . . . . . . . . . . . . . . 896 eth_mmctgfsccr . . . . . . . . . . . . . . . . . . 896 eth_mmctimr . . . . . . . . . . . . . . . . . . . . . . 895 eth_mmctir . . . . . . . . . . . . . . . . . . . . . . . . 893 eth_ptpppscr . . . . . . . . . . . . . . . . . . . . . 905 eth_ptpssir . . . . . . . . . . . . . . . . . . . . . . . 900 eth_ptptsar . . . . . . . . . . . . . . . . . . . . . . . 903 eth_ptptscr . . . . . . . . . . . . . . . . . . . . . . 898 eth_ptptshr . . . . . . . . . . . . . . . . . . . . . . 900 eth_ptptshur . . . . . . . . . . . . . . . . . . . . . 902 eth_ptptslr . . . . . . . . . . . . . . . . . . . . . . . 902 eth_ptptslur . . . . . . . . . . . . . . . . . . . . . 903 eth_ptptssr . . . . . . . . . . . . . . . . . . . . . . . 904 eth_ptptthr . . . . . . . . . . . . . . . . . . . . . . . 904 eth_ptpttlr . . . . . . . . . . . . . . . . . . . . . . . 904 exti_emr . . . . . . . . . . . . . . . . . . . . . . . . . . 166 exti_ftsr . . . . . . . . . . . . . . . . . . . . . . . . . . 167 exti_imr . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 exti_pr . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 exti_rtsr . . . . . . . . . . . . . . . . . . . . . . . . . . 167 exti_swier . . . . . . . . . . . . . . . . . . . . . . . . . 168 f fsmc_bcr1..4 . . . . . . . . . . . . . . . . . . . . . . 1251 fsmc_btr1..4 . . . . . . . . . . . . . . . . . . . . . . 1253 fsmc_bwtr1..4 . . . . . . . . . . . . . . . . . . . . 1255 g gpiox_afrh . . . . . . . . . . . . . . . . . . . . . . . . 150 gpiox_afrl . . . . . . . . . . . . . . . . . . . . . . . . 149 gpiox_bsrr . . . . . . . . . . . . . . . . . . . . . . . . 148 gpiox_idr . . . . . . . . . . . . . . . . . . . . . . . . . . 147 gpiox_lckr . . . . . . . . . . . . . . . . . . . . . . . . 148 gpiox_moder . . . . . . . . . . . . . . . . . . . . . . 145 gpiox_odr . . . . . . . . . . . . . . . . . . . . . . . . . 148 gpiox_ospeedr . . . . . . . . . . . . . . . . . . . . 146 gpiox_otyper . . . . . . . . . . . . . . . . . . . . . . 146 gpiox_pupdr . . . . . . . . . . . . . . . . . . . . . . . 147 h hash_cr . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 hash_csrx . . . . . . . . . . . . . . . . . . . . . . . . . 539 hash_din . . . . . . . . . . . . . . . . . . . . . . . . . . 534 hash_hr0 . . . . . . . . . . . . . . . . . . . . . . . . . . 536 hash_hr1 . . . . . . . . . . . . . . . . . . . . . . . . . . 536 hash_hr2 . . . . . . . . . . . . . . . . . . . . . . . . . . 536 hash_hr3 . . . . . . . . . . . . . . . . . . . . . . . . . . 536 index RM0033 1307/1317 doc id 15403 rev 3 hash_hr4 . . . . . . . . . . . . . . . . . . . . . . . . . .537 hash_imr . . . . . . . . . . . . . . . . . . . . . . . . . . .537 hash_sr . . . . . . . . . . . . . . . . . . . . . . . . . . .538 hash_str . . . . . . . . . . . . . . . . . . . . . . . . . .535 i i2c_ccr . . . . . . . . . . . . . . . . . . . . . . . . . . . .598 i2c_cr1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .588 i2c_cr2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .590 i2c_dr . . . . . . . . . . . . . . . . . . . . . . . . . . . . .593 i2c_oar1 . . . . . . . . . . . . . . . . . . . . . . . . . . .592 i2c_oar2 . . . . . . . . . . . . . . . . . . . . . . . . . . .592 i2c_sr1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .593 i2c_sr2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .597 i2c_trise . . . . . . . . . . . . . . . . . . . . . . . . . . .599 iwdg_kr . . . . . . . . . . . . . . . . . . . . . . . . . . .473 iwdg_pr . . . . . . . . . . . . . . . . . . . . . . . . . . .474 iwdg_rlr . . . . . . . . . . . . . . . . . . . . . . . . . .474 iwdg_sr . . . . . . . . . . . . . . . . . . . . . . . . . . .475 o otg_fs_cid . . . . . . . . . . . . . . . . . . . .973 , 1109 otg_fs_daint . . . . . . . . . . . . . . . . .991 , 1129 otg_fs_daintmsk . . . . . . . . . . . . .992 , 1129 otg_fs_dcfg . . . . . . . . . . . . . . . . . . . . . . .986 otg_fs_dctl . . . . . . . . . . . . . . . . . .987 , 1124 otg_fs_diepctl0 . . . . . . . . . . . . . . . . . . .994 otg_fs_diepempmsk . . . . . . . . . . .993 , 1132 otg_fs_diepintx . . . . . . . . . . . . . .1002 , 1142 otg_fs_diepmsk . . . . . . . . . . . . . . .989 , 1127 otg_fs_dieptsiz0 . . . . . . . . . . . . .1004 , 1145 otg_fs_dieptsizx . . . . . . . . . . . . .1006 , 1147 otg_fs_dieptxfx . . . . . . . . . . . . . .975 , 1109 otg_fs_doepctl0 . . . . . . . . . . . . .998 , 1138 otg_fs_doepctlx . . . . . . . . . . . . .999 , 1139 otg_fs_doepintx . . . . . . . . . . . . .1003 , 1144 otg_fs_doepmsk . . . . . . . . . . . . . .990 , 1128 otg_fs_doeptsiz0 . . . . . . . . . . . .1005 , 1146 otg_fs_doeptsizx . . . . . . . . . . . .1007 , 1148 otg_fs_dsts . . . . . . . . . . . . . . . . . .988 , 1126 otg_fs_dtxfstsx . . . . . . . . . . . . .1007 , 1148 otg_fs_dvbusdis . . . . . . . . . . . . .992 , 1130 otg_fs_dvbuspulse . . . . . . . . . . .993 , 1130 otg_fs_gahbcfg . . . . . . . . . . . . . .957 , 1089 otg_fs_gccfg . . . . . . . . . . . . . . . .972 , 1108 otg_fs_gintmsk . . . . . . . . . . . . . .966 , 1100 otg_fs_gintsts . . . . . . . . . . . . . . .962 , 1096 otg_fs_gnptxfsiz . . . . . . . . . . . . .971 , 1105 otg_fs_gnptxsts . . . . . . . . . . . . .971 , 1105 otg_fs_gotgctl . . . . . . . . . . . . . .953 , 1085 otg_fs_gotgint . . . . . . . . . . . . . .955 , 1087 otg_fs_grstctl . . . . . . . . . . . . . . 960 , 1093 otg_fs_grxfsiz . . . . . . . . . . . . . . 970 , 1104 otg_fs_grxstsp . . . . . . . . . . . . . . 969 , 1103 otg_fs_grxstsr . . . . . . . . . . . . . . 969 , 1103 otg_fs_gusbcfg . . . . . . . . . . . . . 958 , 1090 otg_fs_haint . . . . . . . . . . . . . . . . . 978 , 1113 otg_fs_haintmsk . . . . . . . . . . . . . 979 , 1113 otg_fs_hccharx . . . . . . . . . . . . . . 982 , 1116 otg_fs_hcfg . . . . . . . . . . . . . . . . . 975 , 1110 otg_fs_hcintmskx . . . . . . . . . . . . 984 , 1120 otg_fs_hcintx . . . . . . . . . . . . . . . . 983 , 1119 otg_fs_hctsizx . . . . . . . . . . . . . . . 985 , 1121 otg_fs_hfir . . . . . . . . . . . . . . . . . . 976 , 1111 otg_fs_hfnum . . . . . . . . . . . . . . . . 977 , 1111 otg_fs_hprt . . . . . . . . . . . . . . . . . 979 , 1114 otg_fs_hptxfsiz . . . . . . . . . . . . . . 973 , 1109 otg_fs_hptxsts . . . . . . . . . . . . . . 977 , 1112 otg_fs_pcgcctl . . . . . . . . . . . . . 1008 , 1149 otg_hs_dcfg . . . . . . . . . . . . . . . . . . . . . 1122 otg_hs_deachintmsk . . . . . . . . . . . . . 1133 otg_hs_diepdmax . . . . . . . . . . . . . . . . . 1149 otg_hs_doepdmax . . . . . . . . . . . . . . . . 1149 otg_hs_dthrctl . . . . . . . . . . . . . . . . . . 1131 otg_hs_hcspltx . . . . . . . . . . . . . . . . . . 1118 p pwr_cr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 pwr_csr . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 r rcc_ahb1enr . . . . . . . . . . . . . . . . . . . . . . 109 rcc_ahb1lpenr . . . . . . . . . . . . . . . . . . . . 117 rcc_ahb1rstr . . . . . . . . . . . . . . . . . . . . . 101 rcc_ahb2enr . . . . . . . . . . . . . . . . . . . . . . 111 rcc_ahb2lpenr . . . . . . . . . . . . . . . . . . . . 119 rcc_ahb2rstr . . . . . . . . . . . . . . . . . . . . . 103 rcc_ahb3enr . . . . . . . . . . . . . . . . . . . . . . 112 rcc_ahb3lpenr . . . . . . . . . . . . . . . . . . . . 120 rcc_ahb3rstr . . . . . . . . . . . . . . . . . . . . . 104 rcc_apb1enr . . . . . . . . . . . . . . . . . . . . . . 112 rcc_apb1lpenr . . . . . . . . . . . . . . . . . . . . 121 rcc_apb1rstr . . . . . . . . . . . . . . . . . . . . . 104 rcc_apb2enr . . . . . . . . . . . . . . . . . . . . . . 115 rcc_apb2lpenr . . . . . . . . . . . . . . . . . . . . 124 rcc_apb2rstr . . . . . . . . . . . . . . . . . . . . . 107 rcc_bdcr . . . . . . . . . . . . . . . . . . . . . . . . . 126 rcc_cfgr . . . . . . . . . . . . . . . . . . . . . . . . . . 96 rcc_cir . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 rcc_cr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 rcc_csr . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 rcc_pllcfgr . . . . . . . . . . . . . . . . . . . 94 , 130 RM0033 index doc id 15403 rev 3 1308/1317 rcc_sscgr . . . . . . . . . . . . . . . . . . . . . . . . .129 rng_cr . . . . . . . . . . . . . . . . . . . . . . . . . . . .520 rng_dr . . . . . . . . . . . . . . . . . . . . . . . . . . . .521 rng_sr . . . . . . . . . . . . . . . . . . . . . . . . . . . .520 rtc_alrmar . . . . . . . . . . . . . . . . . . . . . . . .562 rtc_alrmbr . . . . . . . . . . . . . . . . . . . . . . . .563 rtc_bkxr . . . . . . . . . . . . . . . . . . . . . . . . . . .568 rtc_calibr . . . . . . . . . . . . . . . . . . . . . . . . .561 rtc_cr . . . . . . . . . . . . . . . . . . . . . . . . . . . . .556 rtc_dr . . . . . . . . . . . . . . . . . . . . . . . . . . . . .555 rtc_isr . . . . . . . . . . . . . . . . . . . . . . . . . . . .558 rtc_prer . . . . . . . . . . . . . . . . . . . . . . . . . .560 rtc_tafcr . . . . . . . . . . . . . . . . . . . . . . . . .567 rtc_tr . . . . . . . . . . . . . . . . . . . . . . . . . . . . .554 rtc_tsdr . . . . . . . . . . . . . . . . . . . . . . . . . .566 rtc_tstr . . . . . . . . . . . . . . . . . . . . . . . . . .565 rtc_wpr . . . . . . . . . . . . . . . . . . . . . . . . . . .565 rtc_wutr . . . . . . . . . . . . . . . . . . . . . . . . . .560 s sdio_clkcr . . . . . . . . . . . . . . . . . . . . . . . .744 sdio_dcount . . . . . . . . . . . . . . . . . . . . . . .750 sdio_dctrl . . . . . . . . . . . . . . . . . . . . . . . .749 sdio_dlen . . . . . . . . . . . . . . . . . . . . . . . . . .748 sdio_dtimer . . . . . . . . . . . . . . . . . . . . . . . .748 sdio_fifo . . . . . . . . . . . . . . . . . . . . . . . . . .757 sdio_fifocnt . . . . . . . . . . . . . . . . . . . . . . .756 sdio_icr . . . . . . . . . . . . . . . . . . . . . . . . . . .752 sdio_mask . . . . . . . . . . . . . . . . . . . . . . . . .754 sdio_power . . . . . . . . . . . . . . . . . . . . . . . .744 sdio_respcmd . . . . . . . . . . . . . . . . . . . . .747 sdio_respx . . . . . . . . . . . . . . . . . . . . . . . . .747 sdio_sta . . . . . . . . . . . . . . . . . . . . . . . . . . .751 spi_cr1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .693 spi_cr2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .696 spi_crcpr . . . . . . . . . . . . . . . . . . . . . . . . . .698 spi_dr . . . . . . . . . . . . . . . . . . . . . . . . . . . . .698 spi_i2scfgr . . . . . . . . . . . . . . . . . . . . . . . .699 spi_i2spr . . . . . . . . . . . . . . . . . . . . . . . . . . .701 spi_rxcrcr . . . . . . . . . . . . . . . . . . . . . . . .698 spi_sr . . . . . . . . . . . . . . . . . . . . . . . . . . . . .697 spi_txcrcr . . . . . . . . . . . . . . . . . . . . . . . .699 syscfg_exticr1 . . . . . . . . . . . . . . . . . . . .155 syscfg_exticr2 . . . . . . . . . . . . . . . . . . . .156 syscfg_exticr3 . . . . . . . . . . . . . . . . . . . .156 syscfg_exticr4 . . . . . . . . . . . . . . . . . . . .157 syscfg_memrmp . . . . . . . . . . . . . . . . . . .153 t tim2_or . . . . . . . . . . . . . . . . . . . . . . . . . . . .415 tim5_or . . . . . . . . . . . . . . . . . . . . . . . . . . . .416 timx_arr . . . . . . . . . . . . . . . 410 , 448 , 457 , 469 timx_bdtr . . . . . . . . . . . . . . . . . . . . . . . . . . 352 timx_ccer . . . . . . . . . . . . . 345 , 408 , 447 , 456 timx_ccmr1 . . . . . . . . . . . . 341 , 404 , 444 , 454 timx_ccmr2 . . . . . . . . . . . . . . . . . . . . 344 , 407 timx_ccr1 . . . . . . . . . . . . . . 350 , 411 , 449 , 458 timx_ccr2 . . . . . . . . . . . . . . . . . . 351 , 411 , 449 timx_ccr3 . . . . . . . . . . . . . . . . . . . . . . 351 , 412 timx_ccr4 . . . . . . . . . . . . . . . . . . . . . . 352 , 412 timx_cnt . . . . . . . . . . .349 , 410 , 448 , 457 , 468 timx_cr1 . . . . . . . . . . .331 , 394 , 438 , 451 , 466 timx_cr2 . . . . . . . . . . . . . . . 332 , 396 , 439 , 467 timx_dcr . . . . . . . . . . . . . . . . . . . . . . . 354 , 413 timx_dier . . . . . . . . . .336 , 400 , 441 , 451 , 467 timx_dmar . . . . . . . . . . . . . . . . . . . . . 355 , 413 timx_egr . . . . . . . . . . .339 , 403 , 443 , 453 , 468 timx_psc . . . . . . . . . . .349 , 410 , 448 , 457 , 469 timx_rcr . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 timx_smcr . . . . . . . . . . . . . . . . . 334 , 397 , 440 timx_sr . . . . . . . . . . . .338 , 401 , 442 , 452 , 468 u usart_brr . . . . . . . . . . . . . . . . . . . . . . . . . 641 usart_cr1 . . . . . . . . . . . . . . . . . . . . . . . . . 641 usart_cr2 . . . . . . . . . . . . . . . . . . . . . . . . . 644 usart_cr3 . . . . . . . . . . . . . . . . . . . . . . . . . 645 usart_dr . . . . . . . . . . . . . . . . . . . . . . . . . . 640 usart_gtpr . . . . . . . . . . . . . . . . . . . . . . . 648 usart_sr . . . . . . . . . . . . . . . . . . . . . . . . . . 638 w wwdg_cfr . . . . . . . . . . . . . . . . . . . . . . . . . 482 wwdg_cr . . . . . . . . . . . . . . . . . . . . . . . . . . 481 wwdg_sr . . . . . . . . . . . . . . . . . . . . . . . . . . 482 RM0033 revision history doc id 15403 rev 3 1309/1317 revision history table 217. document revision history date version changes 06-jul-2010 1 initial release. 09-dec-2010 2 removed v ddsa from the whole document. updated figure 1: system architecture for fsmc static memctl. updated table 3: number of wait states according to cortex-m3 clock frequency . updated embedded flash memory organization in section 2.3.3 ; updated latency bits in section : flash access control register (flash_acr) to support up to 7 wait states; added section 2.3.5: adaptive real-t ime memory accelerator (art accelerator?) . renamed fsmc nor/sram 1/2 bank1 into fsmc bank1 nor/psram 1/2. updated last two address ranges and added note 1 in table 5: memory mapping vs. boot mode/physical remap . power control (pwr) updated figure 3: power supply overview . updated v ref range in section 4.1.1: independent a/d converter supply and reference voltage ; bor default status updated in section 4.2.2: brownout reset (bor) . reset and clock controller changed hse oscillator frequency to 4-26 mhz and replaced spi2s_ckin by i2s2_ckin/i2s3_ckin in figure 9: clock tree . added note related to rtc_tr register read in section 5.2.8: rtc/awu clock . extended pll input frequency to 2 mhz, and updated caution note related to pllm[5:0] bit in section 5.3.2: rcc pll configuration register (rcc_pllcfgr) . system configuration controller added section 7.1: i/o compensation cell in section 7: system configuration cont roller (syscfg) . added case of fsmc remapped at address 0x0000 0000, and updated description of sysc fg_memrmp register and mem_mode bit in section 7.2.1: syscfg me mory remap register (syscfg_memrmp) . removed not related to ready bit in section 7.2.7: compensation cell control register (syscfg_cmpcr) . adc updated v dda low-speed and v ref ranges in table 32: adc pins updated section 10.2: adc main features . updated section 10.3.2: adc clock . changed pclk to pclk2 for adcpre bit description in section 10.13.16: adc common control register (adc_ccr) . updated jsq bit description, and added note in section 10.13.12: adc injected sequence register (adc_jsqr) . revision history RM0033 1310/1317 doc id 15403 rev 3 09-dec-2010 2 (continued) dac updated v ref range in table 41: dac pins . camera interface (dcmi) recommended 32-bit access for dcmi registers. removed f pixclk maximum value in section 12.4: dcmi clocks . section 12.5: dcmi functional overview ; updated figure 57 to remove nrst , ahb, dma_ack, and change it_cci to dcmi_it. removed section ?slave ahb interface?. updated section 12.5.1: dma interface overview and removed figure dma transfer. changed clock to pixel clock in section 12.5.2: dcmi physical interface , and figure 58 corrected. removed section ?parallel interface width?. section 12.8.1: dcmi contro l register 1 (dcmi_cr) : removed cre bit, updated ess bit description to distinguish between hardware and embedded synchronization, replaced ram by destination memory in cm and capture bit description. added note for err_ie and err_isc. section 12.8.3: dcmi raw in terrupt status register (dcmi_ris) / section 12.8.5: dcmi masked interrupt status register (dcmi_mis) : added note to indicated that err_ris/mis bit is available only in embedded synchronization mode. added note for err_ie and err_isc in section 12.8.4: dcmi interrupt enable register (dcmi_ier) . all ovr_ bit descriptions changed to overrun status. general-purpose timers (tim9 to tim14) updated cc1np and cc2np for tim9/12 in section 15.4.5: input capture mode , section 15.4.6: pwm input mode (only for tim9/12) , section 15.4.10: one-pulse mode (only for tim9/12) . updated urs and udis bit description in section 15.5.1: tim9/12 control register 1 (timx_cr1) . updated description of cc1if and uif bits in section 15.5.5: tim9/12 status register (timx_sr) . updated description of tg and ug bits in section 15.5.6: tim9/12 event generation register (timx_egr) . added cc1np and cc2np bits in section 15.5.8: tim9/12 capture/compare enable register (timx_ccer) . updated udis, urs, and cen bit description in section 15.6.1: tim10/11/13/14 control register 1 (timx_cr1) . removed tim10/11/13/14 timx_cr2 register. updated cc1if and uif bit description in section 15.6.3: tim10/11/13/14 status register (timx_sr) . updated ug bit description in section 15.6.4: tim1 0/11/13/14 event generation register (timx_egr) . updated oc1m and oc1pe bit description; and changed bit 2 register from reserved to oc1fe in section 15.6.5: tim10/11/13/14 capture/compare mode register 1 (timx_ccmr1) . table 217. document revision history date version changes RM0033 revision history doc id 15403 rev 3 1311/1317 09-dec-2010 2 (continued) general-purpose timers (tim 9 to tim14) (continued) added oc1fe bit and updated cc1np bit description in section 15.6.6: tim10/11/13/14 c apture/compare enable register (timx_ccer) . updated ti1_rmp bit description in section 15.6.12: tim10/11/13/14 register map . real-time clock (rtc) whole section 22: real-time clock (rtc) reworked without major content update. renamed tamper pin to tamper1, and afi_tamper to afi_tamper1. renamed tampf to tamp1f in section 22.6.4: rtc initialization and status register (rtc_isr) . renamed tampinsel to tamp1insel, tampe to tamp1e, and tampedge to tamp1trg in section 22.6.13: rtc tamper and alternate function configuration register (rtc_tafcr) , i2c updated last two steps of the clos ing communication sequence in section : master receiver . removed ev6_1 in figure 218: transfer sequence diagram for slave receiver . usart modified section : lin reception . updated table 96: usart mode configuration to add dma support for uart5. spi updated table 99: audio frequency precision (for pllm vco = 1mhz or 2mhz) title to add 2 mhz pll inputs frequency. updated figure 280: pcm standard waveforms (16-bit) . can: update description of lec bits in section : can error status register (can_esr) . ethernet removed eth _rmii_tx_clk alternated function for pc3 in table 137: alternate function mapping . changed fifo size in figure 312: eth block diagram . removed restriction related to ptp frame identification in section : reception of frames with the ptp feature . removed time-stamp low/high[31:0] in figure 342: enhanced transmit descriptor . removed sections ?tx/rxdma descrip tor format with ieee1588 time stamp". table 217. document revision history date version changes revision history RM0033 1312/1317 doc id 15403 rev 3 09-dec-2010 2 (continued) usb otg fs reworked section 29.6.4: host scheduler . usb otg hs updated section 30.1: otg_hs introduction . updated figure 372: usb otg interface block diagram to remove gpio interface and dma. updated section 30.6.4: host scheduler . updated dna and pktdrpsts bit descriptions in section : otg_hs device endpoint-x interr upt register (otg_hs_diepintx) (x = 0..7, where x = endpoint_number) . removed dmaen bit in section : otg_hs ahb configuration register (otg_hs_gahbcfg) . removed gmc bit in section : otg_hs devi ce control register (otg_hs_dctl) . removed otg_hs_diepdmabx and otg_hs_doepdmabx registers. changed sof to micro-sof in figure 373: updating otg_hs_hfir dynamically . fsmc updated figure 409: asynchronous wait during a read access to remove 2hclk cycles between data sampling and falling edge of a[25:0], rising edge of nex, data transition. replaced memxhiz+1 by memxhiz in figure 414: nand/pc card controller timing for common memory access . updated memhizx in fsmc_pmem2 ..4 register description. debug modified section 32.6.2: boundary scan tap . added dbg_rtc_stop bit in section 32.16.4: debug mcu apb1 freeze register (dbgmcu_apb1_fz) . added stm32f2xxx jatap id code. added section 33: device electronic signature . table 217. document revision history date version changes RM0033 revision history doc id 15403 rev 3 1313/1317 15-apr-2011 3 updated otp area in section 2.3.3: embedded flash memory . modified section : embedded bootloader . changed f master to ck_int in the whole document. modified dac bus in table 1: stm32f20x and stm32f21x register boundary addresses . pwr: added note related to voltage regulator activation depending to package in section 4.1.3: voltage regulator . rcc: added note related to i2s pll used as i2s input clock in section 5.2.3: pll configuration . modified vco output frequency for plln bit description in section 5.3.2: rcc pll configuration register (rcc_pllcfgr) . gpios: removed rtf_af1 and rtc_af2 from system functions in section 6.3.2: i/o pin multiplexer and mapping . modified section 6.3.13: using the osc32_in/osc32_out pins as gpio pc14/pc15 port pins and section 6.3.14: using the osc_in/osc_out pins as gpio ph0/ph1 port pins timers: tim1&tim8: updated example and definition of dbl bits in section 13.4.19: tim1&tim8 dma control register (timx_dcr) . added example related to dma bu rst feature and description of dmab bits in section 13.4.20: tim1&tim 8 dma address for full transfer (timx_dmar) . tim2 to tim5: added example and updated definition of dbl bits in section 14.4.17: timx dma control register (timx_dcr) . added example related to dma burst feature and description of dmab bits in section 14.4.18: timx dma a ddress for full transfer (timx_dmar) . updated definition of dbl bits in section 14.4.17: timx dma control re gister (timx_dcr) . iwdg: modified lsi clock frequency in table 69: min/max iwdg timeout period at 32 khz (lsi) title and updated timeout values. wwdg: updated section 18.2: wwdg main features . updated section 18.3: wwdg functional description to remove paragraph related to counter reload using ewi interrupt. added section : advanced watchdog interrupt feature in section 18.4: how to program the watchdog timeout . updated dbp bit definition in section 4.4.1: pwr power control register (pwr_cr) . table 217. document revision history date version changes revision history RM0033 1314/1317 doc id 15403 rev 3 15-apr-2011 3 (continued) crypto: updated section 19.1: cryp introduction . modified figure 195: block diagram . updated section 19.3.1: des/td es cryptographic core , section 19.3.2: aes cryptographic core , and table 73: data types . hash: in section 21.4.5: hash interrupt enable register (hash_imr) , renamed hash_imr into interrupt enable register, and bits dcim and dinim into dcie and dinie, respectively. updated init bit description in section 21.4.1: hash control register (hash_cr) . rtc: added rtc_50hz clock input for synchronous prescaler in figure 214: rtc block diagram . renamed digital calibration into coarse calibration. updated alarmouttype definition. digital calibration renamed coarse calibration. rng: renamed im bit of rng_cr register into ie. i2c: updated berr bit description in section 23.6.6: i 2 c status register 1 (i2c_sr1) . updated note 1 in section 23.6.8: i 2 c clock control register (i2c_ccr) . updated requests in master receiver mode in section 23.3.7: dma requests . added note 3 below figure 217: transfer sequence diagram for slave transmitter on page 574 . added note below figure 218: transfer sequence diagram for slave receiver on page 575 . modified section : closing slave communication on page 575 . modified stopf, addr, bit description in section 23.6.6: i 2 c status register 1 (i2c_sr1) on page 593 . modified section 23.6.7: i 2 c status register 2 (i2c_sr2) on page 597 . usart: updated figure 230: mute mode using address mark detection for address =1. renamed onebite to onebit in usart_cr3 register. table 217. document revision history date version changes RM0033 revision history doc id 15403 rev 3 1315/1317 15-apr-2011 3 (continued) spi: added ti frame error detection in slave transmitter only mode in section : spi ti protocol in slave mode . modified crc error in section 25.3.10: error flags . updated section : dma capability with crc and section 25.3.6: crc calculation . updated description of crcnext in section 25.5.1: spi control register 1 (spi_cr1) (not used in i 2 s mode) . added note related to i2s pll used as i2s input clock in section 25.4.3: clock generator . sdio : updated condition respected by pclk2 and sdio_ck in section 26.3: sdio functional description . ethernet: remove tx_etr signal from figure 316: media independent interface signals . usb otg fs: updated in b-device session request protocol sequence. added caution note related to minimum ahb frequency in section 29.3.2: full-speed otg phy . modified tim2 enable bits in section 29.7.1: host sofs and section 29.7.2: peripheral sofs . updated otg_fs_cid reset value. usb otg hs: added note 1 below figure 372: usb otg interface block diagram . updated in b-device session request protocol sequence. added caution note related to minimum ahb frequency in section 30.3.1: high-speed otg phy . updated fslspcs definition in section : otg_hs host configuration register (otg_hs_hcfg) . modified tim2 enable bits in section 30.7.1: host sofs and section 30.7.2: peripheral sofs . in section : otg_hs host channel-x interrupt register (otg_hs_hcintx) (x = 0..11, where x = channel_number) changed bit 2 of otg_hs_hcintx registers to ahberr. added nptxfe bit description in section : otg_hs core interrupt register (otg_hs_gintsts) . updated maximum values of rxfd and nptxfd in section : otg_hs receive fifo size register (otg_hs_grxfsiz) , and maximum in section : otg_hs nonperiodic transmit fifo size/endpoint 0 transmit fifo size register (otg_hs_gnptxfsiz/ otg_hs_tx0fsiz) , respectively. modified nptxfsav description in section : otg_hs nonperiodic transmit fifo/queue status register (otg_hs_gnptxsts) . updated otg_hs_cid register reset value. table 217. document revision history date version changes revision history RM0033 1316/1317 doc id 15403 rev 3 15-apr-2011 3 (continued) fsmc: updated description of datlat , datast , and addset bits in section : sram/nor-flash chip-s elect timing registers 1..4 (fsmc_btr1..4) . updated description of dat ast , and addset bits in section : sram/nor-flash write timing re gisters 1..4 (fsmc_bwtr1..4) . debug: added revision y in rev_id(15:0) description in section 32.6.1: mcu device id code . table 217. document revision history date version changes RM0033 d o c id 154 03 re v 3 1 317 /13 1 7 pl ea se r e ad c a re fu lly : inf or m at i on i n t hi s d ocumen t i s p r o vi ded so l el y i n co nnecti on wi th st pr oducts. s t mi cr oelect roni cs nv an d i t s su bsi d i a r i e s (? s t ?) re ser ve th e ri ght t o ma ke ch anges , co rr ec ti o ns, mo di f i c at i on s o r i m p r o vem ent s , t o t hi s d ocume nt , and t he pr oducts a nd ser vi c es de scr i bed h e r ei n at any t i me, with ou t no tic e. al l st pr odu ct s a r e s o l d pu rs ua nt to s t ? s t e r m s an d co nd it i o n s of sal e . pur c h a s e r s a r e so le l y r e s pon si bl e fo r t h e c hoi c e , se le ct i o n an d us e o f th e s t pr od uc ts an d s e r v i c e s d e s c r i b e d he re in , and st as s u m es no li a b i l i t y wh at so ev er r e l a t i n g t o t h e cho i ce, se le ct i o n o r u se o f t h e s t pr odu ct s a nd s e r v i c e s de sc ri be d he re in . no l i c e nse , e x p r e s s o r i m pl i e d , b y e s t o p pel or ot he rw is e, t o an y i n t e l l e c t u a l pr op er ty ri gh t s i s gr an te d u nde r t h i s doc ume n t . i f an y pa rt of t h i s do cume n t re f e r s t o an y t h i r d pa rt y p r o duc t s or se rv ic es i t sh al l n o t be d e e m ed a li ce ns e gr an t b y st fo r t h e use of su ch t h i r d par ty pr od uc ts or ser vi c es, or an y in t el l e ct ual p r o per t y c ont a i n ed t her e i n or con si dered as a war r ant y c over i n g t he u se i n a ny manner w hat s oev er o f su ch th i r d p a r t y pr od uct s o r se rv i ces or a n y i n t e ll e c t u a l pr op er t y co nt ai ne d t her ei n . unle ss o t her w ise se t for t h in s t ?s t e rms and co nditions o f sa le s t disc laims an y ex pres s or imp l ied warrant y wit h r espe ct to th e use and/or sa le of st p roduct s in cluding withou t limit ation imp l ied warrant ie s of merch antab il it y, fitne ss f or a parti cul ar p urpos e (and t heir e quivale nts under the laws of any j urisdiction), o r inf rin gement o f any pat e nt, copy right or oth e r in tel lect ual pro pert y rig ht. unle ss e xpre ssly appr oved in writing b y an aut horized st re pres enta tive, st p roduct s are not reco mmended , author iz ed or warrant ed f or us e in milita ry, air cra ft, sp ace, l i f e sa ving, or l i f e su staining appl ications, nor in p roduct s or sy ste ms where failure or malf unction may resu lt in per sonal inj ury , deat h, or s eve re prop erty o r environme ntal d amage. st p roduct s whic h are not s pecified as "automo t ive grade " may only b e used in autom otive app l ications a t user?s own risk. res al e of st pr oduct s wi t h pr ovisions d i f f er ent f r o m t he s t at eme nt s and/ or t echni c al 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